[PATCH 7/8] i386/pc386/include: header files for VESA BIOS EXTENSIONS and VESA Extended Display Identification Data
Joel Sherrill
joel.sherrill at oarcorp.com
Thu Nov 20 15:00:14 UTC 2014
On 11/20/2014 8:00 AM, Jan Dolezal wrote:
> ---
> c/src/lib/libbsp/i386/pc386/Makefile.am | 2 +
> c/src/lib/libbsp/i386/pc386/include/edid.h | 513 +++++++++++++++++++++++++++++
> c/src/lib/libbsp/i386/pc386/include/vbe3.h | 463 ++++++++++++++++++++++++++
> c/src/lib/libbsp/i386/pc386/preinstall.am | 8 +
> 4 files changed, 986 insertions(+)
> create mode 100644 c/src/lib/libbsp/i386/pc386/include/edid.h
> create mode 100644 c/src/lib/libbsp/i386/pc386/include/vbe3.h
>
> diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am b/c/src/lib/libbsp/i386/pc386/Makefile.am
> index 8c06129..de970a3 100644
> --- a/c/src/lib/libbsp/i386/pc386/Makefile.am
> +++ b/c/src/lib/libbsp/i386/pc386/Makefile.am
> @@ -106,6 +106,8 @@ libbsp_a_SOURCES += console/printk_support.c
> libbsp_a_SOURCES += console/vgacons.c
> libbsp_a_SOURCES += console/exar17d15x.c
> libbsp_a_SOURCES += console/rtd316.c
> +include_bsp_HEADERS += include/vbe3.h
> +include_HEADERS += include/edid.h
> if USE_CIRRUS_GD5446
> libbsp_a_SOURCES += console/fb_cirrus.c
> else
> diff --git a/c/src/lib/libbsp/i386/pc386/include/edid.h b/c/src/lib/libbsp/i386/pc386/include/edid.h
> new file mode 100644
> index 0000000..db3ec25
> --- /dev/null
> +++ b/c/src/lib/libbsp/i386/pc386/include/edid.h
> @@ -0,0 +1,513 @@
> +/**
> + * @file edid.h
> + *
> + * @ingroup i386_pc386
> + *
> + * @brief VESA EDID definitions.
> + */
> +
> +/*
> + * edid.h - This file contains definitions for constants related to
> + * VESA Extended Display Identification Data.
> + * More information can be found at
> + * <http://www.vesa.org/vesa-standards/free-standards/>
> + * VESA public standards may be found at
> + * <http://www.vesa.org/wp-content/uploads/2010/12/thankspublic.htm>
> + *
Incorporate this into the file header block.
> + * Copyright (C) 2014 Jan Doležal (dolezj21 at fel.cvut.cz)
> + * CTU in Prague.
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + */
> +
> +#ifndef _EDID_H
> +#define _EDID_H
> +
> +#ifndef ASM /* ASM */
> +
> +#include <stdint.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif /* __cplusplus */
> +
> +#include <rtems/score/basedefs.h>
> +#define EDID_PACKED_ATTRIBUTE RTEMS_COMPILER_PACKED_ATTRIBUTE
> +#define EDID_INLINE_ROUTINE RTEMS_INLINE_ROUTINE
> +
> +/* VESA Enhanced Extended Display Identification Data (E-EDID) Proposed
> + Release A, March 27, 2007 */
> +
> +/* *** Detailed Timing Descriptor Flags *** */
> +#define EDID1_DTD_Flag_InterlacedOff 7
> +#define EDID1_DTD_Flag_InterlacedMask 0x1
> +#define EDID1_DTD_Flag_StereoModeOff 0
> +#define EDID1_DTD_Flag_StereoModeMask 0xC1
> +/* values for stereo flag */
> +#define EDID1_DTD_Stereo_FldSeqRightOnSync 0x40
> +#define EDID1_DTD_Stereo_FldSeqLeftOnSync 0x80
> +#define EDID1_DTD_Stereo_2wItlvdRightOnEven 0x41
> +#define EDID1_DTD_Stereo_2wItlvdLeftOnEven 0x81
> +#define EDID1_DTD_Stereo_4wInterleaved 0xC0
> +#define EDID1_DTD_Stereo_SideBySideItlvd 0xC1
> +/* Analog = 0, Digital = 1 */
> +#define EDID1_DTD_Flag_DigitalOff 4
> +#define EDID1_DTD_Flag_DigitalMask 0x1
> +/* Analog */
> +#define EDID1_DTD_BipolarAnalogComposSyncOff 3
> +#define EDID1_DTD_BipolarAnalogComposSyncMask 0x1
> +#define EDID1_DTD_WithSerrationsOff 2
> +#define EDID1_DTD_WithSerrationsMask 0x1
> +/* Digital */
> +#define EDID1_DTD_DigitalSeparateSyncOff 3
> +#define EDID1_DTD_DigitalSeparateSyncMask 0x1
> + /* when DigitalSeparateSync == 0 -> it is composite
> + and WithSerrations defined up in Analog part applies */
> +#define EDID1_DTD_VerticalSyncIsPositiveOff 2
> +#define EDID1_DTD_VerticalSyncIsPositiveMask 0x1
> +#define EDID1_DTD_HorizontalSyncIsPositiveOff 1
> +#define EDID1_DTD_HorizontalSyncIsPositiveMask 0x1
> +
> +struct DetailedTimingDescriptor {
> + uint8_t PixelClock_div10000[2];
> + uint8_t HorizontalActiveLow;
> + uint8_t HorizontalBlankingLow;
> + uint8_t HorizontalBlanking_ActiveHigh;
> + uint8_t VerticalActiveLow;
> + uint8_t VerticalBlankingLow;
> + uint8_t VerticalBlanking_ActiveHigh;
> + uint8_t HorizontalSyncOffsetLow;
> + uint8_t HorizontalSyncPulseWidthLow;
> + uint8_t VerticalSyncPulseWidth_OffsetLow;
> + uint8_t Vert_Hor_SyncPulseWidth_Offset_High;
> + uint8_t HorizontalImageSizeLow;
> + uint8_t VerticalImageSizeLow;
> + uint8_t Vertical_HorizontalImageSizeHigh;
> + uint8_t HorizontalBorder;
> + uint8_t VerticalBorder;
> + uint8_t Flags;
> +} EDID_PACKED_ATTRIBUTE;
Doxygen on small methods?
> +EDID_INLINE_ROUTINE uint16_t DTD_HorizontalActive (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->HorizontalActiveLow |
> + (dtd->HorizontalBlanking_ActiveHigh & 0xF0) << 4);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_HorizontalBlanking (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->HorizontalBlankingLow |
> + (dtd->HorizontalBlanking_ActiveHigh & 0xF) << 8);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_VerticalActive (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->VerticalActiveLow |
> + (dtd->VerticalBlanking_ActiveHigh & 0xF0) << 4);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_VerticalBlanking (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->VerticalBlankingLow |
> + (dtd->VerticalBlanking_ActiveHigh & 0xF) << 8);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_VerticalSyncPulseWidth (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return ((dtd->VerticalSyncPulseWidth_OffsetLow & 0xF) |
> + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x3) << 4);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_VerticalSyncOffset (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return ((dtd->VerticalSyncPulseWidth_OffsetLow >> 4) |
> + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC) << 2);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_HorizontalSyncPulseWidth (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->HorizontalSyncPulseWidthLow |
> + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0x30) << 4);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_HorizontalSyncOffset (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->HorizontalSyncOffsetLow |
> + (dtd->Vert_Hor_SyncPulseWidth_Offset_High & 0xC0) << 2);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_VerticalImageSize (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->VerticalImageSizeLow |
> + (dtd->Vertical_HorizontalImageSizeHigh & 0xF) << 8);
> +}
> +
> +EDID_INLINE_ROUTINE uint16_t DTD_HorizontalImageSize (
> + struct DetailedTimingDescriptor *dtd)
> +{
> + return (dtd->HorizontalImageSizeLow |
> + (dtd->Vertical_HorizontalImageSizeHigh & 0xF0) << 4);
> +}
> +
> +struct ColorPointData {
> + uint8_t ColorPointWhitePointIndexNumber;
> + uint8_t ColorPointWhiteLowBits;
> + uint8_t ColorPointWhite_x;
> + uint8_t ColorPointWhite_y;
> + uint8_t ColorPointWhiteGamma;
> +} EDID_PACKED_ATTRIBUTE;
> +
> +/* Basic Display Parameters */
> +/* Monitor Descriptor - Data Type Tag */
> +#define EDID_DTT_MonitorSerialNumber 0xFF
> +
> +#define EDID_DTT_ASCIIString 0xFE
> +
> +#define EDID_DTT_MonitorRangeLimits 0xFD
> +struct MonitorRangeLimits {
> + uint8_t MinVerticalRateInHz;
> + uint8_t MaxVerticalRateInHz;
> + uint8_t MinHorizontalInKHz;
> + uint8_t MaxHorizontalInKHz;
> + uint8_t MaxSupportedPixelClockIn10MHz;
> +/* see VESA, Generalized Timing Formula Standard - GTF
> + Version 1.0, December 18, 1996 */
> + uint8_t GTFStandard[8];
> +} EDID_PACKED_ATTRIBUTE;
> +
> +#define EDID_DTT_MonitorName 0xFC
> +
> +#define EDID_DTT_AdditionalColorPointData 0xFB
> +/* Standard Timing Identification */
> +#define EDID_DTT_AdditionalSTI 0xFA
> +
> +#define EDID_DTT_DisplayColorManagement 0xF9
> +
> +#define EDID_DTT_CVT3ByteTimingCodes 0xF8
> +
> +#define EDID1_CVT_AspectRatioOff 2
> +#define EDID1_CVT_AspectRatioMask 0x3
> +#define EDID1_CVT_AddressableLinesHighOff 4
> +#define EDID1_CVT_AddressableLinesHighMask 0xF
> + /* next 5 bits indicate supported vertical rates */
> +#define EDID1_CVT_VerticalRate60HzRBOff 0
> +#define EDID1_CVT_VerticalRate60HzRBMask 0x1
> +#define EDID1_CVT_VerticalRate85HzOff 1
> +#define EDID1_CVT_VerticalRate85HzMask 0x1
> +#define EDID1_CVT_VerticalRate75HzOff 2
> +#define EDID1_CVT_VerticalRate75HzMask 0x1
> +#define EDID1_CVT_VerticalRate60HzOff 3
> +#define EDID1_CVT_VerticalRate60HzMask 0x1
> +#define EDID1_CVT_VerticalRate50HzOff 4
> +#define EDID1_CVT_VerticalRate50HzMask 0x1
> +#define EDID1_CVT_PreferredVerticalRateOff 5
> +#define EDID1_CVT_PreferredVerticalRateMask 0x3
> +
> +#define EDID_CVT_AspectRatio_4_3 0
> +#define EDID_CVT_AspectRatio_16_9 1
> +#define EDID_CVT_AspectRatio_16_10 2
> +#define EDID_CVT_AspectRatio_15_9 3
> +#define EDID_CVT_PrefVertRate50Hz 0
> +#define EDID_CVT_PrefVertRate60Hz 1
> +#define EDID_CVT_PrefVertRate75Hz 2
> +#define EDID_CVT_PrefVertRate85Hz 3
> +struct CVT3ByteCodeDescriptor {
> + uint8_t AddressableLinesLow;
> + uint8_t AspectRatio_AddressableLinesHigh;
> + uint8_t VerticalRate_PreferredVerticalRate;
> +} EDID_PACKED_ATTRIBUTE;
> +struct CVTTimingCodes3B {
> + uint8_t VersionNumber;
> + struct CVT3ByteCodeDescriptor cvt[4];
> +} EDID_PACKED_ATTRIBUTE;
> +
> +EDID_INLINE_ROUTINE uint16_t edid1_CVT_AddressableLinesHigh (
> + struct CVT3ByteCodeDescriptor *cvt)
> +{
> + return (cvt->AddressableLinesLow |
> + (cvt->VerticalRate_PreferredVerticalRate &
> + (EDID1_CVT_AddressableLinesHighMask<<EDID1_CVT_AddressableLinesHighOff)
> + ) << (8-EDID1_CVT_AddressableLinesHighOff) );
> +}
> +
> +EDID_INLINE_ROUTINE uint8_t edid1_CVT_AspectRatio (
> + struct CVT3ByteCodeDescriptor *cvt)
> +{
> + return (cvt->AspectRatio_AddressableLinesHigh >> EDID1_CVT_AspectRatioOff) &
> + EDID1_CVT_AspectRatioMask;
> +}
> +
> +#define EDID_DTT_EstablishedTimingsIII 0xF7
> +struct EstablishedTimingsIII {
> + uint8_t RevisionNumber;
> + uint8_t EST_III[12];
> +} EDID_PACKED_ATTRIBUTE;
> +enum EST_III {
> + EST_1152x864_75Hz = 0,
> + EST_1024x768_85Hz = 1,
> + EST_800x600_85Hz = 2,
> + EST_848x480_60Hz = 3,
> + EST_640x480_85Hz = 4,
> + EST_720x400_85Hz = 5,
> + EST_640x400_85Hz = 6,
> + EST_640x350_85Hz = 7,
> +
> + EST_1280x1024_85Hz = 8,
> + EST_1280x1024_60Hz = 9,
> + EST_1280x960_85Hz = 10,
> + EST_1280x960_60Hz = 11,
> + EST_1280x768_85Hz = 12,
> + EST_1280x768_75Hz = 13,
> + EST_1280x768_60Hz = 14,
> + EST_1280x768_60HzRB = 15,
> +
> + EST_1400x1050_75Hz = 16,
> + EST_1400x1050_60Hz = 17,
> + EST_1400x1050_60HzRB= 18,
> + EST_1400x900_85Hz = 19,
> + EST_1400x900_75Hz = 20,
> + EST_1400x900_60Hz = 21,
> + EST_1400x900_60HzRB = 22,
> + EST_1360x768_60Hz = 23,
> +
> + EST_1600x1200_70Hz = 24,
> + EST_1600x1200_65Hz = 25,
> + EST_1600x1200_60Hz = 26,
> + EST_1680x1050_85Hz = 27,
> + EST_1680x1050_75Hz = 28,
> + EST_1680x1050_60Hz = 29,
> + EST_1680x1050_60HzRB= 30,
> + EST_1400x1050_85Hz = 31,
> +
> + EST_1920x1200_60Hz = 32,
> + EST_1920x1200_60HzRB= 33,
> + EST_1856x1392_75Hz = 34,
> + EST_1856x1392_60Hz = 35,
> + EST_1792x1344_75Hz = 36,
> + EST_1792x1344_60Hz = 37,
> + EST_1600x1200_85Hz = 38,
> + EST_1600x1200_75Hz = 39,
> +
> + EST_1920x1440_75Hz = 44,
> + EST_1920x1440_60Hz = 45,
> + EST_1920x1200_85Hz = 46,
> + EST_1920x1200_75Hz = 47,
> +};
> +
> +#define EDID_DTT_DescriptorSpaceUnused 0x10
> +/* DTT 0x0 - 0xF are manufacturer specific */
> +
> +struct MonitorDescriptor {
> + uint8_t Flag0[2];
> + uint8_t Flag1;
> + uint8_t DataTypeTag;
> + uint8_t Flag2;
> + uint8_t DescriptorData[13];
> +} EDID_PACKED_ATTRIBUTE;
> +
> +union DTD_MD {
> + struct DetailedTimingDescriptor dtd;
> + struct MonitorDescriptor md;
> +} EDID_PACKED_ATTRIBUTE;
> +
> +#define EDID1_STI_ImageAspectRatioOff 0
> +#define EDID1_STI_ImageAspectRatioMask 0x3
> +#define EDID1_STI_RefreshRateOff 2
> +#define EDID1_STI_RefreshRateMask 0x3F
> +
> +#define EDID_STI_DescriptorUnused 0x0101
> +#define EDID_STI_AspectRatio_16_10 0
> +#define EDID_STI_AspectRatio_4_3 1
> +#define EDID_STI_AspectRatio_5_4 2
> +#define EDID_STI_AspectRatio_16_9 3
> +struct StandardTimingIdentification {
> + uint8_t HorizontalActivePixels;
> + uint8_t ImageAspectRatio_RefreshRate;
> +} EDID_PACKED_ATTRIBUTE;
> +
> +/* Video Input Definition */
> +/* Analog = 0, Digital = 1 */
> +#define EDID1_VID_DigitalSignalLevelOff 7
> +#define EDID1_VID_DigitalSignalLevelMask 0x1
> +/* for EDID1_VID_DigitalSignalLevelOff = 1 (Digital) */
> +#define EDID1_VID_ColorBitDepthOff 4
> +#define EDID1_VID_ColorBitDepthMask 0x7 /* see CBD */
> +#define EDID1_VID_DigitalVideoStandardSuppOff 0
> +#define EDID1_VID_DigitalVideoStandardSuppMask 0xF /* see DVS */
> +/* for EDID1_VID_DigitalSignalLevelOff = 0 (Analog) */
> +#define EDID1_VID_SignalLevelStandardOff 5
> +#define EDID1_VID_SignalLevelStandardMask 0x3
> +#define EDID1_VID_VideoSetupBlankOff 4
> +#define EDID1_VID_VideoSetupBlankMask 0x1
> +#define EDID1_VID_SeparateSyncHandVSignalsOff 3
> +#define EDID1_VID_SeparateSyncHandVSignalsMask 0x1
> +#define EDID1_VID_SyncSignalOnHorizontalOff 2
> +#define EDID1_VID_SyncSignalOnHorizontalMask 0x1
> +#define EDID1_VID_SyncSignalOnGreenOff 1
> +#define EDID1_VID_SyncSignalOnGreenMask 0x1
> +#define EDID1_VID_SerationOnVerticalSyncOff 0
> +#define EDID1_VID_SerationOnVerticalSyncMask 0x1
> +/* Analog Interface Data Format - Signal Level Standard */
> +#define EDID_SLS_0700_0300_1000Vpp 0x0
> +#define EDID_SLS_0714_0286_1000Vpp 0x1
> +#define EDID_SLS_1000_0400_1400Vpp 0x2
> +#define EDID_SLS_0700_0000_0700Vpp 0x3
> +
> +/* Color Bit Depths */
> +#define CBD_undef 0x0
> +#define CBD_6bPerPrimaryColor 0x1
> +#define CBD_8bPerPrimaryColor 0x2
> +#define CBD_10bPerPrimaryColor 0x3
> +#define CBD_12bPerPrimaryColor 0x4
> +#define CBD_14bPerPrimaryColor 0x5
> +#define CBD_16bPerPrimaryColor 0x6
> +#define CBD_reserved 0x7
> +
> +/* Digital Video Standard Supported */
> +#define DVS_undef 0x0
> +#define DVS_DVI 0x1
> +#define DVS_HDMI-a 0x2
> +#define DVS_HDMI-b 0x3
> +#define DVS_MDDI 0x4
> +#define DVS_DiplayPort 0x5
> +
> +/* Feature Support */
> +#define EDID1_Feature_GTFSupported_mask 0x1
> +#define EDID1_Feature_GTFSupported_off 0
> +#define EDID1_Feature_PreferredTimingMode_mask 0x1
> +#define EDID1_Feature_PreferredTimingMode_off 1
> +#define EDID1_Feature_StandardDefaultColorSpace_mask 0x1
> +#define EDID1_Feature_StandardDefaultColorSpace_off 2
> +#define EDID1_Feature_DisplayType_mask 0x2
> +#define EDID1_Feature_DisplayType_off 3
> + /* Refer to VESA DPMS Specification */
> +#define EDID1_Feature_ActiveOff_mask 0x1
> +#define EDID1_Feature_ActiveOff_off 5
> +#define EDID1_Feature_Suspend_mask 0x1
> +#define EDID1_Feature_Suspend_off 6
> +#define EDID1_Feature_StandBy_mask 0x1
> +#define EDID1_Feature_StandBy_off 7
> + /* analog - Display Color Type */
> +#define EDID_DisplayType_Monochrome 0
> +#define EDID_DisplayType_RGBcolor 1
> +#define EDID_DisplayType_nonRGBcolor 2
> +#define EDID_DisplayType_undef 3
> + /* digital - Supported Color Encoding Formats */
> +#define EDID_DisplayType_RGB444 0
> +#define EDID_DisplayType_RGB444YCrCb444 1
> +#define EDID_DisplayType_RGB444YCrCb422 2
> +#define EDID_DisplayType_RGB444YCrCb444YCrCb422 3
> +
> +struct edid1 {
> + uint8_t Header[8];
> +/* Vendor Product Identification */
> + uint8_t IDManufacturerName[2];
> + uint8_t IDProductCode[2];
> + uint8_t IDSerialNumber[4];
> + uint8_t WeekofManufacture;
> + uint8_t YearofManufacture;
> +/* EDID Structure Version Revision Level */
> + uint8_t Version;
> + uint8_t Revision;
> +/* Basic Display Parameters Features */
> + /* Video Input Definition */
> + uint8_t VideoInputDefinition;
> + uint8_t MaxHorizontalImageSize;
> + uint8_t MaxVerticalImageSize;
> + uint8_t DisplayTransferCharacteristic;
> + /* Feature Support */
> + uint8_t Features;
> +/* Color Characteristics */
> + uint8_t GreenRedLow;
> + uint8_t WhiteBlueLow;
> + uint8_t RedXHigh;
> + uint8_t RedYHigh;
> + uint8_t GreenXHigh;
> + uint8_t GreenYHigh;
> + uint8_t BlueXHigh;
> + uint8_t BlueYHigh;
> + uint8_t WhiteXHigh;
> + uint8_t WhiteYHigh;
> +/* Established Timings I, II, Manufacturer's */
> + uint8_t EST_I_II_Man[3];
> +/* Standard Timing Identification */
> + struct StandardTimingIdentification STI[8];
> +/* Detailed Timing Descriptions / Monitor Descriptions */
> + union DTD_MD dtd_md[4];
> + uint8_t ExtensionFlag;
> + uint8_t Checksum;
> +} EDID_PACKED_ATTRIBUTE;
> +
> +EDID_INLINE_ROUTINE uint16_t edid1_RedX (struct edid1 *edid) {
> + return (edid->RedXHigh<<2) | (edid->GreenRedLow>>6);
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_RedY (struct edid1 *edid) {
> + return (edid->RedYHigh<<2) | (edid->GreenRedLow>>4)&&0x3;
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_GreenX (struct edid1 *edid) {
> + return (edid->GreenXHigh<<2) | (edid->GreenRedLow>>2)&&0x3;
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_GreenY (struct edid1 *edid) {
> + return (edid->GreenYHigh<<2) | (edid->GreenRedLow&0x3);
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_BlueX (struct edid1 *edid) {
> + return (edid->BlueXHigh<<2) | (edid->WhiteBlueLow>>6);
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_BlueY (struct edid1 *edid) {
> + return (edid->BlueYHigh<<2) | (edid->WhiteBlueLow>>4)&&0x3;
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_WhiteX (struct edid1 *edid) {
> + return (edid->WhiteXHigh<<2) | (edid->WhiteBlueLow>>2)&&0x3;
> +}
> +EDID_INLINE_ROUTINE uint16_t edid1_WhiteY (struct edid1 *edid) {
> + return (edid->WhiteYHigh<<2) | (edid->WhiteBlueLow&0x3);
> +}
> +
> +enum edid1_EstablishedTimings {
> +/* Established Timings I */
> + EST_800x600_60Hz = 0,
> + EST_800x600_56Hz = 1,
> + EST_640x480_75Hz = 2,
> + EST_640x480_72Hz = 3,
> + EST_640x480_67Hz = 4,
> + EST_640x480_60Hz = 5,
> + EST_720x400_88Hz = 6,
> + EST_720x400_70Hz = 7,
> +/* Established Timings II */
> + EST_1280x1024_75Hz = 8,
> + EST_1024x768_75Hz = 9,
> + EST_1024x768_70Hz = 10,
> + EST_1024x768_60Hz = 11,
> + EST_1024x768_87Hz = 12,
> + EST_832x624_75Hz = 13,
> + EST_800x600_75Hz = 14,
> + EST_800x600_72Hz = 15,
> +/* Manufacturer's Timings */
> + EST_1152x870_75Hz = 23,
> +};
> +
> +EDID_INLINE_ROUTINE uint8_t edid1_EstablishedTim (
> + struct edid1 *edid,
> + enum edid1_EstablishedTimings est)
> +{
> + return (uint8_t)(edid->EST_I_II_Man[est/8] & (est%8));
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif /* __cplusplus */
> +
> +#endif /* ASM */
> +
> +#endif /* _VBE_H */
> diff --git a/c/src/lib/libbsp/i386/pc386/include/vbe3.h b/c/src/lib/libbsp/i386/pc386/include/vbe3.h
> new file mode 100644
> index 0000000..2bf1b59
> --- /dev/null
> +++ b/c/src/lib/libbsp/i386/pc386/include/vbe3.h
> @@ -0,0 +1,463 @@
> +/**
> + * @file vbe3.h
> + *
> + * @ingroup i386_pc386
> + *
> + * @brief VESA Bios Extension definitions.
> + */
> +
> +/*
> + * vbe3.h - This file contains definitions for constants related to VBE.
> + * More information can be found at
> + * <http://www.vesa.org/vesa-standards/free-standards/>
> + * VESA public standards may be found at
> + * <http://www.vesa.org/wp-content/uploads/2010/12/thankspublic.htm>
> + *
Again.
> + * Copyright (C) 2014 Jan Doležal (dolezj21 at fel.cvut.cz)
> + * CTU in Prague.
> + *
> + * The license and distribution terms for this file may be
> + * found in the file LICENSE in this distribution or at
> + * http://www.rtems.org/license/LICENSE.
> + */
> +
> +#ifndef _VBE_H
> +#define _VBE_H
> +
> +#ifndef ASM /* ASM */
> +
> +#include <stdint.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif /* __cplusplus */
> +
> +#include <rtems/score/basedefs.h>
> +#define VBE3_PACKED_ATTRIBUTE RTEMS_COMPILER_PACKED_ATTRIBUTE
> +
> +/* VESA BIOS EXTENSION (VBE) Core functions Standard
> + Version: 3.0 Date: September 16, 1998 */
> +
> +/* VBE RETURN STATUS */
> +/* AL == 4Fh: Function is supported */
> +/* AL != 4Fh: Function is not supported */
> +#define VBE_functionSupported 0x4F
> +/* AH == 00h: Function call successful */
> +#define VBE_callSuccessful 0x00
> +/* AH == 01h: Function call failed */
> +#define VBE_callFailed 0x01
> +/* AH == 02h: Function is not supported in the current hardware configuration */
> +#define VBE_notSupportedInCurHWConf 0x02
> +/* AH == 03h: Function call invalid in current video mode */
> +#define VBE_callInvalid 0x03
> +
> +/* VBE Mode Numbers */
> +/* D0-D8 = Mode number */
> +#define VBE_modeNumberMask 0x01FF
> +#define VBE_modeNumberShift 0x00
> +/* If D8 == 0, this is not a VESA defined VBE mode */
> +#define VBE_VESAmodeMask 0x0100
> +/* If D8 == 1, this is a VESA defined VBE mode */
> +/* D9-D12 = Reserved by VESA for future expansion (= 0) */
> +#define VBE_VESAmodeShift 0x08
> +/* If D11 == 0, Use current BIOS default refresh rate */
> +#define VBE_refreshRateCtrlMask 0x0800
> +/* If D11 == 1, Use user specified CRTC values for refresh rate */
> +/* D12-13 = Reserved for VBE/AF (must be 0) */
> +#define VBE_refreshRateCtrlShift 0x0B
> +/* If D14 == 0, Use Banked/Windowed Frame Buffer */
> +#define VBE_linearFlatFrameBufMask 0x4000
> +/* If D14 == 1, Use Linear/Flat Frame Buffer */
> +#define VBE_linearFlatFrameBufShift 0x0E
> +/* If D15 == 0, Clear display memory */
> +#define VBE_preserveDispMemMask 0x8000
> +/* If D15 == 1, Preserve display memory */
> +#define VBE_preserveDispMemShift 0x0F
> +
> +/* Graphics modes */
> +/* 15-bit mode, Resolution: 640x400, Colors: 256 */
> +#define VBE_R640x400C256 0x100
> +/* 15-bit mode, Resolution: 640x480, Colors: 256 */
> +#define VBE_R640x480C256 0x101
> +/* 15-bit mode, Resolution: 800x600, Colors: 16 */
> +#define VBE_R800x600C16 0x102
> +/* 7-bit mode, Resolution: 800x600, Colors: 16 */
> +#define VBE_b7R800x600C16 0x6A
> +/* 15-bit mode, Resolution: 800x600, Colors: 256 */
> +#define VBE_R800x600C256 0x103
> +/* 15-bit mode, Resolution: 1024x768, Colors: 16 */
> +#define VBE_R1024x768C16 0x104
> +/* 15-bit mode, Resolution: 1024x768, Colors: 256 */
> +#define VBE_R1024x768C256 0x105
> +/* 15-bit mode, Resolution: 1280x1024, Colors: 16 */
> +#define VBE_R1280x1024C16 0x106
> +/* 15-bit mode, Resolution: 1280x1024, Colors: 256 */
> +#define VBE_R1280x1024C256 0x107
> +/* 15-bit mode, Resolution: 320x200, Colors: 32K (1:5:5:5) */
> +#define VBE_R320x200C32K 0x10D
> +/* 15-bit mode, Resolution: 320x200, Colors: 64K (5:6:5) */
> +#define VBE_R320x200C64K 0x10E
> +/* 15-bit mode, Resolution: 320x200, Colors: 16.8M (8:8:8) */
> +#define VBE_R320x200C17M 0x10F
> +/* 15-bit mode, Resolution: 640x480, Colors: 32K (1:5:5:5) */
> +#define VBE_R640x480C32K 0x110
> +/* 15-bit mode, Resolution: 640x480, Colors: 64K (5:6:5) */
> +#define VBE_R640x480C64K 0x111
> +/* 15-bit mode, Resolution: 640x480, Colors: 16.8M (8:8:8) */
> +#define VBE_R640x480C17M 0x112
> +/* 15-bit mode, Resolution: 800x600, Colors: 32K (1:5:5:5) */
> +#define VBE_R800x600C32K 0x113
> +/* 15-bit mode, Resolution: 800x600, Colors: 64K (5:6:5) */
> +#define VBE_R800x600C64K 0x114
> +/* 15-bit mode, Resolution: 800x600, Colors: 16.8M (8:8:8) */
> +#define VBE_R800x600C17M 0x115
> +/* 15-bit mode, Resolution: 1024x768, Colors: 32K (1:5:5:5) */
> +#define VBE_R1024x768C32K 0x116
> +/* 15-bit mode, Resolution: 1024x768, Colors: 64K (5:6:5) */
> +#define VBE_R1024x768C64K 0x117
> +/* 15-bit mode, Resolution: 1024x768, Colors: 16.8M (8:8:8) */
> +#define VBE_R1024x768C17M 0x118
> +/* 15-bit mode, Resolution: 1280x1024, Colors: 32K (1:5:5:5) */
> +#define VBE_R1280x1024C32K 0x119
> +/* 15-bit mode, Resolution: 1280x1024, Colors: 64K (5:6:5) */
> +#define VBE_R1280x1024C64K 0x11A
> +/* 15-bit mode, Resolution: 1280x1024, Colors: 16.8M (8:8:8) */
> +#define VBE_R1280x1024C17M 0x11B
> +#define VBE_SpecialMode 0x81FF
> +
> +/* Text modes */
> +#define VBE_C80R60 0x108 /* 15-bit mode, Columns: 80, Rows: 60 */
> +#define VBE_C132R25 0x109 /* 15-bit mode, Columns: 132, Rows: 25 */
> +#define VBE_C132R43 0x10A /* 15-bit mode, Columns: 132, Rows: 43 */
> +#define VBE_C132R50 0x10B /* 15-bit mode, Columns: 132, Rows: 50 */
> +#define VBE_C132R60 0x10C /* 15-bit mode, Columns: 132, Rows: 60 */
> +
> +/* VBE function numbers - passed in AX register */
> +#define VBE_RetVBEConInf 0x4F00 /* Return VBE Controller Information */
> +#define VBE_RetVBEModInf 0x4F01 /* Return VBE Mode Information */
> +#define VBE_SetVBEMod 0x4F02 /* Set VBE Mode */
> +#define VBE_RetCurVBEMod 0x4F03 /* Return Current VBE Mode */
> +#define VBE_SavResSta 0x4F04 /* Save/Restore State */
> +#define VBE_DisWinCon 0x4F05 /* Display Window Control */
> +#define VBE_SetGetLogScaLinLen 0x4F06 /* Set/Get Logical Scan Line Length */
> +#define VBE_SetGetDisSta 0x4F07 /* Set/Get Display Start */
> +#define VBE_SetGetDACPalFor 0x4F08 /* Set/Get DAC Palette Format */
> +#define VBE_SetGetPalDat 0x4F09 /* Set/Get Palette Data */
> +#define VBE_RetVBEProModInt 0x4F0A /* Return VBE Protected Mode Interface */
> +#define VBE_GetSetpixclo 0x4F0B /* Get/Set pixel clock */
> +#define VBE_PowManExt 0x4F10 /* Power Management Extensions (PM) */
> +#define VBE_FlaPanIntExt 0x4F11 /* Flat Panel Interface Extensions (FP) */
> +#define VBE_AudIntExt 0x4F13 /* Audio Interface Extensions (AI) */
> +#define VBE_OEMExt 0x4F14 /* OEM Extensions */
> +#define VBE_DisDatCha 0x4F15 /* Display Data Channel (DDC),
> + Serial Control Interface (SCI) */
> +
> +/* VBE subfunction numbers - passed in BL register */
> +#define VBE_RetVBESupSpeInf 0x00 /* Return VBE Supplemental
> + Specification Information */
> +/* *** Structures *** */
> +struct VBE_FarPtr {
> + uint16_t offset;
> + uint16_t selector;
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +struct VBE_PMInfoBlock {
> + uint8_t Signature[4]; /* PM Info Block Signature */
> + uint16_t EntryPoint; /* Offset of PM entry point within BIOS */
> + uint16_t PMInitialize; /* Offset of PM initialization entry point */
> + uint16_t BIOSDataSel; /* Selector to BIOS data area emulation block */
> + uint16_t A0000Sel; /* Selector to access A0000h physical mem */
> + uint16_t B0000Sel; /* Selector to access B0000h physical mem */
> + uint16_t B8000Sel; /* Selector to access B8000h physical mem */
> + uint16_t CodeSegSel; /* Selector to access code segment as data */
> + uint8_t InProtectMode; /* Set to 1 when in protected mode */
> + uint8_t Checksum; /* Checksum byte for structure */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +/* General VBE signature */
> +#define VBE_SIGNATURE "VESA"
> +/* Signature for VBE 2.0 and higher */
> +#define VBE20plus_SIGNATURE "VBE2"
> +/* for STUB see VBE CORE FUNCTIONS VERSION 3.0 - Appendix 1 */
> +#define VBE_END_OF_VideoModeList 0xFFFF
> +#define VBE_STUB_VideoModeList 0xFFFF
> +struct VBE_VbeInfoBlock {
> + uint8_t VbeSignature[4]; /* VBE Signature */
> + uint16_t VbeVersion; /* VBE Version */
> + uint8_t *OemStringPtr; /* VbeFarPtr to OEM String */
> + uint8_t Capabilities[4]; /* Capabilities of graphics controller */
> + uint32_t *VideoModePtr; /* VbeFarPtr to VideoModeList */
> + uint16_t TotalMemory; /* Number of 64kb memory blocks */
> + /* Added for VBE 2.0+ */
> + uint16_t OemSoftwareRev; /* VBE implementation Software revision */
> + uint8_t *OemVendorNamePtr; /* VbeFarPtr to Vendor Name String */
> + uint8_t *OemProductNamePtr; /* VbeFarPtr to Product Name String */
> + uint8_t *OemProductRevPtr; /* VbeFarPtr to Product Revision String */
> + uint8_t Reserved[222]; /* Reserved for VBE implementation scratch */
> + /* area */
> + uint8_t OemData[256]; /* Data Area for OEM Strings */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +struct VBE_ModeInfoBlock {
> + /* Mandatory information for all VBE revisions */
> + uint16_t ModeAttributes; /* mode attributes */
> + uint8_t WinAAttributes; /* window A attributes */
> + uint8_t WinBAttributes; /* window B attributes */
> + uint16_t WinGranularity; /* window granularity */
> + uint16_t WinSize; /* window size */
> + uint16_t WinASegment; /* window A start segment */
> + uint16_t WinBSegment; /* window B start segment */
> + uint32_t *WinFuncPtr; /* real mode pointer to window function */
> + uint16_t BytesPerScanLine; /* bytes per scan line */
> + /* Mandatory information for VBE 1.2 and above */
> + uint16_t XResolution; /* horizontal resolution in px or chars */
> + uint16_t YResolution; /* vertical resolution in px or chars */
> + uint8_t XCharSize; /* character cell width in pixels */
> + uint8_t YCharSize; /* character cell height in pixels */
> + uint8_t NumberOfPlanes; /* number of memory planes */
> + uint8_t BitsPerPixel; /* bits per pixel */
> + uint8_t NumberOfBanks; /* number of banks */
> + uint8_t MemoryModel; /* memory model type */
> + uint8_t BankSize; /* bank size in KB */
> + uint8_t NumberOfImagePages; /* number of images */
> + uint8_t Reserved0; /* reserved for page function */
> + /* Direct Color fields (required for direct/6 and YUV/7 memory models) */
> + uint8_t RedMaskSize; /* size of direct color red mask in bits */
> + uint8_t RedFieldPosition; /* bit position of lsb of red mask */
> + uint8_t GreenMaskSize; /* size of direct color green mask in b */
> + uint8_t GreenFieldPosition; /* bit position of lsb of green mask */
> + uint8_t BlueMaskSize; /* size of direct color blue mask in b */
> + uint8_t BlueFieldPosition; /* bit position of lsb of blue mask */
> + uint8_t RsvdMaskSize; /* size of direct color reserved mask */
> + uint8_t RsvdFieldPosition; /* bit position of lsb of reserved mask */
> + uint8_t DirectColorModeInfo; /* direct color mode attributes */
> + /* Mandatory information for VBE 2.0 and above */
> + uint32_t *PhysBasePtr; /* physical address for
> + flat memory frame buffer */
> + uint32_t Reserved1; /* Reserved - always set to 0 */
> + uint16_t Reserved2; /* Reserved - always set to 0 */
> + /* Mandatory information for VBE 3.0 and above */
> + uint16_t LinBytesPerScanLine; /* bytes per scan line for linear modes */
> + uint8_t BnkNumberOfImagePages; /* number of images for banked modes */
> + uint8_t LinNumberOfImagePages; /* number of images for linear modes */
> + /* linear modes */
> + uint8_t LinRedMaskSize; /* size of direct color red mask */
> + uint8_t LinRedFieldPosition; /* bit position of lsb of red mask */
> + uint8_t LinGreenMaskSize; /* size of direct color green mask */
> + uint8_t LinGreenFieldPosition; /* bit position of lsb of green mask */
> + uint8_t LinBlueMaskSize; /* size of direct color blue mask */
> + uint8_t LinBlueFieldPosition; /* bit position of lsb of blue mask */
> + uint8_t LinRsvdMaskSize; /* size of direct color reserved mask */
> + uint8_t LinRsvdFieldPosition; /* bit position of lsb of reserved mask */
> + uint32_t MaxPixelClock; /* maximum pixel clock
> + (in Hz) for graphics mode */
> + uint8_t Reserved3[189]; /* remainder of ModeInfoBlock */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +struct VBE_CRTCInfoBlock {
> + uint16_t HorizontalTotal; /* Horizontal total in pixels */
> + uint16_t HorizontalSyncStart; /* Horizontal sync start in pixels */
> + uint16_t HorizontalSyncEnd; /* Horizontal sync end in pixels */
> + uint16_t VerticalTotal; /* Vertical total in lines */
> + uint16_t VerticalSyncStart; /* Vertical sync start in lines */
> + uint16_t VerticalSyncEnd; /* Vertical sync end in lines */
> + uint8_t Flags; /* Flags (Interlaced, Double Scan etc) */
> + uint32_t PixelClock; /* Pixel clock in units of Hz */
> + uint16_t RefreshRate; /* Refresh rate in units of 0.01 Hz */
> + uint8_t Reserved[40]; /* remainder of ModeInfoBlock */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +struct VBE_PaletteEntry {
> + uint8_t Blue; /* Blue channel value (6 or 8 bits) */
> + uint8_t Green; /* Green channel value (6 or 8 bits) */
> + uint8_t Red; /* Red channel value(6 or 8 bits) */
> + uint8_t Alignment; /* DWORD alignment byte (unused) */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +struct VBE_SupVbeInfoBlock {
> + uint8_t SupVbeSignature[7]; /* Supplemental VBE Signature */
> + uint16_t SupVbeVersion; /* Supplemental VBE Version */
> + uint8_t SupVbeSubFunc[8]; /* Bitfield of supported subfunctions */
> + uint16_t OemSoftwareRev; /* OEM Software revision */
> + uint8_t *OemVendorNamePtr; /* VbeFarPtr to Vendor Name String */
> + uint8_t *OemProductNamePtr; /* VbeFarPtr to Product Name String */
> + uint8_t *OemProductRevPtr; /* VbeFarPtr to Product Revision String */
> + uint8_t *OemStringPtr; /* VbeFarPtr to OEM String */
> + uint8_t Reserved[221]; /* Reserved for description
> + strings and future */
> + /* expansion */
> +} VBE3_PACKED_ATTRIBUTE;
> +
> +/* VbeInfoBlock Capabilities */
> +/* D0 = 0 DAC is fixed width, with 6 bits per primary color */
> +/* = 1 DAC width is switchable to 8 bits per primary color */
> +#define VBE_DACswitchableMask 0x0001
> +/* D1 = 0 Controller is VGA compatible */
> +/* = 1 Controller is not VGA compatible */
> +#define VBE_notVGAcompatibleMask 0x0002
> +/* D2 = 0 Normal RAMDAC operation */
> +/* = 1 When programming large blocks of information to the RAMDAC,
> + use the blank bit in Function 09h. */
> +#define VBE_specialRAMDACopMask 0x0004
> +/* D3 = 0 No hardware stereoscopic signaling support */
> +/* = 1 Hardware stereoscopic signaling supported by controller */
> +#define VBE_hwStereoscopicMask 0x0008
> +/* D4 = 0 Stereo signaling supported via external VESA stereo connector */
> +/* = 1 Stereo signaling supported via VESA EVC connector */
> +#define VBE_supportEVCconnMask 0x0010
> +/* D5-31 = Reserved */
> +
> +/* ModeInfoBlock ModeAttributes */
> +/* D0 = Mode supported by hardware configuration */
> +/* 0 = Mode not supported in hardware */
> +/* 1 = Mode supported in hardware */
> +#define VBE_modSupInHWMask 0x0001
> +/* D1 = 1 (Reserved) */
> +/* D2 = TTY Output functions supported by BIOS */
> +/* 0 = TTY Output functions not supported by BIOS */
> +/* 1 = TTY Output functions supported by BIOS */
> +#define VBE_TTYOutSupByBIOSMask 0x0004
> +/* D3 = Monochrome/color mode (see note below) */
> +/* 0 = Monochrome mode */
> +/* 1 = Color mode */
> +#define VBE_ColorModeMask 0x0008
> +/* D4 = Mode type */
> +/* 0 = Text mode */
> +/* 1 = Graphics mode */
> +#define VBE_GraphicsModeMask 0x0010
> +/* D5 = VGA compatible mode */
> +/* 0 = Yes */
> +/* 1 = No */
> +#define VBE_VGACompModeMask 0x0020
> +/* D6 = VGA compatible windowed memory mode is available */
> +/* 0 = Yes */
> +/* 1 = No */
> +#define VBE_VGACompWinMemModeMask 0x0040
> +/* D7 = Linear frame buffer mode is available */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_LinFraBufModeAvaiMask 0x0080
> +/* D8 = Double scan mode is available */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_DblScnModeAvaiMask 0x0100
> +/* D9 = Interlaced mode is available */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_InterlModeAvaiMask 0x0200
> +/* D10 = Hardware triple buffering support */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_HWTripBufSupMask 0x0400
> +/* D11 = Hardware stereoscopic display support */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_HWSterDispSupMask 0x0800
> +/* D12 = Dual display start address support */
> +/* 0 = No */
> +/* 1 = Yes */
> +#define VBE_DualDispStAdrSupMask 0x1000
> +/* D13-D15 = Reserved */
> +
> +/* ModeInfoBlock WinXAttributes */
> +/* D0 = Relocatable window(s) supported */
> +/* 0 = Single non-relocatable window only */
> +/* 1 = Relocatable window(s) are supported */
> +#define VBE_RelocWinSupMask 0x01
> +/* D1 = Window readable */
> +/* 0 = Window is not readable */
> +/* 1 = Window is readable */
> +#define VBE_WinReadableMask 0x02
> +/* D2 = Window writeable */
> +/* 0 = Window is not writeable */
> +/* 1 = Window is writeable */
> +#define VBE_WinWritableMask 0x04
> +/* D3-D7 = Reserved */
> +
> +/* ModeInfoBlock MemoryModel */
> +#define VBE_TextMode 0x00
> +#define VBE_CGAGraphics 0x01
> +#define VBE_HerculesGraphics 0x02
> +#define VBE_Planar 0x03
> +#define VBE_PackedPixel 0x04
> +#define VBE_NonChain4Color256 0x05
> +#define VBE_DirectColor 0x06
> +#define VBE_YUV 0x07
> + /* 0x08-0x0F Reserved, to be defined by VESA */
> + /* 0x10-0xFF To be defined by OEM */
> +
> +/* ModeInfoBlock DirectColorModeInfo */
> +/* D0 = Color ramp is fixed/programmable */
> +/* 0 = Color ramp is fixed */
> +/* 1 = Color ramp is programmable */
> +#define VBE_ColRampProgMask 0x01
> +/* D1 = Bits in Rsvd field are usable/reserved */
> +/* 0 = Bits in Rsvd field are reserved */
> +/* 1 = Bits in Rsvd field are usable by the application */
> +#define VBE_RsvdBitsUsableMask 0x02
> +
> +/* CRTCInfoBlock Flags */
> +/* D0 = Double Scan Mode Enable */
> +/* 0 = Graphics mode is not double scanned */
> +/* 1 = Graphics mode is double scanned */
> +#define VBE_GrModeDblScanMask 0x01
> +/* D1 = Interlaced Mode Enable */
> +/* 0 = Graphics mode is non-interlaced */
> +/* 1 = Graphics mode is interlaced */
> +#define VBE_GrModeInterlMask 0x02
> +/* D2 = Horizontal sync polarity */
> +/* 0 = Horizontal sync polarity is positive (+) */
> +/* 1 = Horizontal sync polarity is negative (-) */
> +#define VBE_HorSncPolNegMask 0x04
> +/* D3 = Vertical sync polarity */
> +/* 0 = Vertical sync polarity is positive (+) */
> +/* 1 = Vertical sync polarity is negative (-) */
> +#define VBE_VerSncPolNegMask 0x08
> +
> +
> +/* VESA BIOS Extensions/Display Data Channel Standard
> + Version: 1.1 November 18, 1999 */
> +
> +/* VBE/DDC subfunction numbers - passed in BL register */
> +#define VBEDDC_Capabilities 0x0 /* Report VBE/DDC Capabilities */
> +#define VBEDDC_ReadEDID 0x1 /* Read EDID */
> +
> +/* DDC Capabilities */
> +/* DDC level supported - returned in BL register */
> +/* 0 - DDC1 not supported; 1 - DDC1 supported */
> +#define VBEDDC_1SupportedMask 0x1
> +/* 0 - DDC2 not supported; 1 - DDC2 supported */
> +#define VBEDDC_2SupportedMask 0x2
> +/* 0 - Screen not blanked during data transfer;
> + 1 - Screen blanked during data transfer */
> +#define VBEDDC_scrBlnkDatTrMs 0x4
> +
> +
> +/* VESA BIOS Extensions/Serial Control Interface Standard
> + Version: 1.0 Revision: 2 Date: July 2, 1997 */
> +
> +/* VBE/SCI subfunction numbers - passed in BL register */
> +#define VBESCI_ReportCapabil 0x10 /* Report VBE/SCI Capabilities */
> +#define VBESCI_BegSCLSDACtrl 0x11 /* Begin SCL/SDA control */
> +#define VBESCI_EndSCLSDACtrl 0x12 /* End SCL/SDA control */
> +#define VBESCI_WrtSCLClkLine 0x13 /* Write SCL clock line */
> +#define VBESCI_WrtSDADatLine 0x14 /* Write SDA data line */
> +#define VBESCI_RdySCLClkLine 0x15 /* Read SCL clock line */
> +#define VBESCI_RdySDADatLine 0x16 /* Read SDA data line */
> +
> +/* SCI Capabilities */
> +/* I2C level supported - returned in BL register */
> +#define VBESCI_capSCLwrtMask 0x1 /* Can write to SCL clock line */
> +#define VBESCI_capSDAwrtMask 0x2 /* Can write to SDA data line */
> +#define VBESCI_capSCLrdyMask 0x4 /* Can read from SCL clock line */
> +#define VBESCI_capSDArdyMask 0x8 /* Can read from SDA data line */
> +
> +
> +#ifdef __cplusplus
> +}
> +#endif /* __cplusplus */
> +
> +#endif /* ASM */
> +
> +#endif /* _VBE_H */
> +
> diff --git a/c/src/lib/libbsp/i386/pc386/preinstall.am b/c/src/lib/libbsp/i386/pc386/preinstall.am
> index 4314f22..b4ac86b 100644
> --- a/c/src/lib/libbsp/i386/pc386/preinstall.am
> +++ b/c/src/lib/libbsp/i386/pc386/preinstall.am
> @@ -147,6 +147,14 @@ $(PROJECT_INCLUDE)/i386_io.h: ../../i386/shared/comm/i386_io.h $(PROJECT_INCLUDE
> $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/i386_io.h
> PREINSTALL_FILES += $(PROJECT_INCLUDE)/i386_io.h
>
> +$(PROJECT_INCLUDE)/bsp/vbe3.h: include/vbe3.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vbe3.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vbe3.h
> +
> +$(PROJECT_INCLUDE)/edid.h: include/edid.h $(PROJECT_INCLUDE)/$(dirstamp)
> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/edid.h
> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/edid.h
> +
> $(PROJECT_INCLUDE)/pcibios.h: ../../i386/shared/pci/pcibios.h $(PROJECT_INCLUDE)/$(dirstamp)
> $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pcibios.h
> PREINSTALL_FILES += $(PROJECT_INCLUDE)/pcibios.h
> --
> 1.9.1
>
>
> _______________________________________________
> devel mailing list
> devel at rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
--
Joel Sherrill, Ph.D. Director of Research & Development
joel.sherrill at OARcorp.com On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
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