Cortex-M0 BPS creation

[Sebastian Huber]

On 22/09/14 13:25, Pavel Pisa wrote:
> Hello Sebastian and Oleg,
>
> On Monday 22 of September 2014 07:35:38 Sebastian Huber wrote:
>> >On 22/09/14 06:36, Мороз Олег wrote:
>>> > >      Hello everyone. i'm new to  BSP development.  We have a project
>>> > >which is uses some kind of cortex-m0 microcontroller. As i understand
>>> > >it's armv6-m family. Is this CPU family is supported by rtems? I'm
>>> > >reading the book called "BSP and device driver development guide"  and it
>>> > >says look at
>>> > >"cpukit/score/cpu/CPU". This directory contains only armv7-m and armv4
>>> > >files. Is it correct?
>> >
>> >The armv7-m support will probably work also for a Cortex-M0.
> I think that M3 context switch would be mostly OK.
> Exception and interrupts model is the same as for M3,
> but I have feeling that there exists option to
> use some simplified one - but it can be for M1.
> But you need to use M0 specific GCC options.
> We use GCC for nRF51 Cortex-M0 with next options
>
>    arm-none-eabi-gcc -mcpu=cortex-m0 -mthumb --std=gnu99 -Wall -mfloat-abi=soft
>
> Else GCC can use Thumb2 instructions which are not supporeted
> by ARMv6-m. For example Thumb instructions CBZ, CBNZ, IT
> emitted by GCC for M3 are not supported by M0.
>
> So toolchain rebuild is required for sure.

We already have a multilib for Cortex-M0

/opt/rtems-4.11/arm-rtems4.11/lib/thumb/armv6-m/libc.a

I didn't work with a Cortex-M0 so far, so maybe we have to adjust this.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.