Multi-Processor communication options ?

[Cudmore, Alan P. (GSFC-5820)]

We are developing a processor card that has two CPUs on a board with
either a shared memory or FIFO interface between them. Either interface
will have the ability to interrupt the CPU upon receipt of data.

Is either one more suitable for the RTEMS Multi-Processor interface?

Are there any problems or inefficiencies with the MP interface on
SPARC/LEON3? One of the CPUs will be dual core.

Is there a BSP with an example of a Multi-Processor interface
implementation?

Thanks,
Alan