Pi2 Mailbox IRQs was Re: Fwd: SMP support for Raspberry Pi 2
Cudmore, Alan P. (GSFC-5820)
alan.p.cudmore at nasa.gov
Mon Aug 17 15:23:31 UTC 2015
Joel and Rohini,
I will have to take some time to catch up.. I apologize that I have not
been able to keep up with the Raspberry Pi work lately, I have just been
too busy with my work projects. ( which is usually a good thing :)
Alan
On 8/15/15, 5:37 PM, "Joel Sherrill" <joel.sherrill at oarcorp.com> wrote:
>Alan .. can you confirm what I am interpreting?
>
>On 08/15/2015 02:56 PM, Rohini Kulkarni wrote:
>>
>>
>> On Sun, Aug 16, 2015 at 1:13 AM, Joel Sherrill
>> <joel.sherrill at oarcorp.com <mailto:joel.sherrill at oarcorp.com>> wrote:
>>
>> On 08/15/2015 02:35 PM, Rohini Kulkarni wrote:
>>
>> Hi
>>
>> I need some help with this. I am unable to figure out yet how
>> to add an interrupt for the mailbox and determine interrupt
>> number to be associated with it.
>>
>> If you can enable it and cause it, the fault handler will be one
>> way to do it :)
>>
>> Can you tell from the documentation which pin(s) on the interrupt
>> controller
>> is associated with the mailbox?
>>
>> FWIW I don't even know what documentation to look at for the SoC to
>> find this. If you point me to it, I will see what I can find.
>>
>>
>> This
>>
>><https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/Q
>>A7_rev3.4.pdf>
>> is the only official document which seems to be available. The Cortex
>> A7 mpcore document didn't help here.
>
>Putitng this back on the devel list.
>
>Page 16 of that PDF (4.10) follows up on a previous section. There
>are sixteen mailboxes. Each core has four associated with it. In
>4.10, there is a list of per-core interrupt sources. There are four
>addresses for core specific interrupt source registers.
>
>It looks like the interrupts are numerically next to the GPU interrupt.
>
>This much looks fairly straight-forward. Pick a mailbox to dedicate
>to interprocessor-interrupts. If you pick Bit 7 (mailbox 3), I would
>expect
>it to be one logical interrupt lower than the GPU interrupt source.
>Check the irq list for the BSP. This should be in a .h file.
>
>You will install one SMP IRQ handler. But based on the core number it
>is running on, you will have to do slightly different things to clear it
>(I think) since the interrupt registers are duplicated per core.
>
>
>>
>> Thanks.
>>
>> On Sat, Aug 15, 2015 at 10:52 PM, Rohini Kulkarni
>> <krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>>
>> wrote:
>>
>>
>>
>> On Wed, Aug 12, 2015 at 1:29 AM, Joel Sherrill
>> <joel.sherrill at oarcorp.com <mailto:joel.sherrill at oarcorp.com>
>> <mailto:joel.sherrill at oarcorp.com
>> <mailto:joel.sherrill at oarcorp.com>>> wrote:
>>
>>
>>
>> On 8/11/2015 2:06 PM, Rohini Kulkarni wrote:
>>
>> Hi,
>>
>> I would have to register the related mailbox
>> interrupt and
>> associate it with a handler that should be same as
>> _SMP_Inter_processor_interrupt_handler(). Am I
>>right?
>>
>>
>> That sounds correct.
>>
>> From where can I get a reference of how to do this?
>>
>>
>> I would look at the Xilinx code that registers
>> interrupts. The API
>> should be the same. Also the clock driver, etc. The
>> actual handler
>> and IRQ number will vary.
>>
>>
>> How do I determine the interrupt number?
>> I could fine the IPi handler being installed here in
>> arm-a9mpcore-smp.c
>>
>> rtems_interrupt_handler_install(
>> ARM_GIC_IRQ_SGI_0,
>> "IPI",
>> RTEMS_INTERRUPT_UNIQUE,
>> bsp_inter_processor_interrupt,
>> NULL
>> );
>>
>>
>> On 11 Aug 2015 00:41, "Joel Sherrill"
>> <joel.sherrill at oarcorp.com <mailto:joel.sherrill at oarcorp.com>
>> <mailto:joel.sherrill at oarcorp.com
>> <mailto:joel.sherrill at oarcorp.com>>
>> <mailto:joel.sherrill at oarcorp.com
>> <mailto:joel.sherrill at oarcorp.com>
>>
>> <mailto:joel.sherrill at oarcorp.com
>> <mailto:joel.sherrill at oarcorp.com>>>> wrote:
>>
>> The source for the CPU supplement is in
>> doc/cpu_supplement in
>> the RTEMS tree.
>>
>> I do not know when the latest online was built
>>so
>> reading it
>> there is probably safest.
>>
>> To build it, you will likely have to install
>>some
>> texinfo and
>> texlive tools.
>>
>> cd $r/doc
>> ../bootstrap
>> cd ../..
>> mkdir b-doc
>> cd b-doc
>> $r/doc/configure --enable-maintainer-mode \
>> --prefix=DIRECTORY
>> make
>> make install
>>
>> That should be similar to how it is built.
>>
>> --joel
>>
>>
>> On 8/10/2015 1:35 PM, Rohini Kulkarni wrote:
>>
>> The documentation that Sebastian was
>> referring to.
>>
>> On Tue, Jul 28, 2015 at 12:24 PM,
>> Sebastian Huber
>> <sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>> wrote:
>>
>> Hello Rohini,
>>
>> please use the devel list.
>>
>> On 28/07/15 07:41, Rohini Kulkarni
>>wrote:
>>
>> Hi,
>>
>> I wish to understand where the
>> interprocessor interrupts are used during the boot
>> process. During final initialization of SMP I can
>>see
>>
>> rtems_interrupt_handler_install(
>> ARM_GIC_IRQ_SGI_0,
>> "IPI",
>> RTEMS_INTERRUPT_UNIQUE,
>>
>>bsp_inter_processor_interrupt,
>> NULL
>> );
>>
>> Raspberry Pi 2 does not have the
>> generic
>> interrupt controller. Interrupt routing will have
>> to be
>> handled differently. So I wish to understand how/
>> where it
>> is used. I suppose this might be the problem.
>>
>>
>> Sorry, that the documentation is so
>> scattered. I think we should move everything into
>> the CPU
>> Architecture Supplement. It would be nice if you
>> can help
>> to improve the documentation since you have a
>> different
>> view point.
>>
>> What is the CPU Architecture Supplement?
>>
>>
>> You must install the IPI during the
>> system
>> initialization. It is raised via the
>> _CPU_SMP_Send_interrupt() function, for an example
>>see
>> arm-a9mpcore-smp.c.
>>
>>
>>
>> Thanks.
>>
>> On Wed, Jul 22, 2015 at 7:08 PM,
>> Rohini
>> Kulkarni <krohini1593 at gmail.com
>> <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>>
>> <mailto:krohini1593 at gmail.com <mailto:krohini1593 at gmail.com>
>> <mailto:krohini1593 at gmail.com
>> <mailto:krohini1593 at gmail.com>>>>>> wrote:
>>
>> Ok. Qemu suggestion seems
>> helpful
>> for the cache configuration
>> issue though. I am trying
>> with Pi 1.
>>
>> Thanks.
>>
>> On 22 Jul 2015 18:59,
>> "Sebastian Huber"
>> <sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>>> wrote:
>>
>> Sorry, I cannot help you
>> here
>> since I never worked with a
>> Raspberry Pi.
>>
>> -- Sebastian
>>Huber,
>> embedded brains GmbH
>>
>> Address : Dornierstr. 4,
>> D-82178
>> Puchheim, Germany
>> Phone : +49 89 189 47
>> 41-16
>> Fax : +49 89 189 47
>> 41-09
>> E-Mail :
>> sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>>
>> PGP : Public key
>> available
>> on request.
>>
>> Diese Nachricht ist keine
>> geschäftliche Mitteilung im Sinne
>> des EHUG.
>>
>>
>>
>>
>> --
>> Rohini Kulkarni
>>
>>
>> --
>> Sebastian Huber, embedded brains GmbH
>>
>> Address : Dornierstr. 4, D-82178
>> Puchheim,
>> Germany
>> Phone : +49 89 189 47 41-16
>> Fax : +49 89 189 47 41-09
>> E-Mail :
>> sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>
>> <mailto:sebastian.huber at embedded-brains.de
>> <mailto:sebastian.huber at embedded-brains.de>>>>
>> PGP : Public key available on
>> request.
>>
>> Diese Nachricht ist keine geschäftliche
>> Mitteilung im Sinne des EHUG.
>>
>>
>>
>>
>> --
>> Rohini Kulkarni
>>
>>
>> --
>> Joel Sherrill, Ph.D. Director of
>> Research
>> & Development
>> joel.sherrill at OARcorp.com On-Line
>> Applications
>> Research
>> Ask me about RTEMS: a free RTOS Huntsville AL
>> 35805
>> Support Available (256) 722-9985
>>
>>
>> -- Joel Sherrill, Ph.D. Director
>> of Research &
>> Development
>> joel.sherrill at OARcorp.com On-Line Applications
>> Research
>> Ask me about RTEMS: a free RTOS Huntsville AL 35805
>> Support Available (256) 722-9985
>>
>>
>>
>>
>> -- Rohini Kulkarni
>>
>>
>>
>>
>> --
>> Rohini Kulkarni
>>
>>
>>
>> --
>> -- Joel Sherrill
>> Ask me about RTEMS: a free RTOS
>> Support and Training Available
>>
>>
>>
>>
>> --
>> Rohini Kulkarni
>
>
>--
>-- Joel Sherrill
>Ask me about RTEMS: a free RTOS
>Support and Training Available
>
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