Problem with system time in lpc176x bsp

[Marcos Díaz]

Hi, thanks for answering, but spnsext01 test works ok.
After a while I noticed the problem:
The ticker interrupt has lower priority than any irq. When I entered the
ticker:
 The bit PENDSTSET of the ICSR register that was used to check whether the
sysclk had a pending interrupt or not went to 0,
But since the ticker has lower priority, my GPIO interrupt preempted the
ticker interrupt before updating the binuptime, and asked for the time,
when checking for that bit inside rtems_timecounter_simple_downcounter_get,
it was 0, but the tick time wasn't added correctly to binuptime and the
timer had already reset. So there is the difference I noticed from time to
time.

The solution I propose include two things: One is to put the interrupt
fence in Clock_isr function before calling Clock_driver_support_at_tick, or
make another Clock_isr function, that "atomically" clears the pending flag
(systick->csr) and updates the binuptime.

The other is to change _ARMV7M_TC_is_pending to not check for the mentioned
bit. instead we should check  for the     systick->csr register, but since
that register clears after each read we should "help" that flag with
another bool:

static bool is_count_pending = false;
static bool _ARMV7M_TC_is_pending(rtems_timecounter_simple *tc)
{

  volatile ARMV7M_Systick *systick = _ARMV7M_Systick;

  if (!is_count_pending)
  {
    is_count_pending = (systick->csr & ARMV7M_SYSTICK_CSR_COUNTFLAG) != 0;
  }

  return is_count_pending;
}

And in the function in charge of clearing that bit we should do this:

static void _ARMV7M_Systick_at_tick(void)
{
  volatile ARMV7M_Systick *systick = _ARMV7M_Systick;

  /* Clear COUNTFLAG */
  systick->csr;

  is_count_pending = false;
}


With this solution I can have any order in priorities between the
interrupts, and it works.
If you approve this I will submit the patch.
I suggest checking for similar problems in other bsps.
Besides this I have another question: What is the best to set for the
ticker priority? It should have a higher/same/lower priority than the other
interrupts?


On Mon, Dec 21, 2015 at 4:39 AM, Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:

> Hello,
>
> works the spnsext01 test on your target?
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
>


-- 

______________________________

<http://www.tallertechnologies.com>


Marcos Díaz

Software Engineer


San Lorenzo 47, 3rd Floor, Office 5

Córdoba, Argentina


Phone: +54 351 4217888 / +54 351 4218211/ +54 351 7617452

Skype: markdiaz22
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