Fwd: [PATCH 007/111] LIBPCI: added PCI layer to cpukit/libpci

Daniel Hellstrom daniel at gaisler.com
Fri Feb 27 14:16:46 UTC 2015


pOn 02/26/2015 08:35 PM, Gedare Bloom wrote:
> On Thu, Feb 26, 2015 at 11:38 AM, Daniel Hellstrom <daniel at gaisler.com> wrote:
>> ---
>>   cpukit/Makefile.am                 |    3 +
>>   cpukit/configure.ac                |   12 +
>>   cpukit/libpci/CHANGES              |   46 ++
>>   cpukit/libpci/Makefile.am          |   46 ++
>>   cpukit/libpci/README               |    4 +
>>   cpukit/libpci/pci.h                |  375 +++++++++++++
>>   cpukit/libpci/pci/access.h         |  351 +++++++++++++
>>   cpukit/libpci/pci/cfg.h            |  244 +++++++++
>>   cpukit/libpci/pci/cfg_auto.h       |   59 +++
>>   cpukit/libpci/pci/cfg_peripheral.h |   20 +
>>   cpukit/libpci/pci/cfg_read.h       |   22 +
>>   cpukit/libpci/pci/cfg_static.h     |   22 +
>>   cpukit/libpci/pci/ids.h            |  802 ++++++++++++++++++++++++++++
>>   cpukit/libpci/pci/ids_extra.h      |   19 +
>>   cpukit/libpci/pci/irq.h            |  105 ++++
>>   cpukit/libpci/pci_access.c         |   74 +++
>>   cpukit/libpci/pci_access_func.c    |   73 +++
>>   cpukit/libpci/pci_access_io.c      |   48 ++
>>   cpukit/libpci/pci_access_mem.c     |   22 +
>>   cpukit/libpci/pci_access_mem_be.c  |   67 +++
>>   cpukit/libpci/pci_access_mem_le.c  |   66 +++
>>   cpukit/libpci/pci_cfg.c            |   55 ++
>>   cpukit/libpci/pci_cfg_auto.c       | 1014 ++++++++++++++++++++++++++++++++++++
>>   cpukit/libpci/pci_cfg_peripheral.c |   32 ++
>>   cpukit/libpci/pci_cfg_print_code.c |  172 ++++++
>>   cpukit/libpci/pci_cfg_read.c       |  357 +++++++++++++
>>   cpukit/libpci/pci_cfg_static.c     |  157 ++++++
>>   cpukit/libpci/pci_find.c           |   52 ++
>>   cpukit/libpci/pci_find_dev.c       |   49 ++
>>   cpukit/libpci/pci_for_each.c       |   62 +++
>>   cpukit/libpci/pci_for_each_child.c |   41 ++
>>   cpukit/libpci/pci_for_each_dev.c   |   18 +
>>   cpukit/libpci/pci_get_dev.c        |   36 ++
>>   cpukit/libpci/pci_irq.c            |   20 +
>>   cpukit/libpci/pci_print.c          |  190 +++++++
>>   cpukit/libpci/preinstall.am        |   66 +++
>>   cpukit/preinstall.am               |    3 +-
>>   cpukit/sapi/include/confdefs.h     |   46 ++
>>   cpukit/wrapup/Makefile.am          |    2 +
>>   doc/ada_user/Makefile.am           |    1 +
>>   doc/ada_user/ada_user.texi         |    2 +
>>   doc/develenv/direct.t              |    3 +
>>   doc/user/Makefile.am               |    9 +-
>>   doc/user/c_user.texi               |    2 +
>>   doc/user/conf.t                    |   53 ++
>>   doc/user/libpci.t                  |  409 +++++++++++++++
>>   46 files changed, 5328 insertions(+), 3 deletions(-)
>>   create mode 100644 cpukit/libpci/CHANGES
>>   create mode 100644 cpukit/libpci/Makefile.am
>>   create mode 100644 cpukit/libpci/README
>>   create mode 100644 cpukit/libpci/pci.h
>>   create mode 100644 cpukit/libpci/pci/access.h
>>   create mode 100644 cpukit/libpci/pci/cfg.h
>>   create mode 100644 cpukit/libpci/pci/cfg_auto.h
>>   create mode 100644 cpukit/libpci/pci/cfg_peripheral.h
>>   create mode 100644 cpukit/libpci/pci/cfg_read.h
>>   create mode 100644 cpukit/libpci/pci/cfg_static.h
>>   create mode 100644 cpukit/libpci/pci/ids.h
>>   create mode 100644 cpukit/libpci/pci/ids_extra.h
>>   create mode 100644 cpukit/libpci/pci/irq.h
>>   create mode 100644 cpukit/libpci/pci_access.c
>>   create mode 100644 cpukit/libpci/pci_access_func.c
>>   create mode 100644 cpukit/libpci/pci_access_io.c
>>   create mode 100644 cpukit/libpci/pci_access_mem.c
>>   create mode 100644 cpukit/libpci/pci_access_mem_be.c
>>   create mode 100644 cpukit/libpci/pci_access_mem_le.c
>>   create mode 100644 cpukit/libpci/pci_cfg.c
>>   create mode 100644 cpukit/libpci/pci_cfg_auto.c
>>   create mode 100644 cpukit/libpci/pci_cfg_peripheral.c
>>   create mode 100644 cpukit/libpci/pci_cfg_print_code.c
>>   create mode 100644 cpukit/libpci/pci_cfg_read.c
>>   create mode 100644 cpukit/libpci/pci_cfg_static.c
>>   create mode 100644 cpukit/libpci/pci_find.c
>>   create mode 100644 cpukit/libpci/pci_find_dev.c
>>   create mode 100644 cpukit/libpci/pci_for_each.c
>>   create mode 100644 cpukit/libpci/pci_for_each_child.c
>>   create mode 100644 cpukit/libpci/pci_for_each_dev.c
>>   create mode 100644 cpukit/libpci/pci_get_dev.c
>>   create mode 100644 cpukit/libpci/pci_irq.c
>>   create mode 100644 cpukit/libpci/pci_print.c
>>   create mode 100644 cpukit/libpci/preinstall.am
>>   create mode 100644 doc/user/libpci.t
>>
>> diff --git a/cpukit/Makefile.am b/cpukit/Makefile.am
>> index 9a78587..0364bf1 100644
>> --- a/cpukit/Makefile.am
>> +++ b/cpukit/Makefile.am
>> @@ -9,6 +9,7 @@ SUBDIRS += dev
>>   SUBDIRS += libcrypt
>>   SUBDIRS += libcsupport libblock libfs
>>   SUBDIRS += libnetworking librpc
>> +SUBDIRS += libpci
>>   SUBDIRS += libi2c
>>   SUBDIRS += libmisc
>>   SUBDIRS += libmd
>> @@ -95,7 +96,9 @@ endif
>>   include_rtems_HEADERS += include/rtems/bspIo.h
>>   include_rtems_HEADERS += include/rtems/userenv.h
>>   include_rtems_HEADERS += include/rtems/fs.h
>> +if !LIBPCI
> shouldn't this be if LIBPCI ?

No, when libpci is enabled we don't want to include the older RTEMS pci library. The new pci.h file is included cpukit/libpci/pci.h

>
>>   include_rtems_HEADERS += include/rtems/pci.h
>> +endif
>>   include_rtems_HEADERS += include/rtems/concat.h
>>   include_rtems_HEADERS += include/rtems/status-checks.h
>>
>> diff --git a/cpukit/configure.ac b/cpukit/configure.ac
>> index 27ffd81..8042c35 100644
>> --- a/cpukit/configure.ac
>> +++ b/cpukit/configure.ac
>> @@ -385,6 +385,17 @@ esac
>>   AM_CONDITIONAL(LIBDL,[test x"$HAVE_LIBDL" = x"yes"])
>>   AC_MSG_RESULT([$HAVE_LIBDL])
>>
>> +# Filter libpci to only build for architectures that have support for it
>> +AC_MSG_CHECKING([whether CPU supports libpci])
>> +case $RTEMS_CPU in
>> +  sparc)
>> +   HAVE_LIBPCI=yes ;;
>> +  *)
>> +   HAVE_LIBPCI=no ;;
>> +esac
>> +AM_CONDITIONAL(LIBPCI,[test x"$HAVE_LIBPCI" = x"yes"])
>> +AC_MSG_RESULT([$HAVE_LIBPCI])
>> +
>>   RTEMS_AMPOLISH3
>>
>>   # Explicitly list all Makefiles here
>> @@ -423,6 +434,7 @@ libgnat/Makefile
>>   libcrypt/Makefile
>>   libcsupport/Makefile
>>   libnetworking/Makefile
>> +libpci/Makefile
>>   librpc/Makefile
>>   libmisc/Makefile
>>   libi2c/Makefile
>> diff --git a/cpukit/libpci/CHANGES b/cpukit/libpci/CHANGES
>> new file mode 100644
>> index 0000000..46064f0
>> --- /dev/null
>> +++ b/cpukit/libpci/CHANGES
>> @@ -0,0 +1,46 @@
>> + 2011-03-03, Daniel Hellstrom <daniel at gaisler.com>
>> +  Added support for ROM BARs at devices and PCI-PCI bridges.
>> +
>> + 2011-02-11, Daniel Hellstrom <daniel at gaisler.com>
>> +  Split Library into different parts, this enables PCI initialization to be done
>> +  outside of the PCI Host driver and smaller systems that don't want
>> +  Configuration Space to be setup.
>> +    - Access Library (Configuration, Memory and I/O Space read/write routines)
>> +    - Configuration Libarary
>> +        A. Auto Config
>> +        B. Static Config (not implemented yet)
>> +    - Interrupt Library (shared interrupt support rely on BSP)
>> +  This file created.
>> +
>> + 2011-02-11, Daniel Hellstrom <daniel at gaisler.com>
>> +  Changed library to use 16-bit identifiers (pci_dev_t), instead to 3 integers
>> +  (BUS,SLOT,FUNC), this reduces the footprint.
>> +
>> + 2010-09-29, Kristoffer Glembo <kristoffer at gaisler.com>
>> +  Fixed I/O BAR size calculation of bridges. Reading/Writing to 0x1C instead of
>> +  faulty 0x1E.
>> +
>> + 2010-06-10, Daniel Hellstrom <daniel at gaisler.com>
>> +  Fix in pci_res_insert(), where the above mentioned optimization failed due to
>> +  bad compare statement. Optimization only affects systems with multiple PCI
>> +  buses.
>> +
>> + 2010-04-19, Daniel Hellstrom <daniel at gaisler.com>
>> +  Optimized resource allocation when bridges are present: the resources lists
>> +  are sorted by boundary instead of size and a reorder aligorithm introduced
>> +  that move resources into unused areas if possible.
>> +
>> + 2010-04-19, Daniel Hellstrom <daniel at gaisler.com>
>> +  Fixed autoconf issue when bridges are present
>> +
>> + 2010-02-03, Daniel Hellstrom <daniel at gaisler.com>
>> +  Fixed initialization problem when first device is a bridge.
>> +
>> + 2010-02-03, Daniel Hellstrom <daniel at gaisler.com>
>> +  PCI Library rewritten from scratch. Support multiple buses/bridges, print
>> +  current PCI configuration space setup, BAR assigment sort implementation
>> +  speeded up drastically (bootup time noticable shorter), interrupt assignment
>> +  implemented, PCI Host driver extracted from library, support for I/O areas.
>> +
>> +
>> +.... not updated ... lots of more changes
> Is this file worth keeping?
No, I will remove it.

>
>> diff --git a/cpukit/libpci/Makefile.am b/cpukit/libpci/Makefile.am
>> new file mode 100644
>> index 0000000..fd42a6f
>> --- /dev/null
>> +++ b/cpukit/libpci/Makefile.am
>> @@ -0,0 +1,46 @@
>> +##
>> +##  $Id: Makefile.am
>> +##
> We don't use $Id anymore.
Ok I will remove all of them from all files in the patch series.

>
>> +
>> +include $(top_srcdir)/automake/compile.am
>> +include $(top_srcdir)/automake/multilib.am
>> +
>> +if LIBPCI
>> +
>> +EXTRA_DIST=
>> +
>> +## PCI Library
>> +include_HEADERS = pci.h
>> +include_pcidir = $(includedir)/pci
>> +include_pci_HEADERS =  pci/access.h pci/cfg.h \
>> +                       pci/cfg_auto.h pci/cfg_static.h \
>> +                       pci/cfg_peripheral.h pci/cfg_read.h \
>> +                       pci/ids.h pci/ids_extra.h pci/irq.h
>> +
>> +noinst_LIBRARIES = libpci.a
>> +
>> +libpci_a_SOURCES  = pci_access.c
>> +libpci_a_SOURCES += pci_access_func.c
>> +libpci_a_SOURCES += pci_access_io.c
>> +libpci_a_SOURCES += pci_access_mem.c
>> +libpci_a_SOURCES += pci_access_mem_be.c
>> +libpci_a_SOURCES += pci_access_mem_le.c
>> +libpci_a_SOURCES += pci_cfg.c
>> +libpci_a_SOURCES += pci_cfg_auto.c
>> +libpci_a_SOURCES += pci_cfg_print_code.c
>> +libpci_a_SOURCES += pci_cfg_read.c
>> +libpci_a_SOURCES += pci_cfg_static.c
>> +libpci_a_SOURCES += pci_cfg_peripheral.c
>> +libpci_a_SOURCES += pci_find.c
>> +libpci_a_SOURCES += pci_find_dev.c
>> +libpci_a_SOURCES += pci_for_each.c
>> +libpci_a_SOURCES += pci_for_each_dev.c
>> +libpci_a_SOURCES += pci_for_each_child.c
>> +libpci_a_SOURCES += pci_get_dev.c
>> +libpci_a_SOURCES += pci_irq.c
>> +libpci_a_SOURCES += pci_print.c
>> +
>> +endif
>> +
>> +include $(srcdir)/preinstall.am
>> +include $(top_srcdir)/automake/local.am
>> diff --git a/cpukit/libpci/README b/cpukit/libpci/README
>> new file mode 100644
>> index 0000000..334f3a9
>> --- /dev/null
>> +++ b/cpukit/libpci/README
>> @@ -0,0 +1,4 @@
>> +PCI Library
>> +
>> +LIBPCI is documented in the ../../doc directory, see ../../doc/README how
>> +to build documentation.
>
> I'd like to see doxygen for these headers (eventually).
>> diff --git a/cpukit/libpci/pci.h b/cpukit/libpci/pci.h
>> new file mode 100644
>> index 0000000..e9955bc
>> --- /dev/null
>> +++ b/cpukit/libpci/pci.h
>> @@ -0,0 +1,375 @@
>> +/*
>> + *
>> + *     PCI defines and function prototypes
>> + *     Copyright 1994, Drew Eckhardt
>> + *     Copyright 1997, 1998 Martin Mares <mj at atrey.karlin.mff.cuni.cz>
>> + *
>> + *      New PCI library written from scratch. Defines in this file was reused.
>> + *      auto-generated pci_ids.h also reused.
>> + *      Copyright 2009, Cobham Gaisler AB
>> + *
>> + *     For more information, please consult the following manuals (look at
>> + *     http://www.pcisig.com/ for how to get them):
>> + *
>> + *     PCI BIOS Specification
>> + *     PCI Local Bus Specification
>> + *     PCI to PCI Bridge Specification
>> + *     PCI System Design Guide
>> + */
>> +
> License needed

This is the text that comes from cpukit/include/rtems/pci.h, it is unclear. The only thing reused are the defines, up to line 283. Should I split the pci.h file here so it is clear what part is the 
"old" license and what is newly developed? Or perhaps I should replace all defines using the ones that FreeBSD uses defined in sys/dev/pci/pcireg.h instead?


>> +#ifndef __PCI_H__
>> +#define __PCI_H__
>> +
>> +#include <pci/ids.h>
>> +
>> +/*
>> + * Under PCI, each device has 256 bytes of configuration address space,
>> + * of which the first 64 bytes are standardized as follows:
>> + */
>> +#define PCI_VENDOR_ID          0x00    /* 16 bits */
>> +#define PCI_DEVICE_ID          0x02    /* 16 bits */
>> +#define PCI_COMMAND            0x04    /* 16 bits */
>> +#define  PCI_COMMAND_IO                0x1     /* Enable response in I/O space */
>> +#define  PCI_COMMAND_MEMORY    0x2     /* Enable response in Memory space */
>> +#define  PCI_COMMAND_MASTER    0x4     /* Enable bus mastering */
>> +#define  PCI_COMMAND_SPECIAL   0x8     /* Enable response to special cycles */
>> +#define  PCI_COMMAND_INVALIDATE        0x10    /* Use memory write and invalidate */
>> +#define  PCI_COMMAND_VGA_PALETTE 0x20  /* Enable palette snooping */
>> +#define  PCI_COMMAND_PARITY    0x40    /* Enable parity checking */
>> +#define  PCI_COMMAND_WAIT      0x80    /* Enable address/data stepping */
>> +#define  PCI_COMMAND_SERR      0x100   /* Enable SERR */
>> +#define  PCI_COMMAND_FAST_BACK 0x200   /* Enable back-to-back writes */
>> +
>> +#define PCI_STATUS             0x06    /* 16 bits */
>> +#define  PCI_STATUS_66MHZ      0x20    /* Support 66 Mhz PCI 2.1 bus */
>> +#define  PCI_STATUS_UDF                0x40    /* Support User Definable Features */
>> +
>> +#define  PCI_STATUS_FAST_BACK  0x80    /* Accept fast-back to back */
>> +#define  PCI_STATUS_PARITY     0x100   /* Detected parity error */
>> +#define  PCI_STATUS_DEVSEL_MASK        0x600   /* DEVSEL timing */
>> +#define  PCI_STATUS_DEVSEL_FAST        0x000
>> +#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
>> +#define  PCI_STATUS_DEVSEL_SLOW 0x400
>> +#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
>> +#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
>> +#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
>> +#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
>> +#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
>> +
>> +#define PCI_CLASS_REVISION     0x08    /* High 24 bits are class, low 8
>> +                                          revision */
>> +#define PCI_REVISION_ID         0x08    /* Revision ID */
>> +#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
>> +#define PCI_CLASS_DEVICE        0x0a    /* Device class */
>> +
>> +#define PCI_CACHE_LINE_SIZE    0x0c    /* 8 bits */
>> +#define PCI_LATENCY_TIMER      0x0d    /* 8 bits */
>> +#define PCI_HEADER_TYPE                0x0e    /* 8 bits */
>> +#define  PCI_HEADER_TYPE_NORMAL        0
>> +#define  PCI_HEADER_TYPE_BRIDGE 1
>> +#define  PCI_HEADER_TYPE_CARDBUS 2
>> +
>> +#define PCI_BIST               0x0f    /* 8 bits */
>> +#define PCI_BIST_CODE_MASK     0x0f    /* Return result */
>> +#define PCI_BIST_START         0x40    /* 1 to start BIST, 2 secs or less */
>> +#define PCI_BIST_CAPABLE       0x80    /* 1 if BIST capable */
>> +
>> +/*
>> + * Base addresses specify locations in memory or I/O space.
>> + * Decoded size can be determined by writing a value of
>> + * 0xffffffff to the register, and reading it back. Only
>> + * 1 bits are decoded.
>> + */
>> +#define PCI_BASE_ADDRESS_0     0x10    /* 32 bits */
>> +#define PCI_BASE_ADDRESS_1     0x14    /* 32 bits [htype 0,1 only] */
>> +#define PCI_BASE_ADDRESS_2     0x18    /* 32 bits [htype 0 only] */
>> +#define PCI_BASE_ADDRESS_3     0x1c    /* 32 bits */
>> +#define PCI_BASE_ADDRESS_4     0x20    /* 32 bits */
>> +#define PCI_BASE_ADDRESS_5     0x24    /* 32 bits */
>> +#define  PCI_BASE_ADDRESS_SPACE        0x01    /* 0 = memory, 1 = I/O */
>> +#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
>> +#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
>> +#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
>> +#define  PCI_BASE_ADDRESS_MEM_TYPE_32  0x00    /* 32 bit address */
>> +#define  PCI_BASE_ADDRESS_MEM_TYPE_1M  0x02    /* Below 1M */
>> +#define  PCI_BASE_ADDRESS_MEM_TYPE_64  0x04    /* 64 bit address */
>> +#define  PCI_BASE_ADDRESS_MEM_PREFETCH 0x08    /* prefetchable? */
>> +#define  PCI_BASE_ADDRESS_MEM_MASK     (~0x0fUL)
>> +#define  PCI_BASE_ADDRESS_IO_MASK      (~0x03UL)
>> +/* bit 1 is reserved if address_space = 1 */
>> +
>> +/* Header type 0 (normal devices) */
>> +#define PCI_CARDBUS_CIS                0x28
>> +#define PCI_SUBSYSTEM_VENDOR_ID        0x2c
>> +#define PCI_SUBSYSTEM_ID       0x2e
>> +#define PCI_ROM_ADDRESS                0x30    /* Bits 31..11 are address, 10..1 reserved */
>> +#define  PCI_ROM_ADDRESS_ENABLE        0x01
>> +#define  PCI_ROM_ADDRESS_MASK  (~0x7ffUL)
>> +
>> +/* 0x34 Capabilities Pointer (PCI 2.3) */
>> +#define PCI_CAP_PTR            0x34    /* 8 bits */
>> +
>> +/* 0x35-0x3b are reserved */
>> +#define PCI_INTERRUPT_LINE     0x3c    /* 8 bits */
>> +#define PCI_INTERRUPT_PIN      0x3d    /* 8 bits */
>> +#define PCI_MIN_GNT            0x3e    /* 8 bits */
>> +#define PCI_MAX_LAT            0x3f    /* 8 bits */
>> +
>> +/* Header type 1 (PCI-to-PCI bridges) */
>> +#define PCI_PRIMARY_BUS                0x18    /* Primary bus number */
>> +#define PCI_SECONDARY_BUS      0x19    /* Secondary bus number */
>> +#define PCI_SUBORDINATE_BUS    0x1a    /* Highest bus number behind the bridge */
>> +#define PCI_SEC_LATENCY_TIMER  0x1b    /* Latency timer for secondary interface */
>> +#define PCI_IO_BASE            0x1c    /* I/O range behind the bridge */
>> +#define PCI_IO_LIMIT           0x1d
>> +#define  PCI_IO_RANGE_TYPE_MASK        0x0f    /* I/O bridging type */
>> +#define  PCI_IO_RANGE_TYPE_16  0x00
>> +#define  PCI_IO_RANGE_TYPE_32  0x01
>> +#define  PCI_IO_RANGE_MASK     (~0x0f)
>> +#define PCI_SEC_STATUS         0x1e    /* Secondary status register, only bit 14 used */
>> +#define PCI_MEMORY_BASE                0x20    /* Memory range behind */
>> +#define PCI_MEMORY_LIMIT       0x22
>> +#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
>> +#define  PCI_MEMORY_RANGE_MASK (~0x0f)
>> +#define PCI_PREF_MEMORY_BASE   0x24    /* Prefetchable memory range behind */
>> +#define PCI_PREF_MEMORY_LIMIT  0x26
>> +#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
>> +#define  PCI_PREF_RANGE_TYPE_32        0x00
>> +#define  PCI_PREF_RANGE_TYPE_64        0x01
>> +#define  PCI_PREF_RANGE_MASK   (~0x0f)
>> +#define PCI_PREF_BASE_UPPER32  0x28    /* Upper half of prefetchable memory range */
>> +#define PCI_PREF_LIMIT_UPPER32 0x2c
>> +#define PCI_IO_BASE_UPPER16    0x30    /* Upper half of I/O addresses */
>> +#define PCI_IO_LIMIT_UPPER16   0x32
>> +/* 0x34-0x3b is reserved */
>> +#define PCI_ROM_ADDRESS1       0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
>> +/* 0x3c-0x3d are same as for htype 0 */
>> +#define PCI_BRIDGE_CONTROL     0x3e
>> +#define  PCI_BRIDGE_CTL_PARITY 0x01    /* Enable parity detection on secondary interface */
>> +#define  PCI_BRIDGE_CTL_SERR   0x02    /* The same for SERR forwarding */
>> +#define  PCI_BRIDGE_CTL_NO_ISA 0x04    /* Disable bridging of ISA ports */
>> +#define  PCI_BRIDGE_CTL_VGA    0x08    /* Forward VGA addresses */
>> +#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
>> +#define  PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
>> +#define  PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
>> +
>> +/* Header type 2 (CardBus bridges) */
>> +/* 0x14-0x15 reserved */
>> +#define PCI_CB_SEC_STATUS      0x16    /* Secondary status */
>> +#define PCI_CB_PRIMARY_BUS     0x18    /* PCI bus number */
>> +#define PCI_CB_CARD_BUS                0x19    /* CardBus bus number */
>> +#define PCI_CB_SUBORDINATE_BUS 0x1a    /* Subordinate bus number */
>> +#define PCI_CB_LATENCY_TIMER   0x1b    /* CardBus latency timer */
>> +#define PCI_CB_MEMORY_BASE_0   0x1c
>> +#define PCI_CB_MEMORY_LIMIT_0  0x20
>> +#define PCI_CB_MEMORY_BASE_1   0x24
>> +#define PCI_CB_MEMORY_LIMIT_1  0x28
>> +#define PCI_CB_IO_BASE_0       0x2c
>> +#define PCI_CB_IO_BASE_0_HI    0x2e
>> +#define PCI_CB_IO_LIMIT_0      0x30
>> +#define PCI_CB_IO_LIMIT_0_HI   0x32
>> +#define PCI_CB_IO_BASE_1       0x34
>> +#define PCI_CB_IO_BASE_1_HI    0x36
>> +#define PCI_CB_IO_LIMIT_1      0x38
>> +#define PCI_CB_IO_LIMIT_1_HI   0x3a
>> +#define  PCI_CB_IO_RANGE_MASK  (~0x03)
>> +/* 0x3c-0x3d are same as for htype 0 */
>> +#define PCI_CB_BRIDGE_CONTROL  0x3e
>> +#define  PCI_CB_BRIDGE_CTL_PARITY      0x01    /* Similar to standard bridge control register */
>> +#define  PCI_CB_BRIDGE_CTL_SERR                0x02
>> +#define  PCI_CB_BRIDGE_CTL_ISA         0x04
>> +#define  PCI_CB_BRIDGE_CTL_VGA         0x08
>> +#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT        0x20
>> +#define  PCI_CB_BRIDGE_CTL_CB_RESET    0x40    /* CardBus reset */
>> +#define  PCI_CB_BRIDGE_CTL_16BIT_INT   0x80    /* Enable interrupt for 16-bit cards */
>> +#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
>> +#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
>> +#define  PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
>> +#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
>> +#define PCI_CB_SUBSYSTEM_ID    0x42
>> +#define PCI_CB_LEGACY_MODE_BASE        0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
>> +/* 0x48-0x7f reserved */
>> +
>> +/* Device classes and subclasses */
>> +
>> +#define PCI_CLASS_NOT_DEFINED          0x0000
>> +#define PCI_CLASS_NOT_DEFINED_VGA      0x0001
>> +
>> +#define PCI_BASE_CLASS_STORAGE         0x01
>> +#define PCI_CLASS_STORAGE_SCSI         0x0100
>> +#define PCI_CLASS_STORAGE_IDE          0x0101
>> +#define PCI_CLASS_STORAGE_FLOPPY       0x0102
>> +#define PCI_CLASS_STORAGE_IPI          0x0103
>> +#define PCI_CLASS_STORAGE_RAID         0x0104
>> +#define PCI_CLASS_STORAGE_OTHER                0x0180
>> +
>> +#define PCI_BASE_CLASS_NETWORK         0x02
>> +#define PCI_CLASS_NETWORK_ETHERNET     0x0200
>> +#define PCI_CLASS_NETWORK_TOKEN_RING   0x0201
>> +#define PCI_CLASS_NETWORK_FDDI         0x0202
>> +#define PCI_CLASS_NETWORK_ATM          0x0203
>> +#define PCI_CLASS_NETWORK_OTHER                0x0280
>> +
>> +#define PCI_BASE_CLASS_DISPLAY         0x03
>> +#define PCI_CLASS_DISPLAY_VGA          0x0300
>> +#define PCI_CLASS_DISPLAY_XGA          0x0301
>> +#define PCI_CLASS_DISPLAY_OTHER                0x0380
>> +
>> +#define PCI_BASE_CLASS_MULTIMEDIA      0x04
>> +#define PCI_CLASS_MULTIMEDIA_VIDEO     0x0400
>> +#define PCI_CLASS_MULTIMEDIA_AUDIO     0x0401
>> +#define PCI_CLASS_MULTIMEDIA_OTHER     0x0480
>> +
>> +#define PCI_BASE_CLASS_MEMORY          0x05
>> +#define  PCI_CLASS_MEMORY_RAM          0x0500
>> +#define  PCI_CLASS_MEMORY_FLASH                0x0501
>> +#define  PCI_CLASS_MEMORY_OTHER                0x0580
>> +
>> +#define PCI_BASE_CLASS_BRIDGE          0x06
>> +#define  PCI_CLASS_BRIDGE_HOST         0x0600
>> +#define  PCI_CLASS_BRIDGE_ISA          0x0601
>> +#define  PCI_CLASS_BRIDGE_EISA         0x0602
>> +#define  PCI_CLASS_BRIDGE_MC           0x0603
>> +#define  PCI_CLASS_BRIDGE_PCI          0x0604
>> +#define  PCI_CLASS_BRIDGE_PCMCIA       0x0605
>> +#define  PCI_CLASS_BRIDGE_NUBUS                0x0606
>> +#define  PCI_CLASS_BRIDGE_CARDBUS      0x0607
>> +#define  PCI_CLASS_BRIDGE_OTHER                0x0680
>> +
>> +#define PCI_BASE_CLASS_COMMUNICATION   0x07
>> +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
>> +#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
>> +#define PCI_CLASS_COMMUNICATION_OTHER  0x0780
>> +
>> +#define PCI_BASE_CLASS_SYSTEM          0x08
>> +#define PCI_CLASS_SYSTEM_PIC           0x0800
>> +#define PCI_CLASS_SYSTEM_DMA           0x0801
>> +#define PCI_CLASS_SYSTEM_TIMER         0x0802
>> +#define PCI_CLASS_SYSTEM_RTC           0x0803
>> +#define PCI_CLASS_SYSTEM_OTHER         0x0880
>> +
>> +#define PCI_BASE_CLASS_INPUT           0x09
>> +#define PCI_CLASS_INPUT_KEYBOARD       0x0900
>> +#define PCI_CLASS_INPUT_PEN            0x0901
>> +#define PCI_CLASS_INPUT_MOUSE          0x0902
>> +#define PCI_CLASS_INPUT_OTHER          0x0980
>> +
>> +#define PCI_BASE_CLASS_DOCKING         0x0a
>> +#define PCI_CLASS_DOCKING_GENERIC      0x0a00
>> +#define PCI_CLASS_DOCKING_OTHER                0x0a01
>> +
>> +#define PCI_BASE_CLASS_PROCESSOR       0x0b
>> +#define PCI_CLASS_PROCESSOR_386                0x0b00
>> +#define PCI_CLASS_PROCESSOR_486                0x0b01
>> +#define PCI_CLASS_PROCESSOR_PENTIUM    0x0b02
>> +#define PCI_CLASS_PROCESSOR_ALPHA      0x0b10
>> +#define PCI_CLASS_PROCESSOR_POWERPC    0x0b20
>> +#define PCI_CLASS_PROCESSOR_CO         0x0b40
>> +
>> +#define PCI_BASE_CLASS_SERIAL          0x0c
>> +#define PCI_CLASS_SERIAL_FIREWIRE      0x0c00
>> +#define PCI_CLASS_SERIAL_ACCESS                0x0c01
>> +#define PCI_CLASS_SERIAL_SSA           0x0c02
>> +#define PCI_CLASS_SERIAL_USB           0x0c03
>> +#define PCI_CLASS_SERIAL_FIBER         0x0c04
>> +
>> +#define PCI_CLASS_OTHERS               0xff
>> +
>> +#define PCI_INVALID_VENDORDEVICEID    0xffffffff
>> +#define PCI_MULTI_FUNCTION            0x80
>> +
>> +#define PCI_MAX_DEVICES                        32
>> +#define PCI_MAX_FUNCTIONS              8
>> +
>> +#include <pci/access.h>
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +/* The PCI Library have the following build time configuration options. It is
>> + * up to the BSP header file (bsp.h) to set options properly.
>> + *
>> + * BSP_PCI_BIG_ENDIAN    - Access inline routines will be for a big-endian PCI
>> + *                         bus, if not defined the routines will assume that
>> + *                         PCI is as the standard defines: little-endian.
>> + *
>> + *                         Note that drivers may be run-time configurable,
>> + *                         meaning that they may adopt to either big-endian or
>> + *                         little-endian PCI bus, the host driver or BSP may
>> + *                         detect endianness during run-time.
>> + */
>> +
>> +/* Error return values */
>> +enum {
>> +       PCISTS_ERR         = -1, /* Undefined Error */
>> +       PCISTS_OK          = 0,
>> +       PCISTS_EINVAL      = 1, /* Bad input arguments */
>> +       PCISTS_MSTABRT     = 2, /* CFG space access error (can be ignored) */
>> +};
>> +
>> +/* PCI System type can be used to determine system for drivers. Normally
>> + * the system is Host, but the peripheral configuration library also supports
>> + * being PCI peripheral not allowed to access configuration space.
>> + *
>> + * The active configuration Library set this variable.
>> + */
>> +enum {
>> +       PCI_SYSTEM_NONE = 0,
>> +       PCI_SYSTEM_HOST = 1,
>> +       PCI_SYSTEM_PERIPHERAL = 2,
>> +};
>> +extern int pci_system_type;
>> +
>> +/* PCI Bus Endianness. The PCI specification is little endian, however on some
>> + * embedded systems (AT697-LEON2 for example) the PCI bus is defined as big
>> + * endian (non-standard) in order to avoid byte-twisting.
>> + */
>> +enum {
>> +       PCI_LITTLE_ENDIAN = 0,
>> +       PCI_BIG_ENDIAN = 1,
>> +};
>> +extern int pci_endian;
>> +
>> +/* Return the number of PCI busses in the system */
>> +extern int pci_bus_count(void);
>> +
>> +/* Scan the PCI bus and print the PCI device/functions/bridges and their
>> + * current resources and size to the system console.
>> + */
>> +extern void pci_print(void);
>> +
>> +/* Print current configuration of a single PCI device by reading PCI
>> + * configuration space
>> + */
>> +extern void pci_print_dev(pci_dev_t dev);
>> +extern void pci_print_device(int bus, int slot, int function);
>> +
>> +/*** PCI Configuration Space direct access routines ***/
>> +
>> +/* Function iterates over all PCI buses/devices/functions and calls
>> + * func(PCIDEV,arg) for each present device. The iteration is stopped if
>> + * func() returns non-zero result the same result is returned. As long
>> + * as func() returns zero the function will keep on iterating, when all
>> + * devices has been processed the function return zero.
>> + *
>> + * The function iterates over all devices/functions on all buses by accessing
>> + * configuration space directly (PCI RAM data structures not used). This
>> + * function is valid to call after PCI buses have been enumrated.
>> + */
>> +extern int pci_for_each(int (*func)(pci_dev_t, void*), void *arg);
>> +
>> +/* Get PCI Configuration space BUS|SLOT|FUNC for a device matching PCI
>> + * Vendor, Device and instance number 'index'.
>> + *
>> + * Return Values
>> + * -1  pci_find_dev did not find a device matching the criterion.
>> + *  0  device was found, *pdev was updated with the device's BUS|SLOT|FUNC
>> + */
>> +extern int pci_find(uint16_t ven, uint16_t dev, int index, pci_dev_t *pdev);
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif
>> +
>> +#endif /* __PCI_H__ */
>> diff --git a/cpukit/libpci/pci/access.h b/cpukit/libpci/pci/access.h
>> new file mode 100644
>> index 0000000..f8365db
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/access.h
>> @@ -0,0 +1,351 @@
>> +/* Routines to access PCI memory/configuration space and other PCI related
>> + * functions the PCI Library provides.
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
> Can you put your copyright on one line? It makes it easier to 'grep'.
Sure, I will do that for libdrvmgr and libpci then.

>
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +
>> +#ifndef __PCI_ACCESS_H__
>> +#define __PCI_ACCESS_H__
>> +
>> +#include <stdint.h>
>> +#include <libcpu/byteorder.h>
> I'm not sure we should include libcpu in cpukit. Although I guess the
> cache manager is done like that.
>
>> +#include <pci.h>
>> +
>> +/* Let BSP configure load/store from PCI */
>> +#include <bsp.h>
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif
>> +
>> +/* Identification of a PCI configuration space device (16-bit) */
>> +typedef uint16_t pci_dev_t;
>> +/* Create a PCI Configuration Space ID */
>> +#define PCI_DEV(bus, slot, func) (((bus)<<8) | ((slot)<<3) | (func))
>> +/* Get Bus of a PCI Configuration Space ID */
>> +#define PCI_DEV_BUS(dev) (((dev) >> 8) & 0xff)
>> +/* Get Slot/Device of a PCI Configuration Space ID */
>> +#define PCI_DEV_SLOT(dev) (((dev) >> 3) & 0x1f)
>> +/* Get Function of a PCI Configuration Space ID */
>> +#define PCI_DEV_FUNC(dev) ((dev) & 0x7)
>> +/* Get Device and Function of a PCI Configuration Space ID */
>> +#define PCI_DEV_DEVFUNC(dev) ((dev) & 0xff)
>> +/* Expand Device into argument lists */
>> +#define PCI_DEV_EXPAND(dev) PCI_DEV_BUS((dev)), PCI_DEV_SLOT((dev)), PCI_DEV_FUNC((dev))
>> +
>> +/* Configuration Space Read/Write Operations */
>> +struct pci_cfg_ops {
>> +       /* Configuration Space Access and Setup Routines */
>> +       int (*read8)(pci_dev_t dev, int ofs, uint8_t *data);
>> +       int (*read16)(pci_dev_t dev, int ofs, uint16_t *data);
>> +       int (*read32)(pci_dev_t dev, int ofs, uint32_t *data);
>> +       int (*write8)(pci_dev_t dev, int ofs, uint8_t data);
>> +       int (*write16)(pci_dev_t dev, int ofs, uint16_t data);
>> +       int (*write32)(pci_dev_t dev, int ofs, uint32_t data);
>> +};
>> +
>> +/* Read a register over PCI I/O Space, and swap it if necessary (due to
>> + * PCI endianness)
>> + */
>> +struct pci_io_ops {
>> +       uint8_t (*read8)(uint8_t *adr);
>> +       uint16_t(*read16)(uint16_t *adr);
>> +       uint32_t (*read32)(uint32_t *adr);
>> +       void (*write8)(uint8_t *adr, uint8_t data);
>> +       void (*write16)(uint16_t *adr, uint16_t data);
>> +       void (*write32)(uint32_t *adr, uint32_t data);
>> +};
>> +
>> +/* Read a register over PCI Memory Space (non-prefetchable memory), and
>> + * swap it if necessary (due to PCI endianness)
>> + */
>> +struct pci_memreg_ops {
>> +       uint8_t (*ld8)(uint8_t *adr);
>> +       void (*st8)(uint8_t *adr, uint8_t data);
>> +
>> +       uint16_t(*ld_le16)(uint16_t *adr);
>> +       void (*st_le16)(uint16_t *adr, uint16_t data);
>> +       uint16_t(*ld_be16)(uint16_t *adr);
>> +       void (*st_be16)(uint16_t *adr, uint16_t data);
>> +
>> +       uint32_t (*ld_le32)(uint32_t *adr);
>> +       void (*st_le32)(uint32_t *adr, uint32_t data);
>> +       uint32_t (*ld_be32)(uint32_t *adr);
>> +       void (*st_be32)(uint32_t *adr, uint32_t data);
>> +};
>> +
>> +typedef uint8_t (*pci_ld8_t)(uint8_t *adr);
>> +typedef void (*pci_st8_t)(uint8_t *adr, uint8_t data);
>> +typedef uint16_t(pci_ld16_t)(uint16_t *adr);
>> +typedef void (*pci_st16_t)(uint16_t *adr, uint16_t data);
>> +typedef uint32_t (*pci_ld32_t)(uint32_t *adr);
>> +typedef void (*pci_st32_t)(uint32_t *adr, uint32_t data);
>> +
>> +struct pci_access_drv {
>> +       /* Configuration */
>> +       struct pci_cfg_ops cfg;
>> +
>> +       /* I/O Access operations */
>> +       struct pci_io_ops io;
>> +
>> +       /* Registers over Memory Access operations. Note that these funcs
>> +        * are only for code that need to be compatible with both Big-Endian
>> +        * and Little-Endian PCI bus or for some other reason need function
>> +        * pointers to access functions. Normally drivers use the inline
>> +        * functions for Registers-over-Memory access to avoid extra function
>> +        * call.
>> +        */
>> +       struct pci_memreg_ops *memreg;
>> +
>> +       /* Translate from PCI address to CPU address (dir=0). Translate
>> +        * CPU address to PCI address (dir!=0). The address will can be
>> +        * used to perform I/O access or memory access by CPU or PCI DMA
>> +        * peripheral.
>> +        *
>> +        * address    In/Out. CPU address or PCI address.
>> +        * type       Access type. 1=I/O, 2=MEMIO, 3=MEM
>> +        * dir        Translate direction. 0=PCI-to-CPU, 0!=CPU-to-PCI,
>> +        *
>> +        * Return Value
>> +        *  0   = Success
>> +        *  -1  = Requested Address not mapped into other address space
>> +        *        i.e. not accessible
>> +        */
>> +       int (*translate)(uint32_t *address, int type, int dir);
>> +};
>> +
>> +/* Access Routines valid after a PCI-Access-Driver has registered */
>> +extern struct pci_access_drv pci_access_ops;
>> +
>> +/* Register PCI Access Driver */
>> +extern int pci_access_drv_register(struct pci_access_drv *drv);
>> +
>> +/* Set/unset bits in command and status register of a PCI device */
>> +extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val);
>> +
>> +/* Enable Memory in command register */
>> +static inline void pci_mem_enable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, PCI_COMMAND_MEMORY);
>> +}
>> +
>> +static inline void pci_mem_disable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_MEMORY, 0);
>> +}
>> +
>> +static inline void pci_io_enable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_IO, PCI_COMMAND_IO);
>> +}
>> +
>> +static inline void pci_io_disable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_IO, 0);
>> +}
>> +
>> +static inline void pci_master_enable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, PCI_COMMAND_MASTER);
>> +}
>> +
>> +static inline void pci_master_disable(pci_dev_t dev)
>> +{
>> +       pci_modify_cmdsts(dev, PCI_COMMAND_MASTER, 0);
>> +}
>> +
>> +/* Configuration Space Access Read Routines */
>> +extern int pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *data);
>> +extern int pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *data);
>> +extern int pci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *data);
>> +
>> +/* Configuration Space Access Write Routines */
>> +extern int pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t data);
>> +extern int pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t data);
>> +extern int pci_cfg_w32(pci_dev_t dev, int ofs, uint32_t data);
>> +
>> +/* Read a register over PCI I/O Space */
>> +extern uint8_t pci_io_r8(uint32_t adr);
>> +extern uint16_t pci_io_r16(uint32_t adr);
>> +extern uint32_t pci_io_r32(uint32_t adr);
>> +
>> +/* Write a register over PCI I/O Space */
>> +extern void pci_io_w8(uint32_t adr, uint8_t data);
>> +extern void pci_io_w16(uint32_t adr, uint16_t data);
>> +extern void pci_io_w32(uint32_t adr, uint32_t data);
>> +
>> +/* Translate PCI address into CPU accessible address */
>> +static inline int pci_pci2cpu(uint32_t *address, int type)
>> +{
>> +       return pci_access_ops.translate(address, type, 0);
>> +}
>> +
>> +/* Translate CPU accessible address into PCI address (for DMA) */
>> +static inline int pci_cpu2pci(uint32_t *address, int type)
>> +{
>> +       return pci_access_ops.translate(address, type, 1);
>> +}
>> +
>> +/*** Read/Write a register over PCI Memory Space ***/
>> +
>> +static inline uint8_t pci_ld8(volatile uint8_t *addr)
>> +{
>> +       return *addr;
>> +}
>> +
>> +static inline void pci_st8(volatile uint8_t *addr, uint8_t val)
>> +{
>> +       *addr = val;
>> +}
>> +
>> +#ifdef BSP_PCI_BIG_ENDIAN
>> +
>> +/* BSP has decided Big Endian PCI Bus (non-standard) */
>> +
>> +static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
>> +{
>> +       return ld_be16(addr);
>> +}
>> +
>> +static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
>> +{
>> +       st_be16(addr, val);
>> +}
>> +
>> +static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
>> +{
>> +       return ld_be32(addr);
>> +}
>> +
>> +static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
>> +{
>> +       st_be32(addr, val);
>> +}
>> +
>> +static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
>> +{
>> +       return ld_le16(addr);
>> +}
>> +
>> +static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
>> +{
>> +       st_le16(addr, val);
>> +}
>> +
>> +static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
>> +{
>> +       return ld_le32(addr);
>> +}
>> +
>> +static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
>> +{
>> +       st_le32(addr, val);
>> +}
>> +
>> +#else
>> +
>> +/* Little Endian PCI Bus */
>> +
>> +static inline uint16_t pci_ld_le16(volatile uint16_t *addr)
>> +{
>> +       return ld_le16(addr);
>> +}
>> +
>> +static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val)
>> +{
>> +       st_le16(addr, val);
>> +}
>> +
>> +static inline uint32_t pci_ld_le32(volatile uint32_t *addr)
>> +{
>> +       return ld_le32(addr);
>> +}
>> +
>> +static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val)
>> +{
>> +       st_le32(addr, val);
>> +}
>> +
>> +static inline uint16_t pci_ld_be16(volatile uint16_t *addr)
>> +{
>> +       return ld_be16(addr);
>> +}
>> +
>> +static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val)
>> +{
>> +       st_be16(addr, val);
>> +}
>> +
>> +static inline uint32_t pci_ld_be32(volatile uint32_t *addr)
>> +{
>> +       return ld_be32(addr);
>> +}
>> +
>> +static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val)
>> +{
>> +       st_be32(addr, val);
>> +}
>> +
>> +#endif
>> +
>> +/* Registers-over-Memory Space access routines. The routines are not inlined
>> + * so it is possible during run-time to select which function implemention
>> + * to use. The use of these functions are not recommended since it will have a
>> + * performance penalty.
>> + *
>> + * 8-bit accesses are the same for Little and Big endian PCI buses.
>> + */
>> +uint8_t pci_mem_ld8(uint8_t *adr);
>> +void pci_mem_st8(uint8_t *adr, uint8_t data);
>> +/* Registers-over-Memory Space - Generic Big endian PCI bus definitions */
>> +uint16_t pci_mem_be_ld_le16(uint16_t *adr);
>> +uint16_t pci_mem_be_ld_be16(uint16_t *adr);
>> +uint32_t pci_mem_be_ld_le32(uint32_t *adr);
>> +uint32_t pci_mem_be_ld_be32(uint32_t *adr);
>> +void pci_mem_be_st_le16(uint16_t *adr, uint16_t data);
>> +void pci_mem_be_st_be16(uint16_t *adr, uint16_t data);
>> +void pci_mem_be_st_le32(uint32_t *adr, uint32_t data);
>> +void pci_mem_be_st_be32(uint32_t *adr, uint32_t data);
>> +/* Registers-over-Memory Space - Generic Little endian PCI bus definitions */
>> +uint16_t pci_mem_le_ld_le16(uint16_t *adr);
>> +uint16_t pci_mem_le_ld_be16(uint16_t *adr);
>> +uint32_t pci_mem_le_ld_le32(uint32_t *adr);
>> +uint32_t pci_mem_le_ld_be32(uint32_t *adr);
>> +void pci_mem_le_st_le16(uint16_t *adr, uint16_t data);
>> +void pci_mem_le_st_be16(uint16_t *adr, uint16_t data);
>> +void pci_mem_le_st_le32(uint32_t *adr, uint32_t data);
>> +void pci_mem_le_st_be32(uint32_t *adr, uint32_t data);
>> +
>> +/* Get Read/Write function for accessing a register over PCI Memory Space
>> + * (non-inline functions).
>> + *
>> + * Arguments
>> + *  wr             0(Read), 1(Write)
>> + *  size           1(Byte), 2(Word), 4(Double Word)
>> + *  func           Where function pointer will be stored
>> + *  endian         PCI_LITTLE_ENDIAN or PCI_BIG_ENDIAN
>> + *  type           1(I/O), 3(REG over MEM), 4(CFG)
>> + *
>> + * Return
>> + *  0              Found function
>> + *  others         No such function defined by host driver or BSP
>> + */
>> +extern int pci_access_func(int wr, int size, void **func, int endian, int type);
>> +
>> +/* Predefined functions for Host drivers or BSPs that define the
>> + * register-over-memory space functions operations.
>> + */
>> +extern struct pci_memreg_ops pci_mem_le_ops; /* For Little-Endian PCI bus */
>> +extern struct pci_memreg_ops pci_mem_be_ops; /* For Big-Endian PCI bus */
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif
>> +
>> +#endif /* !__PCI_ACCESS_H__ */
>> diff --git a/cpukit/libpci/pci/cfg.h b/cpukit/libpci/pci/cfg.h
>> new file mode 100644
>> index 0000000..18c48db
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/cfg.h
>> @@ -0,0 +1,244 @@
>> +/* PCI Configuration Library, two versions of the library exists:
>> + *  - auto configuration (default)
>> + *  - static configuration (user defined config)
>> + * both versions are defined here.
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +
>> +#ifndef __PCI_CFG_H__
>> +#define __PCI_CFG_H__
>> +
>> +#include <pci.h>
>> +
>> +/* PCI Configuration library */
>> +
>> +/* Return the number of PCI buses in system */
>> +extern int pci_bus_count(void);
>> +
>> +/* PCI Address assigned to BARs which failed to fit into the PCI Window or
>> + * is disabled by any other cause.
>> + */
>> +extern uint32_t pci_invalid_address;
>> +
>> +/* PCI Configuration Library of the system */
>> +enum {
>> +       PCI_CONFIG_LIB_NONE = 0,
>> +       PCI_CONFIG_LIB_AUTO = 1,
>> +       PCI_CONFIG_LIB_STATIC = 2,
>> +       PCI_CONFIG_LIB_READ = 3,
>> +       PCI_CONFIG_LIB_PERIPHERAL = 4,
>> +};
>> +extern const int pci_config_lib_type;
>> +
>> +/* Configuration library function pointers, these are set in <rtems/confdefs.h>
>> + * by project configuration or by the BSP. The configuration will pull in the
>> + * PCI Library needed and the PCI initialization functions will call these
>> + * functions on initialization from the host driver.
>> + */
>> +extern int (*pci_config_lib_init)(void);
>> +extern void (*pci_config_lib_register)(void *config);
>> +
>> +/* Configure PCI devices and bridges, and setup the RAM data structures
>> + * describing the PCI devices currently present in the system.
>> + *
>> + * Returns 0 on success, -1 on failure.
>> + */
>> +extern int pci_config_init(void);
>> +
>> +/* Register a config-library specific configuration used by the libarary in
>> + * pci_config_init().
>> + */
>> +extern void pci_config_register(void *config);
>> +
>> +/* Print current PCI configuration (C-code) to terminal, can be used in
>> + * static and peripheral PCI configuration library. The configuration is
>> + * taken from the current configuration library setup.
>> + */
>> +extern void pci_cfg_print(void);
>> +
>> +struct pci_bus; /* Bridge Device and secondary bus information */
>> +struct pci_dev; /* Device/function */
>> +struct pci_res; /* Resource: BAR, ROM or Bridge Window */
>> +
>> +/* The Host Bridge and all subdevices (the PCI RAM data structure) */
>> +extern struct pci_bus pci_hb;
>> +
>> +/* Iterate over all PCI devices on a bus (see search options) and call func(),
>> + * iteration is stopped if a non-zero value is returned by func().
>> + *
>> + * The function iterates over the PCI RAM data structure, it is not
>> + * available until after all devices have been found and pci_hb is populated,
>> + * typically after pci_config_init() is called.
>> + *
>> + * search options: 0 (no child buses), 1 (depth first, recursive)
>> + *
>> + * Return Values
>> + *  0  All PCI devices were processed, func() returned 0 on every call
>> + *  X  func() returned non-zero X value, the search was stopped
>> + */
>> +#define SEARCH_DEPTH 1
> does this define need to be here?
>
>> +extern int pci_for_each_child(
>> +       struct pci_bus *bus,
>> +       int (*func)(struct pci_dev *, void *arg),
>> +       void *arg,
>> +       int search);
>> +
>> +/* Depth first search of all PCI devices in PCI RAM data structure and call
>> + * func(dev, arg), iteration is stopped if a non-zero value is returned by
>> + * func().
>> + *
>> + * The function iterates over the PCI RAM data structure, it is not
>> + * available until after all devices have been found and pci_hb is populated,
>> + * typically after pci_config_init() is called.
>> + *
>> + * Return Values
>> + *  0  All PCI devices were processed, func() returned 0 on every call
>> + *  X  func() returned non-zero X value, the search was stopped
>> + */
>> +extern int pci_for_each_dev(
>> +       int (*func)(struct pci_dev *, void *arg),
>> +       void *arg);
>> +
>> +/* Get PCI device from RAM device tree for a device matching PCI Vendor, Device
>> + * and instance number 'index'.
>> + *
>> + * Return Values
>> + * -1  pci_find_dev did not find a device matching the criterion.
>> + *  0  device was found, *ppdev was updated with the PCI device address
>> + */
>> +extern int pci_find_dev(uint16_t ven, uint16_t dev, int index,
>> +                       struct pci_dev **ppdev);
>> +
>> +/* Get PCI device from RAM device tree by BUS|SLOT|FUNC.
>> + *
>> + * Return Values
>> + * -1  pci_get_dev did not find a device matching the criterion
>> + *  0  device was found, *ppdev was updated with the PCI device address
>> + */
>> +extern int pci_get_dev(pci_dev_t pcidev, struct pci_dev **ppdev);
>> +
>> +/* Resource flags */
>> +#define PCI_RES_IO 1
>> +#define PCI_RES_MEMIO 2
>> +#define PCI_RES_MEM_PREFETCH 1
>> +#define PCI_RES_MEM (PCI_RES_MEMIO | PCI_RES_MEM_PREFETCH)
>> +#define PCI_RES_TYPE_MASK 0x3
>> +#define PCI_RES_IO32 0x08
>> +#define PCI_RES_FAIL 0x10 /* Alloc Failed */
>> +
>> +/* BAR Resouces entry */
>> +struct pci_res {
>> +       struct pci_res  *next;
>> +       uint32_t        size;
>> +       uint32_t        boundary;
>> +       unsigned char   flags; /* I/O, MEM or MEMIO */
>> +       unsigned char   bar;
> You define an enum below for this field, maybe it makes sense to use a
> named enum for it?
pci_res.flags relates to the bit-mask defines of PCI_RES_*
Enums are probably avoided to save space with a 8-bit variable.

>
>> +
>> +       /* Assigned Resource (PCI address), zero if not assigned */
>> +       uint32_t        start;
>> +       uint32_t        end;
>> +};
>> +
>> +/* Get Device from resource pointer */
>> +#define RES2DEV(res) ((struct pci_dev *) \
>> +                       ((void *)res - (res->bar * (sizeof(struct pci_res)))))
>> +
> This is tricky and could probably do with a bit more explanation i.e.
> that bar is a "counter" for the resource within the array of
> resources[] located at the start of the pci_dev. Also, we should avoid
> pointer arithmetic on void* type. I'd prefer to see a cast to
> uintptr_t and explicit arithmetic done in terms of bytes. This mixing
> of types in a non-standard way is asking for trouble some day.

Agree. I will change into this if okay?

/* Get Device from resource pointer. bar is the index of the pci_dev.resources
  * array and used to get the device base address of which the resource is
  * associated with.
  */
#define RES2DEV(res) ((struct pci_dev *) \
     ((uintptr_t *)res - (uintptr_t *)(res->bar * (sizeof(struct pci_res)))))


>
>> +/* Device flags */
>> +#define PCI_DEV_BRIDGE    0x01  /* Device is a Bridge (struct pci_bus) */
>> +#define PCI_DEV_RES_FAIL  0x02  /* Resource alloction for device BARs failed */
>> +
>> +/* Bus Flags */
>> +#define PCI_BUS_IO        0x01 /* 16-bit I/O address decoding */
>> +#define PCI_BUS_MEMIO     0x02  /* Bus support non-prefetchable mem (always) */
>> +#define PCI_BUS_MEM       0x04  /* Bus support prefetchable memory space */
>> +#define PCI_BUS_IO32      0x08 /* 32-bit I/O address decoding */
>> +
>> +#define BRIDGE_RES_COUNT 2 /* Number of BAR resources a bridge can have */
>> +#define BUS_RES_START BRIDGE_RES_COUNT
>> +
>> +/* Bus Resources Array */
>> +enum {
>> +       BUS_RES_IO = 0,
>> +       BUS_RES_MEMIO = 1,
>> +       BUS_RES_MEM = 2,
>> +};
>> +
>> +/* Device Resource array index meaning */
>> +enum {
>> +       /* A Device has up to 6 BARs and an optional ROM BAR */
>> +       DEV_RES_BAR1 = 0,
>> +       DEV_RES_BAR2 = 1,
>> +       DEV_RES_BAR3 = 2,
>> +       DEV_RES_BAR4 = 3,
>> +       DEV_RES_BAR5 = 4,
>> +       DEV_RES_BAR6 = 5,
>> +       DEV_RES_ROM  = 6,
>> +
>> +       /* Bridges have 2 BARs (BAR1 and BAR2) and 3 Windows to secondary bus
>> +        * and an optional ROM BAR
>> +        */
>> +       BRIDGE_RES_BAR1 = 0,
>> +       BRIDGE_RES_BAR2 = 1,
>> +       BRIDGE_RES_IO = 2,
>> +       BRIDGE_RES_MEMIO = 3,
>> +       BRIDGE_RES_MEM = 4,
>> +       BRIDGE_RES_UNUSED1 = 5,
>> +       BRIDGE_RES_ROM = 6,
>> +};
>> +
>> +/* Maximum Number of Resources of a device */
>> +#define DEV_RES_CNT (DEV_RES_ROM + 1)
>> +
>> +/* PCI Device (Bus|Slot|Function) description */
>> +struct pci_dev {
>> +       struct pci_res  resources[DEV_RES_CNT]; /* must be topmost field */
>> +       struct pci_dev  *next;
>> +       struct pci_bus  *bus;
>> +       pci_dev_t       busdevfun;
>> +       uint8_t         flags;
>> +       uint8_t         sysirq;
>> +       uint16_t        vendor;
>> +       uint16_t        device;
>> +       uint16_t        subvendor;
>> +       uint16_t        subdevice;
>> +       uint32_t        classrev;
>> +
>> +       /* static configuration settings */
>> +       uint16_t        command;
>> +};
>> +
>> +/* PCI Bus description */
>> +struct pci_bus {
>> +       struct pci_dev  dev; /* PCI Bridge */
>> +       struct pci_dev  *devs; /* Devices on child (secondary) Bus */
>> +       unsigned int    flags;
>> +
>> +       /* Bridge Information */
>> +       int num;        /* Bus number (0=Root-PCI-bus) */
>> +       int pri;        /* Primary Bus Number */
>> +       int sord;       /* Subordinate Buses (Child bus count) */
>> +
>> +#if defined(PCI_CFG_AUTO_LIB)
>> +       /* Resources of devices on bus. USED INTERNALLY IN AUTO-CFG LIBRARY.
>> +        *
>> +        * BUS_RES_IO    = 0:  I/O resources
>> +        * BUS_RES_MEMIO = 1:  Prefetchable memory resources
>> +        * BUS_RES_MEM   = 2:  Non-Prefetchable memory resources
>> +        */
>> +       struct pci_res  *busres[3];
>> +#endif
>> +};
>> +
>> +#include <pci/cfg_auto.h>
>> +#include <pci/cfg_static.h>
>> +#include <pci/cfg_read.h>
>> +#include <pci/cfg_peripheral.h>
>> +
>> +#endif
>> diff --git a/cpukit/libpci/pci/cfg_auto.h b/cpukit/libpci/pci/cfg_auto.h
>> new file mode 100644
>> index 0000000..25e7336
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/cfg_auto.h
>> @@ -0,0 +1,59 @@
>> +/* PCI Auto Configuration Library
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +#ifndef __PCI_CFG_AUTO_H__
>> +#define __PCI_CFG_AUTO_H__
>> +
>> +#define CFGOPT_NOSETUP_IRQ 0x1 /* Skip IRQ setup */
>> +
>> +/* PCI Memory Layout setup, used by the auto-config library in order to
>> + * determine the addresses of PCI BARs and Buses.
>> + *
>> + * All addresses are in PCI address space, the actual address the CPU access
>> + * may be different, and taken care of elsewhere.
>> + */
>> +struct pci_auto_setup {
>> +       int options;
>> +
>> +       /* PCI prefetchable Memory space (OPTIONAL) */
>> +       uint32_t mem_start;
>> +       uint32_t mem_size; /* 0 = Use MEMIO space for prefetchable mem BARs */
>> +
>> +       /* PCI non-prefetchable Memory */
>> +       uint32_t memio_start;
>> +       uint32_t memio_size;
>> +
>> +       /* PCI I/O space (OPTIONAL) */
>> +       uint32_t io_start;
>> +       uint32_t io_size; /* 0 = No I/O space */
>> +
>> +       /* Get System IRQ connected to a PCI line of a PCI device on bus0.
>> +        * The return IRQ value zero equals no IRQ (IRQ disabled).
>> +        */
>> +       uint8_t (*irq_map)(pci_dev_t dev, int irq_pin);
>> +
>> +       /* IRQ Bridge routing. Returns the interrupt pin (0..3 = A..D) that
>> +        * a device is connected to on parent bus.
>> +        */
>> +       int (*irq_route)(pci_dev_t dev, int irq_pin);
>> +};
>> +
>> +/* Do PCI initialization: Enumrate buses, scan buses for devices, assign
>> + * I/O MEM and MEMIO resources, assign IRQ and so on.
>> + */
>> +extern int pci_config_auto(void);
>> +
>> +/* Register a configuration for the auto library (struct pci_auto_setup *) */
>> +extern void pci_config_auto_register(void *config);
>> +
>> +/* PCI memory map */
>> +extern struct pci_auto_setup pci_auto_cfg;
>> +
>> +#endif
>> diff --git a/cpukit/libpci/pci/cfg_peripheral.h b/cpukit/libpci/pci/cfg_peripheral.h
>> new file mode 100644
>> index 0000000..68f2e24
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/cfg_peripheral.h
>> @@ -0,0 +1,20 @@
>> +/* PCI Peripheral Configuration Library
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +#ifndef __PCI_CFG_PERIPHERAL_H__
>> +#define __PCI_CFG_PERIPHERAL_H__
>> +
>> +/* The user must provide a PCI configuration using the "struct pci_bus pci_hb"
>> + * structure. Nothing else than setting pci_system_type and pci_bus_cnt is done
>> + * by the peripheral library.
>> + */
>> +extern int pci_config_peripheral(void);
>> +
>> +#endif
>> diff --git a/cpukit/libpci/pci/cfg_read.h b/cpukit/libpci/pci/cfg_read.h
>> new file mode 100644
>> index 0000000..af60a4e
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/cfg_read.h
>> @@ -0,0 +1,22 @@
>> +/* PCI Read Configuration Library. Read current config that bootloader/BIOS
>> + * has setup.
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +
>> +#ifndef __PCI_CFG_READ_H__
>> +#define __PCI_CFG_READ_H__
>> +
>> +/* Build PCI device tree in "struct pci_bus pci_hb" according to current setup
>> + * in hardware. Devices/buses are created by reading the resource assignments
>> + * that the BIOS/bootloader has already setup for us.
>> + */
>> +extern int pci_config_read(void);
>> +
>> +#endif
>> diff --git a/cpukit/libpci/pci/cfg_static.h b/cpukit/libpci/pci/cfg_static.h
>> new file mode 100644
>> index 0000000..5633dfc
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/cfg_static.h
>> @@ -0,0 +1,22 @@
>> +/* Static PCI Auto Configuration Library
>> + *
>> + * COPYRIGHT (c) 2010.
>> + * Cobham Gaisler AB.
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.com/license/LICENSE.
>> + */
>> +
>> +#ifndef __PCI_CFG_STATIC_H__
>> +#define __PCI_CFG_STATIC_H__
>> +
>> +/* This function initializes all buses and device accorind to a user defined
>> + * "static" configuration. The configuration can manually created with C
>> + * data structures. Or it can be automatically created on a running target
>> + * using the pci_cfg_print() routine after the AUTO or READ Configuration
>> + * Library has setup the PCI bus
>> + */
>> +extern int pci_config_static(void);
>> +
>> +#endif
>> diff --git a/cpukit/libpci/pci/ids.h b/cpukit/libpci/pci/ids.h
>> new file mode 100644
>> index 0000000..2d2592b
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/ids.h
>> @@ -0,0 +1,802 @@
>> +/* PCI Identifiers - auto generated */
> What is it gerenated from and how/when to regenerate it?
I'm not sure, it was taken from cpukit/include/rtems/pci.h. Perhaps there is a script in FreeBSD that can be utilized to extract the IDs from the public PCI PnP database. The IDs are not important for 
the library. I have separated them to allow it to be auto updated.

>> +#ifndef __PCI_IDS_H__
>> +#define __PCI_IDS_H__
>> +
>> +/* Include non-public PCI ids (not auto generated) */
>> +#include <pci/ids_extra.h>
>> +
>> +/* Not a valid ID, used to match any device ID */
>> +#define PCI_ID_ANY 0xffff
>> +
>> +/*
>> + * Vendor and card ID's: sort these numerically according to vendor
>> + * (and according to card ID within vendor). Send all updates to
>> + * <linux-pcisupport at cck.uni-kl.de>.
>> + */
>> +#define PCI_VENDOR_ID_COMPAQ           0x0e11
>> +#define PCI_DEVICE_ID_COMPAQ_1280      0x3033
>> +#define PCI_DEVICE_ID_COMPAQ_TRIFLEX   0x4000
>> +#define PCI_DEVICE_ID_COMPAQ_SMART2P   0xae10
>> +#define PCI_DEVICE_ID_COMPAQ_NETEL100  0xae32
>> +#define PCI_DEVICE_ID_COMPAQ_NETEL10   0xae34
>> +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I 0xae35
>> +#define PCI_DEVICE_ID_COMPAQ_NETEL100D 0xae40
>> +#define PCI_DEVICE_ID_COMPAQ_NETEL100PI        0xae43
>> +#define PCI_DEVICE_ID_COMPAQ_NETEL100I 0xb011
>> +#define PCI_DEVICE_ID_COMPAQ_THUNDER   0xf130
>> +#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B 0xf150
>> +
>> +#define PCI_VENDOR_ID_NCR              0x1000
>> +#define PCI_DEVICE_ID_NCR_53C810       0x0001
>> +#define PCI_DEVICE_ID_NCR_53C820       0x0002
>> +#define PCI_DEVICE_ID_NCR_53C825       0x0003
>> +#define PCI_DEVICE_ID_NCR_53C815       0x0004
>> +#define PCI_DEVICE_ID_NCR_53C860       0x0006
>> +#define PCI_DEVICE_ID_NCR_53C896       0x000b
>> +#define PCI_DEVICE_ID_NCR_53C895       0x000c
>> +#define PCI_DEVICE_ID_NCR_53C885       0x000d
>> +#define PCI_DEVICE_ID_NCR_53C875       0x000f
>> +#define PCI_DEVICE_ID_NCR_53C875J      0x008f
>> +
>> +#define PCI_VENDOR_ID_ATI              0x1002
>> +#define PCI_DEVICE_ID_ATI_68800                0x4158
>> +#define PCI_DEVICE_ID_ATI_215CT222     0x4354
>> +#define PCI_DEVICE_ID_ATI_210888CX     0x4358
>> +#define PCI_DEVICE_ID_ATI_215GB                0x4742
>> +#define PCI_DEVICE_ID_ATI_215GD                0x4744
>> +#define PCI_DEVICE_ID_ATI_215GI                0x4749
>> +#define PCI_DEVICE_ID_ATI_215GP                0x4750
>> +#define PCI_DEVICE_ID_ATI_215GQ                0x4751
>> +#define PCI_DEVICE_ID_ATI_215GT                0x4754
>> +#define PCI_DEVICE_ID_ATI_215GTB       0x4755
>> +#define PCI_DEVICE_ID_ATI_210888GX     0x4758
>> +#define PCI_DEVICE_ID_ATI_215LG                0x4c47
>> +#define PCI_DEVICE_ID_ATI_264LT                0x4c54
>> +#define PCI_DEVICE_ID_ATI_264VT                0x5654
>> +
>> +#define PCI_VENDOR_ID_VLSI             0x1004
>> +#define PCI_DEVICE_ID_VLSI_82C592      0x0005
>> +#define PCI_DEVICE_ID_VLSI_82C593      0x0006
>> +#define PCI_DEVICE_ID_VLSI_82C594      0x0007
>> +#define PCI_DEVICE_ID_VLSI_82C597      0x0009
>> +#define PCI_DEVICE_ID_VLSI_82C541      0x000c
>> +#define PCI_DEVICE_ID_VLSI_82C543      0x000d
>> +#define PCI_DEVICE_ID_VLSI_82C532      0x0101
>> +#define PCI_DEVICE_ID_VLSI_82C534      0x0102
>> +#define PCI_DEVICE_ID_VLSI_82C535      0x0104
>> +#define PCI_DEVICE_ID_VLSI_82C147      0x0105
>> +#define PCI_DEVICE_ID_VLSI_VAS96011    0x0702
>> +
>> +#define PCI_VENDOR_ID_ADL              0x1005
>> +#define PCI_DEVICE_ID_ADL_2301         0x2301
>> +
>> +#define PCI_VENDOR_ID_NS               0x100b
>> +#define PCI_DEVICE_ID_NS_87415         0x0002
>> +#define PCI_DEVICE_ID_NS_87410         0xd001
>> +
>> +#define PCI_VENDOR_ID_TSENG            0x100c
>> +#define PCI_DEVICE_ID_TSENG_W32P_2     0x3202
>> +#define PCI_DEVICE_ID_TSENG_W32P_b     0x3205
>> +#define PCI_DEVICE_ID_TSENG_W32P_c     0x3206
>> +#define PCI_DEVICE_ID_TSENG_W32P_d     0x3207
>> +#define PCI_DEVICE_ID_TSENG_ET6000     0x3208
>> +
>> +#define PCI_VENDOR_ID_WEITEK           0x100e
>> +#define PCI_DEVICE_ID_WEITEK_P9000     0x9001
>> +#define PCI_DEVICE_ID_WEITEK_P9100     0x9100
>> +
>> +#define PCI_VENDOR_ID_DEC              0x1011
>> +#define PCI_DEVICE_ID_DEC_BRD          0x0001
>> +#define PCI_DEVICE_ID_DEC_TULIP                0x0002
>> +#define PCI_DEVICE_ID_DEC_TGA          0x0004
>> +#define PCI_DEVICE_ID_DEC_TULIP_FAST   0x0009
>> +#define PCI_DEVICE_ID_DEC_TGA2         0x000D
>> +#define PCI_DEVICE_ID_DEC_FDDI         0x000F
>> +#define PCI_DEVICE_ID_DEC_TULIP_PLUS   0x0014
>> +#define PCI_DEVICE_ID_DEC_21142                0x0019
>> +#define PCI_DEVICE_ID_DEC_21052                0x0021
>> +#define PCI_DEVICE_ID_DEC_21150                0x0022
>> +#define PCI_DEVICE_ID_DEC_21152                0x0024
>> +
>> +#define PCI_VENDOR_ID_CIRRUS           0x1013
>> +#define PCI_DEVICE_ID_CIRRUS_7548      0x0038
>> +#define PCI_DEVICE_ID_CIRRUS_5430      0x00a0
>> +#define PCI_DEVICE_ID_CIRRUS_5434_4    0x00a4
>> +#define PCI_DEVICE_ID_CIRRUS_5434_8    0x00a8
>> +#define PCI_DEVICE_ID_CIRRUS_5436      0x00ac
>> +#define PCI_DEVICE_ID_CIRRUS_5446      0x00b8
>> +#define PCI_DEVICE_ID_CIRRUS_5480      0x00bc
>> +#define PCI_DEVICE_ID_CIRRUS_5464      0x00d4
>> +#define PCI_DEVICE_ID_CIRRUS_5465      0x00d6
>> +#define PCI_DEVICE_ID_CIRRUS_6729      0x1100
>> +#define PCI_DEVICE_ID_CIRRUS_6832      0x1110
>> +#define PCI_DEVICE_ID_CIRRUS_7542      0x1200
>> +#define PCI_DEVICE_ID_CIRRUS_7543      0x1202
>> +#define PCI_DEVICE_ID_CIRRUS_7541      0x1204
>> +
>> +#define PCI_VENDOR_ID_IBM              0x1014
>> +#define PCI_DEVICE_ID_IBM_FIRE_CORAL   0x000a
>> +#define PCI_DEVICE_ID_IBM_TR           0x0018
>> +#define PCI_DEVICE_ID_IBM_82G2675      0x001d
>> +#define PCI_DEVICE_ID_IBM_MCA          0x0020
>> +#define PCI_DEVICE_ID_IBM_82351                0x0022
>> +#define PCI_DEVICE_ID_IBM_SERVERAID    0x002e
>> +#define PCI_DEVICE_ID_IBM_TR_WAKE      0x003e
>> +#define PCI_DEVICE_ID_IBM_MPIC         0x0046
>> +#define PCI_DEVICE_ID_IBM_3780IDSP     0x007d
>> +#define PCI_DEVICE_ID_IBM_MPIC_2       0xffff
>> +
>> +#define PCI_VENDOR_ID_WD               0x101c
>> +#define PCI_DEVICE_ID_WD_7197          0x3296
>> +
>> +#define PCI_VENDOR_ID_AMD              0x1022
>> +#define PCI_DEVICE_ID_AMD_LANCE                0x2000
>> +#define PCI_DEVICE_ID_AMD_SCSI         0x2020
>> +
>> +#define PCI_VENDOR_ID_TRIDENT          0x1023
>> +#define PCI_DEVICE_ID_TRIDENT_9397     0x9397
>> +#define PCI_DEVICE_ID_TRIDENT_9420     0x9420
>> +#define PCI_DEVICE_ID_TRIDENT_9440     0x9440
>> +#define PCI_DEVICE_ID_TRIDENT_9660     0x9660
>> +#define PCI_DEVICE_ID_TRIDENT_9750     0x9750
>> +
>> +#define PCI_VENDOR_ID_AI               0x1025
>> +#define PCI_DEVICE_ID_AI_M1435         0x1435
>> +
>> +#define PCI_VENDOR_ID_MATROX           0x102B
>> +#define PCI_DEVICE_ID_MATROX_MGA_2     0x0518
>> +#define PCI_DEVICE_ID_MATROX_MIL       0x0519
>> +#define PCI_DEVICE_ID_MATROX_MYS       0x051A
>> +#define PCI_DEVICE_ID_MATROX_MIL_2     0x051b
>> +#define PCI_DEVICE_ID_MATROX_MIL_2_AGP 0x051f
>> +#define PCI_DEVICE_ID_MATROX_MGA_IMP   0x0d10
>> +
>> +#define PCI_VENDOR_ID_CT               0x102c
>> +#define PCI_DEVICE_ID_CT_65545         0x00d8
>> +#define PCI_DEVICE_ID_CT_65548         0x00dc
>> +#define PCI_DEVICE_ID_CT_65550         0x00e0
>> +#define PCI_DEVICE_ID_CT_65554         0x00e4
>> +#define PCI_DEVICE_ID_CT_65555         0x00e5
>> +
>> +#define PCI_VENDOR_ID_MIRO             0x1031
>> +#define PCI_DEVICE_ID_MIRO_36050       0x5601
>> +
>> +#define PCI_VENDOR_ID_NEC              0x1033
>> +#define PCI_DEVICE_ID_NEC_PCX2         0x0046
>> +
>> +#define PCI_VENDOR_ID_FD               0x1036
>> +#define PCI_DEVICE_ID_FD_36C70         0x0000
>> +
>> +#define PCI_VENDOR_ID_SI               0x1039
>> +#define PCI_DEVICE_ID_SI_5591_AGP      0x0001
>> +#define PCI_DEVICE_ID_SI_6202          0x0002
>> +#define PCI_DEVICE_ID_SI_503           0x0008
>> +#define PCI_DEVICE_ID_SI_ACPI          0x0009
>> +#define PCI_DEVICE_ID_SI_5597_VGA      0x0200
>> +#define PCI_DEVICE_ID_SI_6205          0x0205
>> +#define PCI_DEVICE_ID_SI_501           0x0406
>> +#define PCI_DEVICE_ID_SI_496           0x0496
>> +#define PCI_DEVICE_ID_SI_601           0x0601
>> +#define PCI_DEVICE_ID_SI_5107          0x5107
>> +#define PCI_DEVICE_ID_SI_5511          0x5511
>> +#define PCI_DEVICE_ID_SI_5513          0x5513
>> +#define PCI_DEVICE_ID_SI_5571          0x5571
>> +#define PCI_DEVICE_ID_SI_5591          0x5591
>> +#define PCI_DEVICE_ID_SI_5597          0x5597
>> +#define PCI_DEVICE_ID_SI_7001          0x7001
>> +
>> +#define PCI_VENDOR_ID_HP               0x103c
>> +#define PCI_DEVICE_ID_HP_J2585A                0x1030
>> +#define PCI_DEVICE_ID_HP_J2585B                0x1031
>> +
>> +#define PCI_VENDOR_ID_PCTECH           0x1042
>> +#define PCI_DEVICE_ID_PCTECH_RZ1000    0x1000
>> +#define PCI_DEVICE_ID_PCTECH_RZ1001    0x1001
>> +#define PCI_DEVICE_ID_PCTECH_SAMURAI_0 0x3000
>> +#define PCI_DEVICE_ID_PCTECH_SAMURAI_1 0x3010
>> +#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
>> +
>> +#define PCI_VENDOR_ID_DPT               0x1044
>> +#define PCI_DEVICE_ID_DPT               0xa400
>> +
>> +#define PCI_VENDOR_ID_OPTI             0x1045
>> +#define PCI_DEVICE_ID_OPTI_92C178      0xc178
>> +#define PCI_DEVICE_ID_OPTI_82C557      0xc557
>> +#define PCI_DEVICE_ID_OPTI_82C558      0xc558
>> +#define PCI_DEVICE_ID_OPTI_82C621      0xc621
>> +#define PCI_DEVICE_ID_OPTI_82C700      0xc700
>> +#define PCI_DEVICE_ID_OPTI_82C701      0xc701
>> +#define PCI_DEVICE_ID_OPTI_82C814      0xc814
>> +#define PCI_DEVICE_ID_OPTI_82C822      0xc822
>> +#define PCI_DEVICE_ID_OPTI_82C825      0xd568
>> +
>> +#define PCI_VENDOR_ID_SGS              0x104a
>> +#define PCI_DEVICE_ID_SGS_2000         0x0008
>> +#define PCI_DEVICE_ID_SGS_1764         0x0009
>> +
>> +#define PCI_VENDOR_ID_BUSLOGIC               0x104B
>> +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
>> +#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
>> +#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
>> +
>> +#define PCI_VENDOR_ID_TI               0x104c
>> +#define PCI_DEVICE_ID_TI_TVP4010       0x3d04
>> +#define PCI_DEVICE_ID_TI_TVP4020       0x3d07
>> +#define PCI_DEVICE_ID_TI_PCI1130       0xac12
>> +#define PCI_DEVICE_ID_TI_PCI1031       0xac13
>> +#define PCI_DEVICE_ID_TI_PCI1131       0xac15
>> +#define PCI_DEVICE_ID_TI_PCI1250       0xac16
>> +#define PCI_DEVICE_ID_TI_PCI1220       0xac17
>> +
>> +#define PCI_VENDOR_ID_OAK              0x104e
>> +#define PCI_DEVICE_ID_OAK_OTI107       0x0107
>> +
>> +/* Winbond have two vendor IDs! See 0x10ad as well */
>> +#define PCI_VENDOR_ID_WINBOND2         0x1050
>> +#define PCI_DEVICE_ID_WINBOND2_89C940  0x0940
>> +
>> +#define PCI_VENDOR_ID_MOTOROLA         0x1057
>> +#define PCI_DEVICE_ID_MOTOROLA_MPC105  0x0001
>> +#define PCI_DEVICE_ID_MOTOROLA_MPC106  0x0002
>> +#define PCI_DEVICE_ID_MOTOROLA_RAVEN   0x4801
>> +
>> +#define PCI_VENDOR_ID_PROMISE          0x105a
>> +#define PCI_DEVICE_ID_PROMISE_20246    0x4d33
>> +#define PCI_DEVICE_ID_PROMISE_5300     0x5300
>> +
>> +#define PCI_VENDOR_ID_N9               0x105d
>> +#define PCI_DEVICE_ID_N9_I128          0x2309
>> +#define PCI_DEVICE_ID_N9_I128_2                0x2339
>> +#define PCI_DEVICE_ID_N9_I128_T2R      0x493d
>> +
>> +#define PCI_VENDOR_ID_UMC              0x1060
>> +#define PCI_DEVICE_ID_UMC_UM8673F      0x0101
>> +#define PCI_DEVICE_ID_UMC_UM8891A      0x0891
>> +#define PCI_DEVICE_ID_UMC_UM8886BF     0x673a
>> +#define PCI_DEVICE_ID_UMC_UM8886A      0x886a
>> +#define PCI_DEVICE_ID_UMC_UM8881F      0x8881
>> +#define PCI_DEVICE_ID_UMC_UM8886F      0x8886
>> +#define PCI_DEVICE_ID_UMC_UM9017F      0x9017
>> +#define PCI_DEVICE_ID_UMC_UM8886N      0xe886
>> +#define PCI_DEVICE_ID_UMC_UM8891N      0xe891
>> +
>> +#define PCI_VENDOR_ID_X                        0x1061
>> +#define PCI_DEVICE_ID_X_AGX016         0x0001
>> +
>> +#define PCI_VENDOR_ID_PICOP            0x1066
>> +#define PCI_DEVICE_ID_PICOP_PT86C52X   0x0001
>> +#define PCI_DEVICE_ID_PICOP_PT80C524   0x8002
>> +
>> +#define PCI_VENDOR_ID_APPLE            0x106b
>> +#define PCI_DEVICE_ID_APPLE_BANDIT     0x0001
>> +#define PCI_DEVICE_ID_APPLE_GC         0x0002
>> +#define PCI_DEVICE_ID_APPLE_HYDRA      0x000e
>> +
>> +#define PCI_VENDOR_ID_NEXGEN           0x1074
>> +#define PCI_DEVICE_ID_NEXGEN_82C501    0x4e78
>> +
>> +#define PCI_VENDOR_ID_QLOGIC           0x1077
>> +#define PCI_DEVICE_ID_QLOGIC_ISP1020   0x1020
>> +#define PCI_DEVICE_ID_QLOGIC_ISP1022   0x1022
>> +
>> +#define PCI_VENDOR_ID_CYRIX            0x1078
>> +#define PCI_DEVICE_ID_CYRIX_5510       0x0000
>> +#define PCI_DEVICE_ID_CYRIX_PCI_MASTER 0x0001
>> +#define PCI_DEVICE_ID_CYRIX_5520       0x0002
>> +#define PCI_DEVICE_ID_CYRIX_5530_LEGACY        0x0100
>> +#define PCI_DEVICE_ID_CYRIX_5530_SMI   0x0101
>> +#define PCI_DEVICE_ID_CYRIX_5530_IDE   0x0102
>> +#define PCI_DEVICE_ID_CYRIX_5530_AUDIO 0x0103
>> +#define PCI_DEVICE_ID_CYRIX_5530_VIDEO 0x0104
>> +
>> +#define PCI_VENDOR_ID_LEADTEK          0x107d
>> +#define PCI_DEVICE_ID_LEADTEK_805      0x0000
>> +
>> +#define PCI_VENDOR_ID_CONTAQ           0x1080
>> +#define PCI_DEVICE_ID_CONTAQ_82C599    0x0600
>> +#define PCI_DEVICE_ID_CONTAQ_82C693    0xc693
>> +
>> +#define PCI_VENDOR_ID_FOREX            0x1083
>> +
>> +#define PCI_VENDOR_ID_OLICOM           0x108d
>> +#define PCI_DEVICE_ID_OLICOM_OC3136    0x0001
>> +#define PCI_DEVICE_ID_OLICOM_OC2315    0x0011
>> +#define PCI_DEVICE_ID_OLICOM_OC2325    0x0012
>> +#define PCI_DEVICE_ID_OLICOM_OC2183    0x0013
>> +#define PCI_DEVICE_ID_OLICOM_OC2326    0x0014
>> +#define PCI_DEVICE_ID_OLICOM_OC6151    0x0021
>> +
>> +#define PCI_VENDOR_ID_SUN              0x108e
>> +#define PCI_DEVICE_ID_SUN_EBUS         0x1000
>> +#define PCI_DEVICE_ID_SUN_HAPPYMEAL    0x1001
>> +#define PCI_DEVICE_ID_SUN_SIMBA                0x5000
>> +#define PCI_DEVICE_ID_SUN_PBM          0x8000
>> +#define PCI_DEVICE_ID_SUN_SABRE                0xa000
>> +
>> +#define PCI_VENDOR_ID_CMD              0x1095
>> +#define PCI_DEVICE_ID_CMD_640          0x0640
>> +#define PCI_DEVICE_ID_CMD_643          0x0643
>> +#define PCI_DEVICE_ID_CMD_646          0x0646
>> +#define PCI_DEVICE_ID_CMD_647          0x0647
>> +#define PCI_DEVICE_ID_CMD_670          0x0670
>> +
>> +#define PCI_VENDOR_ID_VISION           0x1098
>> +#define PCI_DEVICE_ID_VISION_QD8500    0x0001
>> +#define PCI_DEVICE_ID_VISION_QD8580    0x0002
>> +
>> +#define PCI_VENDOR_ID_BROOKTREE                0x109e
>> +#define PCI_DEVICE_ID_BROOKTREE_848    0x0350
>> +#define PCI_DEVICE_ID_BROOKTREE_849A   0x0351
>> +#define PCI_DEVICE_ID_BROOKTREE_8474   0x8474
>> +
>> +#define PCI_VENDOR_ID_SIERRA           0x10a8
>> +#define PCI_DEVICE_ID_SIERRA_STB       0x0000
>> +
>> +#define PCI_VENDOR_ID_ACC              0x10aa
>> +#define PCI_DEVICE_ID_ACC_2056         0x0000
>> +
>> +#define PCI_VENDOR_ID_WINBOND          0x10ad
>> +#define PCI_DEVICE_ID_WINBOND_83769    0x0001
>> +#define PCI_DEVICE_ID_WINBOND_82C105   0x0105
>> +#define PCI_DEVICE_ID_WINBOND_83C553   0x0565
>> +
>> +#define PCI_VENDOR_ID_DATABOOK         0x10b3
>> +#define PCI_DEVICE_ID_DATABOOK_87144   0xb106
>> +
>> +#define PCI_VENDOR_ID_PLX              0x10b5
>> +#define PCI_DEVICE_ID_PLX_9050         0x9050
>> +#define PCI_DEVICE_ID_PLX_9060         0x9060
>> +#define PCI_DEVICE_ID_PLX_9060ES       0x906E
>> +#define PCI_DEVICE_ID_PLX_9060SD       0x906D
>> +#define PCI_DEVICE_ID_PLX_9080         0x9080
>> +
>> +#define PCI_VENDOR_ID_MADGE            0x10b6
>> +#define PCI_DEVICE_ID_MADGE_MK2                0x0002
>> +#define PCI_DEVICE_ID_MADGE_C155S      0x1001
>> +
>> +#define PCI_VENDOR_ID_3COM             0x10b7
>> +#define PCI_DEVICE_ID_3COM_3C339       0x3390
>> +#define PCI_DEVICE_ID_3COM_3C590       0x5900
>> +#define PCI_DEVICE_ID_3COM_3C595TX     0x5950
>> +#define PCI_DEVICE_ID_3COM_3C595T4     0x5951
>> +#define PCI_DEVICE_ID_3COM_3C595MII    0x5952
>> +#define PCI_DEVICE_ID_3COM_3C900TPO    0x9000
>> +#define PCI_DEVICE_ID_3COM_3C900COMBO  0x9001
>> +#define PCI_DEVICE_ID_3COM_3C905TX     0x9050
>> +#define PCI_DEVICE_ID_3COM_3C905T4     0x9051
>> +#define PCI_DEVICE_ID_3COM_3C905B_TX   0x9055
>> +
>> +#define PCI_VENDOR_ID_SMC              0x10b8
>> +#define PCI_DEVICE_ID_SMC_EPIC100      0x0005
>> +
>> +#define PCI_VENDOR_ID_AL               0x10b9
>> +#define PCI_DEVICE_ID_AL_M1445         0x1445
>> +#define PCI_DEVICE_ID_AL_M1449         0x1449
>> +#define PCI_DEVICE_ID_AL_M1451         0x1451
>> +#define PCI_DEVICE_ID_AL_M1461         0x1461
>> +#define PCI_DEVICE_ID_AL_M1489         0x1489
>> +#define PCI_DEVICE_ID_AL_M1511         0x1511
>> +#define PCI_DEVICE_ID_AL_M1513         0x1513
>> +#define PCI_DEVICE_ID_AL_M1521         0x1521
>> +#define PCI_DEVICE_ID_AL_M1523         0x1523
>> +#define PCI_DEVICE_ID_AL_M1531         0x1531
>> +#define PCI_DEVICE_ID_AL_M1533         0x1533
>> +#define PCI_DEVICE_ID_AL_M3307         0x3307
>> +#define PCI_DEVICE_ID_AL_M4803         0x5215
>> +#define PCI_DEVICE_ID_AL_M5219         0x5219
>> +#define PCI_DEVICE_ID_AL_M5229         0x5229
>> +#define PCI_DEVICE_ID_AL_M5237         0x5237
>> +#define PCI_DEVICE_ID_AL_M7101         0x7101
>> +
>> +#define PCI_VENDOR_ID_MITSUBISHI       0x10ba
>> +
>> +#define PCI_VENDOR_ID_SURECOM          0x10bd
>> +#define PCI_DEVICE_ID_SURECOM_NE34     0x0e34
>> +
>> +#define PCI_VENDOR_ID_NEOMAGIC          0x10c8
>> +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
>> +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
>> +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
>> +#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
>> +
>> +#define PCI_VENDOR_ID_ASP              0x10cd
>> +#define PCI_DEVICE_ID_ASP_ABP940       0x1200
>> +#define PCI_DEVICE_ID_ASP_ABP940U      0x1300
>> +#define PCI_DEVICE_ID_ASP_ABP940UW     0x2300
>> +
>> +#define PCI_VENDOR_ID_MACRONIX         0x10d9
>> +#define PCI_DEVICE_ID_MACRONIX_MX98713 0x0512
>> +#define PCI_DEVICE_ID_MACRONIX_MX987x5 0x0531
>> +
>> +#define PCI_VENDOR_ID_CERN             0x10dc
>> +#define PCI_DEVICE_ID_CERN_SPSB_PMC    0x0001
>> +#define PCI_DEVICE_ID_CERN_SPSB_PCI    0x0002
>> +#define PCI_DEVICE_ID_CERN_HIPPI_DST   0x0021
>> +#define PCI_DEVICE_ID_CERN_HIPPI_SRC   0x0022
>> +
>> +#define PCI_VENDOR_ID_NVIDIA           0x10de
>> +
>> +#define PCI_VENDOR_ID_IMS              0x10e0
>> +#define PCI_DEVICE_ID_IMS_8849         0x8849
>> +
>> +#define PCI_VENDOR_ID_TEKRAM2          0x10e1
>> +#define PCI_DEVICE_ID_TEKRAM2_690c     0x690c
>> +
>> +#define PCI_VENDOR_ID_TUNDRA           0x10e3
>> +#define PCI_DEVICE_ID_TUNDRA_CA91C042  0x0000
>> +
>> +#define PCI_VENDOR_ID_AMCC             0x10e8
>> +#define PCI_DEVICE_ID_AMCC_MYRINET     0x8043
>> +#define PCI_DEVICE_ID_AMCC_PARASTATION 0x8062
>> +#define PCI_DEVICE_ID_AMCC_S5933       0x807d
>> +#define PCI_DEVICE_ID_AMCC_S5933_HEPC3 0x809c
>> +
>> +#define PCI_VENDOR_ID_INTERG           0x10ea
>> +#define PCI_DEVICE_ID_INTERG_1680      0x1680
>> +#define PCI_DEVICE_ID_INTERG_1682      0x1682
>> +
>> +#define PCI_VENDOR_ID_REALTEK          0x10ec
>> +#define PCI_DEVICE_ID_REALTEK_8029     0x8029
>> +#define PCI_DEVICE_ID_REALTEK_8129     0x8129
>> +#define PCI_DEVICE_ID_REALTEK_8139     0x8139
>> +
>> +#define PCI_VENDOR_ID_TRUEVISION       0x10fa
>> +#define PCI_DEVICE_ID_TRUEVISION_T1000 0x000c
>> +
>> +#define PCI_VENDOR_ID_INIT             0x1101
>> +#define PCI_DEVICE_ID_INIT_320P                0x9100
>> +#define PCI_DEVICE_ID_INIT_360P                0x9500
>> +
>> +#define PCI_VENDOR_ID_TTI              0x1103
>> +#define PCI_DEVICE_ID_TTI_HPT343       0x0003
>> +
>> +#define PCI_VENDOR_ID_VIA              0x1106
>> +#define PCI_DEVICE_ID_VIA_82C505       0x0505
>> +#define PCI_DEVICE_ID_VIA_82C561       0x0561
>> +#define PCI_DEVICE_ID_VIA_82C586_1     0x0571
>> +#define PCI_DEVICE_ID_VIA_82C576       0x0576
>> +#define PCI_DEVICE_ID_VIA_82C585       0x0585
>> +#define PCI_DEVICE_ID_VIA_82C586_0     0x0586
>> +#define PCI_DEVICE_ID_VIA_82C595       0x0595
>> +#define PCI_DEVICE_ID_VIA_82C597_0     0x0597
>> +#define PCI_DEVICE_ID_VIA_82C926       0x0926
>> +#define PCI_DEVICE_ID_VIA_82C416       0x1571
>> +#define PCI_DEVICE_ID_VIA_82C595_97    0x1595
>> +#define PCI_DEVICE_ID_VIA_82C586_2     0x3038
>> +#define PCI_DEVICE_ID_VIA_82C586_3     0x3040
>> +#define PCI_DEVICE_ID_VIA_86C100A      0x6100
>> +#define PCI_DEVICE_ID_VIA_82C597_1     0x8597
>> +
>> +#define PCI_VENDOR_ID_VORTEX           0x1119
>> +#define PCI_DEVICE_ID_VORTEX_GDT60x0   0x0000
>> +#define PCI_DEVICE_ID_VORTEX_GDT6000B  0x0001
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x10   0x0002
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x20   0x0003
>> +#define PCI_DEVICE_ID_VORTEX_GDT6530   0x0004
>> +#define PCI_DEVICE_ID_VORTEX_GDT6550   0x0005
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x17   0x0006
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x27   0x0007
>> +#define PCI_DEVICE_ID_VORTEX_GDT6537   0x0008
>> +#define PCI_DEVICE_ID_VORTEX_GDT6557   0x0009
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x15   0x000a
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x25   0x000b
>> +#define PCI_DEVICE_ID_VORTEX_GDT6535   0x000c
>> +#define PCI_DEVICE_ID_VORTEX_GDT6555   0x000d
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x0100
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x0101
>> +#define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x0102
>> +#define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x0103
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x0104
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x0105
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1        0x0110
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1        0x0111
>> +#define PCI_DEVICE_ID_VORTEX_GDT6537RP1        0x0112
>> +#define PCI_DEVICE_ID_VORTEX_GDT6557RP1        0x0113
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1        0x0114
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1        0x0115
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2        0x0120
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2        0x0121
>> +#define PCI_DEVICE_ID_VORTEX_GDT6537RP2        0x0122
>> +#define PCI_DEVICE_ID_VORTEX_GDT6557RP2        0x0123
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2        0x0124
>> +#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2        0x0125
>> +
>> +#define PCI_VENDOR_ID_EF               0x111a
>> +#define PCI_DEVICE_ID_EF_ATM_FPGA      0x0000
>> +#define PCI_DEVICE_ID_EF_ATM_ASIC      0x0002
>> +
>> +#define PCI_VENDOR_ID_FORE             0x1127
>> +#define PCI_DEVICE_ID_FORE_PCA200PC    0x0210
>> +#define PCI_DEVICE_ID_FORE_PCA200E     0x0300
>> +
>> +#define PCI_VENDOR_ID_IMAGINGTECH      0x112f
>> +#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI        0x0000
>> +
>> +#define PCI_VENDOR_ID_PHILIPS          0x1131
>> +#define PCI_DEVICE_ID_PHILIPS_SAA7145  0x7145
>> +#define PCI_DEVICE_ID_PHILIPS_SAA7146  0x7146
>> +
>> +#define PCI_VENDOR_ID_CYCLONE          0x113c
>> +#define PCI_DEVICE_ID_CYCLONE_SDK      0x0001
>> +
>> +#define PCI_VENDOR_ID_ALLIANCE         0x1142
>> +#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO        0x3210
>> +#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO        0x6422
>> +#define PCI_DEVICE_ID_ALLIANCE_AT24    0x6424
>> +#define PCI_DEVICE_ID_ALLIANCE_AT3D    0x643d
>> +
>> +#define PCI_VENDOR_ID_SK               0x1148
>> +#define PCI_DEVICE_ID_SK_FP            0x4000
>> +#define PCI_DEVICE_ID_SK_TR            0x4200
>> +#define PCI_DEVICE_ID_SK_GE            0x4300
>> +
>> +#define PCI_VENDOR_ID_VMIC             0x114a
>> +#define PCI_DEVICE_ID_VMIC_VME         0x7587
>> +
>> +#define PCI_VENDOR_ID_DIGI             0x114f
>> +#define PCI_DEVICE_ID_DIGI_EPC         0x0002
>> +#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH 0x0003
>> +#define PCI_DEVICE_ID_DIGI_XEM         0x0004
>> +#define PCI_DEVICE_ID_DIGI_XR          0x0005
>> +#define PCI_DEVICE_ID_DIGI_CX          0x0006
>> +#define PCI_DEVICE_ID_DIGI_XRJ         0x0009
>> +#define PCI_DEVICE_ID_DIGI_EPCJ                0x000a
>> +#define PCI_DEVICE_ID_DIGI_XR_920      0x0027
>> +
>> +#define PCI_VENDOR_ID_MUTECH           0x1159
>> +#define PCI_DEVICE_ID_MUTECH_MV1000    0x0001
>> +
>> +#define PCI_VENDOR_ID_RENDITION                0x1163
>> +#define PCI_DEVICE_ID_RENDITION_VERITE 0x0001
>> +#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
>> +
>> +#define PCI_VENDOR_ID_TOSHIBA          0x1179
>> +#define PCI_DEVICE_ID_TOSHIBA_601      0x0601
>> +#define PCI_DEVICE_ID_TOSHIBA_TOPIC95  0x060a
>> +#define PCI_DEVICE_ID_TOSHIBA_TOPIC97  0x060f
>> +
>> +#define PCI_VENDOR_ID_RICOH            0x1180
>> +#define PCI_DEVICE_ID_RICOH_RL5C465    0x0465
>> +#define PCI_DEVICE_ID_RICOH_RL5C466    0x0466
>> +#define PCI_DEVICE_ID_RICOH_RL5C475    0x0475
>> +#define PCI_DEVICE_ID_RICOH_RL5C478    0x0478
>> +
>> +#define PCI_VENDOR_ID_ARTOP            0x1191
>> +#define PCI_DEVICE_ID_ARTOP_ATP8400    0x0004
>> +#define PCI_DEVICE_ID_ARTOP_ATP850UF   0x0005
>> +
>> +#define PCI_VENDOR_ID_ZEITNET          0x1193
>> +#define PCI_DEVICE_ID_ZEITNET_1221     0x0001
>> +#define PCI_DEVICE_ID_ZEITNET_1225     0x0002
>> +
>> +#define PCI_VENDOR_ID_OMEGA            0x119b
>> +#define PCI_DEVICE_ID_OMEGA_82C092G    0x1221
>> +
>> +#define PCI_VENDOR_ID_LITEON           0x11ad
>> +#define PCI_DEVICE_ID_LITEON_LNE100TX  0x0002
>> +
>> +#define PCI_VENDOR_ID_NP               0x11bc
>> +#define PCI_DEVICE_ID_NP_PCI_FDDI      0x0001
>> +
>> +#define PCI_VENDOR_ID_ATT              0x11c1
>> +#define PCI_DEVICE_ID_ATT_L56XMF       0x0440
>> +
>> +#define PCI_VENDOR_ID_SPECIALIX                0x11cb
>> +#define PCI_DEVICE_ID_SPECIALIX_IO8    0x2000
>> +#define PCI_DEVICE_ID_SPECIALIX_XIO    0x4000
>> +#define PCI_DEVICE_ID_SPECIALIX_RIO    0x8000
>> +
>> +#define PCI_VENDOR_ID_AURAVISION       0x11d1
>> +#define PCI_DEVICE_ID_AURAVISION_VXP524        0x01f7
>> +
>> +#define PCI_VENDOR_ID_IKON             0x11d5
>> +#define PCI_DEVICE_ID_IKON_10115       0x0115
>> +#define PCI_DEVICE_ID_IKON_10117       0x0117
>> +
>> +#define PCI_VENDOR_ID_ZORAN            0x11de
>> +#define PCI_DEVICE_ID_ZORAN_36057      0x6057
>> +#define PCI_DEVICE_ID_ZORAN_36120      0x6120
>> +
>> +#define PCI_VENDOR_ID_KINETIC          0x11f4
>> +#define PCI_DEVICE_ID_KINETIC_2915     0x2915
>> +
>> +#define PCI_VENDOR_ID_COMPEX           0x11f6
>> +#define PCI_DEVICE_ID_COMPEX_ENET100VG4        0x0112
>> +#define PCI_DEVICE_ID_COMPEX_RL2000    0x1401
>> +
>> +#define PCI_VENDOR_ID_RP               0x11fe
>> +#define PCI_DEVICE_ID_RP32INTF         0x0001
>> +#define PCI_DEVICE_ID_RP8INTF          0x0002
>> +#define PCI_DEVICE_ID_RP16INTF         0x0003
>> +#define PCI_DEVICE_ID_RP4QUAD         0x0004
>> +#define PCI_DEVICE_ID_RP8OCTA          0x0005
>> +#define PCI_DEVICE_ID_RP8J            0x0006
>> +#define PCI_DEVICE_ID_RPP4            0x000A
>> +#define PCI_DEVICE_ID_RPP8            0x000B
>> +#define PCI_DEVICE_ID_RP8M            0x000C
>> +
>> +#define PCI_VENDOR_ID_CYCLADES         0x120e
>> +#define PCI_DEVICE_ID_CYCLOM_Y_Lo      0x0100
>> +#define PCI_DEVICE_ID_CYCLOM_Y_Hi      0x0101
>> +#define PCI_DEVICE_ID_CYCLOM_Z_Lo      0x0200
>> +#define PCI_DEVICE_ID_CYCLOM_Z_Hi      0x0201
>> +
>> +#define PCI_VENDOR_ID_ESSENTIAL                0x120f
>> +#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER     0x0001
>> +
>> +#define PCI_VENDOR_ID_O2               0x1217
>> +#define PCI_DEVICE_ID_O2_6729          0x6729
>> +#define PCI_DEVICE_ID_O2_6730          0x673a
>> +#define PCI_DEVICE_ID_O2_6832          0x6832
>> +#define PCI_DEVICE_ID_O2_6836          0x6836
>> +
>> +#define PCI_VENDOR_ID_3DFX             0x121a
>> +#define PCI_DEVICE_ID_3DFX_VOODOO      0x0001
>> +#define PCI_DEVICE_ID_3DFX_VOODOO2     0x0002
>> +
>> +#define PCI_VENDOR_ID_SIGMADES         0x1236
>> +#define PCI_DEVICE_ID_SIGMADES_6425    0x6401
>> +
>> +#define PCI_VENDOR_ID_CCUBE            0x123f
>> +
>> +#define PCI_VENDOR_ID_DIPIX            0x1246
>> +
>> +#define PCI_VENDOR_ID_STALLION         0x124d
>> +#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
>> +#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
>> +#define PCI_DEVICE_ID_STALLION_EIOPCI  0x0003
>> +
>> +#define PCI_VENDOR_ID_OPTIBASE         0x1255
>> +#define PCI_DEVICE_ID_OPTIBASE_FORGE   0x1110
>> +#define PCI_DEVICE_ID_OPTIBASE_FUSION  0x1210
>> +#define PCI_DEVICE_ID_OPTIBASE_VPLEX   0x2110
>> +#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC 0x2120
>> +#define PCI_DEVICE_ID_OPTIBASE_VQUEST  0x2130
>> +
>> +#define PCI_VENDOR_ID_SATSAGEM         0x1267
>> +#define PCI_DEVICE_ID_SATSAGEM_PCR2101 0x5352
>> +#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
>> +
>> +#define PCI_VENDOR_ID_HUGHES           0x1273
>> +#define PCI_DEVICE_ID_HUGHES_DIRECPC   0x0002
>> +
>> +#define PCI_VENDOR_ID_ENSONIQ          0x1274
>> +#define PCI_DEVICE_ID_ENSONIQ_AUDIOPCI 0x5000
>> +
>> +#define PCI_VENDOR_ID_ALTEON           0x12ae
>> +#define PCI_DEVICE_ID_ALTEON_ACENIC    0x0001
>> +
>> +#define PCI_VENDOR_ID_PICTUREL         0x12c5
>> +#define PCI_DEVICE_ID_PICTUREL_PCIVST  0x0081
>> +
>> +#define PCI_VENDOR_ID_NVIDIA_SGS       0x12d2
>> +#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
>> +
>> +#define PCI_VENDOR_ID_CBOARDS          0x1307
>> +#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
>> +
>> +#define PCI_VENDOR_ID_SYMPHONY         0x1c1c
>> +#define PCI_DEVICE_ID_SYMPHONY_101     0x0001
>> +
>> +#define PCI_VENDOR_ID_TEKRAM           0x1de1
>> +#define PCI_DEVICE_ID_TEKRAM_DC290     0xdc29
>> +
>> +#define PCI_VENDOR_ID_3DLABS           0x3d3d
>> +#define PCI_DEVICE_ID_3DLABS_300SX     0x0001
>> +#define PCI_DEVICE_ID_3DLABS_500TX     0x0002
>> +#define PCI_DEVICE_ID_3DLABS_DELTA     0x0003
>> +#define PCI_DEVICE_ID_3DLABS_PERMEDIA  0x0004
>> +#define PCI_DEVICE_ID_3DLABS_MX                0x0006
>> +
>> +#define PCI_VENDOR_ID_AVANCE           0x4005
>> +#define PCI_DEVICE_ID_AVANCE_ALG2064   0x2064
>> +#define PCI_DEVICE_ID_AVANCE_2302      0x2302
>> +
>> +#define PCI_VENDOR_ID_NETVIN           0x4a14
>> +#define PCI_DEVICE_ID_NETVIN_NV5000SC  0x5000
>> +
>> +#define PCI_VENDOR_ID_S3               0x5333
>> +#define PCI_DEVICE_ID_S3_PLATO_PXS     0x0551
>> +#define PCI_DEVICE_ID_S3_ViRGE         0x5631
>> +#define PCI_DEVICE_ID_S3_TRIO          0x8811
>> +#define PCI_DEVICE_ID_S3_AURORA64VP    0x8812
>> +#define PCI_DEVICE_ID_S3_TRIO64UVP     0x8814
>> +#define PCI_DEVICE_ID_S3_ViRGE_VX      0x883d
>> +#define PCI_DEVICE_ID_S3_868           0x8880
>> +#define PCI_DEVICE_ID_S3_928           0x88b0
>> +#define PCI_DEVICE_ID_S3_864_1         0x88c0
>> +#define PCI_DEVICE_ID_S3_864_2         0x88c1
>> +#define PCI_DEVICE_ID_S3_964_1         0x88d0
>> +#define PCI_DEVICE_ID_S3_964_2         0x88d1
>> +#define PCI_DEVICE_ID_S3_968           0x88f0
>> +#define PCI_DEVICE_ID_S3_TRIO64V2      0x8901
>> +#define PCI_DEVICE_ID_S3_PLATO_PXG     0x8902
>> +#define PCI_DEVICE_ID_S3_ViRGE_DXGX    0x8a01
>> +#define PCI_DEVICE_ID_S3_ViRGE_GX2     0x8a10
>> +#define PCI_DEVICE_ID_S3_ViRGE_MX      0x8c01
>> +#define PCI_DEVICE_ID_S3_ViRGE_MXP     0x8c02
>> +#define PCI_DEVICE_ID_S3_ViRGE_MXPMV   0x8c03
>> +#define PCI_DEVICE_ID_S3_SONICVIBES    0xca00
>> +
>> +#define PCI_VENDOR_ID_INTEL            0x8086
>> +#define PCI_DEVICE_ID_INTEL_82375      0x0482
>> +#define PCI_DEVICE_ID_INTEL_82424      0x0483
>> +#define PCI_DEVICE_ID_INTEL_82378      0x0484
>> +#define PCI_DEVICE_ID_INTEL_82430      0x0486
>> +#define PCI_DEVICE_ID_INTEL_82434      0x04a3
>> +#define PCI_DEVICE_ID_INTEL_82092AA_0  0x1221
>> +#define PCI_DEVICE_ID_INTEL_82092AA_1  0x1222
>> +#define PCI_DEVICE_ID_INTEL_7116       0x1223
>> +#define PCI_DEVICE_ID_INTEL_82596      0x1226
>> +#define PCI_DEVICE_ID_INTEL_82865      0x1227
>> +#define PCI_DEVICE_ID_INTEL_82557      0x1229
>> +#define PCI_DEVICE_ID_INTEL_82437      0x122d
>> +#define PCI_DEVICE_ID_INTEL_82371FB_0  0x122e
>> +#define PCI_DEVICE_ID_INTEL_82371FB_1  0x1230
>> +#define PCI_DEVICE_ID_INTEL_82371MX    0x1234
>> +#define PCI_DEVICE_ID_INTEL_82437MX    0x1235
>> +#define PCI_DEVICE_ID_INTEL_82441      0x1237
>> +#define PCI_DEVICE_ID_INTEL_82380FB    0x124b
>> +#define PCI_DEVICE_ID_INTEL_82439      0x1250
>> +#define PCI_DEVICE_ID_INTEL_82371SB_0  0x7000
>> +#define PCI_DEVICE_ID_INTEL_82371SB_1  0x7010
>> +#define PCI_DEVICE_ID_INTEL_82371SB_2  0x7020
>> +#define PCI_DEVICE_ID_INTEL_82437VX    0x7030
>> +#define PCI_DEVICE_ID_INTEL_82439TX    0x7100
>> +#define PCI_DEVICE_ID_INTEL_82371AB_0  0x7110
>> +#define PCI_DEVICE_ID_INTEL_82371AB    0x7111
>> +#define PCI_DEVICE_ID_INTEL_82371AB_2  0x7112
>> +#define PCI_DEVICE_ID_INTEL_82371AB_3  0x7113
>> +#define PCI_DEVICE_ID_INTEL_82443LX_0  0x7180
>> +#define PCI_DEVICE_ID_INTEL_82443LX_1  0x7181
>> +#define PCI_DEVICE_ID_INTEL_82443BX_0  0x7190
>> +#define PCI_DEVICE_ID_INTEL_82443BX_1  0x7191
>> +#define PCI_DEVICE_ID_INTEL_82443BX_2  0x7192
>> +#define PCI_DEVICE_ID_INTEL_P6         0x84c4
>> +#define PCI_DEVICE_ID_INTEL_82450GX    0x84c5
>> +
>> +#define PCI_VENDOR_ID_KTI              0x8e2e
>> +#define PCI_DEVICE_ID_KTI_ET32P2       0x3000
>> +
>> +#define PCI_VENDOR_ID_ADAPTEC          0x9004
>> +#define PCI_DEVICE_ID_ADAPTEC_7810     0x1078
>> +#define PCI_DEVICE_ID_ADAPTEC_7850     0x5078
>> +#define PCI_DEVICE_ID_ADAPTEC_7855     0x5578
>> +#define PCI_DEVICE_ID_ADAPTEC_5800     0x5800
>> +#define PCI_DEVICE_ID_ADAPTEC_1480A    0x6075
>> +#define PCI_DEVICE_ID_ADAPTEC_7860     0x6078
>> +#define PCI_DEVICE_ID_ADAPTEC_7861     0x6178
>> +#define PCI_DEVICE_ID_ADAPTEC_7870     0x7078
>> +#define PCI_DEVICE_ID_ADAPTEC_7871     0x7178
>> +#define PCI_DEVICE_ID_ADAPTEC_7872     0x7278
>> +#define PCI_DEVICE_ID_ADAPTEC_7873     0x7378
>> +#define PCI_DEVICE_ID_ADAPTEC_7874     0x7478
>> +#define PCI_DEVICE_ID_ADAPTEC_7895     0x7895
>> +#define PCI_DEVICE_ID_ADAPTEC_7880     0x8078
>> +#define PCI_DEVICE_ID_ADAPTEC_7881     0x8178
>> +#define PCI_DEVICE_ID_ADAPTEC_7882     0x8278
>> +#define PCI_DEVICE_ID_ADAPTEC_7883     0x8378
>> +#define PCI_DEVICE_ID_ADAPTEC_7884     0x8478
>> +#define PCI_DEVICE_ID_ADAPTEC_1030     0x8b78
>> +
>> +#define PCI_VENDOR_ID_ADAPTEC2         0x9005
>> +#define PCI_DEVICE_ID_ADAPTEC2_2940U2  0x0010
>> +#define PCI_DEVICE_ID_ADAPTEC2_7890    0x001f
>> +#define PCI_DEVICE_ID_ADAPTEC2_3940U2  0x0050
>> +#define PCI_DEVICE_ID_ADAPTEC2_7896    0x005f
>> +
>> +#define PCI_VENDOR_ID_ATRONICS         0x907f
>> +#define PCI_DEVICE_ID_ATRONICS_2015    0x2015
>> +
>> +#define PCI_VENDOR_ID_HOLTEK           0x9412
>> +#define PCI_DEVICE_ID_HOLTEK_6565      0x6565
>> +
>> +#define PCI_VENDOR_ID_TIGERJET         0xe159
>> +#define PCI_DEVICE_ID_TIGERJET_300     0x0001
>> +
>> +#define PCI_VENDOR_ID_ARK              0xedd8
>> +#define PCI_DEVICE_ID_ARK_STING                0xa091
>> +#define PCI_DEVICE_ID_ARK_STINGARK     0xa099
>> +#define PCI_DEVICE_ID_ARK_2000MT       0xa0a1
>> +
>> +#endif /* !__PCI_IDS_H__ */
>> diff --git a/cpukit/libpci/pci/ids_extra.h b/cpukit/libpci/pci/ids_extra.h
>> new file mode 100644
>> index 0000000..ffa18cb
>> --- /dev/null
>> +++ b/cpukit/libpci/pci/ids_extra.h
>> @@ -0,0 +1,19 @@
>> +/* RTEMS local PCI data base */
>> +
>> +/* Only included from pci_ids.h */
>> +#ifndef __PCI_IDS_H__
>> +#error pci/ids_extra.h should only be included from pci/ids.h
>> +#endif
>> +
>> +/* Gaisler PCI IDs */
>> +#define PCIID_VENDOR_GAISLER           0x1AC8
>> +#define PCIID_VENDOR_GAISLER_OLD       0x16E3
>> +
>> +/* Gaisler PCI Devices */
>> +#define PCIID_DEVICE_GR_RASTA_IO       0x0010  /* GR-RASTA-IO */
>> +#define PCIID_DEVICE_GR_RASTA_IO_OLD   0x0210  /* old GR-RASTA-IO ID*/
>> +#define PCIID_DEVICE_GR_RASTA_TMTC     0x0011  /* GR-RASTA-TMTC */
>> +#define PCIID_DEVICE_GR_RASTA_ADCDAC   0x0014  /* GR-RASTA-ADCDAC */
>> +#define PCIID_DEVICE_GR_701            0x0701  /* GR-701 */
>> +#define PCIID_DEVICE_GR_TMTC_1553       0x0198  /* GR-TMTC-1553 */
>> +#define PCIID_DEVICE_GR_RASTA_SPW_RTR   0x0062  /* GR-RASTA-SPW-ROUTER */
> This is all the farther I got for now.
Ok, thanks!



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