[PATCH] Temporary fix for ethernet rx intr hang issue and Disable cache

[ragu nath]

Hi Sebastian,

I read about rtems_cache_coherent_allocate(). I understand first we
need to add an area to use this.
I added rtems_cache_coherent_add_area(bsp_nocache_heap_begin,(uintptr_t)
bsp_nocache_heap_size); in bsp start.
Is that right? I do not know how bsp_nocache_heap_begin &
bsp_nocache_heap_size are defined. How to define/check correct vaules
for them?

Can you pls explain how to use rtems_cache_coherent_allocate? I am not
sure which memory needs to be allocated with this.
Do we need to make the mbufs part of this memory?


Thanks,
Ragunath


On Mon, Jun 29, 2015 at 12:49 PM, Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
>
>
> On 25/06/15 18:20, ragunath wrote:
>>
>> This patch has two changes that are needed for networking to work in BBB.
>> We disable cache as it is causing random values to be learned in the cpsw
>> Address
>> Lookup Engine(ALE) causing tx to fail. Vector enable is done after handler
>> is called by the server task.
>>
>> ---
>>   c/src/lib/libbsp/arm/beagle/irq.c                 | 2 ++
>>   c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c | 8 +++++---
>>   2 files changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/c/src/lib/libbsp/arm/beagle/irq.c
>> b/c/src/lib/libbsp/arm/beagle/irq.c
>> index c6485cd..64e7756 100644
>> --- a/c/src/lib/libbsp/arm/beagle/irq.c
>> +++ b/c/src/lib/libbsp/arm/beagle/irq.c
>> @@ -73,6 +73,7 @@ void bsp_interrupt_dispatch(void)
>>         _ARMV4_Status_restore(psr);
>>   +    if(!(irq == 40 || irq == 41 || irq == 42 || irq == 43))
>>       bsp_interrupt_vector_enable(irq);
>>     }
>>   }
>
>
> Why not remove the bsp_interrupt_vector_disable/enable() calls in
> bsp_interrupt_dispatch() unconditionally?
>
>
>> @@ -94,6 +95,7 @@ rtems_status_code
>> bsp_interrupt_vector_enable(rtems_vector_number vector)
>>     uint32_t mask, cur;
>>     uint32_t mir_reg = get_mir_reg(vector, &mask);
>>   +  irqs_enabled[vector] = 1;
>>     cur = mmio_read(omap_intr.base + mir_reg);
>>     mmio_write(omap_intr.base + mir_reg, cur & ~mask);
>>     flush_data_cache();
>> diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
>> b/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
>> index 157edfa..6cd0f38 100644
>> --- a/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
>> +++ b/c/src/lib/libbsp/arm/beagle/startup/bspstartmmu.c
>> @@ -44,15 +44,17 @@ BSP_START_TEXT_SECTION void
>> beagle_setup_mmu_and_cache(void)
>>   {
>>     /* turn mmu off first in case it's on */
>>     uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
>> -    ARM_CP15_CTRL_M | ARM_CP15_CTRL_A, /* clear - mmu off */
>> +    ARM_CP15_CTRL_M | ARM_CP15_CTRL_A | ARM_CP15_CTRL_I |
>> ARM_CP15_CTRL_C,     /* clear - mmu off */
>>       ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
>>     );
>>   -  arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
>> -    ctrl,
>> +  arm_cp15_start_setup_translation_table(
>>       (uint32_t *) bsp_translation_table_base,
>>       ARM_MMU_DEFAULT_CLIENT_DOMAIN,
>>       &beagle_mmu_config_table[0],
>>       RTEMS_ARRAY_SIZE(beagle_mmu_config_table)
>>     );
>> +
>> +  ctrl |= ARM_CP15_CTRL_M;
>> +  arm_cp15_set_control(ctrl);
>>   }
>
>
> I would rather fix the driver. Add cache flush/invalidate calls to the right
> spots or use a non-cacheable memory area, see
> rtems_cache_coherent_allocate() for example.
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>



-- 
ragu