[PATCH 1/2] bsp/tms570: skipped 32bit field definitions and corrected single bit fields
Premysl Houdek
kom541000 at gmail.com
Fri Jul 17 15:04:05 UTC 2015
there is no need to define access macros for field covering
whole registers. In addition, BSP_FLD32 does not work right
for field 32bit length.
Signed-off-by: Premysl Houdek <kom541000 at gmail.com>
---
.../libbsp/arm/tms570/include/ti_herc/reg_adc.h | 292 ++++++------
.../libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h | 18 +-
.../libbsp/arm/tms570/include/ti_herc/reg_crc.h | 234 ++++-----
.../libbsp/arm/tms570/include/ti_herc/reg_dcan.h | 351 +++++++-------
.../libbsp/arm/tms570/include/ti_herc/reg_dcc.h | 32 +-
.../libbsp/arm/tms570/include/ti_herc/reg_dma.h | 215 ++++-----
.../libbsp/arm/tms570/include/ti_herc/reg_dmm.h | 303 ++++++------
.../libbsp/arm/tms570/include/ti_herc/reg_efuse.h | 56 +--
.../libbsp/arm/tms570/include/ti_herc/reg_emac.h | 103 ++--
.../libbsp/arm/tms570/include/ti_herc/reg_emacm.h | 456 +++++++++---------
.../libbsp/arm/tms570/include/ti_herc/reg_emif.h | 111 +++--
.../libbsp/arm/tms570/include/ti_herc/reg_esm.h | 125 ++---
.../libbsp/arm/tms570/include/ti_herc/reg_flash.h | 216 ++++-----
.../arm/tms570/include/ti_herc/reg_flex_ray.h | 527 +++++++--------------
.../libbsp/arm/tms570/include/ti_herc/reg_gio.h | 50 +-
.../libbsp/arm/tms570/include/ti_herc/reg_htu.h | 152 +++---
.../libbsp/arm/tms570/include/ti_herc/reg_i2c.h | 168 +++----
.../libbsp/arm/tms570/include/ti_herc/reg_iomm.h | 93 ++--
.../libbsp/arm/tms570/include/ti_herc/reg_lin.h | 252 +++++-----
.../libbsp/arm/tms570/include/ti_herc/reg_mdio.h | 103 ++--
.../libbsp/arm/tms570/include/ti_herc/reg_n2het.h | 177 +++----
.../libbsp/arm/tms570/include/ti_herc/reg_pbist.h | 82 ++--
.../libbsp/arm/tms570/include/ti_herc/reg_pcr.h | 76 +--
.../libbsp/arm/tms570/include/ti_herc/reg_pll.h | 78 ++-
.../libbsp/arm/tms570/include/ti_herc/reg_pmm.h | 78 +--
.../libbsp/arm/tms570/include/ti_herc/reg_pom.h | 119 ++---
.../libbsp/arm/tms570/include/ti_herc/reg_rti.h | 234 ++++-----
.../libbsp/arm/tms570/include/ti_herc/reg_rtp.h | 133 +++---
.../libbsp/arm/tms570/include/ti_herc/reg_sci.h | 236 ++++-----
.../libbsp/arm/tms570/include/ti_herc/reg_spi.h | 340 ++++++-------
.../libbsp/arm/tms570/include/ti_herc/reg_stc.h | 102 ++--
.../libbsp/arm/tms570/include/ti_herc/reg_sys.h | 231 +++++----
.../libbsp/arm/tms570/include/ti_herc/reg_sys2.h | 35 +-
.../libbsp/arm/tms570/include/ti_herc/reg_tcr.h | 26 +-
.../libbsp/arm/tms570/include/ti_herc/reg_tcram.h | 48 +-
.../libbsp/arm/tms570/include/ti_herc/reg_vim.h | 87 ++--
36 files changed, 2641 insertions(+), 3298 deletions(-)
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
index 9bd9434..1649fbe 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_ADC
-#define LIBBSP_ARM_tms570_ADC
+#ifndef LIBBSP_ARM_TMS570_ADC
+#define LIBBSP_ARM_TMS570_ADC
#include <bsp/utility.h>
@@ -115,71 +115,71 @@ typedef struct{
} tms570_adc_t;
-/*-----------------------TMS570_ADCBUF0-----------------------*/
+/*----------------------TMS570_ADC_BUFx----------------------*/
/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
-#define TMS570_ADC_BUF0_G2_EMPTY_10bit_mode BSP_FLD32(15)
+#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
/* field: G2_CHID_10bit_mode - Group2 Channel Id. */
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
-#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
+#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
-#define TMS570_ADC_BUF0_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
-#define TMS570_ADC_BUF0_G2_EMPTY_12bit_mode BSP_FLD32(31)
+#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
/* field: G2_CHID_12bit_mode - Group2 Channel Id. */
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
-#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
-#define TMS570_ADC_BUF0_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*----------------------TMS570_ADCRSTCR----------------------*/
+/*----------------------TMS570_ADC_RSTCR----------------------*/
/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
-#define TMS570_ADC_RSTCR_RESET BSP_FLD32(0)
+#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
-/*---------------------TMS570_ADCOPMODECR---------------------*/
+/*--------------------TMS570_ADC_OPMODECR--------------------*/
/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
-#define TMS570_ADC_OPMODECR_10_12_BIT BSP_FLD32(31)
+#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
-/*---------------------TMS570_ADCCLOCKCR---------------------*/
+/*---------------------TMS570_ADC_CLOCKCR---------------------*/
/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
#define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*----------------------TMS570_ADCCALCR----------------------*/
+/*----------------------TMS570_ADC_CALCR----------------------*/
/* field: SELF_TEST - ADC Self Test Enable. */
-#define TMS570_ADC_CALCR_SELF_TEST BSP_FLD32(24)
+#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
/* field: CAL_ST - ADC Calibration Conversion Start. */
-#define TMS570_ADC_CALCR_CAL_ST BSP_FLD32(16)
+#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
/* field: BRIDGE_EN - Bridge Enable. */
-#define TMS570_ADC_CALCR_BRIDGE_EN BSP_FLD32(9)
+#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
-#define TMS570_ADC_CALCR_HILO BSP_FLD32(8)
+#define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
/* field: CAL_EN - ADC Calibration Enable. */
-#define TMS570_ADC_CALCR_CAL_EN BSP_FLD32(0)
+#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
-/*---------------------TMS570_ADCGxMODECR---------------------*/
+/*--------------------TMS570_ADC_GxMODECR--------------------*/
/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
-#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_FLD32(16)
+#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
/* field: EV_DATA_FMT - Event Group Read Data Format. */
#define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
@@ -187,12 +187,12 @@ typedef struct{
#define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
-/*----------------------TMS570_ADCEVSRC----------------------*/
+/*----------------------TMS570_ADC_EVSRC----------------------*/
/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
-#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
-#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
/* field: EV_SRC - Event Group Trigger Source. */
#define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
@@ -200,12 +200,12 @@ typedef struct{
#define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_ADCG1SRC----------------------*/
+/*----------------------TMS570_ADC_G1SRC----------------------*/
/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
/* field: G1_SRC - Group1 Trigger Source. */
#define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
@@ -213,12 +213,12 @@ typedef struct{
#define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_ADCG2SRC----------------------*/
+/*----------------------TMS570_ADC_G2SRC----------------------*/
/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_FLD32(4)
+#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
-#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_FLD32(3)
+#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
/* field: G2_SRC - Group2 Trigger Source. */
#define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
@@ -226,32 +226,32 @@ typedef struct{
#define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*---------------------TMS570_ADCGxINTENA---------------------*/
+/*--------------------TMS570_ADC_GxINTENA--------------------*/
/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
-#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_FLD32(3)
+#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
-#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_FLD32(1)
+#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
-#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_FLD32(0)
+#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
-/*---------------------TMS570_ADCGxINTFLG---------------------*/
+/*--------------------TMS570_ADC_GxINTFLG--------------------*/
/* field: EV_END - Event Group Conversion End. */
-#define TMS570_ADC_GxINTFLG_EV_END BSP_FLD32(3)
+#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
-#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_FLD32(2)
+#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
-#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_FLD32(1)
+#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
-#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_FLD32(0)
+#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
-/*---------------------TMS570_ADCGxINTCR---------------------*/
+/*---------------------TMS570_ADC_GxINTCR---------------------*/
/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
#define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
@@ -263,55 +263,55 @@ typedef struct{
#define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*---------------------TMS570_ADCEVDMACR---------------------*/
+/*---------------------TMS570_ADC_EVDMACR---------------------*/
/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
#define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
#define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_FLD32(3)
+#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
-#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
-/*---------------------TMS570_ADCG1DMACR---------------------*/
+/*---------------------TMS570_ADC_G1DMACR---------------------*/
/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
#define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
#define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_FLD32(3)
+#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
-#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
-/*---------------------TMS570_ADCG2DMACR---------------------*/
+/*---------------------TMS570_ADC_G2DMACR---------------------*/
/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
#define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
#define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_FLD32(3)
+#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_FLD32(2)
+#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
-#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_FLD32(0)
+#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
-/*----------------------TMS570_ADCBNDCR----------------------*/
+/*----------------------TMS570_ADC_BNDCR----------------------*/
/* field: BNDA - Buffer Boundary A. */
#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
#define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
@@ -323,9 +323,9 @@ typedef struct{
#define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*----------------------TMS570_ADCBNDEND----------------------*/
+/*---------------------TMS570_ADC_BNDEND---------------------*/
/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
-#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_FLD32(16)
+#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
/* field: BNDEND - Buffer Boundary End. */
#define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
@@ -333,274 +333,274 @@ typedef struct{
#define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_ADCEVSAMP----------------------*/
+/*---------------------TMS570_ADC_EVSAMP---------------------*/
/* field: EV_ACQ - Event Group Acquisition Time. */
#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
#define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
#define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*----------------------TMS570_ADCG1SAMP----------------------*/
+/*---------------------TMS570_ADC_G1SAMP---------------------*/
/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
#define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
#define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*----------------------TMS570_ADCG2SAMP----------------------*/
+/*---------------------TMS570_ADC_G2SAMP---------------------*/
/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
#define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
#define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*-----------------------TMS570_ADCEVSR-----------------------*/
+/*----------------------TMS570_ADC_EVSR----------------------*/
/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
-#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
/* field: EV_BUSY - Event Group Conversion Busy. */
-#define TMS570_ADC_EVSR_EV_BUSY BSP_FLD32(2)
+#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
/* field: EV_STOP - Event Group Conversion Stopped. */
-#define TMS570_ADC_EVSR_EV_STOP BSP_FLD32(1)
+#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
/* field: EV_END - Event Group Conversions Ended. */
-#define TMS570_ADC_EVSR_EV_END BSP_FLD32(0)
+#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
-/*-----------------------TMS570_ADCG1SR-----------------------*/
+/*----------------------TMS570_ADC_G1SR----------------------*/
/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
-#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
/* field: G1_BUSY - Group1 Conversion Busy. */
-#define TMS570_ADC_G1SR_G1_BUSY BSP_FLD32(2)
+#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
/* field: G1_STOP - Group1 Conversion Stopped. */
-#define TMS570_ADC_G1SR_G1_STOP BSP_FLD32(1)
+#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
/* field: G1_END - Group1 Conversions Ended. */
-#define TMS570_ADC_G1SR_G1_END BSP_FLD32(0)
+#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
-/*-----------------------TMS570_ADCG2SR-----------------------*/
+/*----------------------TMS570_ADC_G2SR----------------------*/
/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
-#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_FLD32(3)
+#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
/* field: G2_BUSY - Group2 Conversion Busy. */
-#define TMS570_ADC_G2SR_G2_BUSY BSP_FLD32(2)
+#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
/* field: G2_STOP - Group2 Conversion Stopped. */
-#define TMS570_ADC_G2SR_G2_STOP BSP_FLD32(1)
+#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
/* field: G2_END - Group2 Conversions Ended. */
-#define TMS570_ADC_G2SR_G2_END BSP_FLD32(0)
+#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
-/*----------------------TMS570_ADCGxSEL----------------------*/
+/*----------------------TMS570_ADC_GxSEL----------------------*/
/* field: EV_SEL - Event Group channels selected. */
#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
#define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_ADCCALR-----------------------*/
+/*----------------------TMS570_ADC_CALR----------------------*/
/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
#define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
#define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*---------------------TMS570_ADCSMSTATE---------------------*/
+/*---------------------TMS570_ADC_SMSTATE---------------------*/
/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
#define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*---------------------TMS570_ADCLASTCONV---------------------*/
+/*--------------------TMS570_ADC_LASTCONV--------------------*/
/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
#define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*----------------------TMS570_ADCGxBUF----------------------*/
+/*----------------------TMS570_ADC_GxBUF----------------------*/
/* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
-/*-------------------TMS570_ADCEVEMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
/* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
-/*-------------------TMS570_ADCG1EMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
/* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
-/*-------------------TMS570_ADCG2EMUBUFFER-------------------*/
+/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
/* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTDIR----------------------*/
+/*---------------------TMS570_ADC_EVTDIR---------------------*/
/* field: ADEVT_DIR - ADEVT Pin Direction. */
-#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_FLD32(0)
+#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTOUT----------------------*/
+/*---------------------TMS570_ADC_EVTOUT---------------------*/
/* field: ADEVT_OUT - ADEVT Pin Output Value. */
-#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_FLD32(0)
+#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTIN----------------------*/
+/*----------------------TMS570_ADC_EVTIN----------------------*/
/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
-#define TMS570_ADC_EVTIN_ADEVT_IN BSP_FLD32(0)
+#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTSET----------------------*/
+/*---------------------TMS570_ADC_EVTSET---------------------*/
/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
-#define TMS570_ADC_EVTSET_ADEVT_SET BSP_FLD32(0)
+#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTCLR----------------------*/
+/*---------------------TMS570_ADC_EVTCLR---------------------*/
/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
-#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_FLD32(0)
+#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
-/*----------------------TMS570_ADCEVTPDR----------------------*/
+/*---------------------TMS570_ADC_EVTPDR---------------------*/
/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
-#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_FLD32(0)
+#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
-/*---------------------TMS570_ADCEVTPDIS---------------------*/
+/*---------------------TMS570_ADC_EVTPDIS---------------------*/
/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
-#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_FLD32(0)
+#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
-/*---------------------TMS570_ADCEVTPSEL---------------------*/
+/*---------------------TMS570_ADC_EVTPSEL---------------------*/
/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
-#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_FLD32(0)
+#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
-/*-------------------TMS570_ADCEVSAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
-#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
-/*-------------------TMS570_ADCG1SAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
-#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
-/*-------------------TMS570_ADCG2SAMPDISEN-------------------*/
+/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
-#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_FLD32(0)
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
-/*--------------------TMS570_ADCMAGINTCR1--------------------*/
+/*--------------------TMS570_ADC_MAGINTCRx--------------------*/
/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2(val) BSP_FLD32(val,26, 30)
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
-#define TMS570_ADC_MAGINTCR1_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
+#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
-#define TMS570_ADC_MAGINTCR1_MAG_THR2(val) BSP_FLD32(val,16, 25)
-#define TMS570_ADC_MAGINTCR1_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
-#define TMS570_ADC_MAGINTCR1_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
+#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2(val) BSP_FLD32(val,8, 12)
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
-#define TMS570_ADC_MAGINTCR1_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
-#define TMS570_ADC_MAGINTCR1_CHN_THR_COMP2 BSP_FLD32(1)
+#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
-#define TMS570_ADC_MAGINTCR1_CMP_GE_LT2 BSP_FLD32(0)
+#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
-/*-------------------TMS570_ADCMAGINT1MASK-------------------*/
+/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
-#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*-----------------TMS570_ADCMAGTHRINTENASET-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------TMS570_ADCMAGTHRINTENACLR-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-------------------TMS570_ADCMAGTHRINTFLG-------------------*/
+/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------TMS570_ADCMAGTHRINTOFFSET-----------------*/
+/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_ADCGxFIFORESETCR------------------*/
+/*------------------TMS570_ADC_GxFIFORESETCR------------------*/
/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
-#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_FLD32(0)
+#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
-/*-------------------TMS570_ADCEVRAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*-------------------TMS570_ADCG1RAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*-------------------TMS570_ADCG2RAMWRADDR-------------------*/
+/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
/* field: G2_RAM_ADDR - Group2 results memory write pointer. */
#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*----------------------TMS570_ADCPARCR----------------------*/
+/*----------------------TMS570_ADC_PARCR----------------------*/
/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
-#define TMS570_ADC_PARCR_TEST BSP_FLD32(8)
+#define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
/* field: PARITY_ENA - PARITY ENA */
#define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -608,14 +608,14 @@ typedef struct{
#define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_ADCPARADDR---------------------*/
+/*---------------------TMS570_ADC_PARADDR---------------------*/
/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
#define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
#define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
-/*-------------------TMS570_ADCPWRUPDLYCTRL-------------------*/
+/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
@@ -623,4 +623,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_ADC */
+#endif /* LIBBSP_ARM_TMS570_ADC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
index 30e5c9b..941ed54 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_CCMSR
-#define LIBBSP_ARM_tms570_CCMSR
+#ifndef LIBBSP_ARM_TMS570_CCMSR
+#define LIBBSP_ARM_TMS570_CCMSR
#include <bsp/utility.h>
@@ -47,21 +47,21 @@ typedef struct{
} tms570_ccmsr_t;
-/*---------------------TMS570_CCMSRCCMSR---------------------*/
+/*---------------------TMS570_CCMSR_CCMSR---------------------*/
/* field: CMPE - Compare Error */
-#define TMS570_CCMSR_CCMSR_CMPE BSP_FLD32(16)
+#define TMS570_CCMSR_CCMSR_CMPE BSP_BIT32(16)
/* field: STC - Self-test Complete */
-#define TMS570_CCMSR_CCMSR_STC BSP_FLD32(8)
+#define TMS570_CCMSR_CCMSR_STC BSP_BIT32(8)
/* field: STET - Self-test Error Type */
-#define TMS570_CCMSR_CCMSR_STET BSP_FLD32(1)
+#define TMS570_CCMSR_CCMSR_STET BSP_BIT32(1)
/* field: STE - Self-test Error */
-#define TMS570_CCMSR_CCMSR_STE BSP_FLD32(0)
+#define TMS570_CCMSR_CCMSR_STE BSP_BIT32(0)
-/*--------------------TMS570_CCMSRCCMKEYR--------------------*/
+/*--------------------TMS570_CCMSR_CCMKEYR--------------------*/
/* field: MKEY - Mode Key */
#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -69,4 +69,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_CCMSR */
+#endif /* LIBBSP_ARM_TMS570_CCMSR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
index 8798c12..f1352f6 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_CRC
-#define LIBBSP_ARM_tms570_CRC
+#ifndef LIBBSP_ARM_TMS570_CRC
+#define LIBBSP_ARM_TMS570_CRC
#include <bsp/utility.h>
@@ -91,27 +91,27 @@ typedef struct{
} tms570_crc_t;
-/*----------------------TMS570_CRCCTRL0----------------------*/
+/*----------------------TMS570_CRC_CTRL0----------------------*/
/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
-#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
+#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_BIT32(8)
/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
-#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
+#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_BIT32(0)
-/*----------------------TMS570_CRCCTRL1----------------------*/
+/*----------------------TMS570_CRC_CTRL1----------------------*/
/* field: PWDN - Power Down. */
-#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
+#define TMS570_CRC_CTRL1_PWDN BSP_BIT32(0)
-/*----------------------TMS570_CRCCTRL2----------------------*/
+/*----------------------TMS570_CRC_CTRL2----------------------*/
/* field: CH2_MODE - Channel 2 Mode Selection */
#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
-#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
+#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_BIT32(4)
/* field: CH1_MODE - Channel 1 Mode Selection */
#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
@@ -119,309 +119,261 @@ typedef struct{
#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*-----------------------TMS570_CRCINTS-----------------------*/
+/*----------------------TMS570_CRC_INTS----------------------*/
/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
+#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_BIT32(12)
/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
+#define TMS570_CRC_INTS_CH2_UNDERENS BSP_BIT32(11)
/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
+#define TMS570_CRC_INTS_CH2_OVERENS BSP_BIT32(10)
/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
+#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_BIT32(9)
/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
+#define TMS570_CRC_INTS_CH2_CCITENS BSP_BIT32(8)
/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
+#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_BIT32(4)
/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
+#define TMS570_CRC_INTS_CH1_UNDERENS BSP_BIT32(3)
/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
+#define TMS570_CRC_INTS_CH1_OVERENS BSP_BIT32(2)
/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
+#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_BIT32(1)
/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
+#define TMS570_CRC_INTS_CH1_CCITENS BSP_BIT32(0)
-/*-----------------------TMS570_CRCINTR-----------------------*/
+/*----------------------TMS570_CRC_INTR----------------------*/
/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
+#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_BIT32(12)
/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
+#define TMS570_CRC_INTR_CH2_UNDERENR BSP_BIT32(11)
/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
+#define TMS570_CRC_INTR_CH2_OVERENR BSP_BIT32(10)
/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
+#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_BIT32(9)
/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
+#define TMS570_CRC_INTR_CH2_CCITENR BSP_BIT32(8)
/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
+#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_BIT32(4)
/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
-#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
+#define TMS570_CRC_INTR_CH1_UNDERENR BSP_BIT32(3)
/* field: CH1_OVERENR - CH1_OVERENR */
-#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
+#define TMS570_CRC_INTR_CH1_OVERENR BSP_BIT32(2)
/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
+#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_BIT32(1)
/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
-#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
+#define TMS570_CRC_INTR_CH1_CCITENR BSP_BIT32(0)
-/*----------------------TMS570_CRCSTATUS----------------------*/
+/*---------------------TMS570_CRC_STATUS---------------------*/
/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
+#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_BIT32(12)
/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
+#define TMS570_CRC_STATUS_CH2_UNDER BSP_BIT32(11)
/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
+#define TMS570_CRC_STATUS_CH2_OVER BSP_BIT32(10)
/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
-#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
+#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_BIT32(9)
/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
-#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
+#define TMS570_CRC_STATUS_CH2_CCIT BSP_BIT32(8)
/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
-#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
+#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_BIT32(4)
/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
-#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
+#define TMS570_CRC_STATUS_CH1_UNDER BSP_BIT32(3)
/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
-#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
+#define TMS570_CRC_STATUS_CH1_OVER BSP_BIT32(2)
/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
-#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
+#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_BIT32(1)
/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
-#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
+#define TMS570_CRC_STATUS_CH1_CCIT BSP_BIT32(0)
-/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
+/*------------------TMS570_CRC_INT_OFFS_REG------------------*/
/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_CRCBUSY-----------------------*/
+/*----------------------TMS570_CRC_BUSY----------------------*/
/* field: CH2_BUSY - CH2_BUSY. */
-#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
+#define TMS570_CRC_BUSY_CH2_BUSY BSP_BIT32(8)
/* field: CH1_BUSY - CH1_BUSY. */
-#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
+#define TMS570_CRC_BUSY_CH1_BUSY BSP_BIT32(0)
-/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
+/*-------------------TMS570_CRC_PCOUNT_REG1-------------------*/
/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
+/*-------------------TMS570_CRC_SCOUNT_REG1-------------------*/
/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_CRCCURSEC_REG1-------------------*/
+/*-------------------TMS570_CRC_CURSEC_REG1-------------------*/
/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_CRCWDTOPLD1---------------------*/
+/*--------------------TMS570_CRC_WDTOPLD1--------------------*/
/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*---------------------TMS570_CRCBCTOPLD1---------------------*/
+/*--------------------TMS570_CRC_BCTOPLD1--------------------*/
/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGL1------------------*/
/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGH1------------------*/
/* field: PSASIG1 - register. */
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_CRCREGL1----------------------*/
+/*----------------------TMS570_CRC_REGL1----------------------*/
/* field: CRC1 - Channel 1 CRC Value Low Register. */
-#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_CRCREGH1----------------------*/
+/*----------------------TMS570_CRC_REGH1----------------------*/
/* field: CRC1 - Channel 1 CRC Value Low Register. */
-#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
+/*-----------------TMS570_CRC_PSA_SECSIGREGL1-----------------*/
/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
+/*-----------------TMS570_CRC_PSA_SECSIGREGH1-----------------*/
/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_CRCRAW_DATAREGL1------------------*/
+/*------------------TMS570_CRC_RAW_DATAREGL1------------------*/
/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_CRCRAW_DATAREGH1------------------*/
+/*------------------TMS570_CRC_RAW_DATAREGH1------------------*/
/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
+/*-------------------TMS570_CRC_PCOUNT_REG2-------------------*/
/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
+/*-------------------TMS570_CRC_SCOUNT_REG2-------------------*/
/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_CRCCURSEC_REG2-------------------*/
+/*-------------------TMS570_CRC_CURSEC_REG2-------------------*/
/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_CRCWDTOPLD2---------------------*/
+/*--------------------TMS570_CRC_WDTOPLD2--------------------*/
/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*---------------------TMS570_CRCBCTOPLD2---------------------*/
+/*--------------------TMS570_CRC_BCTOPLD2--------------------*/
/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGL2------------------*/
/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
+/*------------------TMS570_CRC_PSA_SIGREGH2------------------*/
/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_CRCREGL2----------------------*/
+/*----------------------TMS570_CRC_REGL2----------------------*/
/* field: CRC2 - stored at CRC2[31:0] register. */
-#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_CRCREGH2----------------------*/
+/*----------------------TMS570_CRC_REGH2----------------------*/
/* field: CRC2 - Channel 2 CRC Value High Register. */
-#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
+/*-----------------TMS570_CRC_PSA_SECSIGREGL2-----------------*/
/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
+/*-----------------TMS570_CRC_PSA_SECSIGREGH2-----------------*/
/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_CRCRAW_DATAREGL2------------------*/
+/*------------------TMS570_CRC_RAW_DATAREGL2------------------*/
/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_CRCRAW_DATAREGH2------------------*/
+/*------------------TMS570_CRC_RAW_DATAREGH2------------------*/
/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_CRCBUS_SEL---------------------*/
+/*---------------------TMS570_CRC_BUS_SEL---------------------*/
/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
-#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
+#define TMS570_CRC_BUS_SEL_MEn BSP_BIT32(2)
/* field: DTCMEn - Enable/disables the tracing of data TCM */
-#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
+#define TMS570_CRC_BUS_SEL_DTCMEn BSP_BIT32(1)
/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
-#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
+#define TMS570_CRC_BUS_SEL_ITCMEn BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_CRC */
+#endif /* LIBBSP_ARM_TMS570_CRC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
index 80d372e..c278f55 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_DCAN
-#define LIBBSP_ARM_tms570_DCAN
+#ifndef LIBBSP_ARM_TMS570_DCAN
+#define LIBBSP_ARM_TMS570_DCAN
#include <bsp/utility.h>
@@ -91,30 +91,30 @@ typedef struct{
} tms570_dcan_t;
-/*-----------------------TMS570_DCANCTL-----------------------*/
+/*----------------------TMS570_DCAN_CTL----------------------*/
/* field: WUBA - Automatic wake up on bus activity when in local power down mode */
-#define TMS570_DCAN_CTL_WUBA BSP_FLD32(25)
+#define TMS570_DCAN_CTL_WUBA BSP_BIT32(25)
/* field: PDR - Request for local low power down mode */
-#define TMS570_DCAN_CTL_PDR BSP_FLD32(24)
+#define TMS570_DCAN_CTL_PDR BSP_BIT32(24)
/* field: DE3 - Enable DMA request line for IF3 */
-#define TMS570_DCAN_CTL_DE3 BSP_FLD32(20)
+#define TMS570_DCAN_CTL_DE3 BSP_BIT32(20)
/* field: DE2 - Enable DMA request line for IF2 */
-#define TMS570_DCAN_CTL_DE2 BSP_FLD32(19)
+#define TMS570_DCAN_CTL_DE2 BSP_BIT32(19)
/* field: DE1 - Enable DMA request line for IF1 */
-#define TMS570_DCAN_CTL_DE1 BSP_FLD32(18)
+#define TMS570_DCAN_CTL_DE1 BSP_BIT32(18)
/* field: IE1 - Interrupt line 1 Enable */
-#define TMS570_DCAN_CTL_IE1 BSP_FLD32(17)
+#define TMS570_DCAN_CTL_IE1 BSP_BIT32(17)
/* field: InitDbg - Internal Init state while debug access */
-#define TMS570_DCAN_CTL_InitDbg BSP_FLD32(16)
+#define TMS570_DCAN_CTL_InitDbg BSP_BIT32(16)
/* field: SWR - SW Reset Enable */
-#define TMS570_DCAN_CTL_SWR BSP_FLD32(15)
+#define TMS570_DCAN_CTL_SWR BSP_BIT32(15)
/* field: PMD - Parity on/off */
#define TMS570_DCAN_CTL_PMD(val) BSP_FLD32(val,10, 13)
@@ -122,57 +122,57 @@ typedef struct{
#define TMS570_DCAN_CTL_PMD_SET(reg,val) BSP_FLD32SET(reg, val,10, 13)
/* field: ABO - Auto-Bus-On Enable */
-#define TMS570_DCAN_CTL_ABO BSP_FLD32(9)
+#define TMS570_DCAN_CTL_ABO BSP_BIT32(9)
/* field: IDS - Interruption Debug Support Enable */
-#define TMS570_DCAN_CTL_IDS BSP_FLD32(8)
+#define TMS570_DCAN_CTL_IDS BSP_BIT32(8)
/* field: Test - Test Mode Enable */
-#define TMS570_DCAN_CTL_Test BSP_FLD32(7)
+#define TMS570_DCAN_CTL_Test BSP_BIT32(7)
/* field: CCE - Configuration Change Enable */
-#define TMS570_DCAN_CTL_CCE BSP_FLD32(6)
+#define TMS570_DCAN_CTL_CCE BSP_BIT32(6)
/* field: DAR - Disable Automatic Retransmission */
-#define TMS570_DCAN_CTL_DAR BSP_FLD32(5)
+#define TMS570_DCAN_CTL_DAR BSP_BIT32(5)
/* field: EIE - Error Interrupt Enable */
-#define TMS570_DCAN_CTL_EIE BSP_FLD32(3)
+#define TMS570_DCAN_CTL_EIE BSP_BIT32(3)
/* field: SIE - Status Change Interrupt Enable */
-#define TMS570_DCAN_CTL_SIE BSP_FLD32(2)
+#define TMS570_DCAN_CTL_SIE BSP_BIT32(2)
/* field: IE0 - Interrupt line 0 Enable */
-#define TMS570_DCAN_CTL_IE0 BSP_FLD32(1)
+#define TMS570_DCAN_CTL_IE0 BSP_BIT32(1)
/* field: Init - Initialization */
-#define TMS570_DCAN_CTL_Init BSP_FLD32(0)
+#define TMS570_DCAN_CTL_Init BSP_BIT32(0)
-/*-----------------------TMS570_DCANES-----------------------*/
+/*-----------------------TMS570_DCAN_ES-----------------------*/
/* field: PDA - Local power down mode acknowledge */
-#define TMS570_DCAN_ES_PDA BSP_FLD32(10)
+#define TMS570_DCAN_ES_PDA BSP_BIT32(10)
/* field: WakeUp_Pnd - Wake Up Pending */
-#define TMS570_DCAN_ES_WakeUp_Pnd BSP_FLD32(9)
+#define TMS570_DCAN_ES_WakeUp_Pnd BSP_BIT32(9)
/* field: PER - Parity Error Detected */
-#define TMS570_DCAN_ES_PER BSP_FLD32(8)
+#define TMS570_DCAN_ES_PER BSP_BIT32(8)
/* field: BOff - Bus-Off State */
-#define TMS570_DCAN_ES_BOff BSP_FLD32(7)
+#define TMS570_DCAN_ES_BOff BSP_BIT32(7)
/* field: EWarn - Warning State */
-#define TMS570_DCAN_ES_EWarn BSP_FLD32(6)
+#define TMS570_DCAN_ES_EWarn BSP_BIT32(6)
/* field: EPass - Error Passive State */
-#define TMS570_DCAN_ES_EPass BSP_FLD32(5)
+#define TMS570_DCAN_ES_EPass BSP_BIT32(5)
/* field: RxOK - Received a message successfully */
-#define TMS570_DCAN_ES_RxOK BSP_FLD32(4)
+#define TMS570_DCAN_ES_RxOK BSP_BIT32(4)
/* field: TxOK - Transmitted a message successfully */
-#define TMS570_DCAN_ES_TxOK BSP_FLD32(3)
+#define TMS570_DCAN_ES_TxOK BSP_BIT32(3)
/* field: LEC - Last Error Code */
#define TMS570_DCAN_ES_LEC(val) BSP_FLD32(val,0, 2)
@@ -180,9 +180,9 @@ typedef struct{
#define TMS570_DCAN_ES_LEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_DCANERRC----------------------*/
+/*----------------------TMS570_DCAN_ERRC----------------------*/
/* field: RP - Receive Error Passive */
-#define TMS570_DCAN_ERRC_RP BSP_FLD32(15)
+#define TMS570_DCAN_ERRC_RP BSP_BIT32(15)
/* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */
#define TMS570_DCAN_ERRC_REC(val) BSP_FLD32(val,8, 14)
@@ -195,7 +195,7 @@ typedef struct{
#define TMS570_DCAN_ERRC_TEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_DCANBTR-----------------------*/
+/*----------------------TMS570_DCAN_BTR----------------------*/
/* field: BRPE - Baud Rate Prescaler Extension. */
#define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19)
#define TMS570_DCAN_BTR_BRPE_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -222,7 +222,7 @@ typedef struct{
#define TMS570_DCAN_BTR_BRP_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------------TMS570_DCANINT-----------------------*/
+/*----------------------TMS570_DCAN_INT----------------------*/
/* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */
#define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23)
#define TMS570_DCAN_INT_Int1ID_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -234,15 +234,15 @@ typedef struct{
#define TMS570_DCAN_INT_Int0ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_DCANTEST----------------------*/
+/*----------------------TMS570_DCAN_TEST----------------------*/
/* field: RDA - RAM Direct Access Enable */
-#define TMS570_DCAN_TEST_RDA BSP_FLD32(9)
+#define TMS570_DCAN_TEST_RDA BSP_BIT32(9)
/* field: EXL - External Loop Back Mode */
-#define TMS570_DCAN_TEST_EXL BSP_FLD32(8)
+#define TMS570_DCAN_TEST_EXL BSP_BIT32(8)
/* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */
-#define TMS570_DCAN_TEST_Rx BSP_FLD32(7)
+#define TMS570_DCAN_TEST_Rx BSP_BIT32(7)
/* field: Tx - Control of CAN_TX pin */
#define TMS570_DCAN_TEST_Tx(val) BSP_FLD32(val,5, 6)
@@ -250,13 +250,13 @@ typedef struct{
#define TMS570_DCAN_TEST_Tx_SET(reg,val) BSP_FLD32SET(reg, val,5, 6)
/* field: LBack - Loop Back Mode */
-#define TMS570_DCAN_TEST_LBack BSP_FLD32(4)
+#define TMS570_DCAN_TEST_LBack BSP_BIT32(4)
/* field: Silent - Silent Mode */
-#define TMS570_DCAN_TEST_Silent BSP_FLD32(3)
+#define TMS570_DCAN_TEST_Silent BSP_BIT32(3)
-/*----------------------TMS570_DCANPERR----------------------*/
+/*----------------------TMS570_DCAN_PERR----------------------*/
/* field: Word_Number - Word number where parity error has been detected */
#define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10)
#define TMS570_DCAN_PERR_Word_Number_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -268,14 +268,11 @@ typedef struct{
#define TMS570_DCAN_PERR_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_DCANABOTR----------------------*/
+/*---------------------TMS570_DCAN_ABOTR---------------------*/
/* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */
-#define TMS570_DCAN_ABOTR_ABO_Time(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_ABOTR_ABO_Time_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_ABOTR_ABO_Time_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_DCANTXRQX----------------------*/
+/*---------------------TMS570_DCAN_TXRQX---------------------*/
/* field: TxRqstReg8 - TxRqstReg8 */
#define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15)
#define TMS570_DCAN_TXRQX_TxRqstReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -317,14 +314,11 @@ typedef struct{
#define TMS570_DCAN_TXRQX_TxRqstReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*----------------------TMS570_DCANTXRQx----------------------*/
+/*---------------------TMS570_DCAN_TXRQx---------------------*/
/* field: TxRqsX - Transmission Request Bits (for all message objects) */
-#define TMS570_DCAN_TXRQx_TxRqsX(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_TXRQx_TxRqsX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_TXRQx_TxRqsX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_DCANNWDATX---------------------*/
+/*---------------------TMS570_DCAN_NWDATX---------------------*/
/* field: NewDatReg8 - TxRqstReg8 */
#define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15)
#define TMS570_DCAN_NWDATX_NewDatReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -366,14 +360,11 @@ typedef struct{
#define TMS570_DCAN_NWDATX_NewDatReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_DCANNWDATx---------------------*/
+/*---------------------TMS570_DCAN_NWDATx---------------------*/
/* field: NewDatX - New Data Bits (for all message objects) */
-#define TMS570_DCAN_NWDATx_NewDatX(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_NWDATx_NewDatX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_NWDATx_NewDatX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_DCANINTPNDX---------------------*/
+/*--------------------TMS570_DCAN_INTPNDX--------------------*/
/* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
#define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15)
#define TMS570_DCAN_INTPNDX_IntPndReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -415,14 +406,11 @@ typedef struct{
#define TMS570_DCAN_INTPNDX_IntPndReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_DCANINTPNDx---------------------*/
+/*--------------------TMS570_DCAN_INTPNDx--------------------*/
/* field: IntPndX - Interrupt Pending Bits (for all message objects) */
-#define TMS570_DCAN_INTPNDx_IntPndX(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_INTPNDx_IntPndX_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_INTPNDx_IntPndX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_DCANMSGVALX---------------------*/
+/*--------------------TMS570_DCAN_MSGVALX--------------------*/
/* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
#define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15)
#define TMS570_DCAN_MSGVALX_MsgValReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -464,50 +452,44 @@ typedef struct{
#define TMS570_DCAN_MSGVALX_MsgValReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_DCANMSGVALx---------------------*/
+/*--------------------TMS570_DCAN_MSGVALx--------------------*/
/* field: MsgVal1To32 - Message Valid Bits (for all message objects) */
-#define TMS570_DCAN_MSGVALx_MsgVal1To32(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_MSGVALx_MsgVal1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_MSGVALx_MsgVal1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_DCANINTMUXx---------------------*/
+/*--------------------TMS570_DCAN_INTMUXx--------------------*/
/* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */
-#define TMS570_DCAN_INTMUXx_IntMux1To32(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_INTMUXx_IntMux1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_INTMUXx_IntMux1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_DCANIF1CMD---------------------*/
+/*---------------------TMS570_DCAN_IF1CMD---------------------*/
/* field: WR_RD - Write/Read */
-#define TMS570_DCAN_IF1CMD_WR_RD BSP_FLD32(23)
+#define TMS570_DCAN_IF1CMD_WR_RD BSP_BIT32(23)
/* field: Mask - Access Mask bits */
-#define TMS570_DCAN_IF1CMD_Mask BSP_FLD32(22)
+#define TMS570_DCAN_IF1CMD_Mask BSP_BIT32(22)
/* field: Arb - Access Arbitration bits */
-#define TMS570_DCAN_IF1CMD_Arb BSP_FLD32(21)
+#define TMS570_DCAN_IF1CMD_Arb BSP_BIT32(21)
/* field: Control - Access Control bits */
-#define TMS570_DCAN_IF1CMD_Control BSP_FLD32(20)
+#define TMS570_DCAN_IF1CMD_Control BSP_BIT32(20)
/* field: ClrIntPnd - Clear Interrupt Pending bit */
-#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_FLD32(19)
+#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_BIT32(19)
/* field: TxRqst_NewDat - Access Transmission Request bit */
-#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_FLD32(18)
+#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_BIT32(18)
/* field: Data_A - Access Data Bytes 0-3 */
-#define TMS570_DCAN_IF1CMD_Data_A BSP_FLD32(17)
+#define TMS570_DCAN_IF1CMD_Data_A BSP_BIT32(17)
/* field: Data_B - Access Data Bytes 4-7 */
-#define TMS570_DCAN_IF1CMD_Data_B BSP_FLD32(16)
+#define TMS570_DCAN_IF1CMD_Data_B BSP_BIT32(16)
/* field: Busy - Busy flag */
-#define TMS570_DCAN_IF1CMD_Busy BSP_FLD32(15)
+#define TMS570_DCAN_IF1CMD_Busy BSP_BIT32(15)
/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
-#define TMS570_DCAN_IF1CMD_DMA_Active BSP_FLD32(14)
+#define TMS570_DCAN_IF1CMD_DMA_Active BSP_BIT32(14)
/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
#define TMS570_DCAN_IF1CMD_Message_Number(val) BSP_FLD32(val,0, 7)
@@ -515,12 +497,12 @@ typedef struct{
#define TMS570_DCAN_IF1CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_DCANIF1MSK---------------------*/
+/*---------------------TMS570_DCAN_IF1MSK---------------------*/
/* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF1MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF1MSK_MXtd BSP_BIT32(31)
/* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF1MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF1MSK_MDir BSP_BIT32(30)
/* field: Msk - Identifier Mask */
#define TMS570_DCAN_IF1MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -528,15 +510,15 @@ typedef struct{
#define TMS570_DCAN_IF1MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF1ARB---------------------*/
+/*---------------------TMS570_DCAN_IF1ARB---------------------*/
/* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF1ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF1ARB_MsgVal BSP_BIT32(31)
/* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF1ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF1ARB_Xtd BSP_BIT32(30)
/* field: Dir - Message direction */
-#define TMS570_DCAN_IF1ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF1ARB_Dir BSP_BIT32(29)
/* field: ID - Message Identifier */
#define TMS570_DCAN_IF1ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -544,33 +526,33 @@ typedef struct{
#define TMS570_DCAN_IF1ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF1MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF1MCTL--------------------*/
/* field: NewDat - New Data */
-#define TMS570_DCAN_IF1MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF1MCTL_NewDat BSP_BIT32(15)
/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF1MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF1MCTL_MsgLst BSP_BIT32(14)
/* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF1MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF1MCTL_IntPnd BSP_BIT32(13)
/* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF1MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF1MCTL_UMask BSP_BIT32(12)
/* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF1MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF1MCTL_TxIE BSP_BIT32(11)
/* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF1MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF1MCTL_RxIE BSP_BIT32(10)
/* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF1MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF1MCTL_RmtEn BSP_BIT32(9)
/* field: TxRqst - Transmit Request */
-#define TMS570_DCAN_IF1MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF1MCTL_TxRqst BSP_BIT32(8)
/* field: EoB - Data Frame has 0-8 data bits */
-#define TMS570_DCAN_IF1MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF1MCTL_EoB BSP_BIT32(7)
/* field: DLC - Data Length Code */
#define TMS570_DCAN_IF1MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -578,7 +560,7 @@ typedef struct{
#define TMS570_DCAN_IF1MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_DCANIF1DATA---------------------*/
+/*--------------------TMS570_DCAN_IF1DATA--------------------*/
/* field: Data0 - Data 0 */
#define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF1DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -600,7 +582,7 @@ typedef struct{
#define TMS570_DCAN_IF1DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF1DATB---------------------*/
+/*--------------------TMS570_DCAN_IF1DATB--------------------*/
/* field: Data4 - Data 4 */
#define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF1DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -622,36 +604,36 @@ typedef struct{
#define TMS570_DCAN_IF1DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF2CMD---------------------*/
+/*---------------------TMS570_DCAN_IF2CMD---------------------*/
/* field: WR_RD - Write/Read */
-#define TMS570_DCAN_IF2CMD_WR_RD BSP_FLD32(23)
+#define TMS570_DCAN_IF2CMD_WR_RD BSP_BIT32(23)
/* field: Mask - Access Mask bits */
-#define TMS570_DCAN_IF2CMD_Mask BSP_FLD32(22)
+#define TMS570_DCAN_IF2CMD_Mask BSP_BIT32(22)
/* field: Arb - Access Arbitration bits */
-#define TMS570_DCAN_IF2CMD_Arb BSP_FLD32(21)
+#define TMS570_DCAN_IF2CMD_Arb BSP_BIT32(21)
/* field: Control - Access Control bits */
-#define TMS570_DCAN_IF2CMD_Control BSP_FLD32(20)
+#define TMS570_DCAN_IF2CMD_Control BSP_BIT32(20)
/* field: ClrIntPnd - Clear Interrupt Pending bit */
-#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_FLD32(19)
+#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_BIT32(19)
/* field: TxRqst_NewDat - Access Transmission Request bit */
-#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_FLD32(18)
+#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_BIT32(18)
/* field: Data_A - Access Data Bytes 0-3 */
-#define TMS570_DCAN_IF2CMD_Data_A BSP_FLD32(17)
+#define TMS570_DCAN_IF2CMD_Data_A BSP_BIT32(17)
/* field: Data_B - Access Data Bytes 4-7 */
-#define TMS570_DCAN_IF2CMD_Data_B BSP_FLD32(16)
+#define TMS570_DCAN_IF2CMD_Data_B BSP_BIT32(16)
/* field: Busy - Busy flag */
-#define TMS570_DCAN_IF2CMD_Busy BSP_FLD32(15)
+#define TMS570_DCAN_IF2CMD_Busy BSP_BIT32(15)
/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
-#define TMS570_DCAN_IF2CMD_DMA_Active BSP_FLD32(14)
+#define TMS570_DCAN_IF2CMD_DMA_Active BSP_BIT32(14)
/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
#define TMS570_DCAN_IF2CMD_Message_Number(val) BSP_FLD32(val,0, 7)
@@ -659,12 +641,12 @@ typedef struct{
#define TMS570_DCAN_IF2CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_DCANIF2MSK---------------------*/
+/*---------------------TMS570_DCAN_IF2MSK---------------------*/
/* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF2MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF2MSK_MXtd BSP_BIT32(31)
/* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF2MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF2MSK_MDir BSP_BIT32(30)
/* field: Msk - Identifier Mask */
#define TMS570_DCAN_IF2MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -672,15 +654,15 @@ typedef struct{
#define TMS570_DCAN_IF2MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF2ARB---------------------*/
+/*---------------------TMS570_DCAN_IF2ARB---------------------*/
/* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF2ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF2ARB_MsgVal BSP_BIT32(31)
/* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF2ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF2ARB_Xtd BSP_BIT32(30)
/* field: Dir - Message direction */
-#define TMS570_DCAN_IF2ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF2ARB_Dir BSP_BIT32(29)
/* field: ID - Message Identifier */
#define TMS570_DCAN_IF2ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -688,33 +670,33 @@ typedef struct{
#define TMS570_DCAN_IF2ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF2MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF2MCTL--------------------*/
/* field: NewDat - New Data */
-#define TMS570_DCAN_IF2MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF2MCTL_NewDat BSP_BIT32(15)
/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF2MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF2MCTL_MsgLst BSP_BIT32(14)
/* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF2MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF2MCTL_IntPnd BSP_BIT32(13)
/* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF2MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF2MCTL_UMask BSP_BIT32(12)
/* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF2MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF2MCTL_TxIE BSP_BIT32(11)
/* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF2MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF2MCTL_RxIE BSP_BIT32(10)
/* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF2MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF2MCTL_RmtEn BSP_BIT32(9)
/* field: TxRqst - Transmit Request */
-#define TMS570_DCAN_IF2MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF2MCTL_TxRqst BSP_BIT32(8)
/* field: EoB - Data Frame has 0-8 data bits */
-#define TMS570_DCAN_IF2MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF2MCTL_EoB BSP_BIT32(7)
/* field: DLC - Data Length Code */
#define TMS570_DCAN_IF2MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -722,7 +704,7 @@ typedef struct{
#define TMS570_DCAN_IF2MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_DCANIF2DATA---------------------*/
+/*--------------------TMS570_DCAN_IF2DATA--------------------*/
/* field: Data0 - Data 0 */
#define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF2DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -744,7 +726,7 @@ typedef struct{
#define TMS570_DCAN_IF2DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF2DATB---------------------*/
+/*--------------------TMS570_DCAN_IF2DATB--------------------*/
/* field: Data4 - Data 4 */
#define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF2DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -766,47 +748,47 @@ typedef struct{
#define TMS570_DCAN_IF2DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF3OBS---------------------*/
+/*---------------------TMS570_DCAN_IF3OBS---------------------*/
/* field: IF3_Upd - IF3 Update Data */
-#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_FLD32(15)
+#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_BIT32(15)
/* field: IF3_SDB - IF3 Status of Data B read access */
-#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_FLD32(12)
+#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_BIT32(12)
/* field: IF3_SDA - IF3 Status of Data A read access */
-#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_FLD32(11)
+#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_BIT32(11)
/* field: IF3_SC - IF3 Status of Control bits read access */
-#define TMS570_DCAN_IF3OBS_IF3_SC BSP_FLD32(10)
+#define TMS570_DCAN_IF3OBS_IF3_SC BSP_BIT32(10)
/* field: IF3_SA - IF3 Status of Arbitration data read access */
-#define TMS570_DCAN_IF3OBS_IF3_SA BSP_FLD32(9)
+#define TMS570_DCAN_IF3OBS_IF3_SA BSP_BIT32(9)
/* field: IF3_SM - IF3 Status of Mask data read access */
-#define TMS570_DCAN_IF3OBS_IF3_SM BSP_FLD32(8)
+#define TMS570_DCAN_IF3OBS_IF3_SM BSP_BIT32(8)
/* field: Data_B - Data B read observation */
-#define TMS570_DCAN_IF3OBS_Data_B BSP_FLD32(4)
+#define TMS570_DCAN_IF3OBS_Data_B BSP_BIT32(4)
/* field: Data_A - Data A read observation */
-#define TMS570_DCAN_IF3OBS_Data_A BSP_FLD32(3)
+#define TMS570_DCAN_IF3OBS_Data_A BSP_BIT32(3)
/* field: Ctrl - Ctrl read observation */
-#define TMS570_DCAN_IF3OBS_Ctrl BSP_FLD32(2)
+#define TMS570_DCAN_IF3OBS_Ctrl BSP_BIT32(2)
/* field: Arb - Arbitration data read observation */
-#define TMS570_DCAN_IF3OBS_Arb BSP_FLD32(1)
+#define TMS570_DCAN_IF3OBS_Arb BSP_BIT32(1)
/* field: Mask - Mask data read observation */
-#define TMS570_DCAN_IF3OBS_Mask BSP_FLD32(0)
+#define TMS570_DCAN_IF3OBS_Mask BSP_BIT32(0)
-/*---------------------TMS570_DCANIF3MSK---------------------*/
+/*---------------------TMS570_DCAN_IF3MSK---------------------*/
/* field: MXtd - Mask Extended Identifier */
-#define TMS570_DCAN_IF3MSK_MXtd BSP_FLD32(31)
+#define TMS570_DCAN_IF3MSK_MXtd BSP_BIT32(31)
/* field: MDir - Mask Message Direction */
-#define TMS570_DCAN_IF3MSK_MDir BSP_FLD32(30)
+#define TMS570_DCAN_IF3MSK_MDir BSP_BIT32(30)
/* field: Msk - Identifier Mask */
#define TMS570_DCAN_IF3MSK_Msk(val) BSP_FLD32(val,0, 28)
@@ -814,15 +796,15 @@ typedef struct{
#define TMS570_DCAN_IF3MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF3ARB---------------------*/
+/*---------------------TMS570_DCAN_IF3ARB---------------------*/
/* field: MsgVal - Message Valid */
-#define TMS570_DCAN_IF3ARB_MsgVal BSP_FLD32(31)
+#define TMS570_DCAN_IF3ARB_MsgVal BSP_BIT32(31)
/* field: Xtd - Extended Identifier */
-#define TMS570_DCAN_IF3ARB_Xtd BSP_FLD32(30)
+#define TMS570_DCAN_IF3ARB_Xtd BSP_BIT32(30)
/* field: Dir - Message direction */
-#define TMS570_DCAN_IF3ARB_Dir BSP_FLD32(29)
+#define TMS570_DCAN_IF3ARB_Dir BSP_BIT32(29)
/* field: ID - Message Identifier */
#define TMS570_DCAN_IF3ARB_ID(val) BSP_FLD32(val,0, 28)
@@ -830,33 +812,33 @@ typedef struct{
#define TMS570_DCAN_IF3ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
-/*---------------------TMS570_DCANIF3MCTL---------------------*/
+/*--------------------TMS570_DCAN_IF3MCTL--------------------*/
/* field: NewDat - New Data */
-#define TMS570_DCAN_IF3MCTL_NewDat BSP_FLD32(15)
+#define TMS570_DCAN_IF3MCTL_NewDat BSP_BIT32(15)
/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
-#define TMS570_DCAN_IF3MCTL_MsgLst BSP_FLD32(14)
+#define TMS570_DCAN_IF3MCTL_MsgLst BSP_BIT32(14)
/* field: IntPnd - Interrupt Pending */
-#define TMS570_DCAN_IF3MCTL_IntPnd BSP_FLD32(13)
+#define TMS570_DCAN_IF3MCTL_IntPnd BSP_BIT32(13)
/* field: UMask - Use Acceptance Mask */
-#define TMS570_DCAN_IF3MCTL_UMask BSP_FLD32(12)
+#define TMS570_DCAN_IF3MCTL_UMask BSP_BIT32(12)
/* field: TxIE - Transmit Interrupt Enable */
-#define TMS570_DCAN_IF3MCTL_TxIE BSP_FLD32(11)
+#define TMS570_DCAN_IF3MCTL_TxIE BSP_BIT32(11)
/* field: RxIE - Receive Interrupt Enable */
-#define TMS570_DCAN_IF3MCTL_RxIE BSP_FLD32(10)
+#define TMS570_DCAN_IF3MCTL_RxIE BSP_BIT32(10)
/* field: RmtEn - Remote Enable */
-#define TMS570_DCAN_IF3MCTL_RmtEn BSP_FLD32(9)
+#define TMS570_DCAN_IF3MCTL_RmtEn BSP_BIT32(9)
/* field: TxRqst - TxRqst */
-#define TMS570_DCAN_IF3MCTL_TxRqst BSP_FLD32(8)
+#define TMS570_DCAN_IF3MCTL_TxRqst BSP_BIT32(8)
/* field: EoB - End of Block */
-#define TMS570_DCAN_IF3MCTL_EoB BSP_FLD32(7)
+#define TMS570_DCAN_IF3MCTL_EoB BSP_BIT32(7)
/* field: DLC - Data Length Code */
#define TMS570_DCAN_IF3MCTL_DLC(val) BSP_FLD32(val,0, 3)
@@ -864,7 +846,7 @@ typedef struct{
#define TMS570_DCAN_IF3MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_DCANIF3DATA---------------------*/
+/*--------------------TMS570_DCAN_IF3DATA--------------------*/
/* field: Data0 - Data 0 */
#define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF3DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -886,7 +868,7 @@ typedef struct{
#define TMS570_DCAN_IF3DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF3DATB---------------------*/
+/*--------------------TMS570_DCAN_IF3DATB--------------------*/
/* field: Data4 - Data 4 */
#define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7)
#define TMS570_DCAN_IF3DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -908,55 +890,52 @@ typedef struct{
#define TMS570_DCAN_IF3DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
-/*---------------------TMS570_DCANIF3UEy---------------------*/
+/*---------------------TMS570_DCAN_IF3UEy---------------------*/
/* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */
-#define TMS570_DCAN_IF3UEy_IF3UpdEn(val) BSP_FLD32(val,0, 31)
-#define TMS570_DCAN_IF3UEy_IF3UpdEn_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DCAN_IF3UEy_IF3UpdEn_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_DCANTIOC----------------------*/
+/*----------------------TMS570_DCAN_TIOC----------------------*/
/* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */
-#define TMS570_DCAN_TIOC_PU BSP_FLD32(18)
+#define TMS570_DCAN_TIOC_PU BSP_BIT32(18)
/* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */
-#define TMS570_DCAN_TIOC_PD BSP_FLD32(17)
+#define TMS570_DCAN_TIOC_PD BSP_BIT32(17)
/* field: OD - CAN_TX open drain enable. */
-#define TMS570_DCAN_TIOC_OD BSP_FLD32(16)
+#define TMS570_DCAN_TIOC_OD BSP_BIT32(16)
/* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */
-#define TMS570_DCAN_TIOC_Func BSP_FLD32(3)
+#define TMS570_DCAN_TIOC_Func BSP_BIT32(3)
/* field: Dir - CAN_TX data direction. */
-#define TMS570_DCAN_TIOC_Dir BSP_FLD32(2)
+#define TMS570_DCAN_TIOC_Dir BSP_BIT32(2)
/* field: Out - CAN_TX data out write. */
-#define TMS570_DCAN_TIOC_Out BSP_FLD32(1)
+#define TMS570_DCAN_TIOC_Out BSP_BIT32(1)
-/*----------------------TMS570_DCANRIOC----------------------*/
+/*----------------------TMS570_DCAN_RIOC----------------------*/
/* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */
-#define TMS570_DCAN_RIOC_PU BSP_FLD32(18)
+#define TMS570_DCAN_RIOC_PU BSP_BIT32(18)
/* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */
-#define TMS570_DCAN_RIOC_PD BSP_FLD32(17)
+#define TMS570_DCAN_RIOC_PD BSP_BIT32(17)
/* field: OD - CAN_RX open drain enable. */
-#define TMS570_DCAN_RIOC_OD BSP_FLD32(16)
+#define TMS570_DCAN_RIOC_OD BSP_BIT32(16)
/* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */
-#define TMS570_DCAN_RIOC_Func BSP_FLD32(3)
+#define TMS570_DCAN_RIOC_Func BSP_BIT32(3)
/* field: Dir - CAN_RX data direction. */
-#define TMS570_DCAN_RIOC_Dir BSP_FLD32(2)
+#define TMS570_DCAN_RIOC_Dir BSP_BIT32(2)
/* field: Out - CAN_RX data out write. */
-#define TMS570_DCAN_RIOC_Out BSP_FLD32(1)
+#define TMS570_DCAN_RIOC_Out BSP_BIT32(1)
/* field: In - CAN_RX data in. */
-#define TMS570_DCAN_RIOC_In BSP_FLD32(0)
+#define TMS570_DCAN_RIOC_In BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_DCAN */
+#endif /* LIBBSP_ARM_TMS570_DCAN */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
index 73b9232..4c90276 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_DCC
-#define LIBBSP_ARM_tms570_DCC
+#ifndef LIBBSP_ARM_TMS570_DCC
+#define LIBBSP_ARM_TMS570_DCC
#include <bsp/utility.h>
@@ -56,7 +56,7 @@ typedef struct{
} tms570_dcc_t;
-/*----------------------TMS570_DCCGCTRL----------------------*/
+/*----------------------TMS570_DCC_GCTRL----------------------*/
/* field: DONE_INT_ENA - Done Interrupt Enable. */
#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15)
@@ -78,7 +78,7 @@ typedef struct{
#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_DCCREV-----------------------*/
+/*-----------------------TMS570_DCC_REV-----------------------*/
/* field: SCHEME - Reads return 01, writes have no effect. */
#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -110,57 +110,57 @@ typedef struct{
#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*---------------------TMS570_DCCCNT0SEED---------------------*/
+/*--------------------TMS570_DCC_CNT0SEED--------------------*/
/* field: COUNT0_SEED - Seed value for DCC Counter0. */
#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*--------------------TMS570_DCCVALID0SEED--------------------*/
+/*-------------------TMS570_DCC_VALID0SEED-------------------*/
/* field: VALID0_SEED - XXX */
#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DCCCNT1SEED---------------------*/
+/*--------------------TMS570_DCC_CNT1SEED--------------------*/
/* field: COUNT1_SEED - Seed value for DCC Counter1. */
#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*-----------------------TMS570_DCCSTAT-----------------------*/
+/*----------------------TMS570_DCC_STAT----------------------*/
/* field: DONE_FLG - Single-Shot Sequence Done flag. */
-#define TMS570_DCC_STAT_DONE_FLG BSP_FLD32(1)
+#define TMS570_DCC_STAT_DONE_FLG BSP_BIT32(1)
/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
-#define TMS570_DCC_STAT_ERR_FLG BSP_FLD32(0)
+#define TMS570_DCC_STAT_ERR_FLG BSP_BIT32(0)
-/*-----------------------TMS570_DCCCNT0-----------------------*/
+/*----------------------TMS570_DCC_CNT0----------------------*/
/* field: COUNT0 - Current value of DCC Counter0. */
#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*----------------------TMS570_DCCVALID0----------------------*/
+/*---------------------TMS570_DCC_VALID0---------------------*/
/* field: VALID0 - Current value for DCC Valid0. */
#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_DCCCNT1-----------------------*/
+/*----------------------TMS570_DCC_CNT1----------------------*/
/* field: COUNT1 - Current value for DCC Counter1. */
#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
-/*--------------------TMS570_DCCCNT1CLKSRC--------------------*/
+/*-------------------TMS570_DCC_CNT1CLKSRC-------------------*/
/* field: KEY - Key to enable clock source selection for Counter1. */
#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15)
@@ -172,7 +172,7 @@ typedef struct{
#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_DCCCNT0CLKSRC--------------------*/
+/*-------------------TMS570_DCC_CNT0CLKSRC-------------------*/
/* field: CNT0_CLKSRC - Clock Source for Counter0 */
#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -180,4 +180,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_DCC */
+#endif /* LIBBSP_ARM_TMS570_DCC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
index acef5a0..717f05b 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_DMA
-#define LIBBSP_ARM_tms570_DMA
+#ifndef LIBBSP_ARM_TMS570_DMA
+#define LIBBSP_ARM_TMS570_DMA
#include <bsp/utility.h>
@@ -140,26 +140,20 @@ typedef struct{
} tms570_dma_t;
-/*---------------------TMS570_DMASTARTADD---------------------*/
+/*--------------------TMS570_DMA_STARTADD--------------------*/
/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
-#define TMS570_DMA_STARTADD_STARTADDRESS(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_STARTADD_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_STARTADD_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_DMAENDADD----------------------*/
+/*---------------------TMS570_DMA_ENDADD---------------------*/
/* field: ENDADDRESS - End Address defines the address at which the region ends. */
-#define TMS570_DMA_ENDADD_ENDADDRESS(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_ENDADD_ENDADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_ENDADD_ENDADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_DMAGCTRL----------------------*/
+/*----------------------TMS570_DMA_GCTRL----------------------*/
/* field: DMA_EN - DMA enable bit. */
-#define TMS570_DMA_GCTRL_DMA_EN BSP_FLD32(16)
+#define TMS570_DMA_GCTRL_DMA_EN BSP_BIT32(16)
/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
-#define TMS570_DMA_GCTRL_BUS_BUSY BSP_FLD32(14)
+#define TMS570_DMA_GCTRL_BUS_BUSY BSP_BIT32(14)
/* field: DEBUG_MODE - Debug Mode. */
#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
@@ -167,80 +161,80 @@ typedef struct{
#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: DMA_RES - DMA software reset */
-#define TMS570_DMA_GCTRL_DMA_RES BSP_FLD32(0)
+#define TMS570_DMA_GCTRL_DMA_RES BSP_BIT32(0)
-/*-----------------------TMS570_DMAPEND-----------------------*/
+/*----------------------TMS570_DMA_PEND----------------------*/
/* field: PEND - Channel pending register. */
#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMADMASTAT---------------------*/
+/*---------------------TMS570_DMA_DMASTAT---------------------*/
/* field: STCH - Status of DMA channels. */
#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAHWCHENAS---------------------*/
+/*--------------------TMS570_DMA_HWCHENAS--------------------*/
/* field: HWCHENA - Hardware channel enable bit. */
#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAHWCHENAR---------------------*/
+/*--------------------TMS570_DMA_HWCHENAR--------------------*/
/* field: HWCHDIS - HW channel disable bit. */
#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMASWCHENAS---------------------*/
+/*--------------------TMS570_DMA_SWCHENAS--------------------*/
/* field: SWCHENA - SW channel enable bit. */
#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMASWCHENAR---------------------*/
+/*--------------------TMS570_DMA_SWCHENAR--------------------*/
/* field: SWCHDIS - SW channel disable bit. */
#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMACHPRIOS---------------------*/
+/*---------------------TMS570_DMA_CHPRIOS---------------------*/
/* field: CPS - Channel priority set bit. */
#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMACHPRIOR---------------------*/
+/*---------------------TMS570_DMA_CHPRIOR---------------------*/
/* field: CPR - Channel priority reset bit. */
#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAGCHIENAS---------------------*/
+/*--------------------TMS570_DMA_GCHIENAS--------------------*/
/* field: GCHIE - Global channel interrupt enable bit. */
#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAGCHIENAR---------------------*/
+/*--------------------TMS570_DMA_GCHIENAR--------------------*/
/* field: GCHID - Global channel interrupt disable bit. */
#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMADREQASI---------------------*/
+/*---------------------TMS570_DMA_DREQASI---------------------*/
/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
@@ -262,7 +256,7 @@ typedef struct{
#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------------TMS570_DMAPAR0-----------------------*/
+/*----------------------TMS570_DMA_PAR0----------------------*/
/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
@@ -304,7 +298,7 @@ typedef struct{
#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_DMAPAR1-----------------------*/
+/*----------------------TMS570_DMA_PAR1----------------------*/
/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
@@ -346,140 +340,140 @@ typedef struct{
#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_DMAFTCMAP----------------------*/
+/*---------------------TMS570_DMA_FTCMAP---------------------*/
/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_DMALFSMAP----------------------*/
+/*---------------------TMS570_DMA_LFSMAP---------------------*/
/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_DMAHBCMAP----------------------*/
+/*---------------------TMS570_DMA_HBCMAP---------------------*/
/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_DMABTCMAP----------------------*/
+/*---------------------TMS570_DMA_BTCMAP---------------------*/
/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_DMABERMAP----------------------*/
+/*---------------------TMS570_DMA_BERMAP---------------------*/
/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMAFTCINTENAS--------------------*/
+/*-------------------TMS570_DMA_FTCINTENAS-------------------*/
/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMAFTCINTENAR--------------------*/
+/*-------------------TMS570_DMA_FTCINTENAR-------------------*/
/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMALFSINTENAS--------------------*/
+/*-------------------TMS570_DMA_LFSINTENAS-------------------*/
/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMALFSINTENAR--------------------*/
+/*-------------------TMS570_DMA_LFSINTENAR-------------------*/
/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMAHBCINTENAS--------------------*/
+/*-------------------TMS570_DMA_HBCINTENAS-------------------*/
/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMAHBCINTENAR--------------------*/
+/*-------------------TMS570_DMA_HBCINTENAR-------------------*/
/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMABTCINTENAS--------------------*/
+/*-------------------TMS570_DMA_BTCINTENAS-------------------*/
/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMABTCINTENAR--------------------*/
+/*-------------------TMS570_DMA_BTCINTENAR-------------------*/
/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAGINTFLAG---------------------*/
+/*--------------------TMS570_DMA_GINTFLAG--------------------*/
/* field: GINT - Global interrupt flags. */
#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAFTCFLAG---------------------*/
+/*---------------------TMS570_DMA_FTCFLAG---------------------*/
/* field: FTCI - Frame transfer complete (FTC) flags. */
#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMALFSFLAG---------------------*/
+/*---------------------TMS570_DMA_LFSFLAG---------------------*/
/* field: LFSI - Last frame started (LFS) flags. */
#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMAHBCFLAG---------------------*/
+/*---------------------TMS570_DMA_HBCFLAG---------------------*/
/* field: HBCI - Half block transfer (HBC) complete flags. */
#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMABTCFLAG---------------------*/
+/*---------------------TMS570_DMA_BTCFLAG---------------------*/
/* field: BTCI - Block transfer complete (BTC) flags. */
#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_DMABERFLAG---------------------*/
+/*---------------------TMS570_DMA_BERFLAG---------------------*/
/* field: BERI - Bus error (BER) flags. */
#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_DMAFTCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_FTCAOFFSET-------------------*/
/* field: sbz - These bits should always be programmed as zero. */
#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
@@ -491,130 +485,118 @@ typedef struct{
#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMALFSAOFFSET--------------------*/
+/*-------------------TMS570_DMA_LFSAOFFSET-------------------*/
/* field: LFSA - Channel causing LFS interrupt Group A. */
#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMAHBCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_HBCAOFFSET-------------------*/
/* field: HBCA - Channel causing HBC interrupt Group A. */
#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMABTCAOFFSET--------------------*/
+/*-------------------TMS570_DMA_BTCAOFFSET-------------------*/
/* field: BTCA - Channel causing BTC interrupt Group A. */
#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMABERAOFFSET--------------------*/
+/*-------------------TMS570_DMA_BERAOFFSET-------------------*/
/* field: BERA - Channel causing BER interrupt Group A. */
#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMAFTCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_FTCBOFFSET-------------------*/
/* field: FTCB - Channel causing FTC interrupt Group B. */
#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMALFSBOFFSET--------------------*/
+/*-------------------TMS570_DMA_LFSBOFFSET-------------------*/
/* field: LFSB - Channel causing LFS interrupt Group B. */
#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMAHBCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_HBCBOFFSET-------------------*/
/* field: HBCB - Channel causing HBC interrupt Group B. */
#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMABTCBOFFSET--------------------*/
+/*-------------------TMS570_DMA_BTCBOFFSET-------------------*/
/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*--------------------TMS570_DMABERBOFFSET--------------------*/
+/*-------------------TMS570_DMA_BERBOFFSET-------------------*/
/* field: BERB - Channel causing BER interrupt Group B. */
#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*----------------------TMS570_DMAPTCRL----------------------*/
+/*----------------------TMS570_DMA_PTCRL----------------------*/
/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
-#define TMS570_DMA_PTCRL_PENDB BSP_FLD32(24)
+#define TMS570_DMA_PTCRL_PENDB BSP_BIT32(24)
/* field: BYB - Bypass FIFO B. */
-#define TMS570_DMA_PTCRL_BYB BSP_FLD32(18)
+#define TMS570_DMA_PTCRL_BYB BSP_BIT32(18)
/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
-#define TMS570_DMA_PTCRL_PSFRHQPB BSP_FLD32(17)
+#define TMS570_DMA_PTCRL_PSFRHQPB BSP_BIT32(17)
/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
-#define TMS570_DMA_PTCRL_PSFRLQPB BSP_FLD32(16)
+#define TMS570_DMA_PTCRL_PSFRLQPB BSP_BIT32(16)
-/*----------------------TMS570_DMARTCTRL----------------------*/
+/*---------------------TMS570_DMA_RTCTRL---------------------*/
/* field: RTC - RAM Test Control. */
-#define TMS570_DMA_RTCTRL_RTC BSP_FLD32(0)
+#define TMS570_DMA_RTCTRL_RTC BSP_BIT32(0)
-/*----------------------TMS570_DMADCTRL----------------------*/
+/*----------------------TMS570_DMA_DCTRL----------------------*/
/* field: CHNUM - Channel Number. */
#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: DMADBGS - DMA debug status. */
-#define TMS570_DMA_DCTRL_DMADBGS BSP_FLD32(16)
+#define TMS570_DMA_DCTRL_DMADBGS BSP_BIT32(16)
/* field: DBGEN - Debug Enable. */
-#define TMS570_DMA_DCTRL_DBGEN BSP_FLD32(0)
+#define TMS570_DMA_DCTRL_DBGEN BSP_BIT32(0)
-/*-----------------------TMS570_DMAWPR-----------------------*/
+/*-----------------------TMS570_DMA_WPR-----------------------*/
/* field: WP - Watch point. */
-#define TMS570_DMA_WPR_WP(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_DMAWMR-----------------------*/
+/*-----------------------TMS570_DMA_WMR-----------------------*/
/* field: WM - Watch mask. */
-#define TMS570_DMA_WMR_WM(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_DMAPBACSADDR--------------------*/
+/*--------------------TMS570_DMA_PBACSADDR--------------------*/
/* field: PBACSA - Port B Active Channel Source Address. */
-#define TMS570_DMA_PBACSADDR_PBACSA(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_PBACSADDR_PBACSA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_PBACSADDR_PBACSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_DMAPBACDADDR--------------------*/
+/*--------------------TMS570_DMA_PBACDADDR--------------------*/
/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
-#define TMS570_DMA_PBACDADDR_PBACDA(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_PBACDADDR_PBACDA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_PBACDADDR_PBACDA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_DMAPBACTC----------------------*/
+/*---------------------TMS570_DMA_PBACTC---------------------*/
/* field: PBFTCOUNT - Port B active channel frame count. */
#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
@@ -626,12 +608,12 @@ typedef struct{
#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
-/*----------------------TMS570_DMADMAPCR----------------------*/
+/*---------------------TMS570_DMA_DMAPCR---------------------*/
/* field: ERRA - Error action. */
-#define TMS570_DMA_DMAPCR_ERRA BSP_FLD32(16)
+#define TMS570_DMA_DMAPCR_ERRA BSP_BIT32(16)
/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
-#define TMS570_DMA_DMAPCR_TEST BSP_FLD32(8)
+#define TMS570_DMA_DMAPCR_TEST BSP_BIT32(8)
/* field: PARITY_ENA - Parity error detection enable. */
#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -639,9 +621,9 @@ typedef struct{
#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_DMADMAPAR----------------------*/
+/*---------------------TMS570_DMA_DMAPAR---------------------*/
/* field: EDFLAG - Parity Error Detection Flag. */
-#define TMS570_DMA_DMAPAR_EDFLAG BSP_FLD32(24)
+#define TMS570_DMA_DMAPAR_EDFLAG BSP_BIT32(24)
/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
@@ -649,12 +631,12 @@ typedef struct{
#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
-/*--------------------TMS570_DMADMAMPCTRL--------------------*/
+/*--------------------TMS570_DMA_DMAMPCTRL--------------------*/
/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_FLD32(28)
+#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_BIT32(28)
/* field: INT3ENA - Interrupt enable of region 3. */
-#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_FLD32(27)
+#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_BIT32(27)
/* field: REG3AP - Region 3 access permission. */
#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
@@ -662,13 +644,13 @@ typedef struct{
#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
/* field: REG3ENA - Region 3 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_FLD32(24)
+#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_BIT32(24)
/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_FLD32(20)
+#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_BIT32(20)
/* field: INT2ENA - Interrupt enable of region 2. */
-#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_FLD32(19)
+#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_BIT32(19)
/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
@@ -676,13 +658,13 @@ typedef struct{
#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
/* field: REG2ENA - Region 2 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_FLD32(16)
+#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_BIT32(16)
/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_FLD32(12)
+#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_BIT32(12)
/* field: INT1ENA - Interrupt enable of region 1. */
-#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_FLD32(11)
+#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_BIT32(11)
/* field: REG1AP - Region 1 access permission. */
#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
@@ -690,13 +672,13 @@ typedef struct{
#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
/* field: REG1ENA - Region 1 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_FLD32(8)
+#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_BIT32(8)
/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
-#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_FLD32(4)
+#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_BIT32(4)
/* field: INT0ENA - Interrupt enable of region 0. */
-#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_FLD32(3)
+#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_BIT32(3)
/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
@@ -704,29 +686,26 @@ typedef struct{
#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
/* field: REG0ENA - Region 0 enable. */
-#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_FLD32(0)
+#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_BIT32(0)
-/*---------------------TMS570_DMADMAMPST---------------------*/
+/*---------------------TMS570_DMA_DMAMPST---------------------*/
/* field: REG3FT - Region 3 fault. */
-#define TMS570_DMA_DMAMPST_REG3FT BSP_FLD32(24)
+#define TMS570_DMA_DMAMPST_REG3FT BSP_BIT32(24)
/* field: REG2FT - Region 2 fault. */
-#define TMS570_DMA_DMAMPST_REG2FT BSP_FLD32(16)
+#define TMS570_DMA_DMAMPST_REG2FT BSP_BIT32(16)
/* field: REG1FT - Region 1 fault. */
-#define TMS570_DMA_DMAMPST_REG1FT BSP_FLD32(8)
+#define TMS570_DMA_DMAMPST_REG1FT BSP_BIT32(8)
/* field: REG0FT - Region 0 fault. */
-#define TMS570_DMA_DMAMPST_REG0FT BSP_FLD32(0)
+#define TMS570_DMA_DMAMPST_REG0FT BSP_BIT32(0)
-/*---------------------TMS570_DMADMAMPROS---------------------*/
+/*--------------------TMS570_DMA_DMAMPROS--------------------*/
/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
-#define TMS570_DMA_DMAMPROS_STARTADDRESS(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMA_DMAMPROS_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMA_DMAMPROS_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_DMA */
+#endif /* LIBBSP_ARM_TMS570_DMA */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
index 1d45ac7..55d656e 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_DMM
-#define LIBBSP_ARM_tms570_DMM
+#ifndef LIBBSP_ARM_TMS570_DMM
+#define LIBBSP_ARM_TMS570_DMM
#include <bsp/utility.h>
@@ -81,18 +81,18 @@ typedef struct{
} tms570_dmm_t;
-/*---------------------TMS570_DMMGLBCTRL---------------------*/
+/*---------------------TMS570_DMM_GLBCTRL---------------------*/
/* field: BUSY - Busy indicator. */
-#define TMS570_DMM_GLBCTRL_BUSY BSP_FLD32(24)
+#define TMS570_DMM_GLBCTRL_BUSY BSP_BIT32(24)
/* field: CONTCLK - Continuous DMMCLK input. */
-#define TMS570_DMM_GLBCTRL_CONTCLK BSP_FLD32(18)
+#define TMS570_DMM_GLBCTRL_CONTCLK BSP_BIT32(18)
/* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
-#define TMS570_DMM_GLBCTRL_COS BSP_FLD32(17)
+#define TMS570_DMM_GLBCTRL_COS BSP_BIT32(17)
/* field: RESET - Reset. */
-#define TMS570_DMM_GLBCTRL_RESET BSP_FLD32(16)
+#define TMS570_DMM_GLBCTRL_RESET BSP_BIT32(16)
/* field: DDM_WIDTH - Packet Width in direct data mode. */
#define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10)
@@ -100,7 +100,7 @@ typedef struct{
#define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
/* field: TM_DMM - Packet Format. */
-#define TMS570_DMM_GLBCTRL_TM_DMM BSP_FLD32(8)
+#define TMS570_DMM_GLBCTRL_TM_DMM BSP_BIT32(8)
/* field: ON_OFF - Switch module on or off */
#define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
@@ -108,313 +108,310 @@ typedef struct{
#define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_DMMINTSET----------------------*/
+/*---------------------TMS570_DMM_INTSET---------------------*/
/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
-#define TMS570_DMM_INTSET_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTSET_PROG_BUFF BSP_BIT32(17)
/* field: EO_BUFF - EO_BUFF */
-#define TMS570_DMM_INTSET_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTSET_EO_BUFF BSP_BIT32(16)
/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTSET_DEST3REG2 BSP_BIT32(15)
/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTSET_DEST3REG1 BSP_BIT32(14)
/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTSET_DEST2REG2 BSP_BIT32(13)
/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTSET_DEST2REG1 BSP_BIT32(12)
/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTSET_DEST1REG2 BSP_BIT32(11)
/* field: DEST1REG1 - DEST1REG1 */
-#define TMS570_DMM_INTSET_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTSET_DEST1REG1 BSP_BIT32(10)
/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTSET_DEST0REG2 BSP_BIT32(9)
/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTSET_DEST0REG1 BSP_BIT32(8)
/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
-#define TMS570_DMM_INTSET_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTSET_BUSERROR BSP_BIT32(7)
/* field: BUFF_OVF - Buffer Overflow. */
-#define TMS570_DMM_INTSET_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTSET_BUFF_OVF BSP_BIT32(6)
/* field: SRC_OVF - Source Overflow. */
-#define TMS570_DMM_INTSET_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTSET_SRC_OVF BSP_BIT32(5)
/* field: DEST3_ERR - Destination 3 Error. */
-#define TMS570_DMM_INTSET_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTSET_DEST3_ERR BSP_BIT32(4)
/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTSET_DEST2_ERR BSP_BIT32(3)
/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTSET_DEST1_ERR BSP_BIT32(2)
/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
-#define TMS570_DMM_INTSET_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTSET_DEST0_ERR BSP_BIT32(1)
/* field: PACKET_ERR_INT - Packet Error. */
-#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_BIT32(0)
-/*----------------------TMS570_DMMINTCLR----------------------*/
+/*---------------------TMS570_DMM_INTCLR---------------------*/
/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
-#define TMS570_DMM_INTCLR_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTCLR_PROG_BUFF BSP_BIT32(17)
/* field: EO_BUFF - End of Buffer Interrupt Set. */
-#define TMS570_DMM_INTCLR_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTCLR_EO_BUFF BSP_BIT32(16)
/* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
-#define TMS570_DMM_INTCLR_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTCLR_DEST3REG2 BSP_BIT32(15)
/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTCLR_DEST3REG1 BSP_BIT32(14)
/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTCLR_DEST2REG2 BSP_BIT32(13)
/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTCLR_DEST2REG1 BSP_BIT32(12)
/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTCLR_DEST1REG2 BSP_BIT32(11)
/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTCLR_DEST1REG1 BSP_BIT32(10)
/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTCLR_DEST0REG2 BSP_BIT32(9)
/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTCLR_DEST0REG1 BSP_BIT32(8)
/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
-#define TMS570_DMM_INTCLR_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTCLR_BUSERROR BSP_BIT32(7)
/* field: BUFF_OVF - Buffer Overflow. */
-#define TMS570_DMM_INTCLR_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTCLR_BUFF_OVF BSP_BIT32(6)
/* field: SRC_OVF - Source Overflow. */
-#define TMS570_DMM_INTCLR_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTCLR_SRC_OVF BSP_BIT32(5)
/* field: DEST3_ERR - Destination 3 Error. */
-#define TMS570_DMM_INTCLR_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTCLR_DEST3_ERR BSP_BIT32(4)
/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTCLR_DEST2_ERR BSP_BIT32(3)
/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTCLR_DEST1_ERR BSP_BIT32(2)
/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
-#define TMS570_DMM_INTCLR_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTCLR_DEST0_ERR BSP_BIT32(1)
/* field: PACKET_ERR_INT - Packet Error. */
-#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_BIT32(0)
-/*----------------------TMS570_DMMINTLVL----------------------*/
+/*---------------------TMS570_DMM_INTLVL---------------------*/
/* field: PROG_BUFF - Programmable Buffer Interrupt Level */
-#define TMS570_DMM_INTLVL_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTLVL_PROG_BUFF BSP_BIT32(17)
/* field: EO_BUFF - End of Buffer Interrupt Level */
-#define TMS570_DMM_INTLVL_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTLVL_EO_BUFF BSP_BIT32(16)
/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTLVL_DEST3REG2 BSP_BIT32(15)
/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTLVL_DEST3REG1 BSP_BIT32(14)
/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTLVL_DEST2REG2 BSP_BIT32(13)
/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTLVL_DEST2REG1 BSP_BIT32(12)
/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTLVL_DEST1REG2 BSP_BIT32(11)
/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTLVL_DEST1REG1 BSP_BIT32(10)
/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTLVL_DEST0REG2 BSP_BIT32(9)
/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTLVL_DEST0REG1 BSP_BIT32(8)
/* field: BUSERROR - BMM Bus Error Response */
-#define TMS570_DMM_INTLVL_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTLVL_BUSERROR BSP_BIT32(7)
/* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
-#define TMS570_DMM_INTLVL_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTLVL_BUFF_OVF BSP_BIT32(6)
/* field: SRC_OVF - Source Overflow Interrupt Level */
-#define TMS570_DMM_INTLVL_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTLVL_SRC_OVF BSP_BIT32(5)
/* field: DEST3_ERR - Destination 3 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTLVL_DEST3_ERR BSP_BIT32(4)
/* field: DEST2_ERR - Destination 2 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTLVL_DEST2_ERR BSP_BIT32(3)
/* field: DEST1_ERR - Destination 1 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTLVL_DEST1_ERR BSP_BIT32(2)
/* field: DEST0_ERR - Destination 0 Error Interrupt Level */
-#define TMS570_DMM_INTLVL_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTLVL_DEST0_ERR BSP_BIT32(1)
/* field: PACKET_ERR_INT - Packet Error Interrupt Level */
-#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_BIT32(0)
-/*----------------------TMS570_DMMINTFLG----------------------*/
+/*---------------------TMS570_DMM_INTFLG---------------------*/
/* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
-#define TMS570_DMM_INTFLG_PROG_BUFF BSP_FLD32(17)
+#define TMS570_DMM_INTFLG_PROG_BUFF BSP_BIT32(17)
/* field: EO_BUFF - End of Buffer Interrupt Flag */
-#define TMS570_DMM_INTFLG_EO_BUFF BSP_FLD32(16)
+#define TMS570_DMM_INTFLG_EO_BUFF BSP_BIT32(16)
/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3REG2 BSP_FLD32(15)
+#define TMS570_DMM_INTFLG_DEST3REG2 BSP_BIT32(15)
/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3REG1 BSP_FLD32(14)
+#define TMS570_DMM_INTFLG_DEST3REG1 BSP_BIT32(14)
/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2REG2 BSP_FLD32(13)
+#define TMS570_DMM_INTFLG_DEST2REG2 BSP_BIT32(13)
/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2REG1 BSP_FLD32(12)
+#define TMS570_DMM_INTFLG_DEST2REG1 BSP_BIT32(12)
/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1REG2 BSP_FLD32(11)
+#define TMS570_DMM_INTFLG_DEST1REG2 BSP_BIT32(11)
/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1REG1 BSP_FLD32(10)
+#define TMS570_DMM_INTFLG_DEST1REG1 BSP_BIT32(10)
/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0REG2 BSP_FLD32(9)
+#define TMS570_DMM_INTFLG_DEST0REG2 BSP_BIT32(9)
/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0REG1 BSP_FLD32(8)
+#define TMS570_DMM_INTFLG_DEST0REG1 BSP_BIT32(8)
/* field: BUSERROR - BMM Bus Error Response. */
-#define TMS570_DMM_INTFLG_BUSERROR BSP_FLD32(7)
+#define TMS570_DMM_INTFLG_BUSERROR BSP_BIT32(7)
/* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
-#define TMS570_DMM_INTFLG_BUFF_OVF BSP_FLD32(6)
+#define TMS570_DMM_INTFLG_BUFF_OVF BSP_BIT32(6)
/* field: SRC_OVF - Source Overflow Interrupt Flag */
-#define TMS570_DMM_INTFLG_SRC_OVF BSP_FLD32(5)
+#define TMS570_DMM_INTFLG_SRC_OVF BSP_BIT32(5)
/* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST3_ERR BSP_FLD32(4)
+#define TMS570_DMM_INTFLG_DEST3_ERR BSP_BIT32(4)
/* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST2_ERR BSP_FLD32(3)
+#define TMS570_DMM_INTFLG_DEST2_ERR BSP_BIT32(3)
/* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST1_ERR BSP_FLD32(2)
+#define TMS570_DMM_INTFLG_DEST1_ERR BSP_BIT32(2)
/* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_DEST0_ERR BSP_FLD32(1)
+#define TMS570_DMM_INTFLG_DEST0_ERR BSP_BIT32(1)
/* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
-#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_FLD32(0)
+#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_BIT32(0)
-/*-----------------------TMS570_DMMOFF1-----------------------*/
+/*----------------------TMS570_DMM_OFF1----------------------*/
/* field: OFFSET - User and privilege mode (read): */
#define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
#define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*-----------------------TMS570_DMMOFF2-----------------------*/
+/*----------------------TMS570_DMM_OFF2----------------------*/
/* field: OFFSET - User and privilege mode (read): */
#define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
#define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*---------------------TMS570_DMMDDMDEST---------------------*/
+/*---------------------TMS570_DMM_DDMDEST---------------------*/
/* field: STARTADDR - These bits define the starting address of the buffer. */
-#define TMS570_DMM_DDMDEST_STARTADDR(val) BSP_FLD32(val,0, 31)
-#define TMS570_DMM_DDMDEST_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_DMM_DDMDEST_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_DMMDDMBL----------------------*/
+/*----------------------TMS570_DMM_DDMBL----------------------*/
/* field: BLOCKSIZE - These bits define the size of the buffer region */
#define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
#define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_DMMDDMPT----------------------*/
+/*----------------------TMS570_DMM_DDMPT----------------------*/
/* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
#define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
#define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14)
#define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
-/*----------------------TMS570_DMMINTPT----------------------*/
+/*----------------------TMS570_DMM_INTPT----------------------*/
/* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
#define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
#define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14)
#define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
-/*--------------------TMS570_DMMDEST0REG1--------------------*/
+/*--------------------TMS570_DMM_DESTxREG1--------------------*/
/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
-#define TMS570_DMM_DEST0REG1_BASEADDR(val) BSP_FLD32(val,18, 31)
-#define TMS570_DMM_DEST0REG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
-#define TMS570_DMM_DEST0REG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DESTxREG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
-#define TMS570_DMM_DEST0REG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_DMM_DEST0REG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_DMM_DEST0REG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DESTxREG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
-/*---------------------TMS570_DMMDEST0BL1---------------------*/
+/*--------------------TMS570_DMM_DESTxBL1--------------------*/
/* field: BLOCKSIZE - These bits define the length of the buffer region. */
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
-#define TMS570_DMM_DEST0BL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DESTxBL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_DMMDEST0REG2--------------------*/
+/*--------------------TMS570_DMM_DESTxREG2--------------------*/
/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
-#define TMS570_DMM_DEST0REG2_BASEADDR(val) BSP_FLD32(val,18, 31)
-#define TMS570_DMM_DEST0REG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
-#define TMS570_DMM_DEST0REG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DESTxREG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
-#define TMS570_DMM_DEST0REG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_DMM_DEST0REG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_DMM_DEST0REG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DESTxREG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
-/*---------------------TMS570_DMMDEST0BL2---------------------*/
+/*--------------------TMS570_DMM_DESTxBL2--------------------*/
/* field: BLOCKSIZE - These bits define the length of the buffer region. */
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
-#define TMS570_DMM_DEST0BL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DESTxBL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_DMMPC0-----------------------*/
+/*-----------------------TMS570_DMM_PC0-----------------------*/
/* field: ENAFUNC - Functional mode of DMMENA pin. */
-#define TMS570_DMM_PC0_ENAFUNC BSP_FLD32(18)
+#define TMS570_DMM_PC0_ENAFUNC BSP_BIT32(18)
/* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
#define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17)
@@ -422,15 +419,15 @@ typedef struct{
#define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKFUNC - Functional mode of DMMCLK pin. */
-#define TMS570_DMM_PC0_CLKFUNC BSP_FLD32(1)
+#define TMS570_DMM_PC0_CLKFUNC BSP_BIT32(1)
/* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
-#define TMS570_DMM_PC0_SYNCFUNC BSP_FLD32(0)
+#define TMS570_DMM_PC0_SYNCFUNC BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC1-----------------------*/
+/*-----------------------TMS570_DMM_PC1-----------------------*/
/* field: ENADIR - Direction of DMMENA pin. */
-#define TMS570_DMM_PC1_ENADIR BSP_FLD32(18)
+#define TMS570_DMM_PC1_ENADIR BSP_BIT32(18)
/* field: DATAxDIR - Direction of DMMDATA[x] pin. */
#define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17)
@@ -438,15 +435,15 @@ typedef struct{
#define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKDIR - Direction of DMMCLK pin. */
-#define TMS570_DMM_PC1_CLKDIR BSP_FLD32(1)
+#define TMS570_DMM_PC1_CLKDIR BSP_BIT32(1)
/* field: SYNCDIR - Direction of DMMSYNC pin. */
-#define TMS570_DMM_PC1_SYNCDIR BSP_FLD32(0)
+#define TMS570_DMM_PC1_SYNCDIR BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC2-----------------------*/
+/*-----------------------TMS570_DMM_PC2-----------------------*/
/* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
-#define TMS570_DMM_PC2_ENAIN BSP_FLD32(18)
+#define TMS570_DMM_PC2_ENAIN BSP_BIT32(18)
/* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
#define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17)
@@ -454,15 +451,15 @@ typedef struct{
#define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
-#define TMS570_DMM_PC2_CLKIN BSP_FLD32(1)
+#define TMS570_DMM_PC2_CLKIN BSP_BIT32(1)
/* field: SYNCIN - DMMSYNC input. */
-#define TMS570_DMM_PC2_SYNCIN BSP_FLD32(0)
+#define TMS570_DMM_PC2_SYNCIN BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC3-----------------------*/
+/*-----------------------TMS570_DMM_PC3-----------------------*/
/* field: ENAOUT - Output state of DMMENA pin. */
-#define TMS570_DMM_PC3_ENAOUT BSP_FLD32(18)
+#define TMS570_DMM_PC3_ENAOUT BSP_BIT32(18)
/* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
#define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17)
@@ -470,15 +467,15 @@ typedef struct{
#define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKOUT - Output state of DMMCLK pin. */
-#define TMS570_DMM_PC3_CLKOUT BSP_FLD32(1)
+#define TMS570_DMM_PC3_CLKOUT BSP_BIT32(1)
/* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
-#define TMS570_DMM_PC3_SYNCOUT BSP_FLD32(0)
+#define TMS570_DMM_PC3_SYNCOUT BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC4-----------------------*/
+/*-----------------------TMS570_DMM_PC4-----------------------*/
/* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
-#define TMS570_DMM_PC4_ENASET BSP_FLD32(18)
+#define TMS570_DMM_PC4_ENASET BSP_BIT32(18)
/* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
#define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17)
@@ -486,15 +483,15 @@ typedef struct{
#define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
-#define TMS570_DMM_PC4_CLKSET BSP_FLD32(1)
+#define TMS570_DMM_PC4_CLKSET BSP_BIT32(1)
/* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
-#define TMS570_DMM_PC4_SYNCSET BSP_FLD32(0)
+#define TMS570_DMM_PC4_SYNCSET BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC5-----------------------*/
+/*-----------------------TMS570_DMM_PC5-----------------------*/
/* field: ENACLR - Sets output state of DMMENA pin to logic low. */
-#define TMS570_DMM_PC5_ENACLR BSP_FLD32(18)
+#define TMS570_DMM_PC5_ENACLR BSP_BIT32(18)
/* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
#define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17)
@@ -502,15 +499,15 @@ typedef struct{
#define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
-#define TMS570_DMM_PC5_CLKCLR BSP_FLD32(1)
+#define TMS570_DMM_PC5_CLKCLR BSP_BIT32(1)
/* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
-#define TMS570_DMM_PC5_SYNCCLR BSP_FLD32(0)
+#define TMS570_DMM_PC5_SYNCCLR BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC6-----------------------*/
+/*-----------------------TMS570_DMM_PC6-----------------------*/
/* field: ENAPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_ENAPDR BSP_FLD32(18)
+#define TMS570_DMM_PC6_ENAPDR BSP_BIT32(18)
/* field: DATAxPDR - Open Drain enable. */
#define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17)
@@ -518,15 +515,15 @@ typedef struct{
#define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_CLKPDR BSP_FLD32(1)
+#define TMS570_DMM_PC6_CLKPDR BSP_BIT32(1)
/* field: SYNCPDR - Open Drain enable. */
-#define TMS570_DMM_PC6_SYNCPDR BSP_FLD32(0)
+#define TMS570_DMM_PC6_SYNCPDR BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC7-----------------------*/
+/*-----------------------TMS570_DMM_PC7-----------------------*/
/* field: ENAPDIS - Pull disable. */
-#define TMS570_DMM_PC7_ENAPDIS BSP_FLD32(18)
+#define TMS570_DMM_PC7_ENAPDIS BSP_BIT32(18)
/* field: DATAxPDIS - Pull disable. */
#define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17)
@@ -534,15 +531,15 @@ typedef struct{
#define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKPDIS - Pull disable. */
-#define TMS570_DMM_PC7_CLKPDIS BSP_FLD32(1)
+#define TMS570_DMM_PC7_CLKPDIS BSP_BIT32(1)
/* field: SYNCPDIS - Pull disable. */
-#define TMS570_DMM_PC7_SYNCPDIS BSP_FLD32(0)
+#define TMS570_DMM_PC7_SYNCPDIS BSP_BIT32(0)
-/*-----------------------TMS570_DMMPC8-----------------------*/
+/*-----------------------TMS570_DMM_PC8-----------------------*/
/* field: ENAPSEL - Pull disable. */
-#define TMS570_DMM_PC8_ENAPSEL BSP_FLD32(18)
+#define TMS570_DMM_PC8_ENAPSEL BSP_BIT32(18)
/* field: DATAxPSEL - Pull disable. */
#define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17)
@@ -550,11 +547,11 @@ typedef struct{
#define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
/* field: CLKPSEL - Pull disable. */
-#define TMS570_DMM_PC8_CLKPSEL BSP_FLD32(1)
+#define TMS570_DMM_PC8_CLKPSEL BSP_BIT32(1)
/* field: SYNCPSEL - Pull disable. */
-#define TMS570_DMM_PC8_SYNCPSEL BSP_FLD32(0)
+#define TMS570_DMM_PC8_SYNCPSEL BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_DMM */
+#endif /* LIBBSP_ARM_TMS570_DMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
index 190536c..decf5bb 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_EFUSE
-#define LIBBSP_ARM_tms570_EFUSE
+#ifndef LIBBSP_ARM_TMS570_EFUSE
+#define LIBBSP_ARM_TMS570_EFUSE
#include <bsp/utility.h>
@@ -53,33 +53,33 @@ typedef struct{
} tms570_efuse_t;
-/*--------------------TMS570_EFUSEEFCBOUND--------------------*/
+/*-------------------TMS570_EFUSE_EFCBOUND-------------------*/
/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_FLD32(21)
+#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_BIT32(21)
/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_FLD32(20)
+#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_BIT32(20)
/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_FLD32(19)
+#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_BIT32(19)
/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */
-#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_FLD32(18)
+#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_BIT32(18)
/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */
-#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_FLD32(17)
+#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_BIT32(17)
/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */
-#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_FLD32(16)
+#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_BIT32(16)
/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */
-#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_FLD32(15)
+#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_BIT32(15)
/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */
-#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_FLD32(14)
+#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_BIT32(14)
/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
-#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_FLD32(13)
+#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_BIT32(13)
/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
#define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3)
@@ -87,26 +87,26 @@ typedef struct{
#define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_EFUSEEFCPINS--------------------*/
+/*--------------------TMS570_EFUSE_EFCPINS--------------------*/
/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */
-#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_FLD32(15)
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_BIT32(15)
/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */
-#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_FLD32(14)
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_BIT32(14)
/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */
-#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_FLD32(12)
+#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_BIT32(12)
/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */
-#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_FLD32(11)
+#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_BIT32(11)
/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */
-#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_FLD32(10)
+#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_BIT32(10)
-/*------------------TMS570_EFUSEEFC_ERR_STAT------------------*/
+/*-----------------TMS570_EFUSE_EFC_ERR_STAT-----------------*/
/* field: Instruc_Done - Instruction done. */
-#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_FLD32(5)
+#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_BIT32(5)
/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */
#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4)
@@ -114,19 +114,13 @@ typedef struct{
#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*-------------------TMS570_EFUSEEFC_ST_CY-------------------*/
+/*-------------------TMS570_EFUSE_EFC_ST_CY-------------------*/
/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */
-#define TMS570_EFUSE_EFC_ST_CY_Cycles(val) BSP_FLD32(val,0, 31)
-#define TMS570_EFUSE_EFC_ST_CY_Cycles_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EFUSE_EFC_ST_CY_Cycles_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_EFUSEEFC_ST_SIG-------------------*/
+/*------------------TMS570_EFUSE_EFC_ST_SIG------------------*/
/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
-#define TMS570_EFUSE_EFC_ST_SIG_Signature(val) BSP_FLD32(val,0, 31)
-#define TMS570_EFUSE_EFC_ST_SIG_Signature_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EFUSE_EFC_ST_SIG_Signature_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_EFUSE */
+#endif /* LIBBSP_ARM_TMS570_EFUSE */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
index 5783e99..31fe7ef 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_EMAC
-#define LIBBSP_ARM_tms570_EMAC
+#ifndef LIBBSP_ARM_TMS570_EMAC
+#define LIBBSP_ARM_TMS570_EMAC
#include <bsp/utility.h>
@@ -61,19 +61,16 @@ typedef struct{
} tms570_emac_t;
-/*----------------------TMS570_EMACREVID----------------------*/
+/*---------------------TMS570_EMAC_REVID---------------------*/
/* field: REV - Identifies the MDIO Module revision. */
-#define TMS570_EMAC_REVID_REV(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_EMACCONTROL---------------------*/
+/*--------------------TMS570_EMAC_CONTROL--------------------*/
/* field: IDLE - State machine IDLE status bit. */
-#define TMS570_EMAC_CONTROL_IDLE BSP_FLD32(31)
+#define TMS570_EMAC_CONTROL_IDLE BSP_BIT32(31)
/* field: ENABLE - State machine enable control bit. */
-#define TMS570_EMAC_CONTROL_ENABLE BSP_FLD32(30)
+#define TMS570_EMAC_CONTROL_ENABLE BSP_BIT32(30)
/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
@@ -81,13 +78,13 @@ typedef struct{
#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: PREAMBLE - Preamble disable */
-#define TMS570_EMAC_CONTROL_PREAMBLE BSP_FLD32(20)
+#define TMS570_EMAC_CONTROL_PREAMBLE BSP_BIT32(20)
/* field: FAULT - Fault indicator. */
-#define TMS570_EMAC_CONTROL_FAULT BSP_FLD32(19)
+#define TMS570_EMAC_CONTROL_FAULT BSP_BIT32(19)
/* field: FAULTENB - Fault detect enable. */
-#define TMS570_EMAC_CONTROL_FAULTENB BSP_FLD32(18)
+#define TMS570_EMAC_CONTROL_FAULTENB BSP_BIT32(18)
/* field: CLKDIV - Clock Divider bits. */
#define TMS570_EMAC_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
@@ -95,77 +92,71 @@ typedef struct{
#define TMS570_EMAC_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_EMACALIVE----------------------*/
+/*---------------------TMS570_EMAC_ALIVE---------------------*/
/* field: ALIVE - MDIO Alive bits. */
-#define TMS570_EMAC_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_EMACLINK----------------------*/
+/*----------------------TMS570_EMAC_LINK----------------------*/
/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
-#define TMS570_EMAC_LINK_LINK(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMAC_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMAC_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_EMACLINKINTRAW-------------------*/
+/*-------------------TMS570_EMAC_LINKINTRAW-------------------*/
/* field: USERPHY1 - MDIO Link change event, raw value. */
-#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_FLD32(1)
+#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_BIT32(1)
/* field: USERPHY0 - MDIO Link change event, raw value. */
-#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_FLD32(0)
+#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_BIT32(0)
-/*------------------TMS570_EMACLINKINTMASKED------------------*/
+/*-----------------TMS570_EMAC_LINKINTMASKED-----------------*/
/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
-#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
+#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_BIT32(1)
/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
-#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
+#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_BIT32(0)
-/*-------------------TMS570_EMACUSERINTRAW-------------------*/
+/*-------------------TMS570_EMAC_USERINTRAW-------------------*/
/* field: USERACCESS1 - MDIO User command complete event bit. */
-#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_FLD32(1)
+#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO User command complete event bit. */
-#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_FLD32(0)
+#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_BIT32(0)
-/*------------------TMS570_EMACUSERINTMASKED------------------*/
+/*-----------------TMS570_EMAC_USERINTMASKED-----------------*/
/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
+#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
+#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_BIT32(0)
-/*-----------------TMS570_EMACUSERINTMASKSET-----------------*/
+/*-----------------TMS570_EMAC_USERINTMASKSET-----------------*/
/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
-#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
+#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
-#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
+#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_BIT32(0)
-/*----------------TMS570_EMACUSERINTMASKCLEAR----------------*/
+/*----------------TMS570_EMAC_USERINTMASKCLEAR----------------*/
/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
-#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
+#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
-#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
+#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0)
-/*-------------------TMS570_EMACUSERACCESS0-------------------*/
+/*------------------TMS570_EMAC_USERACCESS0------------------*/
/* field: GO - Go bit. */
-#define TMS570_EMAC_USERACCESS0_GO BSP_FLD32(31)
+#define TMS570_EMAC_USERACCESS0_GO BSP_BIT32(31)
/* field: WRITE - Write enable bit. */
-#define TMS570_EMAC_USERACCESS0_WRITE BSP_FLD32(30)
+#define TMS570_EMAC_USERACCESS0_WRITE BSP_BIT32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_EMAC_USERACCESS0_ACK BSP_FLD32(29)
+#define TMS570_EMAC_USERACCESS0_ACK BSP_BIT32(29)
/* field: REGADR - Register address bits. */
#define TMS570_EMAC_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
@@ -183,12 +174,12 @@ typedef struct{
#define TMS570_EMAC_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_EMACUSERPHYSEL0-------------------*/
+/*------------------TMS570_EMAC_USERPHYSEL0------------------*/
/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_FLD32(7)
+#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_BIT32(7)
/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
+#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_BIT32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_EMAC_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -196,15 +187,15 @@ typedef struct{
#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*-------------------TMS570_EMACUSERACCESS1-------------------*/
+/*------------------TMS570_EMAC_USERACCESS1------------------*/
/* field: GO - Go bit. */
-#define TMS570_EMAC_USERACCESS1_GO BSP_FLD32(31)
+#define TMS570_EMAC_USERACCESS1_GO BSP_BIT32(31)
/* field: WRITE - Write enable bit. */
-#define TMS570_EMAC_USERACCESS1_WRITE BSP_FLD32(30)
+#define TMS570_EMAC_USERACCESS1_WRITE BSP_BIT32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_EMAC_USERACCESS1_ACK BSP_FLD32(29)
+#define TMS570_EMAC_USERACCESS1_ACK BSP_BIT32(29)
/* field: REGADR - Register address bits. */
#define TMS570_EMAC_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
@@ -222,12 +213,12 @@ typedef struct{
#define TMS570_EMAC_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_EMACUSERPHYSEL1-------------------*/
+/*------------------TMS570_EMAC_USERPHYSEL1------------------*/
/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_FLD32(7)
+#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_BIT32(7)
/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
+#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_BIT32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_EMAC_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -236,4 +227,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_EMAC */
+#endif /* LIBBSP_ARM_TMS570_EMAC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
index 18cc7a8..c6e6321 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_EMACM
-#define LIBBSP_ARM_tms570_EMACM
+#ifndef LIBBSP_ARM_TMS570_EMACM
+#define LIBBSP_ARM_TMS570_EMACM
#include <bsp/utility.h>
@@ -102,160 +102,154 @@ typedef struct{
} tms570_emacm_t;
-/*--------------------TMS570_EMACMTXREVID--------------------*/
+/*--------------------TMS570_EMACM_TXREVID--------------------*/
/* field: TXREV - Transmit module revision */
-#define TMS570_EMACM_TXREVID_TXREV(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_TXREVID_TXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXREVID_TXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_EMACMTXCONTROL-------------------*/
+/*-------------------TMS570_EMACM_TXCONTROL-------------------*/
/* field: TXEN - Transmit enable */
-#define TMS570_EMACM_TXCONTROL_TXEN BSP_FLD32(0)
+#define TMS570_EMACM_TXCONTROL_TXEN BSP_BIT32(0)
-/*-------------------TMS570_EMACMTXTEARDOWN-------------------*/
+/*------------------TMS570_EMACM_TXTEARDOWN------------------*/
/* field: TXTDNCH - Transmit teardown channel. */
#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*--------------------TMS570_EMACMRXREVID--------------------*/
+/*--------------------TMS570_EMACM_RXREVID--------------------*/
/* field: RXREV - Receive module revision */
-#define TMS570_EMACM_RXREVID_RXREV(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_RXREVID_RXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXREVID_RXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_EMACMRXCONTROL-------------------*/
+/*-------------------TMS570_EMACM_RXCONTROL-------------------*/
/* field: RXEN - Receive enable */
-#define TMS570_EMACM_RXCONTROL_RXEN BSP_FLD32(0)
+#define TMS570_EMACM_RXCONTROL_RXEN BSP_BIT32(0)
-/*-------------------TMS570_EMACMRXTEARDOWN-------------------*/
+/*------------------TMS570_EMACM_RXTEARDOWN------------------*/
/* field: RXTDNCH - Receive teardown channel. */
#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*------------------TMS570_EMACMTXINTSTATRAW------------------*/
+/*-----------------TMS570_EMACM_TXINTSTATRAW-----------------*/
/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_BIT32(7)
/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_BIT32(6)
/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_BIT32(5)
/* field: TX4PEND - X4PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_BIT32(4)
/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_BIT32(3)
/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_BIT32(2)
/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_BIT32(1)
/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_BIT32(0)
-/*----------------TMS570_EMACMTXINTSTATMASKED----------------*/
+/*----------------TMS570_EMACM_TXINTSTATMASKED----------------*/
/* field: TX7PEND - TX7PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_BIT32(7)
/* field: TX6PEND - TX6PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_BIT32(6)
/* field: TX5PEND - TX5PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_BIT32(5)
/* field: TX4PEND - TX4PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_BIT32(4)
/* field: TX3PEND - TX3PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_BIT32(3)
/* field: TX2PEND - TX2PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_BIT32(2)
/* field: TX1PEND - TX1PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_BIT32(1)
/* field: TX0PEND - TX0PEND masked interrupt read */
-#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_BIT32(0)
-/*------------------TMS570_EMACMTXINTMASKSET------------------*/
+/*-----------------TMS570_EMACM_TXINTMASKSET-----------------*/
/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_BIT32(7)
/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_BIT32(6)
/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_BIT32(5)
/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_BIT32(4)
/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_BIT32(3)
/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_BIT32(2)
/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_BIT32(1)
/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_BIT32(0)
-/*-----------------TMS570_EMACMTXINTMASKCLEAR-----------------*/
+/*----------------TMS570_EMACM_TXINTMASKCLEAR----------------*/
/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_BIT32(7)
/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_BIT32(6)
/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_BIT32(5)
/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_BIT32(4)
/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_BIT32(3)
/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_BIT32(2)
/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_BIT32(1)
/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_BIT32(0)
-/*------------------TMS570_EMACMMACINVECTOR------------------*/
+/*------------------TMS570_EMACM_MACINVECTOR------------------*/
/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
-#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_FLD32(27)
+#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_BIT32(27)
/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
-#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_FLD32(26)
+#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_BIT32(26)
/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
-#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_FLD32(25)
+#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_BIT32(25)
/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
-#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_FLD32(24)
+#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_BIT32(24)
/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
@@ -273,266 +267,266 @@ typedef struct{
#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_EMACMMACEOIVECTOR------------------*/
+/*-----------------TMS570_EMACM_MACEOIVECTOR-----------------*/
/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*------------------TMS570_EMACMRXINTSTATRAW------------------*/
+/*-----------------TMS570_EMACM_RXINTSTATRAW-----------------*/
/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_FLD32(15)
+#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_BIT32(15)
/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_FLD32(14)
+#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_BIT32(14)
/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_FLD32(13)
+#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_BIT32(13)
/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_FLD32(12)
+#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_BIT32(12)
/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_FLD32(11)
+#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_BIT32(11)
/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_FLD32(10)
+#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_BIT32(10)
/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_FLD32(9)
+#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_BIT32(9)
/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_FLD32(8)
+#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_BIT32(8)
/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_BIT32(7)
/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_BIT32(6)
/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_BIT32(5)
/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_BIT32(4)
/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_BIT32(3)
/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_BIT32(2)
/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_BIT32(1)
/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
-#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_BIT32(0)
-/*----------------TMS570_EMACMRXINTSTATMASKED----------------*/
+/*----------------TMS570_EMACM_RXINTSTATMASKED----------------*/
/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_FLD32(15)
+#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_BIT32(15)
/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_FLD32(14)
+#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_BIT32(14)
/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_FLD32(13)
+#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_BIT32(13)
/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_FLD32(12)
+#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_BIT32(12)
/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_FLD32(11)
+#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_BIT32(11)
/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_FLD32(10)
+#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_BIT32(10)
/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_FLD32(9)
+#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_BIT32(9)
/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_FLD32(8)
+#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_BIT32(8)
/* field: RX7PEND - RX7PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_FLD32(7)
+#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_BIT32(7)
/* field: RX6PEND - RX6PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_FLD32(6)
+#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_BIT32(6)
/* field: RX5PEND - RX5PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_FLD32(5)
+#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_BIT32(5)
/* field: RX4PEND - RX4PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_FLD32(4)
+#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_BIT32(4)
/* field: RX3PEND - RX3PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_FLD32(3)
+#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_BIT32(3)
/* field: RX2PEND - RX2PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_FLD32(2)
+#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_BIT32(2)
/* field: RX1PEND - RX1PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_FLD32(1)
+#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_BIT32(1)
/* field: RX0PEND - RX0PEND masked interrupt read */
-#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_FLD32(0)
+#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_BIT32(0)
-/*------------------TMS570_EMACMRXINTMASKSET------------------*/
+/*-----------------TMS570_EMACM_RXINTMASKSET-----------------*/
/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_FLD32(15)
+#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_BIT32(15)
/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_FLD32(14)
+#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_BIT32(14)
/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_FLD32(13)
+#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_BIT32(13)
/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_FLD32(12)
+#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_BIT32(12)
/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_FLD32(11)
+#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_BIT32(11)
/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_FLD32(10)
+#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_BIT32(10)
/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_FLD32(9)
+#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_BIT32(9)
/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_FLD32(8)
+#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_BIT32(8)
/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_BIT32(7)
/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_BIT32(6)
/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_BIT32(5)
/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_BIT32(4)
/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_BIT32(3)
/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_BIT32(2)
/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_BIT32(1)
/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_BIT32(0)
-/*-----------------TMS570_EMACMRXINTMASKCLEAR-----------------*/
+/*----------------TMS570_EMACM_RXINTMASKCLEAR----------------*/
/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_FLD32(15)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_BIT32(15)
/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_FLD32(14)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_BIT32(14)
/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_FLD32(13)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_BIT32(13)
/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_FLD32(12)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_BIT32(12)
/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_FLD32(11)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_BIT32(11)
/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_FLD32(10)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_BIT32(10)
/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_FLD32(9)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_BIT32(9)
/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_FLD32(8)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_BIT32(8)
/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_FLD32(7)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_BIT32(7)
/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_FLD32(6)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_BIT32(6)
/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_FLD32(5)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_BIT32(5)
/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_FLD32(4)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_BIT32(4)
/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_FLD32(3)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_BIT32(3)
/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_FLD32(2)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_BIT32(2)
/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_FLD32(1)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_BIT32(1)
/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
-#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_FLD32(0)
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_BIT32(0)
-/*-----------------TMS570_EMACMMACINTSTATRAW-----------------*/
+/*-----------------TMS570_EMACM_MACINTSTATRAW-----------------*/
/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
-#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_FLD32(1)
+#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_BIT32(1)
/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
-#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_FLD32(0)
+#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_BIT32(0)
-/*----------------TMS570_EMACMMACINTSTATMASKED----------------*/
+/*---------------TMS570_EMACM_MACINTSTATMASKED---------------*/
/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
-#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_FLD32(1)
+#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_BIT32(1)
/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
-#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_FLD32(0)
+#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_BIT32(0)
-/*-----------------TMS570_EMACMMACINTMASKSET-----------------*/
+/*-----------------TMS570_EMACM_MACINTMASKSET-----------------*/
/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_FLD32(1)
+#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_BIT32(1)
/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_FLD32(0)
+#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_BIT32(0)
-/*----------------TMS570_EMACMMACINTMASKCLEAR----------------*/
+/*----------------TMS570_EMACM_MACINTMASKCLEAR----------------*/
/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_FLD32(1)
+#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_BIT32(1)
/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
-#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_FLD32(0)
+#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_BIT32(0)
-/*------------------TMS570_EMACMRXMBPENABLE------------------*/
+/*------------------TMS570_EMACM_RXMBPENABLE------------------*/
/* field: RXPASSCRC - Pass receive CRC enable bit */
-#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_FLD32(30)
+#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_BIT32(30)
/* field: RXQOSEN - Receive quality of service enable bit */
-#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_FLD32(29)
+#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_BIT32(29)
/* field: RXNOCHAIN - Receive no buffer chaining bit */
-#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_FLD32(28)
+#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_BIT32(28)
/* field: RXCMFEN - Receive copy MAC control frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_FLD32(24)
+#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_BIT32(24)
/* field: RXCSFEN - Receive copy short frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_FLD32(23)
+#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_BIT32(23)
/* field: RXCEFEN - Receive copy error frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_FLD32(22)
+#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_BIT32(22)
/* field: RXCAFEN - Receive copy all frames enable bit. */
-#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_FLD32(21)
+#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_BIT32(21)
/* field: RXPROMCH - Receive promiscuous channel select */
#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
@@ -540,7 +534,7 @@ typedef struct{
#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
/* field: RXBROADEN - Receive broadcast enable. */
-#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_FLD32(13)
+#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_BIT32(13)
/* field: RXBROADCH - Receive broadcast channel select */
#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
@@ -548,137 +542,137 @@ typedef struct{
#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: RXMULTEN - RX multicast enable. */
-#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_FLD32(5)
+#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_BIT32(5)
-/*------------------TMS570_EMACMRXUNICASTSET------------------*/
+/*-----------------TMS570_EMACM_RXUNICASTSET-----------------*/
/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_FLD32(7)
+#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_BIT32(7)
/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_FLD32(6)
+#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_BIT32(6)
/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_FLD32(5)
+#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_BIT32(5)
/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_FLD32(4)
+#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_BIT32(4)
/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_FLD32(3)
+#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_BIT32(3)
/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_FLD32(2)
+#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_BIT32(2)
/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_FLD32(1)
+#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_BIT32(1)
/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_FLD32(0)
+#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_BIT32(0)
-/*-----------------TMS570_EMACMRXUNICASTCLEAR-----------------*/
+/*----------------TMS570_EMACM_RXUNICASTCLEAR----------------*/
/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_FLD32(7)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_BIT32(7)
/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_FLD32(6)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_BIT32(6)
/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_FLD32(5)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_BIT32(5)
/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_FLD32(4)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_BIT32(4)
/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_FLD32(3)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_BIT32(3)
/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_FLD32(2)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_BIT32(2)
/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_FLD32(1)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_BIT32(1)
/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
-#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_FLD32(0)
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_BIT32(0)
-/*--------------------TMS570_EMACMRXMAXLEN--------------------*/
+/*-------------------TMS570_EMACM_RXMAXLEN-------------------*/
/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------TMS570_EMACMRXBUFFEROFFSET-----------------*/
+/*----------------TMS570_EMACM_RXBUFFEROFFSET----------------*/
/* field: RXBUFFEROFFSET - Receive buffer offset value. */
#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------TMS570_EMACMRXFILTERLOWTHRESH---------------*/
+/*---------------TMS570_EMACM_RXFILTERLOWTHRESH---------------*/
/* field: RXFILTERTHRESH - Receive filter low threshold. */
#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_EMACMRXFLOWTHRESH------------------*/
+/*-----------------TMS570_EMACM_RXFLOWTHRESH-----------------*/
/* field: RXnFLOWTHRESH - Receive flow threshold. */
#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_EMACMRXFREEBUFFER------------------*/
+/*-----------------TMS570_EMACM_RXFREEBUFFER-----------------*/
/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_EMACMMACCONTROL-------------------*/
+/*------------------TMS570_EMACM_MACCONTROL------------------*/
/* field: RMIISPEED - RMII interface transmit and receive speed select. */
-#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_FLD32(15)
+#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_BIT32(15)
/* field: RXOFFLENBLOCK - Receive offset / length word write block. */
-#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_FLD32(14)
+#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_BIT32(14)
/* field: RXOWNERSHIP - Receive ownership write bit value. */
-#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_FLD32(13)
+#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_BIT32(13)
/* field: CMDIDLE - Command Idle bit */
-#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_FLD32(11)
+#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_BIT32(11)
/* field: TXSHORTGAPEN - Transmit Short Gap Enable */
-#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_FLD32(10)
+#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_BIT32(10)
/* field: TXPTYPE - Transmit queue priority type */
-#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_FLD32(9)
+#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_BIT32(9)
/* field: TXPACE - Transmit pacing enable bit */
-#define TMS570_EMACM_MACCONTROL_TXPACE BSP_FLD32(6)
+#define TMS570_EMACM_MACCONTROL_TXPACE BSP_BIT32(6)
/* field: GMIIEN - GMII enable bit */
-#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_FLD32(5)
+#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_BIT32(5)
/* field: TXFLOWEN - Transmit flow control enable bit. */
-#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_FLD32(4)
+#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_BIT32(4)
/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
-#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_FLD32(3)
+#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_BIT32(3)
/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
-#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_FLD32(1)
+#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_BIT32(1)
/* field: FULLDUPLEX - Full duplex mode. */
-#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_FLD32(0)
+#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_BIT32(0)
-/*-------------------TMS570_EMACMMACSTATUS-------------------*/
+/*-------------------TMS570_EMACM_MACSTATUS-------------------*/
/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
-#define TMS570_EMACM_MACSTATUS_IDLE BSP_FLD32(31)
+#define TMS570_EMACM_MACSTATUS_IDLE BSP_BIT32(31)
/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
@@ -701,31 +695,31 @@ typedef struct{
#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
-#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_FLD32(2)
+#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_BIT32(2)
/* field: RXFLOWACT - Receive flow control active bit. */
-#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_FLD32(1)
+#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_BIT32(1)
/* field: TXFLOWACT - Transmit flow control active bit. */
-#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_FLD32(0)
+#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_BIT32(0)
-/*-------------------TMS570_EMACMEMCONTROL-------------------*/
+/*-------------------TMS570_EMACM_EMCONTROL-------------------*/
/* field: SOFT - Emulation soft bit. */
-#define TMS570_EMACM_EMCONTROL_SOFT BSP_FLD32(1)
+#define TMS570_EMACM_EMCONTROL_SOFT BSP_BIT32(1)
/* field: FREE - Emulation free bit. */
-#define TMS570_EMACM_EMCONTROL_FREE BSP_FLD32(0)
+#define TMS570_EMACM_EMCONTROL_FREE BSP_BIT32(0)
-/*------------------TMS570_EMACMFIFOCONTROL------------------*/
+/*------------------TMS570_EMACM_FIFOCONTROL------------------*/
/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*-------------------TMS570_EMACMMACCONFIG-------------------*/
+/*-------------------TMS570_EMACM_MACCONFIG-------------------*/
/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -747,12 +741,12 @@ typedef struct{
#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_EMACMSOFTRESET-------------------*/
+/*-------------------TMS570_EMACM_SOFTRESET-------------------*/
/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
-#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_FLD32(0)
+#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_BIT32(0)
-/*------------------TMS570_EMACMMACSRCADDRLO------------------*/
+/*-----------------TMS570_EMACM_MACSRCADDRLO-----------------*/
/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -764,7 +758,7 @@ typedef struct{
#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_EMACMMACSRCADDRHI------------------*/
+/*-----------------TMS570_EMACM_MACSRCADDRHI-----------------*/
/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -786,21 +780,15 @@ typedef struct{
#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_EMACMMACHASH1--------------------*/
+/*-------------------TMS570_EMACM_MACHASH1-------------------*/
/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
-#define TMS570_EMACM_MACHASH1_MACHASH1(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_MACHASH1_MACHASH1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_MACHASH1_MACHASH1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_EMACMMACHASH2--------------------*/
+/*-------------------TMS570_EMACM_MACHASH2-------------------*/
/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
-#define TMS570_EMACM_MACHASH2_MACHASH2(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_MACHASH2_MACHASH2_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_MACHASH2_MACHASH2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_EMACMBOFFTEST--------------------*/
+/*-------------------TMS570_EMACM_BOFFTEST-------------------*/
/* field: RNDNUM - Backoff random number generator. */
#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
@@ -817,33 +805,33 @@ typedef struct{
#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*-------------------TMS570_EMACMTPACETEST-------------------*/
+/*-------------------TMS570_EMACM_TPACETEST-------------------*/
/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*--------------------TMS570_EMACMRXPAUSE--------------------*/
+/*--------------------TMS570_EMACM_RXPAUSE--------------------*/
/* field: PAUSETIMER - Receive pause timer value. */
#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_EMACMTXPAUSE--------------------*/
+/*--------------------TMS570_EMACM_TXPAUSE--------------------*/
/* field: PAUSETIMER - Transmit pause timer value. */
#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_EMACMMACADDRLO-------------------*/
+/*-------------------TMS570_EMACM_MACADDRLO-------------------*/
/* field: VALID - Address valid bit. */
-#define TMS570_EMACM_MACADDRLO_VALID BSP_FLD32(20)
+#define TMS570_EMACM_MACADDRLO_VALID BSP_BIT32(20)
/* field: MATCHFILT - Match or filter bit */
-#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_FLD32(19)
+#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_BIT32(19)
/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
@@ -861,7 +849,7 @@ typedef struct{
#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_EMACMMACADDRHI-------------------*/
+/*-------------------TMS570_EMACM_MACADDRHI-------------------*/
/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -883,40 +871,28 @@ typedef struct{
#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_EMACMMACINDEX--------------------*/
+/*-------------------TMS570_EMACM_MACINDEX-------------------*/
/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*---------------------TMS570_EMACMTXHDP---------------------*/
+/*---------------------TMS570_EMACM_TXHDP---------------------*/
/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
-#define TMS570_EMACM_TXHDP_TXnHDP(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_TXHDP_TXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXHDP_TXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_EMACMRXHDP---------------------*/
+/*---------------------TMS570_EMACM_RXHDP---------------------*/
/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
-#define TMS570_EMACM_RXHDP_RXnHDP(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_RXHDP_RXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXHDP_RXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_EMACMTXCP----------------------*/
+/*---------------------TMS570_EMACM_TXCP---------------------*/
/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
-#define TMS570_EMACM_TXCP_TXnCP(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_TXCP_TXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_TXCP_TXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_EMACMRXCP----------------------*/
+/*---------------------TMS570_EMACM_RXCP---------------------*/
/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
-#define TMS570_EMACM_RXCP_RXnCP(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMACM_RXCP_RXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMACM_RXCP_RXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_EMACM */
+#endif /* LIBBSP_ARM_TMS570_EMACM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
index b4e227b..0810fd0 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_EMIF
-#define LIBBSP_ARM_tms570_EMIF
+#ifndef LIBBSP_ARM_TMS570_EMIF
+#define LIBBSP_ARM_TMS570_EMIF
#include <bsp/utility.h>
@@ -62,19 +62,16 @@ typedef struct{
} tms570_emif_t;
-/*----------------------TMS570_EMIFMIDR----------------------*/
+/*----------------------TMS570_EMIF_MIDR----------------------*/
/* field: REV - Module ID of EMIF. See the device-specific data manual. */
-#define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31)
-#define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_EMIFAWCC----------------------*/
+/*----------------------TMS570_EMIF_AWCC----------------------*/
/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
-#define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29)
+#define TMS570_EMIF_AWCC_WP1 BSP_BIT32(29)
/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
-#define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28)
+#define TMS570_EMIF_AWCC_WP0 BSP_BIT32(28)
/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
@@ -102,18 +99,18 @@ typedef struct{
#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_EMIFSDCR----------------------*/
+/*----------------------TMS570_EMIF_SDCR----------------------*/
/* field: SR - Self-Refresh mode bit. */
-#define TMS570_EMIF_SDCR_SR BSP_FLD32(31)
+#define TMS570_EMIF_SDCR_SR BSP_BIT32(31)
/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
-#define TMS570_EMIF_SDCR_PD BSP_FLD32(30)
+#define TMS570_EMIF_SDCR_PD BSP_BIT32(30)
/* field: PDWR - Perform refreshes during power down. */
-#define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29)
+#define TMS570_EMIF_SDCR_PDWR BSP_BIT32(29)
/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
-#define TMS570_EMIF_SDCR_NM BSP_FLD32(14)
+#define TMS570_EMIF_SDCR_NM BSP_BIT32(14)
/* field: CL - CAS Latency. */
#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
@@ -121,7 +118,7 @@ typedef struct{
#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
-#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8)
+#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_BIT32(8)
/* field: IBANK - Internal SDRAM Bank size. */
#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
@@ -134,19 +131,19 @@ typedef struct{
#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*----------------------TMS570_EMIFSDRCR----------------------*/
+/*---------------------TMS570_EMIF_SDRCR---------------------*/
/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
-/*---------------------TMS570_EMIFCE2CFG---------------------*/
+/*---------------------TMS570_EMIF_CE2CFG---------------------*/
/* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE2CFG_SS BSP_BIT32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE2CFG_EW BSP_BIT32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -189,12 +186,12 @@ typedef struct{
#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_EMIFCE3CFG---------------------*/
+/*---------------------TMS570_EMIF_CE3CFG---------------------*/
/* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE3CFG_SS BSP_BIT32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE3CFG_EW BSP_BIT32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -237,12 +234,12 @@ typedef struct{
#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_EMIFCE4CFG---------------------*/
+/*---------------------TMS570_EMIF_CE4CFG---------------------*/
/* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE4CFG_SS BSP_BIT32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE4CFG_EW BSP_BIT32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -285,12 +282,12 @@ typedef struct{
#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_EMIFCE5CFG---------------------*/
+/*---------------------TMS570_EMIF_CE5CFG---------------------*/
/* field: SS - Select Strobe bit. */
-#define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31)
+#define TMS570_EMIF_CE5CFG_SS BSP_BIT32(31)
/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
-#define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30)
+#define TMS570_EMIF_CE5CFG_EW BSP_BIT32(30)
/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
@@ -333,7 +330,7 @@ typedef struct{
#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_EMIFSDTIMR---------------------*/
+/*---------------------TMS570_EMIF_SDTIMR---------------------*/
/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
@@ -370,68 +367,68 @@ typedef struct{
#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
-/*---------------------TMS570_EMIFSDSRETR---------------------*/
+/*--------------------TMS570_EMIF_SDSRETR--------------------*/
/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*---------------------TMS570_EMIFINTRAW---------------------*/
+/*---------------------TMS570_EMIF_INTRAW---------------------*/
/* field: WR - Wait Rise. */
-#define TMS570_EMIF_INTRAW_WR BSP_FLD32(2)
+#define TMS570_EMIF_INTRAW_WR BSP_BIT32(2)
/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
-#define TMS570_EMIF_INTRAW_LT BSP_FLD32(1)
+#define TMS570_EMIF_INTRAW_LT BSP_BIT32(1)
/* field: AT - Asynchronous Timeout. */
-#define TMS570_EMIF_INTRAW_AT BSP_FLD32(0)
+#define TMS570_EMIF_INTRAW_AT BSP_BIT32(0)
-/*---------------------TMS570_EMIFINTMSK---------------------*/
+/*---------------------TMS570_EMIF_INTMSK---------------------*/
/* field: WR_MASKED - Wait Rise Masked. */
-#define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2)
+#define TMS570_EMIF_INTMSK_WR_MASKED BSP_BIT32(2)
/* field: LT_MASKED - Masked Line Trap. */
-#define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1)
+#define TMS570_EMIF_INTMSK_LT_MASKED BSP_BIT32(1)
/* field: AT_MASKED - Asynchronous Timeout Masked. */
-#define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0)
+#define TMS570_EMIF_INTMSK_AT_MASKED BSP_BIT32(0)
-/*--------------------TMS570_EMIFINTMSKSET--------------------*/
+/*-------------------TMS570_EMIF_INTMSKSET-------------------*/
/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
-#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2)
+#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_BIT32(2)
/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
-#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1)
+#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_BIT32(1)
/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
-#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0)
+#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_BIT32(0)
-/*--------------------TMS570_EMIFINTMSKCLR--------------------*/
+/*-------------------TMS570_EMIF_INTMSKCLR-------------------*/
/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
-#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2)
+#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_BIT32(2)
/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
-#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1)
+#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_BIT32(1)
/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
-#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0)
+#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_BIT32(0)
-/*----------------------TMS570_EMIFPMCR----------------------*/
+/*----------------------TMS570_EMIF_PMCR----------------------*/
/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
-#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25)
+#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_BIT32(25)
/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
-#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24)
+#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_BIT32(24)
/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
@@ -439,10 +436,10 @@ typedef struct{
#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
-#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17)
+#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_BIT32(17)
/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
-#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16)
+#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_BIT32(16)
/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
@@ -450,10 +447,10 @@ typedef struct{
#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
-#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9)
+#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_BIT32(9)
/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
-#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8)
+#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_BIT32(8)
/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
@@ -461,11 +458,11 @@ typedef struct{
#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
-#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1)
+#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_BIT32(1)
/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
-#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0)
+#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_EMIF */
+#endif /* LIBBSP_ARM_TMS570_EMIF */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
index 5a65bca..3ea4b6b 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_ESM
-#define LIBBSP_ARM_tms570_ESM
+#ifndef LIBBSP_ARM_TMS570_ESM
+#define LIBBSP_ARM_TMS570_ESM
#include <bsp/utility.h>
@@ -66,150 +66,105 @@ typedef struct{
} tms570_esm_t;
-/*---------------------TMS570_ESMEEPAPR1---------------------*/
+/*---------------------TMS570_ESM_EEPAPR1---------------------*/
/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
-#define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_ESMDEPAPR1---------------------*/
+/*---------------------TMS570_ESM_DEPAPR1---------------------*/
/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
-#define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_ESMIESR1----------------------*/
+/*----------------------TMS570_ESM_IESR1----------------------*/
/* field: INTENSET - Set interrupt Enable */
-#define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_ESMIECR1----------------------*/
+/*----------------------TMS570_ESM_IECR1----------------------*/
/* field: INTENCLR - Clear Interrupt Enable */
-#define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_ESMILSR1----------------------*/
+/*----------------------TMS570_ESM_ILSR1----------------------*/
/* field: INTLVLSET - Set Interrupt Priority */
-#define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_ESMILCR1----------------------*/
+/*----------------------TMS570_ESM_ILCR1----------------------*/
/* field: INTLVLCLR - Clear Interrupt Priority. */
-#define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------------TMS570_ESMSR------------------------*/
+/*-----------------------TMS570_ESM_SR-----------------------*/
/* field: ESF - Error Status Flag. Provides status information on a pending error. */
-#define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_ESMEPSR-----------------------*/
+/*----------------------TMS570_ESM_EPSR----------------------*/
/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
-#define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
+#define TMS570_ESM_EPSR_EPSF BSP_BIT32(0)
-/*----------------------TMS570_ESMIOFFHR----------------------*/
+/*---------------------TMS570_ESM_IOFFHR---------------------*/
/* field: INTOFFH - Offset High Level Interrupt. */
#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*----------------------TMS570_ESMIOFFLR----------------------*/
+/*---------------------TMS570_ESM_IOFFLR---------------------*/
/* field: INTOFFL - Offset Low Level Interrupt. */
#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*-----------------------TMS570_ESMLTCR-----------------------*/
+/*----------------------TMS570_ESM_LTCR----------------------*/
/* field: LTC - ERROR Pin Low-Time Counter */
#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_ESMLTCPR----------------------*/
+/*----------------------TMS570_ESM_LTCPR----------------------*/
/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_ESMEKR-----------------------*/
+/*-----------------------TMS570_ESM_EKR-----------------------*/
/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_ESMSSR2-----------------------*/
+/*----------------------TMS570_ESM_SSR2----------------------*/
/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
-#define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
-#define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_ESMIEPSR4----------------------*/
+/*---------------------TMS570_ESM_IEPSR4---------------------*/
/* field: IEPSET - Set Influence on ERROR Pin */
-#define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+/* Whole 32 bits */
-
-/*----------------------TMS570_ESMIEPCR4----------------------*/
+/*---------------------TMS570_ESM_IEPCR4---------------------*/
/* field: IEPCLR - Clear Influence on ERROR Pin */
-#define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
-
+/* Whole 32 bits */
-/*----------------------TMS570_ESMIESR4----------------------*/
+/*----------------------TMS570_ESM_IESR4----------------------*/
/* field: INTENSET - Set Interrupt Enable */
-#define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+/* Whole 32 bits */
-
-/*----------------------TMS570_ESMIECR4----------------------*/
+/*----------------------TMS570_ESM_IECR4----------------------*/
/* field: INTENCLR - Clear Interrupt Enable */
-#define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
-
+/* Whole 32 bits */
-/*----------------------TMS570_ESMILSR4----------------------*/
+/*----------------------TMS570_ESM_ILSR4----------------------*/
/* field: INTLVLSET - Set Interrupt Level */
-#define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+/* Whole 32 bits */
-
-/*----------------------TMS570_ESMILCR4----------------------*/
+/*----------------------TMS570_ESM_ILCR4----------------------*/
/* field: INTLVLCLR - Clear Interrupt Level */
-#define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_ESMSR4-----------------------*/
+/*-----------------------TMS570_ESM_SR4-----------------------*/
/* field: ESF - Error Status Flag. Provides status information on a pending error. */
-#define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
-#define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
-#define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_ESM */
+#endif /* LIBBSP_ARM_TMS570_ESM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
index ac0fc40..6c5a127 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_FLASH
-#define LIBBSP_ARM_tms570_FLASH
+#ifndef LIBBSP_ARM_TMS570_FLASH
+#define LIBBSP_ARM_TMS570_FLASH
#include <bsp/utility.h>
@@ -95,22 +95,22 @@ typedef struct{
} tms570_flash_t;
-/*--------------------TMS570_FLASHFRDCNTL--------------------*/
+/*--------------------TMS570_FLASH_FRDCNTL--------------------*/
/* field: RWAIT - Random/data Read Wait State */
#define TMS570_FLASH_FRDCNTL_RWAIT(val) BSP_FLD32(val,8, 11)
#define TMS570_FLASH_FRDCNTL_RWAIT_GET(reg) BSP_FLD32GET(reg,8, 11)
#define TMS570_FLASH_FRDCNTL_RWAIT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: ASWSTEN - Address Setup Wait State Enable */
-#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_FLD32(4)
+#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_BIT32(4)
/* field: ENPIPE - Enable Pipeline Mode */
-#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_FLD32(0)
+#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_BIT32(0)
-/*-------------------TMS570_FLASHFEDACTRL1-------------------*/
+/*-------------------TMS570_FLASH_FEDACTRL1-------------------*/
/* field: SUSP_IGNR - Suspend Ignore. */
-#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_FLD32(24)
+#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_BIT32(24)
/* field: EDACMODE - Error Correction Mode. */
#define TMS570_FLASH_FEDACTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
@@ -118,13 +118,13 @@ typedef struct{
#define TMS570_FLASH_FEDACTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: EOFEN - Event on Ones Fail Enable */
-#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_FLD32(10)
+#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_BIT32(10)
/* field: EZFEN - Event on Zeros Fail Enable */
-#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_FLD32(9)
+#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_BIT32(9)
/* field: EPEN - Error Profiling Enable. */
-#define TMS570_FLASH_FEDACTRL1_EPEN BSP_FLD32(8)
+#define TMS570_FLASH_FEDACTRL1_EPEN BSP_BIT32(8)
/* field: EDACEN - Error Detection and Correction Enable */
#define TMS570_FLASH_FEDACTRL1_EDACEN(val) BSP_FLD32(val,0, 3)
@@ -132,21 +132,21 @@ typedef struct{
#define TMS570_FLASH_FEDACTRL1_EDACEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_FLASHFEDACTRL2-------------------*/
+/*-------------------TMS570_FLASH_FEDACTRL2-------------------*/
/* field: SEC_THRESHOLD - Single Error Correction Threshold */
#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_FLASHFCORERRCNT-------------------*/
+/*------------------TMS570_FLASH_FCORERRCNT------------------*/
/* field: FERRCNT - Single Error Correction Count */
#define TMS570_FLASH_FCORERRCNT_FERRCNT(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_FCORERRCNT_FERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_FCORERRCNT_FERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_FLASHFCORERRADD-------------------*/
+/*------------------TMS570_FLASH_FCORERRADD------------------*/
/* field: COR_ERR_ADD - Correctable Error Address */
#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -158,12 +158,12 @@ typedef struct{
#define TMS570_FLASH_FCORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-------------------TMS570_FLASHFCORERRPOS-------------------*/
+/*------------------TMS570_FLASH_FCORERRPOS------------------*/
/* field: BUS2 - Bus 2 Error */
-#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_FLD32(9)
+#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_BIT32(9)
/* field: TYPE - ErrorType */
-#define TMS570_FLASH_FCORERRPOS_TYPE BSP_FLD32(8)
+#define TMS570_FLASH_FCORERRPOS_TYPE BSP_BIT32(8)
/* field: ERR_POS - The bit address of the single bit error */
#define TMS570_FLASH_FCORERRPOS_ERR_POS(val) BSP_FLD32(val,0, 7)
@@ -171,53 +171,53 @@ typedef struct{
#define TMS570_FLASH_FCORERRPOS_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_FLASHFEDACSTATUS------------------*/
+/*------------------TMS570_FLASH_FEDACSTATUS------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_FLASH_FEDACSTATUS_Reserved(val) BSP_FLD32(val,26, 31)
#define TMS570_FLASH_FEDACSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,26, 31)
#define TMS570_FLASH_FEDACSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
/* field: FSM_DONE - Flash State Machine Done */
-#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_FLD32(24)
+#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_BIT32(24)
/* field: COMB2_MAL_G - Bus 2 Compare Malfunction Flag. */
-#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_FLD32(19)
+#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_BIT32(19)
/* field: ECC_B2_MAL_ - Bus 2 ECC Malfunction Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_FLD32(18)
+#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_BIT32(18)
/* field: B2_UNC_ERR - Bus 2 uncorrectable error */
-#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_FLD32(17)
+#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_BIT32(17)
/* field: B2_COR_ERR - Bus 2 Correctable Error */
-#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_FLD32(16)
+#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_BIT32(16)
/* field: D_UNC_ERR - Diagnostic Uncorrectable Error */
-#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_FLD32(12)
+#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_BIT32(12)
/* field: ADD_TAG_ERR - Address Tag Register Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_FLD32(11)
+#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_BIT32(11)
/* field: ADD_PAR_ERR - Address Parity Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_FLD32(10)
+#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_BIT32(10)
/* field: B1_UNC_ERR - Bus 1 Uncorrectable Error Flag */
-#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_FLD32(8)
+#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_BIT32(8)
/* field: D_CORR_ERR - Diagnostic Correctable Error Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_FLD32(3)
+#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_BIT32(3)
/* field: ERR_ONE_FLG - Error on One Fail Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_FLD32(2)
+#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_BIT32(2)
/* field: ERR_ZERO__FLG - Error on Zero Fail Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_FLD32(1)
+#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_BIT32(1)
/* field: ERR_PRF_FLG - Error Profiling Status Flag */
-#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_FLD32(0)
+#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_BIT32(0)
-/*-------------------TMS570_FLASHFUNCERRADD-------------------*/
+/*------------------TMS570_FLASH_FUNCERRADD------------------*/
/* field: UNC_ERR_ADD - Un-correctable Error Address */
#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -229,7 +229,7 @@ typedef struct{
#define TMS570_FLASH_FUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-------------------TMS570_FLASHFEDACSDIS-------------------*/
+/*-------------------TMS570_FLASH_FEDACSDIS-------------------*/
/* field: BankID1_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse(val) BSP_FLD32(val,29, 31)
#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -271,7 +271,7 @@ typedef struct{
#define TMS570_FLASH_FEDACSDIS_SectorID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_FLASHFPRIMADDTAG------------------*/
+/*------------------TMS570_FLASH_FPRIMADDTAG------------------*/
/* field: PRIM_ADD_TAG - Primary Address Tag Register */
#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG(val) BSP_FLD32(val,4, 31)
#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
@@ -283,33 +283,33 @@ typedef struct{
#define TMS570_FLASH_FPRIMADDTAG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_FLASHFDUPADDTAG-------------------*/
+/*------------------TMS570_FLASH_FDUPADDTAG------------------*/
/* field: DUP_ADD_TAG - Primary Address Tag Register */
#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG(val) BSP_FLD32(val,4, 31)
#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
-/*---------------------TMS570_FLASHFBPROT---------------------*/
+/*--------------------TMS570_FLASH_FBPROT--------------------*/
/* field: PROTL1DIS - PROTL1DIS: Level 1 Protection Disabled */
-#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_FLD32(0)
+#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_BIT32(0)
-/*----------------------TMS570_FLASHFBSE----------------------*/
+/*---------------------TMS570_FLASH_FBSE---------------------*/
/* field: BSE - Bank Sector Enable */
#define TMS570_FLASH_FBSE_BSE(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_FBSE_BSE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_FBSE_BSE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_FLASHFBBUSY---------------------*/
+/*--------------------TMS570_FLASH_FBBUSY--------------------*/
/* field: BUSY - Bank Busy */
#define TMS570_FLASH_FBBUSY_BUSY(val) BSP_FLD32(val,0, 7)
#define TMS570_FLASH_FBBUSY_BUSY_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_FLASH_FBBUSY_BUSY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_FLASHFBAC----------------------*/
+/*---------------------TMS570_FLASH_FBAC---------------------*/
/* field: OTPPROTDIS - OTP Sector Protection Disable. */
#define TMS570_FLASH_FBAC_OTPPROTDIS(val) BSP_FLD32(val,16, 23)
#define TMS570_FLASH_FBAC_OTPPROTDIS_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -326,7 +326,7 @@ typedef struct{
#define TMS570_FLASH_FBAC_VREADST_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_FLASHFBFALLBACK-------------------*/
+/*------------------TMS570_FLASH_FBFALLBACK------------------*/
/* field: BANKPWR7 - Bank 7 Fallback Power Mode */
#define TMS570_FLASH_FBFALLBACK_BANKPWR7(val) BSP_FLD32(val,14, 15)
#define TMS570_FLASH_FBFALLBACK_BANKPWR7_GET(reg) BSP_FLD32GET(reg,14, 15)
@@ -343,14 +343,14 @@ typedef struct{
#define TMS570_FLASH_FBFALLBACK_BANKPWR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_FLASHFBPRDY---------------------*/
+/*--------------------TMS570_FLASH_FBPRDY--------------------*/
/* field: BANKBUSY - Bank busy bits (one bit for each bank) */
#define TMS570_FLASH_FBPRDY_BANKBUSY(val) BSP_FLD32(val,16, 23)
#define TMS570_FLASH_FBPRDY_BANKBUSY_GET(reg) BSP_FLD32GET(reg,16, 23)
#define TMS570_FLASH_FBPRDY_BANKBUSY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: PUMPRDY - Flash pump ready flag */
-#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_FLD32(15)
+#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_BIT32(15)
/* field: BANKRDY - Bank ready bits (one bit for each bank) */
#define TMS570_FLASH_FBPRDY_BANKRDY(val) BSP_FLD32(val,0, 7)
@@ -358,99 +358,93 @@ typedef struct{
#define TMS570_FLASH_FBPRDY_BANKRDY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_FLASHFPAC1---------------------*/
+/*---------------------TMS570_FLASH_FPAC1---------------------*/
/* field: PSLEEP - Pump Sleep. */
#define TMS570_FLASH_FPAC1_PSLEEP(val) BSP_FLD32(val,16, 26)
#define TMS570_FLASH_FPAC1_PSLEEP_GET(reg) BSP_FLD32GET(reg,16, 26)
#define TMS570_FLASH_FPAC1_PSLEEP_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
/* field: PUMPPWR - Flash Charge Pump Fallback Power Mode */
-#define TMS570_FLASH_FPAC1_PUMPPWR BSP_FLD32(0)
+#define TMS570_FLASH_FPAC1_PUMPPWR BSP_BIT32(0)
-/*---------------------TMS570_FLASHFPAC2---------------------*/
+/*---------------------TMS570_FLASH_FPAC2---------------------*/
/* field: PAGP - Pump Active Grace Period */
#define TMS570_FLASH_FPAC2_PAGP(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_FPAC2_PAGP_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_FPAC2_PAGP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_FLASHFMAC----------------------*/
+/*---------------------TMS570_FLASH_FMAC---------------------*/
/* field: BANK - Bank Enable. */
#define TMS570_FLASH_FMAC_BANK(val) BSP_FLD32(val,0, 2)
#define TMS570_FLASH_FMAC_BANK_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_FLASH_FMAC_BANK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*---------------------TMS570_FLASHFMSTAT---------------------*/
+/*--------------------TMS570_FLASH_FMSTAT--------------------*/
/* field: ILA - Illegal Address */
-#define TMS570_FLASH_FMSTAT_ILA BSP_FLD32(14)
+#define TMS570_FLASH_FMSTAT_ILA BSP_BIT32(14)
/* field: PGV - Program Verify */
-#define TMS570_FLASH_FMSTAT_PGV BSP_FLD32(12)
+#define TMS570_FLASH_FMSTAT_PGV BSP_BIT32(12)
/* field: EV - Erase Verify */
-#define TMS570_FLASH_FMSTAT_EV BSP_FLD32(10)
+#define TMS570_FLASH_FMSTAT_EV BSP_BIT32(10)
/* field: BUSY - Busy */
-#define TMS570_FLASH_FMSTAT_BUSY BSP_FLD32(8)
+#define TMS570_FLASH_FMSTAT_BUSY BSP_BIT32(8)
/* field: ERS - Erase Active */
-#define TMS570_FLASH_FMSTAT_ERS BSP_FLD32(7)
+#define TMS570_FLASH_FMSTAT_ERS BSP_BIT32(7)
/* field: PGM - Program Active */
-#define TMS570_FLASH_FMSTAT_PGM BSP_FLD32(6)
+#define TMS570_FLASH_FMSTAT_PGM BSP_BIT32(6)
/* field: INVDAT - Invalid Data */
-#define TMS570_FLASH_FMSTAT_INVDAT BSP_FLD32(5)
+#define TMS570_FLASH_FMSTAT_INVDAT BSP_BIT32(5)
/* field: CSTAT - Command Status */
-#define TMS570_FLASH_FMSTAT_CSTAT BSP_FLD32(4)
+#define TMS570_FLASH_FMSTAT_CSTAT BSP_BIT32(4)
/* field: VOLTSTAT - Core Voltage Status */
-#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_FLD32(3)
+#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_BIT32(3)
/* field: ESUSP - Erase Suspended */
-#define TMS570_FLASH_FMSTAT_ESUSP BSP_FLD32(2)
+#define TMS570_FLASH_FMSTAT_ESUSP BSP_BIT32(2)
/* field: PSUSP - Program Suspended */
-#define TMS570_FLASH_FMSTAT_PSUSP BSP_FLD32(1)
+#define TMS570_FLASH_FMSTAT_PSUSP BSP_BIT32(1)
/* field: SLOCK - Sector Lock Status */
-#define TMS570_FLASH_FMSTAT_SLOCK BSP_FLD32(0)
+#define TMS570_FLASH_FMSTAT_SLOCK BSP_BIT32(0)
-/*--------------------TMS570_FLASHFEMUDMSW--------------------*/
+/*-------------------TMS570_FLASH_FEMUDMSW-------------------*/
/* field: EMU_DMSW - EEPROM Emulation Most Significant Data Word */
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLASHFEMUDLSW--------------------*/
+/*-------------------TMS570_FLASH_FEMUDLSW-------------------*/
/* field: EMU_DLSW - EEPROM Emulation Least Significant Data Word */
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLASHFEMUECC--------------------*/
+/*--------------------TMS570_FLASH_FEMUECC--------------------*/
/* field: EMU_ECC - This register can be written by the CPU in any mode. */
#define TMS570_FLASH_FEMUECC_EMU_ECC(val) BSP_FLD32(val,0, 7)
#define TMS570_FLASH_FEMUECC_EMU_ECC_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_FLASH_FEMUECC_EMU_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_FLASHFEMUADDR--------------------*/
+/*-------------------TMS570_FLASH_FEMUADDR-------------------*/
/* field: EMU_ADDR - EEPROM Emulation Address */
#define TMS570_FLASH_FEMUADDR_EMU_ADDR(val) BSP_FLD32(val,3, 21)
#define TMS570_FLASH_FEMUADDR_EMU_ADDR_GET(reg) BSP_FLD32GET(reg,3, 21)
#define TMS570_FLASH_FEMUADDR_EMU_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,3, 21)
-/*-------------------TMS570_FLASHFDIAGCTRL-------------------*/
+/*-------------------TMS570_FLASH_FDIAGCTRL-------------------*/
/* field: DIAG_TRIG - Diagnostic Trigger */
-#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_FLD32(24)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_BIT32(24)
/* field: DIAG_EN_KEY - Diagnostic Enable Key */
#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY(val) BSP_FLD32(val,16, 19)
@@ -463,23 +457,17 @@ typedef struct{
#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
-/*-------------------TMS570_FLASHFRAWDATAH-------------------*/
+/*-------------------TMS570_FLASH_FRAWDATAH-------------------*/
/* field: RAW_DATA_ - Uncorrected Raw Data */
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA_(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FRAWDATAH_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLASHFRAWDATAL-------------------*/
+/*-------------------TMS570_FLASH_FRAWDATAL-------------------*/
/* field: RAW_DATA_ - Uncorrected Raw Data. Same as FRAW_DATAH but stores lower 32 bits. */
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA_(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLASH_FRAWDATAL_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLASHFRAWECC--------------------*/
+/*--------------------TMS570_FLASH_FRAWECC--------------------*/
/* field: PIPE_BUF - Error came from pipeline buffer hit */
-#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_FLD32(8)
+#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_BIT32(8)
/* field: RAW_ECC - Uncorrected Raw ECC */
#define TMS570_FLASH_FRAWECC_RAW_ECC(val) BSP_FLD32(val,0, 7)
@@ -487,9 +475,9 @@ typedef struct{
#define TMS570_FLASH_FRAWECC_RAW_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_FLASHFPAROVR--------------------*/
+/*--------------------TMS570_FLASH_FPAROVR--------------------*/
/* field: BNK_INV_PAR - Buffer Invert Parity */
-#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_FLD32(16)
+#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_BIT32(16)
/* field: BUS_PAR_DIS - Disable Bus Parity */
#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS(val) BSP_FLD32(val,12, 15)
@@ -502,7 +490,7 @@ typedef struct{
#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
/* field: ADD_INV_PAR - Address Odd Parity */
-#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_FLD32(8)
+#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_BIT32(8)
/* field: DAT_INV_PAR - Data Odd Parity */
#define TMS570_FLASH_FPAROVR_DAT_INV_PAR(val) BSP_FLD32(val,0, 7)
@@ -510,7 +498,7 @@ typedef struct{
#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_FLASHFEDACSDIS2-------------------*/
+/*------------------TMS570_FLASH_FEDACSDIS2------------------*/
/* field: BankID3_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse(val) BSP_FLD32(val,29, 31)
#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -552,28 +540,28 @@ typedef struct{
#define TMS570_FLASH_FEDACSDIS2_SectorID2_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_FLASHFSMWRENA--------------------*/
+/*-------------------TMS570_FLASH_FSMWRENA-------------------*/
/* field: WR_ENA - Flash State Machine Write Enable */
#define TMS570_FLASH_FSMWRENA_WR_ENA(val) BSP_FLD32(val,0, 2)
#define TMS570_FLASH_FSMWRENA_WR_ENA_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_FLASH_FSMWRENA_WR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-------------------TMS570_FLASHFSMSECTOR-------------------*/
+/*-------------------TMS570_FLASH_FSMSECTOR-------------------*/
/* field: SECT_ERASED - Sectors Erased */
#define TMS570_FLASH_FSMSECTOR_SECT_ERASED(val) BSP_FLD32(val,16, 31)
#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_GET(reg) BSP_FLD32GET(reg,16, 31)
#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
-/*------------------TMS570_FLASHEEPROMCONFIG------------------*/
+/*-----------------TMS570_FLASH_EEPROMCONFIG-----------------*/
/* field: EWAIT - EEPROM Wait state Counter */
#define TMS570_FLASH_EEPROMCONFIG_EWAIT(val) BSP_FLD32(val,16, 19)
#define TMS570_FLASH_EEPROMCONFIG_EWAIT_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_FLASH_EEPROMCONFIG_EWAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: AUTOSUSP_EN - Auto Suspend Enable */
-#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_FLD32(8)
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_BIT32(8)
/* field: AUTOSTART_GRACE - Auto-suspend Startup Grace Period */
#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE(val) BSP_FLD32(val,0, 7)
@@ -581,37 +569,37 @@ typedef struct{
#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_FLASHEECTRL1--------------------*/
+/*--------------------TMS570_FLASH_EECTRL1--------------------*/
/* field: EDACMODE - Error Correction Mode. */
#define TMS570_FLASH_EECTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
#define TMS570_FLASH_EECTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_FLASH_EECTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: EE_EOFEN - EEPROM Emulation Event on a correctable One's Fail Enable bit */
-#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_FLD32(10)
+#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_BIT32(10)
/* field: EE_EZFEN - EEPROM Emulation Event on a correctable Zero's Fail Enable bit */
-#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_FLD32(9)
+#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_BIT32(9)
/* field: EE_EPEN - EEPROM Emulation Error Profiling Enable. */
-#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_FLD32(8)
+#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_BIT32(8)
-/*--------------------TMS570_FLASHEECTRL2--------------------*/
+/*--------------------TMS570_FLASH_EECTRL2--------------------*/
/* field: EE_SEC_THRESHOLD - EEPROM Emulation Single Error Correction Threshold */
#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*------------------TMS570_FLASHEECORERRCNT------------------*/
+/*------------------TMS570_FLASH_EECORERRCNT------------------*/
/* field: EE_ERRCNT - Single Error Correction Count */
#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT(val) BSP_FLD32(val,0, 15)
#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*------------------TMS570_FLASHEECORERRADD------------------*/
+/*------------------TMS570_FLASH_EECORERRADD------------------*/
/* field: COR_ERR_ADD - Correctable Error Address */
#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -623,9 +611,9 @@ typedef struct{
#define TMS570_FLASH_EECORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*------------------TMS570_FLASHEECORERRPOS------------------*/
+/*------------------TMS570_FLASH_EECORERRPOS------------------*/
/* field: TYPE - ErrorType */
-#define TMS570_FLASH_EECORERRPOS_TYPE BSP_FLD32(8)
+#define TMS570_FLASH_EECORERRPOS_TYPE BSP_BIT32(8)
/* field: EE_ERR_POS - The bit address of the single bit error */
#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS(val) BSP_FLD32(val,0, 7)
@@ -633,33 +621,33 @@ typedef struct{
#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_FLASHEESTATUS--------------------*/
+/*-------------------TMS570_FLASH_EESTATUS-------------------*/
/* field: EE_D_UNC_ERR - Diagnostic Mode Uncorrectable Error Status Flag */
-#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_FLD32(12)
+#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_BIT32(12)
/* field: EE_UNC_ERR - EEPROM Emulation Uncorrectable Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_FLD32(8)
+#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_BIT32(8)
/* field: EE_CMG - EEPROM Emulation Compare Malfunction Good */
-#define TMS570_FLASH_EESTATUS_EE_CMG BSP_FLD32(6)
+#define TMS570_FLASH_EESTATUS_EE_CMG BSP_BIT32(6)
/* field: EE_CME - . */
-#define TMS570_FLASH_EESTATUS_EE_CME BSP_FLD32(4)
+#define TMS570_FLASH_EESTATUS_EE_CME BSP_BIT32(4)
/* field: EE_D_COR_ERR - Diagnostic Correctable Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_FLD32(3)
+#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_BIT32(3)
/* field: EE_ERR_ONE_FLG - Error on One Fail Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_FLD32(2)
+#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_BIT32(2)
/* field: EE_ERR_ZERO_FLG - Error on Zero Fail Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_FLD32(1)
+#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_BIT32(1)
/* field: EE_ERR_PRF_FLG - Error Profiling Error Flag */
-#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_FLD32(0)
+#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_BIT32(0)
-/*------------------TMS570_FLASHEEUNCERRADD------------------*/
+/*------------------TMS570_FLASH_EEUNCERRADD------------------*/
/* field: UNC_ERR_ADD - Un-correctable Error Address */
#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
@@ -671,7 +659,7 @@ typedef struct{
#define TMS570_FLASH_EEUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*--------------------TMS570_FLASHFCFGBANK--------------------*/
+/*-------------------TMS570_FLASH_FCFGBANK-------------------*/
/* field: EE_BANK_WIDTH - Bank 7 width (144 bits wide) */
#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH(val) BSP_FLD32(val,20, 31)
#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,20, 31)
@@ -684,4 +672,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_FLASH */
+#endif /* LIBBSP_ARM_TMS570_FLASH */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
index 799ad1b..e077ab6 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_FLEX_RAY
-#define LIBBSP_ARM_tms570_FLEX_RAY
+#ifndef LIBBSP_ARM_TMS570_FLEX_RAY
+#define LIBBSP_ARM_TMS570_FLEX_RAY
#include <bsp/utility.h>
@@ -121,7 +121,7 @@ typedef struct{
} tms570_flex_ray_t;
-/*--------------------TMS570_FLEX_RAYGSN0--------------------*/
+/*--------------------TMS570_FLEX_RAY_GSN0--------------------*/
/* field: Data_A - Data_A(15-0) */
#define TMS570_FLEX_RAY_GSN0_Data_A(val) BSP_FLD32(val,16, 31)
#define TMS570_FLEX_RAY_GSN0_Data_A_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -133,7 +133,7 @@ typedef struct{
#define TMS570_FLEX_RAY_GSN0_Data_B_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_FLEX_RAYGSN1--------------------*/
+/*--------------------TMS570_FLEX_RAY_GSN1--------------------*/
/* field: Data_C - Data_C(15-0) */
#define TMS570_FLEX_RAY_GSN1_Data_C(val) BSP_FLD32(val,16, 31)
#define TMS570_FLEX_RAY_GSN1_Data_C_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -145,12 +145,12 @@ typedef struct{
#define TMS570_FLEX_RAY_GSN1_Data_D_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_FLEX_RAYGCS---------------------*/
+/*--------------------TMS570_FLEX_RAY_GCS--------------------*/
/* field: ENDVBM - Endianness Correction on VBusp Master */
-#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_FLD32(31)
+#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_BIT32(31)
/* field: ENDVBS - Endianness correction on VBusp Slave */
-#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_FLD32(30)
+#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_BIT32(30)
/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
#define TMS570_FLEX_RAY_GCS_ENDRx(val) BSP_FLD32(val,28, 29)
@@ -168,10 +168,10 @@ typedef struct{
#define TMS570_FLEX_RAY_GCS_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
/* field: PRIO - Transfer Priority */
-#define TMS570_FLEX_RAY_GCS_PRIO BSP_FLD32(21)
+#define TMS570_FLEX_RAY_GCS_PRIO BSP_BIT32(21)
/* field: PEFT - Parity for Test */
-#define TMS570_FLEX_RAY_GCS_PEFT BSP_FLD32(20)
+#define TMS570_FLEX_RAY_GCS_PEFT BSP_BIT32(20)
/* field: PELx - Parity Lock */
#define TMS570_FLEX_RAY_GCS_PELx(val) BSP_FLD32(val,16, 19)
@@ -179,36 +179,36 @@ typedef struct{
#define TMS570_FLEX_RAY_GCS_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: CETESM - Clear ETESM Register */
-#define TMS570_FLEX_RAY_GCS_CETESM BSP_FLD32(14)
+#define TMS570_FLEX_RAY_GCS_CETESM BSP_BIT32(14)
/* field: CTTCC - Clear TTCC Register */
-#define TMS570_FLEX_RAY_GCS_CTTCC BSP_FLD32(13)
+#define TMS570_FLEX_RAY_GCS_CTTCC BSP_BIT32(13)
/* field: CTTSM - Clear TTSM Register */
-#define TMS570_FLEX_RAY_GCS_CTTSM BSP_FLD32(12)
+#define TMS570_FLEX_RAY_GCS_CTTSM BSP_BIT32(12)
/* field: ETSM - Enable Transfer Status Mirrored */
-#define TMS570_FLEX_RAY_GCS_ETSM BSP_FLD32(8)
+#define TMS570_FLEX_RAY_GCS_ETSM BSP_BIT32(8)
/* field: SILE - Status Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCS_SILE BSP_FLD32(5)
+#define TMS570_FLEX_RAY_GCS_SILE BSP_BIT32(5)
/* field: EILE - Error Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCS_EILE BSP_FLD32(4)
+#define TMS570_FLEX_RAY_GCS_EILE BSP_BIT32(4)
/* field: TUH - Transfer Unit Halted */
-#define TMS570_FLEX_RAY_GCS_TUH BSP_FLD32(1)
+#define TMS570_FLEX_RAY_GCS_TUH BSP_BIT32(1)
/* field: TUE - Transfer Unit Enabled */
-#define TMS570_FLEX_RAY_GCS_TUE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_GCS_TUE BSP_BIT32(0)
-/*---------------------TMS570_FLEX_RAYGCR---------------------*/
+/*--------------------TMS570_FLEX_RAY_GCR--------------------*/
/* field: ENDVBM - Endianness Correction on VBusp Master */
-#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_FLD32(31)
+#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_BIT32(31)
/* field: ENDVBS - Endianness correction on VBusp Slave */
-#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_FLD32(30)
+#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_BIT32(30)
/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
#define TMS570_FLEX_RAY_GCR_ENDRx(val) BSP_FLD32(val,28, 29)
@@ -226,10 +226,10 @@ typedef struct{
#define TMS570_FLEX_RAY_GCR_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
/* field: PRIO - Transfer Priority */
-#define TMS570_FLEX_RAY_GCR_PRIO BSP_FLD32(21)
+#define TMS570_FLEX_RAY_GCR_PRIO BSP_BIT32(21)
/* field: PEFT - Parity for Test */
-#define TMS570_FLEX_RAY_GCR_PEFT BSP_FLD32(20)
+#define TMS570_FLEX_RAY_GCR_PEFT BSP_BIT32(20)
/* field: PELx - Parity Lock */
#define TMS570_FLEX_RAY_GCR_PELx(val) BSP_FLD32(val,16, 19)
@@ -237,41 +237,41 @@ typedef struct{
#define TMS570_FLEX_RAY_GCR_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: CETESM - Clear ETESM Register */
-#define TMS570_FLEX_RAY_GCR_CETESM BSP_FLD32(14)
+#define TMS570_FLEX_RAY_GCR_CETESM BSP_BIT32(14)
/* field: CTTCC - Clear TTCC Register */
-#define TMS570_FLEX_RAY_GCR_CTTCC BSP_FLD32(13)
+#define TMS570_FLEX_RAY_GCR_CTTCC BSP_BIT32(13)
/* field: CTTSM - Clear TTSM Register */
-#define TMS570_FLEX_RAY_GCR_CTTSM BSP_FLD32(12)
+#define TMS570_FLEX_RAY_GCR_CTTSM BSP_BIT32(12)
/* field: ETSM - Enable Transfer Status Mirrored */
-#define TMS570_FLEX_RAY_GCR_ETSM BSP_FLD32(8)
+#define TMS570_FLEX_RAY_GCR_ETSM BSP_BIT32(8)
/* field: SILE - Status Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCR_SILE BSP_FLD32(5)
+#define TMS570_FLEX_RAY_GCR_SILE BSP_BIT32(5)
/* field: EILE - Error Interrupt Line Enable */
-#define TMS570_FLEX_RAY_GCR_EILE BSP_FLD32(4)
+#define TMS570_FLEX_RAY_GCR_EILE BSP_BIT32(4)
/* field: TUH - Transfer Unit Halted */
-#define TMS570_FLEX_RAY_GCR_TUH BSP_FLD32(1)
+#define TMS570_FLEX_RAY_GCR_TUH BSP_BIT32(1)
/* field: TUE - Transfer Unit Enabled */
-#define TMS570_FLEX_RAY_GCR_TUE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_GCR_TUE BSP_BIT32(0)
-/*--------------------TMS570_FLEX_RAYTSCB--------------------*/
+/*--------------------TMS570_FLEX_RAY_TSCB--------------------*/
/* field: TSMS - Transfer State Machine Status */
#define TMS570_FLEX_RAY_TSCB_TSMS(val) BSP_FLD32(val,16, 20)
#define TMS570_FLEX_RAY_TSCB_TSMS_GET(reg) BSP_FLD32GET(reg,16, 20)
#define TMS570_FLEX_RAY_TSCB_TSMS_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
/* field: STUH - Status of Transfer Unit State Machine for Halt Detection */
-#define TMS570_FLEX_RAY_TSCB_STUH BSP_FLD32(12)
+#define TMS570_FLEX_RAY_TSCB_STUH BSP_BIT32(12)
/* field: IDLE - Detects Transfer State Machine State IDLE */
-#define TMS570_FLEX_RAY_TSCB_IDLE BSP_FLD32(8)
+#define TMS570_FLEX_RAY_TSCB_IDLE BSP_BIT32(8)
/* field: BN - Buffer Number */
#define TMS570_FLEX_RAY_TSCB_BN(val) BSP_FLD32(val,0, 6)
@@ -279,114 +279,75 @@ typedef struct{
#define TMS570_FLEX_RAY_TSCB_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*--------------------TMS570_FLEX_RAYLTBCC--------------------*/
+/*-------------------TMS570_FLEX_RAY_LTBCC-------------------*/
/* field: BN - Buffer number. */
#define TMS570_FLEX_RAY_LTBCC_BN(val) BSP_FLD32(val,0, 6)
#define TMS570_FLEX_RAY_LTBCC_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_FLEX_RAY_LTBCC_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*--------------------TMS570_FLEX_RAYLTBSM--------------------*/
+/*-------------------TMS570_FLEX_RAY_LTBSM-------------------*/
/* field: BN - Buffer number. */
#define TMS570_FLEX_RAY_LTBSM_BN(val) BSP_FLD32(val,0, 6)
#define TMS570_FLEX_RAY_LTBSM_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
#define TMS570_FLEX_RAY_LTBSM_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*---------------------TMS570_FLEX_RAYTBA---------------------*/
+/*--------------------TMS570_FLEX_RAY_TBA--------------------*/
/* field: TBA - Transfer Base Address. */
-#define TMS570_FLEX_RAY_TBA_TBA(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TBA_TBA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TBA_TBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYNTBA--------------------*/
+/*--------------------TMS570_FLEX_RAY_NTBA--------------------*/
/* field: nTBA - nTBA(31-0) */
-#define TMS570_FLEX_RAY_NTBA_nTBA(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_NTBA_nTBA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_NTBA_nTBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYBAMS--------------------*/
+/*--------------------TMS570_FLEX_RAY_BAMS--------------------*/
/* field: BAMS - Base Address of Mirrored Status32-bit base pointer, 2 LSB are not significant (32-bit */
-#define TMS570_FLEX_RAY_BAMS_BAMS(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_BAMS_BAMS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_BAMS_BAMS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYSAMP--------------------*/
+/*--------------------TMS570_FLEX_RAY_SAMP--------------------*/
/* field: SAMP - Start Address Memory Protection. */
-#define TMS570_FLEX_RAY_SAMP_SAMP(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_SAMP_SAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_SAMP_SAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYEAMP--------------------*/
+/*--------------------TMS570_FLEX_RAY_EAMP--------------------*/
/* field: EAMP - End Address Memory Protection. */
-#define TMS570_FLEX_RAY_EAMP_EAMP(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_EAMP_EAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_EAMP_EAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYTSMO1--------------------*/
+/*-------------------TMS570_FLEX_RAY_TSMO1-------------------*/
/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO1_TSMO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMO1_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO1_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYTSMO2--------------------*/
+/*-------------------TMS570_FLEX_RAY_TSMO2-------------------*/
/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO2_TSMO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMO2_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO2_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYTSMO3--------------------*/
+/*-------------------TMS570_FLEX_RAY_TSMO3-------------------*/
/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO3_TSMO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMO3_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO3_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYTSMO4--------------------*/
+/*-------------------TMS570_FLEX_RAY_TSMO4-------------------*/
/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
-#define TMS570_FLEX_RAY_TSMO4_TSMO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMO4_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMO4_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYTCCO1--------------------*/
+/*-------------------TMS570_FLEX_RAY_TCCO1-------------------*/
/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO1_TCCO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCO1_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO1_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYTCCO2--------------------*/
+/*-------------------TMS570_FLEX_RAY_TCCO2-------------------*/
/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO2_TCCO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCO2_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO2_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYTCCO3--------------------*/
+/*-------------------TMS570_FLEX_RAY_TCCO3-------------------*/
/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO3_TCCO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCO3_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO3_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_FLEX_RAYTCCO4--------------------*/
+/*-------------------TMS570_FLEX_RAY_TCCO4-------------------*/
/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
-#define TMS570_FLEX_RAY_TCCO4_TCCO1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCO4_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCO4_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_FLEX_RAYTOOFF--------------------*/
+/*-------------------TMS570_FLEX_RAY_TOOFF-------------------*/
/* field: TDIR - Transfer Direction. */
-#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_FLD32(8)
+#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_BIT32(8)
/* field: OFF - Offset Vector */
#define TMS570_FLEX_RAY_TOOFF_OFF(val) BSP_FLD32(val,0, 7)
@@ -394,19 +355,19 @@ typedef struct{
#define TMS570_FLEX_RAY_TOOFF_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*--------------------TMS570_FLEX_RAYPEADR--------------------*/
+/*-------------------TMS570_FLEX_RAY_PEADR-------------------*/
/* field: ADR - Address of failing TCR location. */
#define TMS570_FLEX_RAY_PEADR_ADR(val) BSP_FLD32(val,0, 8)
#define TMS570_FLEX_RAY_PEADR_ADR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_FLEX_RAY_PEADR_ADR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*--------------------TMS570_FLEX_RAYTEIF--------------------*/
+/*--------------------TMS570_FLEX_RAY_TEIF--------------------*/
/* field: MPV - Memory Protection Violation. */
-#define TMS570_FLEX_RAY_TEIF_MPV BSP_FLD32(17)
+#define TMS570_FLEX_RAY_TEIF_MPV BSP_BIT32(17)
/* field: PE - Parity Error. The flag signals a parity error to the host. */
-#define TMS570_FLEX_RAY_TEIF_PE BSP_FLD32(16)
+#define TMS570_FLEX_RAY_TEIF_PE BSP_BIT32(16)
/* field: RSTAT - Status of VBUS on read transfers. */
#define TMS570_FLEX_RAY_TEIF_RSTAT(val) BSP_FLD32(val,8, 10)
@@ -419,13 +380,13 @@ typedef struct{
#define TMS570_FLEX_RAY_TEIF_WSTAT_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TNR - Transfer Not Ready. */
-#define TMS570_FLEX_RAY_TEIF_TNR BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIF_TNR BSP_BIT32(1)
/* field: FAC - Forbidden Access. */
-#define TMS570_FLEX_RAY_TEIF_FAC BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIF_FAC BSP_BIT32(0)
-/*-------------------TMS570_FLEX_RAYTEIRES-------------------*/
+/*-------------------TMS570_FLEX_RAY_TEIRES-------------------*/
/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
#define TMS570_FLEX_RAY_TEIRES_RSTATE(val) BSP_FLD32(val,8, 10)
#define TMS570_FLEX_RAY_TEIRES_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -437,13 +398,13 @@ typedef struct{
#define TMS570_FLEX_RAY_TEIRES_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TNRE - Transfer Not Ready Enable. */
-#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_BIT32(1)
/* field: FACE - Forbidden Access Enable. */
-#define TMS570_FLEX_RAY_TEIRES_FACE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIRES_FACE BSP_BIT32(0)
-/*-------------------TMS570_FLEX_RAYTEIRER-------------------*/
+/*-------------------TMS570_FLEX_RAY_TEIRER-------------------*/
/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
#define TMS570_FLEX_RAY_TEIRER_RSTATE(val) BSP_FLD32(val,8, 10)
#define TMS570_FLEX_RAY_TEIRER_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -455,347 +416,203 @@ typedef struct{
#define TMS570_FLEX_RAY_TEIRER_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
/* field: TNRE - Transfer Not Ready Enable. */
-#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_FLD32(1)
+#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_BIT32(1)
/* field: FACE - Forbidden Access Enable. */
-#define TMS570_FLEX_RAY_TEIRER_FACE BSP_FLD32(0)
+#define TMS570_FLEX_RAY_TEIRER_FACE BSP_BIT32(0)
-/*-------------------TMS570_FLEX_RAYTTSMS1-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMS1-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTSMR1-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMR1-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTSMS2-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMS2-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTSMR2-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMR2-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTSMS3-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMS3-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTSMR3-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMR3-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTSMS4-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMS4-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTSMR4-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTSMR4-------------------*/
/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTCCS1-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCS1-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTCCR1-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCR1-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTCCS2-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCS2-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTCCR2-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCR2-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTCCS3-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCS3-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTCCR3-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCR3-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTTCCS4-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCS4-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTTCCR4-------------------*/
+/*-------------------TMS570_FLEX_RAY_TTCCR4-------------------*/
/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYETESMS1-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMS1------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYETESMR1-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMR1------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYETESMS2-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMS2------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYETESMR2-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMR2------------------*/
/* field: ETESMS1 - message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYETESMS3-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMS3------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYETESMR3-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMR3------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYETESMS4-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMS4------------------*/
/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYETESMR4-------------------*/
+/*------------------TMS570_FLEX_RAY_ETESMR4------------------*/
/* field: ETESMS1 - message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYCESMS1-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMS1-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS1_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMS1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYCESMR1-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMR1-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR1_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMR1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYCESMS2-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMS2-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS2_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMS2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYCESMR2-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMR2-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR2_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMR2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYCESMS3-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMS3-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS3_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMS3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYCESMR3-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMR3-------------------*/
/* field: CESMS1 - CESMS1(31-0) */
-#define TMS570_FLEX_RAY_CESMR3_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMR3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYCESMS4-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMS4-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMS4_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMS4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMS4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYCESMR4-------------------*/
+/*-------------------TMS570_FLEX_RAY_CESMR4-------------------*/
/* field: CESMS1 - Clear on Event to System Memory Set 1. */
-#define TMS570_FLEX_RAY_CESMR4_CESMS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_CESMR4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_CESMR4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTSMIES1-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIES1------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTSMIER1-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIER1------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTSMIES2-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIES2------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTSMIER2-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIER2------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTSMIES3-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIES3------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTSMIER3-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIER3------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTSMIES4-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIES4------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTSMIER4-------------------*/
+/*------------------TMS570_FLEX_RAY_TSMIER4------------------*/
/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTCCIES1-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIES1------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTCCIER1-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIER1------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTCCIES2-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIES2------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTCCIER2-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIER2------------------*/
/* field: TCCIES1 - to message buffers 0 to 31. */
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTCCIES3-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIES3------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTCCIER3-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIER3------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_FLEX_RAYTCCIES4-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIES4------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_FLEX_RAYTCCIER4-------------------*/
+/*------------------TMS570_FLEX_RAY_TCCIER4------------------*/
/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1(val) BSP_FLD32(val,0, 31)
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_FLEX_RAY */
+#endif /* LIBBSP_ARM_TMS570_FLEX_RAY */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
index bc7c857..3cb7851 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_GIO
-#define LIBBSP_ARM_tms570_GIO
+#ifndef LIBBSP_ARM_TMS570_GIO
+#define LIBBSP_ARM_TMS570_GIO
#include <bsp/utility.h>
@@ -70,68 +70,68 @@ typedef struct{
} tms570_gio_t;
-/*-----------------------TMS570_GIODIR-----------------------*/
+/*-----------------------TMS570_GIO_DIR-----------------------*/
/* field: GIODIR - GIO data direction, pins [7:0] */
#define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIODIN-----------------------*/
+/*-----------------------TMS570_GIO_DIN-----------------------*/
/* field: GIODIN - GIO data input, pins [7:0] */
#define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIODOUT-----------------------*/
+/*----------------------TMS570_GIO_DOUT----------------------*/
/* field: GIODOUT - IO data output, pins[7:0]. */
#define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIODSET-----------------------*/
+/*----------------------TMS570_GIO_DSET----------------------*/
/* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */
#define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIODCLR-----------------------*/
+/*----------------------TMS570_GIO_DCLR----------------------*/
/* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */
#define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOPDR-----------------------*/
+/*-----------------------TMS570_GIO_PDR-----------------------*/
/* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */
#define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_GIOPULDIS----------------------*/
+/*---------------------TMS570_GIO_PULDIS---------------------*/
/* field: GIOPULDIS - GIO pull disable, pins[7:0]. */
#define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOPSL-----------------------*/
+/*-----------------------TMS570_GIO_PSL-----------------------*/
/* field: GIOPSL - GIO pull select, pins[7:0] */
#define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7)
#define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOGCR0-----------------------*/
+/*----------------------TMS570_GIO_GCR0----------------------*/
/* field: RESET - GIO reset. */
-#define TMS570_GIO_GCR0_RESET BSP_FLD32(0)
+#define TMS570_GIO_GCR0_RESET BSP_BIT32(0)
-/*----------------------TMS570_GIOINTDET----------------------*/
+/*---------------------TMS570_GIO_INTDET---------------------*/
/* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */
#define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -153,7 +153,7 @@ typedef struct{
#define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOPOL-----------------------*/
+/*-----------------------TMS570_GIO_POL-----------------------*/
/* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */
#define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -175,7 +175,7 @@ typedef struct{
#define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_GIOENASET----------------------*/
+/*---------------------TMS570_GIO_ENASET---------------------*/
/* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */
#define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -197,7 +197,7 @@ typedef struct{
#define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_GIOENACLR----------------------*/
+/*---------------------TMS570_GIO_ENACLR---------------------*/
/* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */
#define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -219,7 +219,7 @@ typedef struct{
#define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_GIOLVLSET----------------------*/
+/*---------------------TMS570_GIO_LVLSET---------------------*/
/* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */
#define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -241,7 +241,7 @@ typedef struct{
#define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_GIOLVLCLR----------------------*/
+/*---------------------TMS570_GIO_LVLCLR---------------------*/
/* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */
#define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -263,7 +263,7 @@ typedef struct{
#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOFLG-----------------------*/
+/*-----------------------TMS570_GIO_FLG-----------------------*/
/* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */
#define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31)
#define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -285,35 +285,35 @@ typedef struct{
#define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_GIOOFF1-----------------------*/
+/*----------------------TMS570_GIO_OFF1----------------------*/
/* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */
#define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------------TMS570_GIOOFF2-----------------------*/
+/*----------------------TMS570_GIO_OFF2----------------------*/
/* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------------TMS570_GIOEMU1-----------------------*/
+/*----------------------TMS570_GIO_EMU1----------------------*/
/* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */
#define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------------TMS570_GIOEMU2-----------------------*/
+/*----------------------TMS570_GIO_EMU2----------------------*/
/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*----------------------TMS570_GIOports----------------------*/
+/*----------------------TMS570_GIO_ports----------------------*/
/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
#define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5)
#define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
@@ -321,4 +321,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_GIO */
+#endif /* LIBBSP_ARM_TMS570_GIO */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
index f033303..3df27be 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_HTU
-#define LIBBSP_ARM_tms570_HTU
+#ifndef LIBBSP_ARM_TMS570_HTU
+#define LIBBSP_ARM_TMS570_HTU
#include <bsp/utility.h>
@@ -75,114 +75,114 @@ typedef struct{
} tms570_htu_t;
-/*------------------------TMS570_HTUGC------------------------*/
+/*-----------------------TMS570_HTU_GC-----------------------*/
/* field: VBUSHOLD - Hold the VBUS bus */
-#define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24)
+#define TMS570_HTU_GC_VBUSHOLD BSP_BIT32(24)
/* field: HTUEN - Transfer Unit Enable Bit */
-#define TMS570_HTU_GC_HTUEN BSP_FLD32(16)
+#define TMS570_HTU_GC_HTUEN BSP_BIT32(16)
/* field: DEBM - Debug Mode */
-#define TMS570_HTU_GC_DEBM BSP_FLD32(8)
+#define TMS570_HTU_GC_DEBM BSP_BIT32(8)
/* field: HTURES - HTU Software Reset Request */
-#define TMS570_HTU_GC_HTURES BSP_FLD32(0)
+#define TMS570_HTU_GC_HTURES BSP_BIT32(0)
-/*----------------------TMS570_HTUCPENA----------------------*/
+/*----------------------TMS570_HTU_CPENA----------------------*/
/* field: CPENA - CP Enable Bits */
#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_HTUBUSY0----------------------*/
+/*----------------------TMS570_HTU_BUSY0----------------------*/
/* field: BUSY0A - Busy Flag for CP A of DCP 0 */
-#define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24)
+#define TMS570_HTU_BUSY0_BUSY0A BSP_BIT32(24)
/* field: BUSY0B - Busy Flag for CP B of DCP 0 */
-#define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16)
+#define TMS570_HTU_BUSY0_BUSY0B BSP_BIT32(16)
/* field: BUSY1A - Busy Flag for CP A of DCP 1 */
-#define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8)
+#define TMS570_HTU_BUSY0_BUSY1A BSP_BIT32(8)
/* field: BUSY1B - Busy Flag for CP B of DCP 1 */
-#define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0)
+#define TMS570_HTU_BUSY0_BUSY1B BSP_BIT32(0)
-/*----------------------TMS570_HTUBUSY1----------------------*/
+/*----------------------TMS570_HTU_BUSY1----------------------*/
/* field: BUSY2A - Busy Flag for CP A of DCP 2 */
-#define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24)
+#define TMS570_HTU_BUSY1_BUSY2A BSP_BIT32(24)
/* field: BUSY2B - Busy Flag for CP B of DCP 2 */
-#define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16)
+#define TMS570_HTU_BUSY1_BUSY2B BSP_BIT32(16)
/* field: BUSY3A - Busy Flag for CP A of DCP 3 */
-#define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8)
+#define TMS570_HTU_BUSY1_BUSY3A BSP_BIT32(8)
/* field: BUSY3B - Busy Flag for CP B of DCP 3 */
-#define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0)
+#define TMS570_HTU_BUSY1_BUSY3B BSP_BIT32(0)
-/*----------------------TMS570_HTUBUSY2----------------------*/
+/*----------------------TMS570_HTU_BUSY2----------------------*/
/* field: BUSY4A - Busy Flag for CP A of DCP 4 */
-#define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24)
+#define TMS570_HTU_BUSY2_BUSY4A BSP_BIT32(24)
/* field: BUSY4B - Busy Flag for CP B of DCP 4 */
-#define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16)
+#define TMS570_HTU_BUSY2_BUSY4B BSP_BIT32(16)
/* field: BUSY5A - Busy Flag for CP A of DCP 5 */
-#define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8)
+#define TMS570_HTU_BUSY2_BUSY5A BSP_BIT32(8)
/* field: BUSY5B - Busy Flag for CP B of DCP 5 */
-#define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0)
+#define TMS570_HTU_BUSY2_BUSY5B BSP_BIT32(0)
-/*----------------------TMS570_HTUBUSY3----------------------*/
+/*----------------------TMS570_HTU_BUSY3----------------------*/
/* field: BUSY6A - Busy Flag for CP A of DCP 6 */
-#define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24)
+#define TMS570_HTU_BUSY3_BUSY6A BSP_BIT32(24)
/* field: BUSY6B - Busy Flag for CP B of DCP 6 */
-#define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16)
+#define TMS570_HTU_BUSY3_BUSY6B BSP_BIT32(16)
/* field: BUSY7A - Busy Flag for CP A of DCP 7 */
-#define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8)
+#define TMS570_HTU_BUSY3_BUSY7A BSP_BIT32(8)
/* field: BUSY7B - Busy Flag for CP B of DCP 7 */
-#define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0)
+#define TMS570_HTU_BUSY3_BUSY7B BSP_BIT32(0)
-/*-----------------------TMS570_HTUACPE-----------------------*/
+/*----------------------TMS570_HTU_ACPE----------------------*/
/* field: ERRF - Error Flag */
-#define TMS570_HTU_ACPE_ERRF BSP_FLD32(31)
+#define TMS570_HTU_ACPE_ERRF BSP_BIT32(31)
-/*---------------------TMS570_HTURLBECTRL---------------------*/
+/*--------------------TMS570_HTU_RLBECTRL--------------------*/
/* field: BERINTENA - Bus Error Interrupt Enable Bit */
-#define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16)
+#define TMS570_HTU_RLBECTRL_BERINTENA BSP_BIT32(16)
/* field: CORL - Continue On Request Lost Error */
-#define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8)
+#define TMS570_HTU_RLBECTRL_CORL BSP_BIT32(8)
/* field: RLINTENA - Request Lost Interrupt Enable Bit */
-#define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0)
+#define TMS570_HTU_RLBECTRL_RLINTENA BSP_BIT32(0)
-/*----------------------TMS570_HTUBFINTS----------------------*/
+/*---------------------TMS570_HTU_BFINTS---------------------*/
/* field: BFINTENA - Bus Full Interrupt Enable Bits. */
#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_HTUBFINTC----------------------*/
+/*---------------------TMS570_HTU_BFINTC---------------------*/
/* field: BFINTDIS - */
#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_HTUINTOFF0---------------------*/
+/*---------------------TMS570_HTU_INTOFF0---------------------*/
/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -194,7 +194,7 @@ typedef struct{
#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*---------------------TMS570_HTUINTOFF1---------------------*/
+/*---------------------TMS570_HTU_INTOFF1---------------------*/
/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -206,76 +206,64 @@ typedef struct{
#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*-----------------------TMS570_HTUBIM-----------------------*/
+/*-----------------------TMS570_HTU_BIM-----------------------*/
/* field: BIM - Buffer Initialization Mode */
#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_HTURLOSTFL---------------------*/
+/*---------------------TMS570_HTU_RLOSTFL---------------------*/
/* field: CPRLFL - CP Request Lost Flags */
#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_HTUBFINTFL---------------------*/
+/*---------------------TMS570_HTU_BFINTFL---------------------*/
/* field: BFINTFL - Buffer Full Interrupt Flags */
#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_HTUBERINTFL---------------------*/
+/*--------------------TMS570_HTU_BERINTFL--------------------*/
/* field: BERINTFL - Bus Error Interrupt Flags */
#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_HTUMP1S-----------------------*/
+/*----------------------TMS570_HTU_MP1S----------------------*/
/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
-#define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_HTUMP1E-----------------------*/
+/*----------------------TMS570_HTU_MP1E----------------------*/
/* field: ENDADDRESS1 - The end address defines at which address the region ends. */
-#define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_HTUDCTRL----------------------*/
+/*----------------------TMS570_HTU_DCTRL----------------------*/
/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: HTUDBGS - HTU Debug Status. */
-#define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16)
+#define TMS570_HTU_DCTRL_HTUDBGS BSP_BIT32(16)
/* field: DBREN - Debug Request Enable */
-#define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0)
+#define TMS570_HTU_DCTRL_DBREN BSP_BIT32(0)
-/*-----------------------TMS570_HTUWPR-----------------------*/
+/*-----------------------TMS570_HTU_WPR-----------------------*/
/* field: WP - Watch Point Register */
-#define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_HTUWMR-----------------------*/
+/*-----------------------TMS570_HTU_WMR-----------------------*/
/* field: WM - Watch Mask Register */
-#define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------------TMS570_HTUID------------------------*/
+/*-----------------------TMS570_HTU_ID-----------------------*/
/* field: CLASS - Module Class */
#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -292,12 +280,12 @@ typedef struct{
#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_HTUPCR-----------------------*/
+/*-----------------------TMS570_HTU_PCR-----------------------*/
/* field: COPE - Continue on Parity Error */
-#define TMS570_HTU_PCR_COPE BSP_FLD32(16)
+#define TMS570_HTU_PCR_COPE BSP_BIT32(16)
/* field: TEST - Test. */
-#define TMS570_HTU_PCR_TEST BSP_FLD32(8)
+#define TMS570_HTU_PCR_TEST BSP_BIT32(8)
/* field: PARITY_ENA - Enable/Disable Parity Checking. */
#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -305,9 +293,9 @@ typedef struct{
#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_HTUPAR-----------------------*/
+/*-----------------------TMS570_HTU_PAR-----------------------*/
/* field: PEFT - Parity Error Fault Flag. */
-#define TMS570_HTU_PAR_PEFT BSP_FLD32(16)
+#define TMS570_HTU_PAR_PEFT BSP_BIT32(16)
/* field: PAOFF - PAOFF */
#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
@@ -315,17 +303,17 @@ typedef struct{
#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*-----------------------TMS570_HTUMPCS-----------------------*/
+/*----------------------TMS570_HTU_MPCS----------------------*/
/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: MPEFT1 - MPEFT1 */
-#define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17)
+#define TMS570_HTU_MPCS_MPEFT1 BSP_BIT32(17)
/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
-#define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16)
+#define TMS570_HTU_MPCS_MPEFT0 BSP_BIT32(16)
/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
@@ -333,19 +321,13 @@ typedef struct{
#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
-/*-----------------------TMS570_HTUMP0S-----------------------*/
+/*----------------------TMS570_HTU_MP0S----------------------*/
/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
-#define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_HTUMP0E-----------------------*/
+/*----------------------TMS570_HTU_MP0E----------------------*/
/* field: ENDADDRESS0 - The end address defines at which address the region ends. */
-#define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31)
-#define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_HTU */
+#endif /* LIBBSP_ARM_TMS570_HTU */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
index c4441ca..63ed3f8 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_I2C
-#define LIBBSP_ARM_tms570_I2C
+#ifndef LIBBSP_ARM_TMS570_I2C
+#define LIBBSP_ARM_TMS570_I2C
#include <bsp/utility.h>
@@ -72,155 +72,155 @@ typedef struct{
} tms570_i2c_t;
-/*-----------------------TMS570_I2COAR-----------------------*/
+/*-----------------------TMS570_I2C_OAR-----------------------*/
/* field: OA - Own address */
#define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9)
#define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*-----------------------TMS570_I2CIMR-----------------------*/
+/*-----------------------TMS570_I2C_IMR-----------------------*/
/* field: AASEN - Address As Slave Interrupt Enable */
-#define TMS570_I2C_IMR_AASEN BSP_FLD32(6)
+#define TMS570_I2C_IMR_AASEN BSP_BIT32(6)
/* field: SCDEN - Stop Condition Interrupt Enable */
-#define TMS570_I2C_IMR_SCDEN BSP_FLD32(5)
+#define TMS570_I2C_IMR_SCDEN BSP_BIT32(5)
/* field: TXRDYEN - Transmit Data Ready Interrupt Enable */
-#define TMS570_I2C_IMR_TXRDYEN BSP_FLD32(4)
+#define TMS570_I2C_IMR_TXRDYEN BSP_BIT32(4)
/* field: RXRDYEN - Receive Data Ready Interrupt Enable */
-#define TMS570_I2C_IMR_RXRDYEN BSP_FLD32(3)
+#define TMS570_I2C_IMR_RXRDYEN BSP_BIT32(3)
/* field: ARDYEN - Register Access Ready Interrupt Enable */
-#define TMS570_I2C_IMR_ARDYEN BSP_FLD32(2)
+#define TMS570_I2C_IMR_ARDYEN BSP_BIT32(2)
/* field: NACKEN - No Acknowledgement Interrupt Enable */
-#define TMS570_I2C_IMR_NACKEN BSP_FLD32(1)
+#define TMS570_I2C_IMR_NACKEN BSP_BIT32(1)
/* field: ALEN - Arbitration Lost Interrupt Enable */
-#define TMS570_I2C_IMR_ALEN BSP_FLD32(0)
+#define TMS570_I2C_IMR_ALEN BSP_BIT32(0)
-/*-----------------------TMS570_I2CSTR-----------------------*/
+/*-----------------------TMS570_I2C_STR-----------------------*/
/* field: SDIR - Slave direction */
-#define TMS570_I2C_STR_SDIR BSP_FLD32(14)
+#define TMS570_I2C_STR_SDIR BSP_BIT32(14)
/* field: NACKSNT - No acknowledge sent */
-#define TMS570_I2C_STR_NACKSNT BSP_FLD32(13)
+#define TMS570_I2C_STR_NACKSNT BSP_BIT32(13)
/* field: BB - Bus busy */
-#define TMS570_I2C_STR_BB BSP_FLD32(12)
+#define TMS570_I2C_STR_BB BSP_BIT32(12)
/* field: RSFULL - Receiver shift full */
-#define TMS570_I2C_STR_RSFULL BSP_FLD32(11)
+#define TMS570_I2C_STR_RSFULL BSP_BIT32(11)
/* field: XSMT - XSMT */
-#define TMS570_I2C_STR_XSMT BSP_FLD32(10)
+#define TMS570_I2C_STR_XSMT BSP_BIT32(10)
/* field: AAS - Address as slave */
-#define TMS570_I2C_STR_AAS BSP_FLD32(9)
+#define TMS570_I2C_STR_AAS BSP_BIT32(9)
/* field: AD0 - Address zero status */
-#define TMS570_I2C_STR_AD0 BSP_FLD32(8)
+#define TMS570_I2C_STR_AD0 BSP_BIT32(8)
/* field: SCD - SCD */
-#define TMS570_I2C_STR_SCD BSP_FLD32(5)
+#define TMS570_I2C_STR_SCD BSP_BIT32(5)
/* field: TXRDY - Transmit data ready interrupt flag */
-#define TMS570_I2C_STR_TXRDY BSP_FLD32(4)
+#define TMS570_I2C_STR_TXRDY BSP_BIT32(4)
/* field: RXRDY - Receive data ready interrupt flag */
-#define TMS570_I2C_STR_RXRDY BSP_FLD32(3)
+#define TMS570_I2C_STR_RXRDY BSP_BIT32(3)
/* field: ARDY - Register access ready interrupt flag */
-#define TMS570_I2C_STR_ARDY BSP_FLD32(2)
+#define TMS570_I2C_STR_ARDY BSP_BIT32(2)
/* field: NACK - No acknowledgement interrupt */
-#define TMS570_I2C_STR_NACK BSP_FLD32(1)
+#define TMS570_I2C_STR_NACK BSP_BIT32(1)
/* field: AL - Arbitration lost interrupt flag */
-#define TMS570_I2C_STR_AL BSP_FLD32(0)
+#define TMS570_I2C_STR_AL BSP_BIT32(0)
-/*-----------------------TMS570_I2CCKL-----------------------*/
+/*-----------------------TMS570_I2C_CKL-----------------------*/
/* field: CLKL - Low time clock division factor */
#define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_I2CCKH-----------------------*/
+/*-----------------------TMS570_I2C_CKH-----------------------*/
/* field: CLKH - High time clock division factor */
#define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_I2CCNT-----------------------*/
+/*-----------------------TMS570_I2C_CNT-----------------------*/
/* field: CNT - Data counter */
#define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15)
#define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_I2CDRR-----------------------*/
+/*-----------------------TMS570_I2C_DRR-----------------------*/
/* field: DATARX - Receive data */
#define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_I2CSAR-----------------------*/
+/*-----------------------TMS570_I2C_SAR-----------------------*/
/* field: SA - 7- or 10-bit programmable slave address */
#define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9)
#define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*-----------------------TMS570_I2CDXR-----------------------*/
+/*-----------------------TMS570_I2C_DXR-----------------------*/
/* field: DATATX - Transmit data */
#define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_I2CMDR-----------------------*/
+/*-----------------------TMS570_I2C_MDR-----------------------*/
/* field: NACKMOD - No-acknowledge (NACK) mode */
-#define TMS570_I2C_MDR_NACKMOD BSP_FLD32(15)
+#define TMS570_I2C_MDR_NACKMOD BSP_BIT32(15)
/* field: FREE - Free running bit */
-#define TMS570_I2C_MDR_FREE BSP_FLD32(14)
+#define TMS570_I2C_MDR_FREE BSP_BIT32(14)
/* field: STT - Start condition */
-#define TMS570_I2C_MDR_STT BSP_FLD32(13)
+#define TMS570_I2C_MDR_STT BSP_BIT32(13)
/* field: STP - Stop condition */
-#define TMS570_I2C_MDR_STP BSP_FLD32(11)
+#define TMS570_I2C_MDR_STP BSP_BIT32(11)
/* field: MST - Master/slave mode bit */
-#define TMS570_I2C_MDR_MST BSP_FLD32(10)
+#define TMS570_I2C_MDR_MST BSP_BIT32(10)
/* field: TRX - Transmit/receive bit */
-#define TMS570_I2C_MDR_TRX BSP_FLD32(9)
+#define TMS570_I2C_MDR_TRX BSP_BIT32(9)
/* field: XA - Expand address enable bit */
-#define TMS570_I2C_MDR_XA BSP_FLD32(8)
+#define TMS570_I2C_MDR_XA BSP_BIT32(8)
/* field: RM - RM */
-#define TMS570_I2C_MDR_RM BSP_FLD32(7)
+#define TMS570_I2C_MDR_RM BSP_BIT32(7)
/* field: DLB - Digital loop back enable bit */
-#define TMS570_I2C_MDR_DLB BSP_FLD32(6)
+#define TMS570_I2C_MDR_DLB BSP_BIT32(6)
/* field: nIRS - I2C reset enable bit */
-#define TMS570_I2C_MDR_nIRS BSP_FLD32(5)
+#define TMS570_I2C_MDR_nIRS BSP_BIT32(5)
/* field: STB - Start byte mode enable bit (Master mode only) */
-#define TMS570_I2C_MDR_STB BSP_FLD32(4)
+#define TMS570_I2C_MDR_STB BSP_BIT32(4)
/* field: FDF - Free data format enable bit */
-#define TMS570_I2C_MDR_FDF BSP_FLD32(3)
+#define TMS570_I2C_MDR_FDF BSP_BIT32(3)
/* field: BC - Bit count */
#define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2)
@@ -228,7 +228,7 @@ typedef struct{
#define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_I2CIVR-----------------------*/
+/*-----------------------TMS570_I2C_IVR-----------------------*/
/* field: TESTMD - Reserved for internal testing. */
#define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11)
#define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11)
@@ -240,22 +240,22 @@ typedef struct{
#define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_I2CEMDR-----------------------*/
+/*----------------------TMS570_I2C_EMDR----------------------*/
/* field: IGNACK - Ignore NACK mode */
-#define TMS570_I2C_EMDR_IGNACK BSP_FLD32(1)
+#define TMS570_I2C_EMDR_IGNACK BSP_BIT32(1)
/* field: BCM - Backwards compatibility mode */
-#define TMS570_I2C_EMDR_BCM BSP_FLD32(0)
+#define TMS570_I2C_EMDR_BCM BSP_BIT32(0)
-/*-----------------------TMS570_I2CPSC-----------------------*/
+/*-----------------------TMS570_I2C_PSC-----------------------*/
/* field: PSC - Prescale */
#define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_I2CPID11----------------------*/
+/*----------------------TMS570_I2C_PID11----------------------*/
/* field: CLASS - Peripheral class */
#define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15)
#define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -267,97 +267,97 @@ typedef struct{
#define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_I2CPID12----------------------*/
+/*----------------------TMS570_I2C_PID12----------------------*/
/* field: TYPE - Peripheral type */
#define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7)
#define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_I2CDMACR----------------------*/
+/*----------------------TMS570_I2C_DMACR----------------------*/
/* field: TXDMAEN - Transmitter DMA enable */
-#define TMS570_I2C_DMACR_TXDMAEN BSP_FLD32(1)
+#define TMS570_I2C_DMACR_TXDMAEN BSP_BIT32(1)
/* field: RXDMAEN - Receive DMA enable */
-#define TMS570_I2C_DMACR_RXDMAEN BSP_FLD32(0)
+#define TMS570_I2C_DMACR_RXDMAEN BSP_BIT32(0)
-/*-----------------------TMS570_I2CPFNC-----------------------*/
+/*----------------------TMS570_I2C_PFNC----------------------*/
/* field: PINFUNC - SDA and SCL Pin Function */
-#define TMS570_I2C_PFNC_PINFUNC BSP_FLD32(0)
+#define TMS570_I2C_PFNC_PINFUNC BSP_BIT32(0)
-/*-----------------------TMS570_I2CDIR-----------------------*/
+/*-----------------------TMS570_I2C_DIR-----------------------*/
/* field: SDADIR - SDA direction */
-#define TMS570_I2C_DIR_SDADIR BSP_FLD32(1)
+#define TMS570_I2C_DIR_SDADIR BSP_BIT32(1)
/* field: SCLDIR - SCL direction */
-#define TMS570_I2C_DIR_SCLDIR BSP_FLD32(0)
+#define TMS570_I2C_DIR_SCLDIR BSP_BIT32(0)
-/*-----------------------TMS570_I2CDIN-----------------------*/
+/*-----------------------TMS570_I2C_DIN-----------------------*/
/* field: SDAIN - Serial data in */
-#define TMS570_I2C_DIN_SDAIN BSP_FLD32(1)
+#define TMS570_I2C_DIN_SDAIN BSP_BIT32(1)
/* field: SCLIN - Serial clock data in */
-#define TMS570_I2C_DIN_SCLIN BSP_FLD32(0)
+#define TMS570_I2C_DIN_SCLIN BSP_BIT32(0)
-/*-----------------------TMS570_I2CDOUT-----------------------*/
+/*----------------------TMS570_I2C_DOUT----------------------*/
/* field: SDAOUT - SDA Data Output */
-#define TMS570_I2C_DOUT_SDAOUT BSP_FLD32(1)
+#define TMS570_I2C_DOUT_SDAOUT BSP_BIT32(1)
/* field: SCLOUT - SCL Data Output */
-#define TMS570_I2C_DOUT_SCLOUT BSP_FLD32(0)
+#define TMS570_I2C_DOUT_SCLOUT BSP_BIT32(0)
-/*-----------------------TMS570_I2CSET-----------------------*/
+/*-----------------------TMS570_I2C_SET-----------------------*/
/* field: SDASET - Serial Data Set */
-#define TMS570_I2C_SET_SDASET BSP_FLD32(1)
+#define TMS570_I2C_SET_SDASET BSP_BIT32(1)
/* field: SCLSET - Serial Clock Set */
-#define TMS570_I2C_SET_SCLSET BSP_FLD32(0)
+#define TMS570_I2C_SET_SCLSET BSP_BIT32(0)
-/*-----------------------TMS570_I2CCLR-----------------------*/
+/*-----------------------TMS570_I2C_CLR-----------------------*/
/* field: SDACLR - Serial Data Clear */
-#define TMS570_I2C_CLR_SDACLR BSP_FLD32(1)
+#define TMS570_I2C_CLR_SDACLR BSP_BIT32(1)
/* field: SCLCLR - Serial Clock Clear */
-#define TMS570_I2C_CLR_SCLCLR BSP_FLD32(0)
+#define TMS570_I2C_CLR_SCLCLR BSP_BIT32(0)
-/*-----------------------TMS570_I2CPDR-----------------------*/
+/*-----------------------TMS570_I2C_PDR-----------------------*/
/* field: SDAPDR - SDA pin open drain enable */
-#define TMS570_I2C_PDR_SDAPDR BSP_FLD32(1)
+#define TMS570_I2C_PDR_SDAPDR BSP_BIT32(1)
/* field: SCLPDR - SCL pin open drain enable */
-#define TMS570_I2C_PDR_SCLPDR BSP_FLD32(0)
+#define TMS570_I2C_PDR_SCLPDR BSP_BIT32(0)
-/*-----------------------TMS570_I2CPDIS-----------------------*/
+/*----------------------TMS570_I2C_PDIS----------------------*/
/* field: SDAPDIS - SDA pull disable */
-#define TMS570_I2C_PDIS_SDAPDIS BSP_FLD32(1)
+#define TMS570_I2C_PDIS_SDAPDIS BSP_BIT32(1)
/* field: SCLPDIS - SCL pull disable */
-#define TMS570_I2C_PDIS_SCLPDIS BSP_FLD32(0)
+#define TMS570_I2C_PDIS_SCLPDIS BSP_BIT32(0)
-/*-----------------------TMS570_I2CPSEL-----------------------*/
+/*----------------------TMS570_I2C_PSEL----------------------*/
/* field: SDAPSEL - SDA pull select */
-#define TMS570_I2C_PSEL_SDAPSEL BSP_FLD32(1)
+#define TMS570_I2C_PSEL_SDAPSEL BSP_BIT32(1)
/* field: SCLPSEL - SCL pull select */
-#define TMS570_I2C_PSEL_SCLPSEL BSP_FLD32(0)
+#define TMS570_I2C_PSEL_SCLPSEL BSP_BIT32(0)
-/*-----------------------TMS570_I2CpSRS-----------------------*/
+/*----------------------TMS570_I2C_pSRS----------------------*/
/* field: SDASRS - SDA Slew Rate select */
-#define TMS570_I2C_pSRS_SDASRS BSP_FLD32(1)
+#define TMS570_I2C_pSRS_SDASRS BSP_BIT32(1)
/* field: SCLSRS - SCL Slew Rate select */
-#define TMS570_I2C_pSRS_SCLSRS BSP_FLD32(0)
+#define TMS570_I2C_pSRS_SCLSRS BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_I2C */
+#endif /* LIBBSP_ARM_TMS570_I2C */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
index 8a8c05f..f6197e8 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_IOMM
-#define LIBBSP_ARM_tms570_IOMM
+#ifndef LIBBSP_ARM_TMS570_IOMM
+#define LIBBSP_ARM_TMS570_IOMM
#include <bsp/utility.h>
@@ -96,29 +96,29 @@ typedef struct{
} tms570_iomm_t;
-/*---------------------TMS570_IOMMPINMMR0---------------------*/
+/*--------------------TMS570_IOMM_PINMMRx--------------------*/
/* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
-#define TMS570_IOMM_PINMMR0_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_IOMM_PINMMRx_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
-#define TMS570_IOMM_PINMMR0_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_IOMM_PINMMRx_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_IOMM_PINMMR0_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_IOMM_PINMMRx_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
-#define TMS570_IOMM_PINMMR0_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_IOMM_PINMMRx_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_IOMMREVISION_REG------------------*/
+/*------------------TMS570_IOMM_REVISION_REG------------------*/
/* field: REV_SCHEME - Revision Scheme */
#define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -150,65 +150,56 @@ typedef struct{
#define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-------------------TMS570_IOMMENDIAN_REG-------------------*/
+/*-------------------TMS570_IOMM_ENDIAN_REG-------------------*/
/* field: ENDIAN - Device endianness */
-#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_FLD32(0)
+#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_BIT32(0)
-/*--------------------TMS570_IOMMKICK_REG0--------------------*/
+/*-------------------TMS570_IOMM_KICK_REG0-------------------*/
/* field: KICK0 - Kicker 0 Register. */
-#define TMS570_IOMM_KICK_REG0_KICK0(val) BSP_FLD32(val,0, 31)
-#define TMS570_IOMM_KICK_REG0_KICK0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_KICK_REG0_KICK0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_IOMMKICK_REG1--------------------*/
+/*-------------------TMS570_IOMM_KICK_REG1-------------------*/
/* field: KICK1 - Kicker 1 Register. */
-#define TMS570_IOMM_KICK_REG1_KICK1(val) BSP_FLD32(val,0, 31)
-#define TMS570_IOMM_KICK_REG1_KICK1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_KICK_REG1_KICK1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------TMS570_IOMMERR_RAW_STATUS_REG---------------*/
+/*---------------TMS570_IOMM_ERR_RAW_STATUS_REG---------------*/
/* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */
-#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_BIT32(1)
/* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */
-#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_BIT32(0)
-/*-------------TMS570_IOMMERR_ENABLED_STATUS_REG-------------*/
+/*-------------TMS570_IOMM_ERR_ENABLED_STATUS_REG-------------*/
/* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */
-#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_BIT32(1)
/* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */
-#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_BIT32(0)
-/*-----------------TMS570_IOMMERR_ENABLE_REG-----------------*/
+/*-----------------TMS570_IOMM_ERR_ENABLE_REG-----------------*/
/* field: ADDR_ERR_EN - Addressing Error Signaling Enable */
-#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_BIT32(1)
/* field: PROT_ERR_EN - Protection ErrorSignaling Enable */
-#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_BIT32(0)
-/*---------------TMS570_IOMMERR_ENABLE_CLR_REG---------------*/
+/*---------------TMS570_IOMM_ERR_ENABLE_CLR_REG---------------*/
/* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */
-#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_FLD32(1)
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_BIT32(1)
/* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */
-#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_FLD32(0)
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_BIT32(0)
-/*----------------TMS570_IOMMFAULT_ADDRESS_REG----------------*/
+/*---------------TMS570_IOMM_FAULT_ADDRESS_REG---------------*/
/* field: FAULT_ADDR - Fault Address. */
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR(val) BSP_FLD32(val,0, 31)
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------TMS570_IOMMFAULT_STATUS_REG----------------*/
+/*----------------TMS570_IOMM_FAULT_STATUS_REG----------------*/
/* field: FAULT_ID - Faulting Transaction ID */
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27)
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -230,15 +221,15 @@ typedef struct{
#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*-----------------TMS570_IOMMFAULT_CLEAR_REG-----------------*/
+/*----------------TMS570_IOMM_FAULT_CLEAR_REG----------------*/
/* field: FAULT_CLEAR - Fault Clear */
-#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_FLD32(0)
+#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_BIT32(0)
-/*---------------------TMS570_IOMMPINMUX---------------------*/
+/*---------------------TMS570_IOMM_PINMUX---------------------*/
/* field: FAULT_CLEAR - Fault Clear */
-#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_FLD32(0)
+#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_IOMM */
+#endif /* LIBBSP_ARM_TMS570_IOMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
index 2729b33..d2c3a3b 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_LIN
-#define LIBBSP_ARM_tms570_LIN
+#ifndef LIBBSP_ARM_TMS570_LIN
+#define LIBBSP_ARM_TMS570_LIN
#include <bsp/utility.h>
@@ -79,350 +79,350 @@ typedef struct{
} tms570_lin_t;
-/*-----------------------TMS570_LINGCR0-----------------------*/
+/*----------------------TMS570_LIN_GCR0----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_LIN_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
#define TMS570_LIN_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
#define TMS570_LIN_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
/* field: RESET - This bit resets the SCI module. */
-#define TMS570_LIN_GCR0_RESET BSP_FLD32(0)
+#define TMS570_LIN_GCR0_RESET BSP_BIT32(0)
-/*-----------------------TMS570_LINGCR1-----------------------*/
+/*----------------------TMS570_LIN_GCR1----------------------*/
/* field: TXENA - Transmit enable. */
-#define TMS570_LIN_GCR1_TXENA BSP_FLD32(25)
+#define TMS570_LIN_GCR1_TXENA BSP_BIT32(25)
/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
-#define TMS570_LIN_GCR1_RXENA BSP_FLD32(24)
+#define TMS570_LIN_GCR1_RXENA BSP_BIT32(24)
/* field: CONT - Continue on suspend. */
-#define TMS570_LIN_GCR1_CONT BSP_FLD32(17)
+#define TMS570_LIN_GCR1_CONT BSP_BIT32(17)
/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
-#define TMS570_LIN_GCR1_LOOP_BACK BSP_FLD32(16)
+#define TMS570_LIN_GCR1_LOOP_BACK BSP_BIT32(16)
/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
-#define TMS570_LIN_GCR1_POWERDOWN BSP_FLD32(9)
+#define TMS570_LIN_GCR1_POWERDOWN BSP_BIT32(9)
/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
-#define TMS570_LIN_GCR1_SLEEP BSP_FLD32(8)
+#define TMS570_LIN_GCR1_SLEEP BSP_BIT32(8)
/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
-#define TMS570_LIN_GCR1_SWnRST BSP_FLD32(7)
+#define TMS570_LIN_GCR1_SWnRST BSP_BIT32(7)
/* field: CLOCK - CLOCK */
-#define TMS570_LIN_GCR1_CLOCK BSP_FLD32(5)
+#define TMS570_LIN_GCR1_CLOCK BSP_BIT32(5)
/* field: STOP - SCI number of stop bits per frame. */
-#define TMS570_LIN_GCR1_STOP BSP_FLD32(4)
+#define TMS570_LIN_GCR1_STOP BSP_BIT32(4)
/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
-#define TMS570_LIN_GCR1_PARITY BSP_FLD32(3)
+#define TMS570_LIN_GCR1_PARITY BSP_BIT32(3)
/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
-#define TMS570_LIN_GCR1_PARITY_ENA BSP_FLD32(2)
+#define TMS570_LIN_GCR1_PARITY_ENA BSP_BIT32(2)
/* field: TIMING_MODE - SCI timing mode bit. */
-#define TMS570_LIN_GCR1_TIMING_MODE BSP_FLD32(1)
+#define TMS570_LIN_GCR1_TIMING_MODE BSP_BIT32(1)
/* field: COMM_MODE - SCI communication mode bit. */
-#define TMS570_LIN_GCR1_COMM_MODE BSP_FLD32(0)
+#define TMS570_LIN_GCR1_COMM_MODE BSP_BIT32(0)
-/*-----------------------TMS570_LINGCR2-----------------------*/
+/*----------------------TMS570_LIN_GCR2----------------------*/
/* field: CC - Compare checksum. LIN mode only. */
-#define TMS570_LIN_GCR2_CC BSP_FLD32(17)
+#define TMS570_LIN_GCR2_CC BSP_BIT32(17)
/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
-#define TMS570_LIN_GCR2_SC BSP_FLD32(16)
+#define TMS570_LIN_GCR2_SC BSP_BIT32(16)
/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
-#define TMS570_LIN_GCR2_GEN_WU BSP_FLD32(8)
+#define TMS570_LIN_GCR2_GEN_WU BSP_BIT32(8)
/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
-#define TMS570_LIN_GCR2_POWERDOWN BSP_FLD32(0)
+#define TMS570_LIN_GCR2_POWERDOWN BSP_BIT32(0)
-/*----------------------TMS570_LINSETINT----------------------*/
+/*---------------------TMS570_LIN_SETINT---------------------*/
/* field: SET_FE_INT - */
-#define TMS570_LIN_SETINT_SET_FE_INT BSP_FLD32(26)
+#define TMS570_LIN_SETINT_SET_FE_INT BSP_BIT32(26)
/* field: SET_OE_INT - SET OE INT */
-#define TMS570_LIN_SETINT_SET_OE_INT BSP_FLD32(25)
+#define TMS570_LIN_SETINT_SET_OE_INT BSP_BIT32(25)
/* field: SET_PE_INT - Set parity interrupt. */
-#define TMS570_LIN_SETINT_SET_PE_INT BSP_FLD32(24)
+#define TMS570_LIN_SETINT_SET_PE_INT BSP_BIT32(24)
/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
-#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
/* field: SET_RX_DMA - SET RX DMA */
-#define TMS570_LIN_SETINT_SET_RX_DMA BSP_FLD32(17)
+#define TMS570_LIN_SETINT_SET_RX_DMA BSP_BIT32(17)
/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
-#define TMS570_LIN_SETINT_SET_TX_DMA BSP_FLD32(16)
+#define TMS570_LIN_SETINT_SET_TX_DMA BSP_BIT32(16)
/* field: SET_RX_INT - SET RX INT */
-#define TMS570_LIN_SETINT_SET_RX_INT BSP_FLD32(9)
+#define TMS570_LIN_SETINT_SET_RX_INT BSP_BIT32(9)
/* field: SET_TX_INT - Set transmitter interrupt. */
-#define TMS570_LIN_SETINT_SET_TX_INT BSP_FLD32(8)
+#define TMS570_LIN_SETINT_SET_TX_INT BSP_BIT32(8)
/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
-#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
-#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_BIT32(0)
-/*---------------------TMS570_LINCLEARINT---------------------*/
+/*--------------------TMS570_LIN_CLEARINT--------------------*/
/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_BIT32(26)
/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_BIT32(25)
/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_BIT32(24)
/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
/* field: CLR_TX_DMA - CLR TX DMA */
-#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_BIT32(9)
/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_BIT32(8)
/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
-#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
-/*--------------------TMS570_LINSETINTLVL--------------------*/
+/*--------------------TMS570_LIN_SETINTLVL--------------------*/
/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
-#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
-#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
-#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
-/*-------------------TMS570_LINCLEARINTLVL-------------------*/
+/*-------------------TMS570_LIN_CLEARINTLVL-------------------*/
/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
/* field: CLR_PE_INT_LVL - */
-#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
-#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
-#define TMS570_LIN_CLEARINTLVL_8 BSP_FLD32(8)
+#define TMS570_LIN_CLEARINTLVL_8 BSP_BIT32(8)
/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
-#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
-/*-----------------------TMS570_LINFLR-----------------------*/
+/*-----------------------TMS570_LIN_FLR-----------------------*/
/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
-#define TMS570_LIN_FLR_FE BSP_FLD32(26)
+#define TMS570_LIN_FLR_FE BSP_BIT32(26)
/* field: OE - Overrun error flag. */
-#define TMS570_LIN_FLR_OE BSP_FLD32(25)
+#define TMS570_LIN_FLR_OE BSP_BIT32(25)
/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
-#define TMS570_LIN_FLR_PE BSP_FLD32(24)
+#define TMS570_LIN_FLR_PE BSP_BIT32(24)
/* field: RXWAKE - Receiver wakeup detect flag. */
-#define TMS570_LIN_FLR_RXWAKE BSP_FLD32(12)
+#define TMS570_LIN_FLR_RXWAKE BSP_BIT32(12)
/* field: TX_EMPTY - Transmitter empty flag. */
-#define TMS570_LIN_FLR_TX_EMPTY BSP_FLD32(11)
+#define TMS570_LIN_FLR_TX_EMPTY BSP_BIT32(11)
/* field: TXWAKE - Transmitter wakeup method select. */
-#define TMS570_LIN_FLR_TXWAKE BSP_FLD32(10)
+#define TMS570_LIN_FLR_TXWAKE BSP_BIT32(10)
/* field: RXRDY - Receiver ready flag. */
-#define TMS570_LIN_FLR_RXRDY BSP_FLD32(9)
+#define TMS570_LIN_FLR_RXRDY BSP_BIT32(9)
/* field: TXRDY - Transmitter buffer register ready flag. */
-#define TMS570_LIN_FLR_TXRDY BSP_FLD32(8)
+#define TMS570_LIN_FLR_TXRDY BSP_BIT32(8)
/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
-#define TMS570_LIN_FLR_BUSY BSP_FLD32(3)
+#define TMS570_LIN_FLR_BUSY BSP_BIT32(3)
/* field: IDLE - SCI receiver in idle state. */
-#define TMS570_LIN_FLR_IDLE BSP_FLD32(2)
+#define TMS570_LIN_FLR_IDLE BSP_BIT32(2)
/* field: WAKEUP - Wakeup flag. */
-#define TMS570_LIN_FLR_WAKEUP BSP_FLD32(1)
+#define TMS570_LIN_FLR_WAKEUP BSP_BIT32(1)
/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
-#define TMS570_LIN_FLR_BRKDT BSP_FLD32(0)
+#define TMS570_LIN_FLR_BRKDT BSP_BIT32(0)
-/*---------------------TMS570_LININTVECT0---------------------*/
+/*--------------------TMS570_LIN_INTVECT0--------------------*/
/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
#define TMS570_LIN_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
#define TMS570_LIN_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_LIN_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_LININTVECT1---------------------*/
+/*--------------------TMS570_LIN_INTVECT1--------------------*/
/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
#define TMS570_LIN_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
#define TMS570_LIN_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_LIN_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_LINFORMAT----------------------*/
+/*---------------------TMS570_LIN_FORMAT---------------------*/
/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
#define TMS570_LIN_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
#define TMS570_LIN_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_LIN_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_LINBRS-----------------------*/
+/*-----------------------TMS570_LIN_BRS-----------------------*/
/* field: BAUD - SCI 24-bit baud selection. */
#define TMS570_LIN_BRS_BAUD(val) BSP_FLD32(val,0, 23)
#define TMS570_LIN_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_LIN_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*------------------------TMS570_LINED------------------------*/
+/*-----------------------TMS570_LIN_ED-----------------------*/
/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
#define TMS570_LIN_ED_ED(val) BSP_FLD32(val,0, 7)
#define TMS570_LIN_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_LIN_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------------TMS570_LINRD------------------------*/
+/*-----------------------TMS570_LIN_RD-----------------------*/
/* field: RD - Receiver data. */
#define TMS570_LIN_RD_RD(val) BSP_FLD32(val,0, 7)
#define TMS570_LIN_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_LIN_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------------TMS570_LINTD------------------------*/
+/*-----------------------TMS570_LIN_TD-----------------------*/
/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
#define TMS570_LIN_TD_TD(val) BSP_FLD32(val,0, 7)
#define TMS570_LIN_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_LIN_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_LINPIO0-----------------------*/
+/*----------------------TMS570_LIN_PIO0----------------------*/
/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
-#define TMS570_LIN_PIO0_TX_FUNC BSP_FLD32(2)
+#define TMS570_LIN_PIO0_TX_FUNC BSP_BIT32(2)
/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
-#define TMS570_LIN_PIO0_RX_FUNC BSP_FLD32(1)
+#define TMS570_LIN_PIO0_RX_FUNC BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO1-----------------------*/
+/*----------------------TMS570_LIN_PIO1----------------------*/
/* field: TX_DIR - Transmit pin direction. */
-#define TMS570_LIN_PIO1_TX_DIR BSP_FLD32(2)
+#define TMS570_LIN_PIO1_TX_DIR BSP_BIT32(2)
/* field: RX_DIR - Receive pin direction. */
-#define TMS570_LIN_PIO1_RX_DIR BSP_FLD32(1)
+#define TMS570_LIN_PIO1_RX_DIR BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO2-----------------------*/
+/*----------------------TMS570_LIN_PIO2----------------------*/
/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
-#define TMS570_LIN_PIO2_TX_IN BSP_FLD32(2)
+#define TMS570_LIN_PIO2_TX_IN BSP_BIT32(2)
/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
-#define TMS570_LIN_PIO2_RX_IN BSP_FLD32(1)
+#define TMS570_LIN_PIO2_RX_IN BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO3-----------------------*/
+/*----------------------TMS570_LIN_PIO3----------------------*/
/* field: TX_OUT - Transmit pin out. */
-#define TMS570_LIN_PIO3_TX_OUT BSP_FLD32(2)
+#define TMS570_LIN_PIO3_TX_OUT BSP_BIT32(2)
/* field: RX_OUT - Receive pin out. */
-#define TMS570_LIN_PIO3_RX_OUT BSP_FLD32(1)
+#define TMS570_LIN_PIO3_RX_OUT BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO4-----------------------*/
+/*----------------------TMS570_LIN_PIO4----------------------*/
/* field: TX_SET - Transmit pin set. */
-#define TMS570_LIN_PIO4_TX_SET BSP_FLD32(2)
+#define TMS570_LIN_PIO4_TX_SET BSP_BIT32(2)
/* field: RX_SET - Receive pin set. */
-#define TMS570_LIN_PIO4_RX_SET BSP_FLD32(1)
+#define TMS570_LIN_PIO4_RX_SET BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO5-----------------------*/
+/*----------------------TMS570_LIN_PIO5----------------------*/
/* field: TX_CLR - Transmit pin clear. */
-#define TMS570_LIN_PIO5_TX_CLR BSP_FLD32(2)
+#define TMS570_LIN_PIO5_TX_CLR BSP_BIT32(2)
/* field: RX_CLR - Receive pin clear. */
-#define TMS570_LIN_PIO5_RX_CLR BSP_FLD32(1)
+#define TMS570_LIN_PIO5_RX_CLR BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO6-----------------------*/
+/*----------------------TMS570_LIN_PIO6----------------------*/
/* field: TX_PDR - Transmit pin open drain enable. */
-#define TMS570_LIN_PIO6_TX_PDR BSP_FLD32(2)
+#define TMS570_LIN_PIO6_TX_PDR BSP_BIT32(2)
/* field: RX_PDR - Receive pin open drain enable. */
-#define TMS570_LIN_PIO6_RX_PDR BSP_FLD32(1)
+#define TMS570_LIN_PIO6_RX_PDR BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO7-----------------------*/
+/*----------------------TMS570_LIN_PIO7----------------------*/
/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
-#define TMS570_LIN_PIO7_TX_PD BSP_FLD32(2)
+#define TMS570_LIN_PIO7_TX_PD BSP_BIT32(2)
/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
-#define TMS570_LIN_PIO7_RX_PD BSP_FLD32(1)
+#define TMS570_LIN_PIO7_RX_PD BSP_BIT32(1)
-/*-----------------------TMS570_LINPIO8-----------------------*/
+/*----------------------TMS570_LIN_PIO8----------------------*/
/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
-#define TMS570_LIN_PIO8_TX_PSL BSP_FLD32(2)
+#define TMS570_LIN_PIO8_TX_PSL BSP_BIT32(2)
/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
-#define TMS570_LIN_PIO8_RX_PSL BSP_FLD32(1)
+#define TMS570_LIN_PIO8_RX_PSL BSP_BIT32(1)
-/*-----------------------TMS570_LINCOMP-----------------------*/
+/*----------------------TMS570_LIN_COMP----------------------*/
/* field: SDEL - 2-bit synch delimiter compare. These bits are effective in LIN mode only. */
#define TMS570_LIN_COMP_SDEL(val) BSP_FLD32(val,8, 9)
#define TMS570_LIN_COMP_SDEL_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -434,7 +434,7 @@ typedef struct{
#define TMS570_LIN_COMP_SBREAK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_LINRD0-----------------------*/
+/*-----------------------TMS570_LIN_RD0-----------------------*/
/* field: RD0 - Receive buffer 0. Byte 0 of the response data byte. */
#define TMS570_LIN_RD0_RD0(val) BSP_FLD32(val,24, 31)
#define TMS570_LIN_RD0_RD0_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -456,7 +456,7 @@ typedef struct{
#define TMS570_LIN_RD0_RD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_LINRD1-----------------------*/
+/*-----------------------TMS570_LIN_RD1-----------------------*/
/* field: RD4 - Receive buffer 4. Byte 4 of the response data byte. */
#define TMS570_LIN_RD1_RD4(val) BSP_FLD32(val,24, 31)
#define TMS570_LIN_RD1_RD4_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -478,7 +478,7 @@ typedef struct{
#define TMS570_LIN_RD1_RD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_LINMASK-----------------------*/
+/*----------------------TMS570_LIN_MASK----------------------*/
/* field: RX_ID_MASK - Receive ID mask. These bits are effective in LIN mode only. */
#define TMS570_LIN_MASK_RX_ID_MASK(val) BSP_FLD32(val,16, 23)
#define TMS570_LIN_MASK_RX_ID_MASK_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -490,7 +490,7 @@ typedef struct{
#define TMS570_LIN_MASK_TX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------------TMS570_LINID------------------------*/
+/*-----------------------TMS570_LIN_ID-----------------------*/
/* field: RECEIVED_ID - Received identification. These bits are effective in LIN mode only. */
#define TMS570_LIN_ID_RECEIVED_ID(val) BSP_FLD32(val,16, 23)
#define TMS570_LIN_ID_RECEIVED_ID_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -507,7 +507,7 @@ typedef struct{
#define TMS570_LIN_ID_ID_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_LINTD0-----------------------*/
+/*-----------------------TMS570_LIN_TD0-----------------------*/
/* field: TD0 - 8-Bit transmit buffer 0. */
#define TMS570_LIN_TD0_TD0(val) BSP_FLD32(val,24, 31)
#define TMS570_LIN_TD0_TD0_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -529,7 +529,7 @@ typedef struct{
#define TMS570_LIN_TD0_TD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_LINTD1-----------------------*/
+/*-----------------------TMS570_LIN_TD1-----------------------*/
/* field: TD4 - 8-Bit transmit buffer 4. */
#define TMS570_LIN_TD1_TD4(val) BSP_FLD32(val,24, 31)
#define TMS570_LIN_TD1_TD4_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -551,22 +551,22 @@ typedef struct{
#define TMS570_LIN_TD1_TD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_LINMBRSR----------------------*/
+/*----------------------TMS570_LIN_MBRSR----------------------*/
/* field: MBR - Maximum baud rate prescaler. This bit is effective in LIN mode only. */
#define TMS570_LIN_MBRSR_MBR(val) BSP_FLD32(val,0, 12)
#define TMS570_LIN_MBRSR_MBR_GET(reg) BSP_FLD32GET(reg,0, 12)
#define TMS570_LIN_MBRSR_MBR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
-/*--------------------TMS570_LINIODFTCTRL--------------------*/
+/*--------------------TMS570_LIN_IODFTCTRL--------------------*/
/* field: FEN - Frame error enable. This bit is used to create a frame error. */
-#define TMS570_LIN_IODFTCTRL_FEN BSP_FLD32(26)
+#define TMS570_LIN_IODFTCTRL_FEN BSP_BIT32(26)
/* field: PEN - Parity error enable. This bit is used to create a parity error. */
-#define TMS570_LIN_IODFTCTRL_PEN BSP_FLD32(25)
+#define TMS570_LIN_IODFTCTRL_PEN BSP_BIT32(25)
/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
-#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
/* field: PIN_SAMPLE_MASK - Pin sample mask. */
#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
@@ -584,11 +584,11 @@ typedef struct{
#define TMS570_LIN_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
-#define TMS570_LIN_IODFTCTRL_LPBENA BSP_FLD32(1)
+#define TMS570_LIN_IODFTCTRL_LPBENA BSP_BIT32(1)
/* field: RXPENA - Module analog loopback through receive pin enable. */
-#define TMS570_LIN_IODFTCTRL_RXPENA BSP_FLD32(0)
+#define TMS570_LIN_IODFTCTRL_RXPENA BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_LIN */
+#endif /* LIBBSP_ARM_TMS570_LIN */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
index 33ae386..704a0bc 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_MDIO
-#define LIBBSP_ARM_tms570_MDIO
+#ifndef LIBBSP_ARM_TMS570_MDIO
+#define LIBBSP_ARM_TMS570_MDIO
#include <bsp/utility.h>
@@ -61,19 +61,16 @@ typedef struct{
} tms570_mdio_t;
-/*----------------------TMS570_MDIOREVID----------------------*/
+/*---------------------TMS570_MDIO_REVID---------------------*/
/* field: REV - Identifies the MDIO Module revision. */
-#define TMS570_MDIO_REVID_REV(val) BSP_FLD32(val,0, 31)
-#define TMS570_MDIO_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_MDIOCONTROL---------------------*/
+/*--------------------TMS570_MDIO_CONTROL--------------------*/
/* field: IDLE - State machine IDLE status bit. */
-#define TMS570_MDIO_CONTROL_IDLE BSP_FLD32(31)
+#define TMS570_MDIO_CONTROL_IDLE BSP_BIT32(31)
/* field: ENABLE - State machine enable control bit. */
-#define TMS570_MDIO_CONTROL_ENABLE BSP_FLD32(30)
+#define TMS570_MDIO_CONTROL_ENABLE BSP_BIT32(30)
/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
@@ -81,13 +78,13 @@ typedef struct{
#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: PREAMBLE - Preamble disable */
-#define TMS570_MDIO_CONTROL_PREAMBLE BSP_FLD32(20)
+#define TMS570_MDIO_CONTROL_PREAMBLE BSP_BIT32(20)
/* field: FAULT - Fault indicator. */
-#define TMS570_MDIO_CONTROL_FAULT BSP_FLD32(19)
+#define TMS570_MDIO_CONTROL_FAULT BSP_BIT32(19)
/* field: FAULTENB - Fault detect enable. */
-#define TMS570_MDIO_CONTROL_FAULTENB BSP_FLD32(18)
+#define TMS570_MDIO_CONTROL_FAULTENB BSP_BIT32(18)
/* field: CLKDIV - Clock Divider bits. */
#define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
@@ -95,77 +92,71 @@ typedef struct{
#define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_MDIOALIVE----------------------*/
+/*---------------------TMS570_MDIO_ALIVE---------------------*/
/* field: ALIVE - MDIO Alive bits. */
-#define TMS570_MDIO_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
-#define TMS570_MDIO_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_MDIOLINK----------------------*/
+/*----------------------TMS570_MDIO_LINK----------------------*/
/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
-#define TMS570_MDIO_LINK_LINK(val) BSP_FLD32(val,0, 31)
-#define TMS570_MDIO_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_MDIO_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_MDIOLINKINTRAW-------------------*/
+/*-------------------TMS570_MDIO_LINKINTRAW-------------------*/
/* field: USERPHY1 - MDIO Link change event, raw value. */
-#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_FLD32(1)
+#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_BIT32(1)
/* field: USERPHY0 - MDIO Link change event, raw value. */
-#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_FLD32(0)
+#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_BIT32(0)
-/*------------------TMS570_MDIOLINKINTMASKED------------------*/
+/*-----------------TMS570_MDIO_LINKINTMASKED-----------------*/
/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
-#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
+#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_BIT32(1)
/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
-#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
+#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_BIT32(0)
-/*-------------------TMS570_MDIOUSERINTRAW-------------------*/
+/*-------------------TMS570_MDIO_USERINTRAW-------------------*/
/* field: USERACCESS1 - MDIO User command complete event bit. */
-#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO User command complete event bit. */
-#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_BIT32(0)
-/*------------------TMS570_MDIOUSERINTMASKED------------------*/
+/*-----------------TMS570_MDIO_USERINTMASKED-----------------*/
/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
-#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_BIT32(0)
-/*-----------------TMS570_MDIOUSERINTMASKSET-----------------*/
+/*-----------------TMS570_MDIO_USERINTMASKSET-----------------*/
/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
-#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
-#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_BIT32(0)
-/*----------------TMS570_MDIOUSERINTMASKCLEAR----------------*/
+/*----------------TMS570_MDIO_USERINTMASKCLEAR----------------*/
/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
-#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_BIT32(1)
/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
-#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_BIT32(0)
-/*-------------------TMS570_MDIOUSERACCESS0-------------------*/
+/*------------------TMS570_MDIO_USERACCESS0------------------*/
/* field: GO - Go bit. */
-#define TMS570_MDIO_USERACCESS0_GO BSP_FLD32(31)
+#define TMS570_MDIO_USERACCESS0_GO BSP_BIT32(31)
/* field: WRITE - Write enable bit. */
-#define TMS570_MDIO_USERACCESS0_WRITE BSP_FLD32(30)
+#define TMS570_MDIO_USERACCESS0_WRITE BSP_BIT32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_MDIO_USERACCESS0_ACK BSP_FLD32(29)
+#define TMS570_MDIO_USERACCESS0_ACK BSP_BIT32(29)
/* field: REGADR - Register address bits. */
#define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
@@ -183,12 +174,12 @@ typedef struct{
#define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_MDIOUSERPHYSEL0-------------------*/
+/*------------------TMS570_MDIO_USERPHYSEL0------------------*/
/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_FLD32(7)
+#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_BIT32(7)
/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
+#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_BIT32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -196,15 +187,15 @@ typedef struct{
#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*-------------------TMS570_MDIOUSERACCESS1-------------------*/
+/*------------------TMS570_MDIO_USERACCESS1------------------*/
/* field: GO - Go bit. */
-#define TMS570_MDIO_USERACCESS1_GO BSP_FLD32(31)
+#define TMS570_MDIO_USERACCESS1_GO BSP_BIT32(31)
/* field: WRITE - Write enable bit. */
-#define TMS570_MDIO_USERACCESS1_WRITE BSP_FLD32(30)
+#define TMS570_MDIO_USERACCESS1_WRITE BSP_BIT32(30)
/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
-#define TMS570_MDIO_USERACCESS1_ACK BSP_FLD32(29)
+#define TMS570_MDIO_USERACCESS1_ACK BSP_BIT32(29)
/* field: REGADR - Register address bits. */
#define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
@@ -222,12 +213,12 @@ typedef struct{
#define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_MDIOUSERPHYSEL1-------------------*/
+/*------------------TMS570_MDIO_USERPHYSEL1------------------*/
/* field: LINKSEL - Link status determination select bit. */
-#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_FLD32(7)
+#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_BIT32(7)
/* field: LINKINTENB - Link change interrupt enable. */
-#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
+#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_BIT32(6)
/* field: PHYADRMON - PHY address whose link status is to be monitored. */
#define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
@@ -236,4 +227,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_MDIO */
+#endif /* LIBBSP_ARM_TMS570_MDIO */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
index 1b3c870..06b8bbe 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_NHET
-#define LIBBSP_ARM_tms570_NHET
+#ifndef LIBBSP_ARM_TMS570_NHET
+#define LIBBSP_ARM_TMS570_NHET
#include <bsp/utility.h>
@@ -82,9 +82,9 @@ typedef struct{
} tms570_nhet_t;
-/*-----------------------TMS570_NHETGCR-----------------------*/
+/*----------------------TMS570_NHET_GCR----------------------*/
/* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */
-#define TMS570_NHET_GCR_HET_PIN_ENA BSP_FLD32(24)
+#define TMS570_NHET_GCR_HET_PIN_ENA BSP_BIT32(24)
/* field: MP - Master Priority */
#define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22)
@@ -92,16 +92,16 @@ typedef struct{
#define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22)
/* field: PPF - Protect Program Fields */
-#define TMS570_NHET_GCR_PPF BSP_FLD32(18)
+#define TMS570_NHET_GCR_PPF BSP_BIT32(18)
/* field: IS - Ignore Suspend */
-#define TMS570_NHET_GCR_IS BSP_FLD32(17)
+#define TMS570_NHET_GCR_IS BSP_BIT32(17)
/* field: CMS - Clk_master/slave */
-#define TMS570_NHET_GCR_CMS BSP_FLD32(16)
+#define TMS570_NHET_GCR_CMS BSP_BIT32(16)
-/*-----------------------TMS570_NHETPFR-----------------------*/
+/*----------------------TMS570_NHET_PFR----------------------*/
/* field: LRPFC - oop Resolution Pre-scale Factor Code */
#define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10)
#define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10)
@@ -113,125 +113,113 @@ typedef struct{
#define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*----------------------TMS570_NHETADDR----------------------*/
+/*----------------------TMS570_NHET_ADDR----------------------*/
/* field: HETADDR - N2HET Current Address */
#define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8)
#define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*----------------------TMS570_NHETOFF1----------------------*/
+/*----------------------TMS570_NHET_OFF1----------------------*/
/* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */
#define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5)
#define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*----------------------TMS570_NHETOFF2----------------------*/
+/*----------------------TMS570_NHET_OFF2----------------------*/
/* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */
#define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5)
#define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5)
#define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*---------------------TMS570_NHETINTENAS---------------------*/
+/*--------------------TMS570_NHET_INTENAS--------------------*/
/* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */
-#define TMS570_NHET_INTENAS_HETINTENAS(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_INTENAS_HETINTENAS_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_INTENAS_HETINTENAS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_NHETINTENAC---------------------*/
+/*--------------------TMS570_NHET_INTENAC--------------------*/
/* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */
-#define TMS570_NHET_INTENAC_HETINTENAC(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_INTENAC_HETINTENAC_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_INTENAC_HETINTENAC_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_NHETEXC1----------------------*/
+/*----------------------TMS570_NHET_EXC1----------------------*/
/* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */
-#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_FLD32(24)
+#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_BIT32(24)
/* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */
-#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_FLD32(16)
+#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_BIT32(16)
/* field: PRGM_OVRFL_ENA - Program Overflow Enable */
-#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_FLD32(8)
+#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_BIT32(8)
/* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_FLD32(2)
+#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_BIT32(2)
/* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_FLD32(1)
+#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_BIT32(1)
/* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */
-#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_FLD32(0)
+#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_BIT32(0)
-/*----------------------TMS570_NHETEXC2----------------------*/
+/*----------------------TMS570_NHET_EXC2----------------------*/
/* field: DEBUG_STATUS_FLAG - Debug Status Flag. */
-#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_FLD32(8)
+#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_BIT32(8)
/* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */
-#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_FLD32(2)
+#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_BIT32(2)
/* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */
-#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_FLD32(1)
+#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_BIT32(1)
/* field: PRGM_OVERFL_FLAG - Program Overflow Flag */
-#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_FLD32(0)
+#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_BIT32(0)
-/*-----------------------TMS570_NHETPRY-----------------------*/
+/*----------------------TMS570_NHET_PRY----------------------*/
/* field: HETPRY - HET Interrupt Priority Level bits */
-#define TMS570_NHET_PRY_HETPRY(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PRY_HETPRY_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PRY_HETPRY_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_NHETFLG-----------------------*/
+/*----------------------TMS570_NHET_FLG----------------------*/
/* field: HETFLAG - Interrupt Flag Register Bits */
-#define TMS570_NHET_FLG_HETFLAG(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_FLG_HETFLAG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_FLG_HETFLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_NHETAND-----------------------*/
+/*----------------------TMS570_NHET_AND----------------------*/
/* field: AND_SHARE - AND Share Enable */
#define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_NHETHRSH----------------------*/
+/*----------------------TMS570_NHET_HRSH----------------------*/
/* field: HR_SHARE - HR Share Bits */
#define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_NHETXOR-----------------------*/
+/*----------------------TMS570_NHET_XOR----------------------*/
/* field: XOR_SHARE - XOR Share Enable */
#define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15)
#define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_NHETREQENS---------------------*/
+/*---------------------TMS570_NHET_REQENS---------------------*/
/* field: REQ_ENA_n - Request Enable Bits */
#define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7)
#define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_NHETREQENC---------------------*/
+/*---------------------TMS570_NHET_REQENC---------------------*/
/* field: REQ_DIS_n - Request Disable Bits */
#define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7)
#define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_NHETREQDS----------------------*/
+/*---------------------TMS570_NHET_REQDS---------------------*/
/* field: TDBS_n - HTU, DMA or Both Select Bits */
#define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23)
#define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23)
@@ -243,65 +231,41 @@ typedef struct{
#define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_NHETDIR-----------------------*/
+/*----------------------TMS570_NHET_DIR----------------------*/
/* field: HETDIR_n - Data direction of NHET pins */
-#define TMS570_NHET_DIR_HETDIR_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_DIR_HETDIR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DIR_HETDIR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_NHETDIN-----------------------*/
+/*----------------------TMS570_NHET_DIN----------------------*/
/* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */
-#define TMS570_NHET_DIN_HETDIN_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_DIN_HETDIN_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DIN_HETDIN_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_NHETDOUT----------------------*/
+/*----------------------TMS570_NHET_DOUT----------------------*/
/* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */
-#define TMS570_NHET_DOUT_HETDOUT_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_DOUT_HETDOUT_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DOUT_HETDOUT_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_NHETDSET----------------------*/
+/*----------------------TMS570_NHET_DSET----------------------*/
/* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */
-#define TMS570_NHET_DSET_HETDSET_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_DSET_HETDSET_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DSET_HETDSET_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_NHETDCLR----------------------*/
+/*----------------------TMS570_NHET_DCLR----------------------*/
/* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */
-#define TMS570_NHET_DCLR_HETDCLR_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_DCLR_HETDCLR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_DCLR_HETDCLR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_NHETPDR-----------------------*/
+/*----------------------TMS570_NHET_PDR----------------------*/
/* field: HETPDR_n - Open drain control for HET[n] pins */
-#define TMS570_NHET_PDR_HETPDR_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PDR_HETPDR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PDR_HETPDR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_NHETPULDIS---------------------*/
+/*---------------------TMS570_NHET_PULDIS---------------------*/
/* field: HETPULDIS_n - Pull disable for N2HET pins */
-#define TMS570_NHET_PULDIS_HETPULDIS_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PULDIS_HETPULDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PULDIS_HETPULDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_NHETPSL-----------------------*/
+/*----------------------TMS570_NHET_PSL----------------------*/
/* field: HETPSL_n - Pull select for NHET pins */
-#define TMS570_NHET_PSL_HETPSL_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PSL_HETPSL_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PSL_HETPSL_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_NHETPCR-----------------------*/
+/*----------------------TMS570_NHET_PCR----------------------*/
/* field: TEST - Test Bit. */
-#define TMS570_NHET_PCR_TEST BSP_FLD32(8)
+#define TMS570_NHET_PCR_TEST BSP_BIT32(8)
/* field: PARITY_ENA - Enable/disable parity checking. */
#define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
@@ -309,21 +273,18 @@ typedef struct{
#define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_NHETPAR-----------------------*/
+/*----------------------TMS570_NHET_PAR----------------------*/
/* field: PAOFF - Parity Error Address Offset. */
#define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12)
#define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12)
#define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12)
-/*-----------------------TMS570_NHETPPR-----------------------*/
+/*----------------------TMS570_NHET_PPR----------------------*/
/* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */
-#define TMS570_NHET_PPR_HETPPR_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PPR_HETPPR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PPR_HETPPR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_NHETSFPRLD---------------------*/
+/*---------------------TMS570_NHET_SFPRLD---------------------*/
/* field: CCDIV - Counter Clock Divider */
#define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17)
#define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17)
@@ -335,14 +296,11 @@ typedef struct{
#define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*----------------------TMS570_NHETSFENA----------------------*/
+/*---------------------TMS570_NHET_SFENA---------------------*/
/* field: HETSFENA_n - Suppression Filter Enable Bits */
-#define TMS570_NHET_SFENA_HETSFENA_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_SFENA_HETSFENA_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_SFENA_HETSFENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_NHETLBPSEL---------------------*/
+/*---------------------TMS570_NHET_LBPSEL---------------------*/
/* field: LBPTYPE - Loop Back Pair Type Select Bits */
#define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31)
#define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -354,7 +312,7 @@ typedef struct{
#define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_NHETLBPDIR---------------------*/
+/*---------------------TMS570_NHET_LBPDIR---------------------*/
/* field: LBPTSTENA - Loopback Test Enable Key */
#define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19)
#define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -366,12 +324,9 @@ typedef struct{
#define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_NHETPINDIS---------------------*/
+/*---------------------TMS570_NHET_PINDIS---------------------*/
/* field: HETPINDIS_n - N2HET Pin Disable Bits */
-#define TMS570_NHET_PINDIS_HETPINDIS_n(val) BSP_FLD32(val,0, 31)
-#define TMS570_NHET_PINDIS_HETPINDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_NHET_PINDIS_HETPINDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_NHET */
+#endif /* LIBBSP_ARM_TMS570_NHET */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
index 9c7441e..2c5ed29 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_PBIST
-#define LIBBSP_ARM_tms570_PBIST
+#ifndef LIBBSP_ARM_TMS570_PBIST
+#define LIBBSP_ARM_TMS570_PBIST
#include <bsp/utility.h>
@@ -67,14 +67,11 @@ typedef struct{
} tms570_pbist_t;
-/*----------------------TMS570_PBISTDNW----------------------*/
+/*----------------------TMS570_PBIST_DNW----------------------*/
/* field: Reserved - Do not write */
-#define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_PBISTRAMT----------------------*/
+/*---------------------TMS570_PBIST_RAMT---------------------*/
/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -106,108 +103,93 @@ typedef struct{
#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*----------------------TMS570_PBISTDLR----------------------*/
+/*----------------------TMS570_PBIST_DLR----------------------*/
/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
-#define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4)
+#define TMS570_PBIST_DLR_DLR4 BSP_BIT32(4)
/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
-#define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2)
+#define TMS570_PBIST_DLR_DLR2 BSP_BIT32(2)
-/*----------------------TMS570_PBISTPACT----------------------*/
+/*---------------------TMS570_PBIST_PACT---------------------*/
/* field: PACT1 - PBIST Activate */
-#define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1)
+#define TMS570_PBIST_PACT_PACT1 BSP_BIT32(1)
/* field: PACT0 - ROM Clock Enable Register */
-#define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0)
+#define TMS570_PBIST_PACT_PACT0 BSP_BIT32(0)
-/*--------------------TMS570_PBISTPBISTID--------------------*/
+/*--------------------TMS570_PBIST_PBISTID--------------------*/
/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_PBISTOVER----------------------*/
+/*---------------------TMS570_PBIST_OVER---------------------*/
/* field: OVER0 - RINFO Override Bit */
-#define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0)
+#define TMS570_PBIST_OVER_OVER0 BSP_BIT32(0)
-/*---------------------TMS570_PBISTFSRF0---------------------*/
+/*---------------------TMS570_PBIST_FSRF0---------------------*/
/* field: FSRF0 - Fail Status 0. */
-#define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0)
+#define TMS570_PBIST_FSRF0_FSRF0 BSP_BIT32(0)
-/*---------------------TMS570_PBISTFSRC0---------------------*/
+/*---------------------TMS570_PBIST_FSRC0---------------------*/
/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_PBISTFSRC1---------------------*/
+/*---------------------TMS570_PBIST_FSRC1---------------------*/
/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_PBISTFSRA0---------------------*/
+/*---------------------TMS570_PBIST_FSRA0---------------------*/
/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_PBISTFSRA1---------------------*/
+/*---------------------TMS570_PBIST_FSRA1---------------------*/
/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_PBISTFSRDL0---------------------*/
+/*--------------------TMS570_PBIST_FSRDL0--------------------*/
/* field: FSRDL1 - Failure data on port 1 */
-#define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_PBISTFSRDL1---------------------*/
+/*--------------------TMS570_PBIST_FSRDL1--------------------*/
/* field: FSRDL1 - Failure data on port 1 */
-#define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_PBISTROM----------------------*/
+/*----------------------TMS570_PBIST_ROM----------------------*/
/* field: ROM - ROM Mask */
#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*----------------------TMS570_PBISTALGO----------------------*/
+/*---------------------TMS570_PBIST_ALGO---------------------*/
/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_PBISTRINFOL---------------------*/
+/*--------------------TMS570_PBIST_RINFOL--------------------*/
/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_PBISTRINFOUL--------------------*/
+/*--------------------TMS570_PBIST_RINFOUL--------------------*/
/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31)
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_PBIST */
+#endif /* LIBBSP_ARM_TMS570_PBIST */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
index 99c5ac7..4d5613a 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_PCR
-#define LIBBSP_ARM_tms570_PCR
+#ifndef LIBBSP_ARM_TMS570_PCR
+#define LIBBSP_ARM_TMS570_PCR
#include <bsp/utility.h>
@@ -76,75 +76,45 @@ typedef struct{
} tms570_pcr_t;
-/*--------------------TMS570_PCRPMPROTSET0--------------------*/
+/*-------------------TMS570_PCR_PMPROTSET0-------------------*/
/* field: PCSPROTSET - Peripheral memory frame protection set. */
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTSET0_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_PCRPMPROTSET1--------------------*/
+/*-------------------TMS570_PCR_PMPROTSET1-------------------*/
/* field: PCSPROTSET - Peripheral memory frame protection set. */
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTSET1_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_PCRPMPROTCLR0--------------------*/
+/*-------------------TMS570_PCR_PMPROTCLR0-------------------*/
/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_PCRPMPROTCLR1--------------------*/
+/*-------------------TMS570_PCR_PMPROTCLR1-------------------*/
/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_PCRPPROTSET0--------------------*/
+/*--------------------TMS570_PCR_PPROTSETx--------------------*/
/* field: PROTSET - Peripheral select quadrant protection set. */
-#define TMS570_PCR_PPROTSET0_PROTSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PPROTSET0_PROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PPROTSET0_PROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_PCRPPROTCLR0--------------------*/
+/*--------------------TMS570_PCR_PPROTCLRx--------------------*/
/* field: PROTCLR - Peripheral select quadrant protection clear. */
-#define TMS570_PCR_PPROTCLR0_PROTCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PPROTCLR0_PROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PPROTCLR0_PROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_PCRPCSPWRDWNSET0------------------*/
+/*------------------TMS570_PCR_PCSPWRDWNSETx------------------*/
/* field: PWRDNSET - Peripheral memory clock power-down set. */
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_PCRPCSPWRDWNCLR0------------------*/
+/*------------------TMS570_PCR_PCSPWRDWNCLRx------------------*/
/* field: PWRDNCLR - Peripheral memory clock power-down clear. */
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_PCRPSPWRDWNSET0-------------------*/
+/*------------------TMS570_PCR_PSPWRDWNSETx------------------*/
/* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-------------------TMS570_PCRPSPWRDWNCLR0-------------------*/
+/*------------------TMS570_PCR_PSPWRDWNCLRx------------------*/
/* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_PCR */
+#endif /* LIBBSP_ARM_TMS570_PCR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
index b56ed4e..1cb8b03 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_PLL
-#define LIBBSP_ARM_tms570_PLL
+#ifndef LIBBSP_ARM_TMS570_PLL
+#define LIBBSP_ARM_TMS570_PLL
#include <bsp/utility.h>
@@ -67,7 +67,7 @@ typedef struct{
} tms570_pll_t;
-/*---------------------TMS570_PLLPLLCTL3---------------------*/
+/*---------------------TMS570_PLL_PLLCTL3---------------------*/
/* field: ODPLL2 - Internal PLL Output Divider */
#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -89,7 +89,7 @@ typedef struct{
#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_PLLCLKSLIP---------------------*/
+/*---------------------TMS570_PLL_CLKSLIP---------------------*/
/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
@@ -101,20 +101,20 @@ typedef struct{
#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_PLLSSWPLL1---------------------*/
+/*---------------------TMS570_PLL_SSWPLL1---------------------*/
/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: COUNTER_READ_READY - Counter read ready. */
-#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_FLD32(6)
+#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_BIT32(6)
/* field: COUNTER_RESET - Counter reset. */
-#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_FLD32(5)
+#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_BIT32(5)
/* field: COUNTER_EN - Counter enable. */
-#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_FLD32(4)
+#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_BIT32(4)
/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
@@ -122,24 +122,18 @@ typedef struct{
#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
-#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_FLD32(0)
+#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_BIT32(0)
-/*---------------------TMS570_PLLSSWPLL2---------------------*/
+/*---------------------TMS570_PLL_SSWPLL2---------------------*/
/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_PLLSSWPLL3---------------------*/
+/*---------------------TMS570_PLL_SSWPLL3---------------------*/
/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_PLLCSDIS----------------------*/
+/*----------------------TMS570_PLL_CSDIS----------------------*/
/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -151,7 +145,7 @@ typedef struct{
#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_PLLCSDISSET---------------------*/
+/*--------------------TMS570_PLL_CSDISSET--------------------*/
/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -163,7 +157,7 @@ typedef struct{
#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_PLLCSDISCLR---------------------*/
+/*--------------------TMS570_PLL_CSDISCLR--------------------*/
/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -175,7 +169,7 @@ typedef struct{
#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_PLLCSVSTAT---------------------*/
+/*---------------------TMS570_PLL_CSVSTAT---------------------*/
/* field: CLKSR_7_3V - Clock source[7-0] valid. */
#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -187,9 +181,9 @@ typedef struct{
#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_PLLPLLCTL1---------------------*/
+/*---------------------TMS570_PLL_PLLCTL1---------------------*/
/* field: ROS - Reset on PLL Slip */
-#define TMS570_PLL_PLLCTL1_ROS BSP_FLD32(31)
+#define TMS570_PLL_PLLCTL1_ROS BSP_BIT32(31)
/* field: MASK_SLIP - Mask detection of PLL slip */
#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
@@ -202,7 +196,7 @@ typedef struct{
#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: ROF - Reset on Oscillator Fail */
-#define TMS570_PLL_PLLCTL1_ROF BSP_FLD32(23)
+#define TMS570_PLL_PLLCTL1_ROF BSP_BIT32(23)
/* field: REFCLKDIV - Reference Clock Divider */
#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
@@ -215,9 +209,9 @@ typedef struct{
#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_PLLPLLCTL2---------------------*/
+/*---------------------TMS570_PLL_PLLCTL2---------------------*/
/* field: FMENA - Frequency Modulation Enable. */
-#define TMS570_PLL_PLLCTL2_FMENA BSP_FLD32(31)
+#define TMS570_PLL_PLLCTL2_FMENA BSP_BIT32(31)
/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
@@ -240,12 +234,12 @@ typedef struct{
#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*--------------------TMS570_PLLLPOMONCTL--------------------*/
+/*--------------------TMS570_PLL_LPOMONCTL--------------------*/
/* field: BIAS_ENABLE - Bias enable. */
-#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
-#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
/* field: HFTRIM - High frequency oscillator trim value. */
#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
@@ -253,15 +247,15 @@ typedef struct{
#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
-/*---------------------TMS570_PLLCLKTEST---------------------*/
+/*---------------------TMS570_PLL_CLKTEST---------------------*/
/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
-#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
/* field: RANGEDETCTRL - Range detection control. */
-#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
-#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
@@ -269,9 +263,9 @@ typedef struct{
#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
-/*----------------------TMS570_PLLGPREG1----------------------*/
+/*---------------------TMS570_PLL_GPREG1---------------------*/
/* field: EMIF_FUNC - Enable EMIF functions to be output. */
-#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_FLD32(31)
+#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_BIT32(31)
/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
@@ -289,16 +283,16 @@ typedef struct{
#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_PLLGLBSTAT---------------------*/
+/*---------------------TMS570_PLL_GLBSTAT---------------------*/
/* field: FBSLIP - PLL over cycle slip detection. */
-#define TMS570_PLL_GLBSTAT_FBSLIP BSP_FLD32(9)
+#define TMS570_PLL_GLBSTAT_FBSLIP BSP_BIT32(9)
/* field: RFSLIP - PLL under cycle slip detection. */
-#define TMS570_PLL_GLBSTAT_RFSLIP BSP_FLD32(8)
+#define TMS570_PLL_GLBSTAT_RFSLIP BSP_BIT32(8)
/* field: OSCFAIL - Oscillator fail flag bit. */
-#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_FLD32(0)
+#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_PLL */
+#endif /* LIBBSP_ARM_TMS570_PLL */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
index 5f70db2..c834b83 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_PMM
-#define LIBBSP_ARM_tms570_PMM
+#ifndef LIBBSP_ARM_TMS570_PMM
+#define LIBBSP_ARM_TMS570_PMM
#include <bsp/utility.h>
@@ -66,7 +66,7 @@ typedef struct{
} tms570_pmm_t;
-/*-----------------TMS570_PMMLOGICPDPWRCTRL0-----------------*/
+/*-----------------TMS570_PMM_LOGICPDPWRCTRL0-----------------*/
/* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27)
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -88,7 +88,7 @@ typedef struct{
#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_PMMMEMPDPWRCTRL0------------------*/
+/*------------------TMS570_PMM_MEMPDPWRCTRL0------------------*/
/* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27)
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -105,57 +105,57 @@ typedef struct{
#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
-/*-------------------TMS570_PMMPDCLKDISREG-------------------*/
+/*-------------------TMS570_PMM_PDCLKDISREG-------------------*/
/* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_BIT32(3)
/* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_BIT32(2)
/* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_BIT32(1)
/* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
-#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_BIT32(0)
-/*------------------TMS570_PMMPDCLKDISSETREG------------------*/
+/*-----------------TMS570_PMM_PDCLKDISSETREG-----------------*/
/* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_BIT32(3)
/* field: PDCLK_DISSET_2 - Privileged Mode only. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_BIT32(2)
/* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_BIT32(1)
/* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */
-#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_BIT32(0)
-/*------------------TMS570_PMMPDCLKDISCLRREG------------------*/
+/*-----------------TMS570_PMM_PDCLKDISCLRREG-----------------*/
/* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_FLD32(3)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_BIT32(3)
/* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_FLD32(2)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_BIT32(2)
/* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_FLD32(1)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_BIT32(1)
/* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
-#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_FLD32(0)
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_BIT32(0)
-/*------------------TMS570_PMMLOGICPDPWRSTAT------------------*/
+/*-----------------TMS570_PMM_LOGICPDPWRSTAT-----------------*/
/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24)
/* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16)
/* field: DOMAIN_ON0 - Current state of power domain PD2. */
-#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8)
/* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */
#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
@@ -163,15 +163,15 @@ typedef struct{
#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*-------------------TMS570_PMMMEMPDPWRSTAT-------------------*/
+/*------------------TMS570_PMM_MEMPDPWRSTAT------------------*/
/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_BIT32(24)
/* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_BIT32(16)
/* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */
-#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_BIT32(8)
/* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */
#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
@@ -179,27 +179,27 @@ typedef struct{
#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*-------------------TMS570_PMMGLOBALCTRL1-------------------*/
+/*-------------------TMS570_PMM_GLOBALCTRL1-------------------*/
/* field: PMCTRL_PWRDN - PMC/PSCON Power Down */
-#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_FLD32(8)
+#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_BIT32(8)
/* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */
-#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_FLD32(0)
+#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_BIT32(0)
-/*--------------------TMS570_PMMGLOBALSTAT--------------------*/
+/*-------------------TMS570_PMM_GLOBALSTAT-------------------*/
/* field: PMCTRL_IDLE - State of PMC and all PSCONs. */
-#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_FLD32(0)
+#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_BIT32(0)
-/*--------------------TMS570_PMMPRCKEYREG--------------------*/
+/*--------------------TMS570_PMM_PRCKEYREG--------------------*/
/* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */
#define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_PMMLPDDCSTAT1--------------------*/
+/*-------------------TMS570_PMM_LPDDCSTAT1-------------------*/
/* field: LCMPE - Logic Power Domain Compare Error */
#define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -211,7 +211,7 @@ typedef struct{
#define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_PMMLPDDCSTAT2--------------------*/
+/*-------------------TMS570_PMM_LPDDCSTAT2-------------------*/
/* field: LSTET - Logic Power Domain Self-test Error Type */
#define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19)
#define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19)
@@ -223,7 +223,7 @@ typedef struct{
#define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_PMMMPDDCSTAT1--------------------*/
+/*-------------------TMS570_PMM_MPDDCSTAT1-------------------*/
/* field: MCMPE - Memory Power Domain Compare Error */
#define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18)
#define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18)
@@ -235,7 +235,7 @@ typedef struct{
#define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*--------------------TMS570_PMMMPDDCSTAT2--------------------*/
+/*-------------------TMS570_PMM_MPDDCSTAT2-------------------*/
/* field: MSTET - Memory Power Domain Self-test Error Type */
#define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18)
#define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18)
@@ -247,7 +247,7 @@ typedef struct{
#define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-------------------TMS570_PMMISODIAGSTAT-------------------*/
+/*-------------------TMS570_PMM_ISODIAGSTAT-------------------*/
/* field: ISO_DIAG - Isolation Diagnostic */
#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3)
#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -255,4 +255,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_PMM */
+#endif /* LIBBSP_ARM_TMS570_PMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
index d6616c6..1a4df19 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_POM
-#define LIBBSP_ARM_tms570_POM
+#ifndef LIBBSP_ARM_TMS570_POM
+#define LIBBSP_ARM_TMS570_POM
#include <bsp/utility.h>
@@ -82,28 +82,28 @@ typedef struct{
} tms570_pom_t;
-/*--------------------TMS570_POMPROGSTART--------------------*/
+/*--------------------TMS570_POM_PROGSTART--------------------*/
/* field: STARTADDRESS - Defines the start address of the program memory region. */
#define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
#define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
#define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
-/*---------------------TMS570_POMOVLSTART---------------------*/
+/*--------------------TMS570_POM_OVLSTART--------------------*/
/* field: STARTADDRESS - Defines the start address of the overlay memory region. */
#define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
#define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
#define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
-/*---------------------TMS570_POMREGSIZE---------------------*/
+/*---------------------TMS570_POM_REGSIZE---------------------*/
/* field: SIZE - Region size */
#define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3)
#define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_POMGLBCTRL---------------------*/
+/*---------------------TMS570_POM_GLBCTRL---------------------*/
/* field: OTADDR - Overlay target Address. */
#define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31)
#define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31)
@@ -120,7 +120,7 @@ typedef struct{
#define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------------TMS570_POMREV-----------------------*/
+/*-----------------------TMS570_POM_REV-----------------------*/
/* field: SCHEME - Used to distinguish between different ID schemes. */
#define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31)
#define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
@@ -152,68 +152,53 @@ typedef struct{
#define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*---------------------TMS570_POMCLKCTRL---------------------*/
+/*---------------------TMS570_POM_CLKCTRL---------------------*/
/* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */
-#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_FLD32(0)
+#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_BIT32(0)
-/*-----------------------TMS570_POMFLG-----------------------*/
+/*-----------------------TMS570_POM_FLG-----------------------*/
/* field: TO - Timeout. */
-#define TMS570_POM_FLG_TO BSP_FLD32(0)
+#define TMS570_POM_FLG_TO BSP_BIT32(0)
-/*----------------------TMS570_POMITCTRL----------------------*/
+/*---------------------TMS570_POM_ITCTRL---------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_ITCTRL_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_ITCTRL_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_ITCTRL_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_POMCLAIMSET---------------------*/
+/*--------------------TMS570_POM_CLAIMSET--------------------*/
/* field: SET1 - The module is claimed */
-#define TMS570_POM_CLAIMSET_SET1 BSP_FLD32(1)
+#define TMS570_POM_CLAIMSET_SET1 BSP_BIT32(1)
/* field: SET0 - The module is claimed */
-#define TMS570_POM_CLAIMSET_SET0 BSP_FLD32(0)
+#define TMS570_POM_CLAIMSET_SET0 BSP_BIT32(0)
-/*---------------------TMS570_POMCLAIMCLR---------------------*/
+/*--------------------TMS570_POM_CLAIMCLR--------------------*/
/* field: CLR1 - The module is claimed */
-#define TMS570_POM_CLAIMCLR_CLR1 BSP_FLD32(1)
+#define TMS570_POM_CLAIMCLR_CLR1 BSP_BIT32(1)
/* field: CLR0 - The module is claimed */
-#define TMS570_POM_CLAIMCLR_CLR0 BSP_FLD32(0)
+#define TMS570_POM_CLAIMCLR_CLR0 BSP_BIT32(0)
-/*--------------------TMS570_POMLOCKACCESS--------------------*/
+/*-------------------TMS570_POM_LOCKACCESS-------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_LOCKACCESS_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_LOCKACCESS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_LOCKACCESS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_POMLOCKSTATUS--------------------*/
+/*-------------------TMS570_POM_LOCKSTATUS-------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_LOCKSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_LOCKSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_LOCKSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_POMAUTHSTATUS--------------------*/
+/*-------------------TMS570_POM_AUTHSTATUS-------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_AUTHSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_AUTHSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_AUTHSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_POMDEVID----------------------*/
+/*----------------------TMS570_POM_DEVID----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_DEVID_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_DEVID_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_DEVID_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_POMDEVTYPE---------------------*/
+/*---------------------TMS570_POM_DEVTYPE---------------------*/
/* field: Sub_Type - Other */
#define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -225,7 +210,7 @@ typedef struct{
#define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_POMPERIPHERALID4------------------*/
+/*------------------TMS570_POM_PERIPHERALID4------------------*/
/* field: 4KB_Count - Only 4KB implemented */
#define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -237,35 +222,26 @@ typedef struct{
#define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_POMPERIPHERALID5------------------*/
+/*------------------TMS570_POM_PERIPHERALID5------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID5_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_PERIPHERALID5_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID5_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_POMPERIPHERALID6------------------*/
+/*------------------TMS570_POM_PERIPHERALID6------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID6_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_PERIPHERALID6_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID6_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_POMPERIPHERALID7------------------*/
+/*------------------TMS570_POM_PERIPHERALID7------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID7_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_PERIPHERALID7_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID7_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_POMPERIPHERALID0------------------*/
+/*------------------TMS570_POM_PERIPHERALID0------------------*/
/* field: Part_Number - Reads 0, since POMREV defines the module */
#define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------TMS570_POMPERIPHERALID1------------------*/
+/*------------------TMS570_POM_PERIPHERALID1------------------*/
/* field: JEP106_Identity - Part of TI JEDEC number */
#define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -277,14 +253,14 @@ typedef struct{
#define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_POMPERIPHERALID2------------------*/
+/*------------------TMS570_POM_PERIPHERALID2------------------*/
/* field: Revision - Reads 0, since POMREV defines the module */
#define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7)
#define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
/* field: JEDEC - Indicates JEDEC assigned value */
-#define TMS570_POM_PERIPHERALID2_JEDEC BSP_FLD32(3)
+#define TMS570_POM_PERIPHERALID2_JEDEC BSP_BIT32(3)
/* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */
#define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2)
@@ -292,21 +268,18 @@ typedef struct{
#define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*------------------TMS570_POMPERIPHERALID3------------------*/
+/*------------------TMS570_POM_PERIPHERALID3------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
-#define TMS570_POM_PERIPHERALID3_Reserved(val) BSP_FLD32(val,0, 31)
-#define TMS570_POM_PERIPHERALID3_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_POM_PERIPHERALID3_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_POMCOMPONENTID0-------------------*/
+/*------------------TMS570_POM_COMPONENTID0------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_POMCOMPONENTID1-------------------*/
+/*------------------TMS570_POM_COMPONENTID1------------------*/
/* field: Component_Class - CoreSight Component */
#define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7)
#define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7)
@@ -318,14 +291,14 @@ typedef struct{
#define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_POMCOMPONENTID2-------------------*/
+/*------------------TMS570_POM_COMPONENTID2------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-------------------TMS570_POMCOMPONENTID3-------------------*/
+/*------------------TMS570_POM_COMPONENTID3------------------*/
/* field: Preamble - Preamble */
#define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7)
#define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
@@ -333,4 +306,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_POM */
+#endif /* LIBBSP_ARM_TMS570_POM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
index b6ebe49..029b3b5 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_RTI
-#define LIBBSP_ARM_tms570_RTI
+#ifndef LIBBSP_ARM_TMS570_RTI
+#define LIBBSP_ARM_TMS570_RTI
#include <bsp/utility.h>
@@ -85,275 +85,239 @@ typedef struct{
} tms570_rti_t;
-/*----------------------TMS570_RTICOMPx----------------------*/
+/*----------------------TMS570_RTI_COMPx----------------------*/
/* field: COMPx - Compare x. */
-#define TMS570_RTI_COMPx_COMPx(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_COMPx_COMPx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMPx_COMPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_RTIUDCPx----------------------*/
+/*----------------------TMS570_RTI_UDCPx----------------------*/
/* field: UDCPx - Update compare x. */
-#define TMS570_RTI_UDCPx_UDCPx(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_UDCPx_UDCPx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_UDCPx_UDCPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-----------------------TMS570_RTIFRCx-----------------------*/
+/*----------------------TMS570_RTI_FRCx----------------------*/
/* field: FRC0 - FRC0 */
-#define TMS570_RTI_FRCx_FRC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_FRCx_FRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_FRCx_FRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_RTIUCx-----------------------*/
+/*-----------------------TMS570_RTI_UCx-----------------------*/
/* field: UC0 - Up counter 0. */
-#define TMS570_RTI_UCx_UC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_UCx_UC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_UCx_UC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_RTICPUCx----------------------*/
+/*----------------------TMS570_RTI_CPUCx----------------------*/
/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
-#define TMS570_RTI_CPUCx_CPUC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_CPUCx_CPUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CPUCx_CPUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*----------------------TMS570_RTICAFRCx----------------------*/
+/*---------------------TMS570_RTI_CAFRCx---------------------*/
/* field: CAFRC0 - Capture free running counter 0. */
-#define TMS570_RTI_CAFRCx_CAFRC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_CAFRCx_CAFRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CAFRCx_CAFRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_RTICAUCx----------------------*/
+/*----------------------TMS570_RTI_CAUCx----------------------*/
/* field: CAUC0 - Capture up counter 0. */
-#define TMS570_RTI_CAUCx_CAUC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_CAUCx_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_CAUCx_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_RTIrsvd-----------------------*/
+/*----------------------TMS570_RTI_rsvd----------------------*/
/* field: CAUC0 - Capture up counter 0. */
-#define TMS570_RTI_rsvd_CAUC0(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_rsvd_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_rsvd_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_RTIGCTRL----------------------*/
+/*----------------------TMS570_RTI_GCTRL----------------------*/
/* field: NTUSEL - Select NTU signal. */
#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: COS - Continue on suspend. */
-#define TMS570_RTI_GCTRL_COS BSP_FLD32(15)
+#define TMS570_RTI_GCTRL_COS BSP_BIT32(15)
/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
-#define TMS570_RTI_GCTRL_CNT1EN BSP_FLD32(1)
+#define TMS570_RTI_GCTRL_CNT1EN BSP_BIT32(1)
/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
-#define TMS570_RTI_GCTRL_CNT0EN BSP_FLD32(0)
+#define TMS570_RTI_GCTRL_CNT0EN BSP_BIT32(0)
-/*----------------------TMS570_RTITBCTRL----------------------*/
+/*---------------------TMS570_RTI_TBCTRL---------------------*/
/* field: INC - Increment free running counter 0. */
-#define TMS570_RTI_TBCTRL_INC BSP_FLD32(1)
+#define TMS570_RTI_TBCTRL_INC BSP_BIT32(1)
/* field: TBEXT - Timebase external. */
-#define TMS570_RTI_TBCTRL_TBEXT BSP_FLD32(0)
+#define TMS570_RTI_TBCTRL_TBEXT BSP_BIT32(0)
-/*---------------------TMS570_RTICAPCTRL---------------------*/
+/*---------------------TMS570_RTI_CAPCTRL---------------------*/
/* field: CAPCNTR1 - Capture counter 1. */
-#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_FLD32(1)
+#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_BIT32(1)
/* field: CAPCNTR0 - Capture counter 0. */
-#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_FLD32(0)
+#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_BIT32(0)
-/*---------------------TMS570_RTICOMPCTRL---------------------*/
+/*--------------------TMS570_RTI_COMPCTRL--------------------*/
/* field: COMPSEL3 - Compare select 3. */
-#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_FLD32(12)
+#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_BIT32(12)
/* field: COMPSEL2 - Compare select 2. */
-#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_FLD32(8)
+#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_BIT32(8)
/* field: COMPSEL1 - Compare select 1. */
-#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_FLD32(4)
+#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_BIT32(4)
/* field: COMPSEL0 - Compare select 0. */
-#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_FLD32(0)
+#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_BIT32(0)
-/*---------------------TMS570_RTITBLCOMP---------------------*/
+/*---------------------TMS570_RTI_TBLCOMP---------------------*/
/* field: TBLCOMP - Timebase low compare value. */
-#define TMS570_RTI_TBLCOMP_TBLCOMP(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_TBLCOMP_TBLCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_TBLCOMP_TBLCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_RTITBHCOMP---------------------*/
+/*---------------------TMS570_RTI_TBHCOMP---------------------*/
/* field: TBHCOMP - Timebase high compare value. */
-#define TMS570_RTI_TBHCOMP_TBHCOMP(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_TBHCOMP_TBHCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_TBHCOMP_TBHCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_RTISETINTENA--------------------*/
+/*--------------------TMS570_RTI_SETINTENA--------------------*/
/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
-#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_FLD32(18)
+#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_BIT32(18)
/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
-#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_FLD32(17)
+#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_BIT32(17)
/* field: SETTBINT - Set timebase interrupt. */
-#define TMS570_RTI_SETINTENA_SETTBINT BSP_FLD32(16)
+#define TMS570_RTI_SETINTENA_SETTBINT BSP_BIT32(16)
/* field: SETDMA3 - Set compare DMA request 3. */
-#define TMS570_RTI_SETINTENA_SETDMA3 BSP_FLD32(11)
+#define TMS570_RTI_SETINTENA_SETDMA3 BSP_BIT32(11)
/* field: SETDMA2 - Set compare DMA request 2. */
-#define TMS570_RTI_SETINTENA_SETDMA2 BSP_FLD32(10)
+#define TMS570_RTI_SETINTENA_SETDMA2 BSP_BIT32(10)
/* field: SETDMA1 - Set compare DMA request 1. */
-#define TMS570_RTI_SETINTENA_SETDMA1 BSP_FLD32(9)
+#define TMS570_RTI_SETINTENA_SETDMA1 BSP_BIT32(9)
/* field: SETDMA0 - Set compare DMA request 0. */
-#define TMS570_RTI_SETINTENA_SETDMA0 BSP_FLD32(8)
+#define TMS570_RTI_SETINTENA_SETDMA0 BSP_BIT32(8)
/* field: SETINT3 - Set compare interrupt 3. */
-#define TMS570_RTI_SETINTENA_SETINT3 BSP_FLD32(3)
+#define TMS570_RTI_SETINTENA_SETINT3 BSP_BIT32(3)
/* field: SETINT2 - Set compare interrupt 2. */
-#define TMS570_RTI_SETINTENA_SETINT2 BSP_FLD32(2)
+#define TMS570_RTI_SETINTENA_SETINT2 BSP_BIT32(2)
/* field: SETINT1 - Set compare interrupt 1. */
-#define TMS570_RTI_SETINTENA_SETINT1 BSP_FLD32(1)
+#define TMS570_RTI_SETINTENA_SETINT1 BSP_BIT32(1)
/* field: SETINT0 - Set compare interrupt 0. */
-#define TMS570_RTI_SETINTENA_SETINT0 BSP_FLD32(0)
+#define TMS570_RTI_SETINTENA_SETINT0 BSP_BIT32(0)
-/*-------------------TMS570_RTICLEARINTENA-------------------*/
+/*-------------------TMS570_RTI_CLEARINTENA-------------------*/
/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_FLD32(18)
+#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_BIT32(18)
/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_FLD32(17)
+#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_BIT32(17)
/* field: CLEARTBINT - Clear timebase interrupt. */
-#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_FLD32(16)
+#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_BIT32(16)
/* field: CLEARDMA3 - Clear compare DMA request 3. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_FLD32(11)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_BIT32(11)
/* field: CLEARDMA2 - Clear compare DMA request 2. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_FLD32(10)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_BIT32(10)
/* field: CLEARDMA1 - Clear compare DMA request 1. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_FLD32(9)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_BIT32(9)
/* field: CLEARDMA0 - Clear compare DMA request 0. */
-#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_FLD32(8)
+#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_BIT32(8)
/* field: CLEARINT3 - Clear compare interrupt 3. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_FLD32(3)
+#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_BIT32(3)
/* field: CLEARINT2 - Clear compare interrupt 2. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_FLD32(2)
+#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_BIT32(2)
/* field: CLEARINT1 - Clear compare interrupt 1. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_FLD32(1)
+#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_BIT32(1)
/* field: CLEARINT0 - Clear compare interrupt 0. */
-#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_FLD32(0)
+#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_BIT32(0)
-/*---------------------TMS570_RTIINTFLAG---------------------*/
+/*---------------------TMS570_RTI_INTFLAG---------------------*/
/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
-#define TMS570_RTI_INTFLAG_OVL1INT BSP_FLD32(18)
+#define TMS570_RTI_INTFLAG_OVL1INT BSP_BIT32(18)
/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
-#define TMS570_RTI_INTFLAG_OVL0INT BSP_FLD32(17)
+#define TMS570_RTI_INTFLAG_OVL0INT BSP_BIT32(17)
/* field: TBINT - Timebase interrupt flag. */
-#define TMS570_RTI_INTFLAG_TBINT BSP_FLD32(16)
+#define TMS570_RTI_INTFLAG_TBINT BSP_BIT32(16)
/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
-#define TMS570_RTI_INTFLAG_INT3 BSP_FLD32(3)
+#define TMS570_RTI_INTFLAG_INT3 BSP_BIT32(3)
/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
-#define TMS570_RTI_INTFLAG_INT2 BSP_FLD32(2)
+#define TMS570_RTI_INTFLAG_INT2 BSP_BIT32(2)
/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
-#define TMS570_RTI_INTFLAG_INT1 BSP_FLD32(1)
+#define TMS570_RTI_INTFLAG_INT1 BSP_BIT32(1)
/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
-#define TMS570_RTI_INTFLAG_INT0 BSP_FLD32(0)
+#define TMS570_RTI_INTFLAG_INT0 BSP_BIT32(0)
-/*---------------------TMS570_RTIDWDCTRL---------------------*/
+/*---------------------TMS570_RTI_DWDCTRL---------------------*/
/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
-#define TMS570_RTI_DWDCTRL_DWDCTRL(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_DWDCTRL_DWDCTRL_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_DWDCTRL_DWDCTRL_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_RTIDWDPRLD---------------------*/
+/*---------------------TMS570_RTI_DWDPRLD---------------------*/
/* field: DWDPRLD - Digital Watchdog Preload Value. */
#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_RTIWDSTATUS---------------------*/
+/*--------------------TMS570_RTI_WDSTATUS--------------------*/
/* field: DWWD_ST - Windowed Watchdog Status */
-#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_FLD32(5)
+#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_BIT32(5)
/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
-#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_FLD32(4)
+#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_BIT32(4)
/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
-#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_FLD32(3)
+#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_BIT32(3)
/* field: KEY_ST - Watchdog key status. */
-#define TMS570_RTI_WDSTATUS_KEY_ST BSP_FLD32(2)
+#define TMS570_RTI_WDSTATUS_KEY_ST BSP_BIT32(2)
/* field: DWD_ST - DWD status. */
-#define TMS570_RTI_WDSTATUS_DWD_ST BSP_FLD32(1)
+#define TMS570_RTI_WDSTATUS_DWD_ST BSP_BIT32(1)
-/*----------------------TMS570_RTIWDKEY----------------------*/
+/*----------------------TMS570_RTI_WDKEY----------------------*/
/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_RTIDWDCNTR---------------------*/
+/*---------------------TMS570_RTI_DWDCNTR---------------------*/
/* field: DWDCNTR - DWD down counter. */
#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
-/*--------------------TMS570_RTIWWDRXNCTRL--------------------*/
+/*-------------------TMS570_RTI_WWDRXNCTRL-------------------*/
/* field: WWDRXN - The DWWD reaction */
#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_RTIWWDSIZECTRL-------------------*/
+/*-------------------TMS570_RTI_WWDSIZECTRL-------------------*/
/* field: WWDSIZE - The DWWD window size */
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*-------------------TMS570_RTIINTCLRENABLE-------------------*/
+/*------------------TMS570_RTI_INTCLRENABLE------------------*/
/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -375,33 +339,21 @@ typedef struct{
#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_RTICOMP0CLR---------------------*/
+/*--------------------TMS570_RTI_COMP0CLR--------------------*/
/* field: CMP0CLR - Compare 0 clear. */
-#define TMS570_RTI_COMP0CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_COMP0CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP0CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_RTICOMP1CLR---------------------*/
+/*--------------------TMS570_RTI_COMP1CLR--------------------*/
/* field: CMP0CLR - Compare 1 clear. */
-#define TMS570_RTI_COMP1CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_COMP1CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP1CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_RTICOMP2CLR---------------------*/
+/*--------------------TMS570_RTI_COMP2CLR--------------------*/
/* field: CMP2CLR - Compare 2 clear. */
-#define TMS570_RTI_COMP2CLR_CMP2CLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_COMP2CLR_CMP2CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP2CLR_CMP2CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_RTICOMP3CLR---------------------*/
+/*--------------------TMS570_RTI_COMP3CLR--------------------*/
/* field: CMP3CLR - Compare 3 clear. */
-#define TMS570_RTI_COMP3CLR_CMP3CLR(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTI_COMP3CLR_CMP3CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTI_COMP3CLR_CMP3CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-#endif /* LIBBSP_ARM_tms570_RTI */
+#endif /* LIBBSP_ARM_TMS570_RTI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
index 1faee61..cd54b29 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_RTP
-#define LIBBSP_ARM_tms570_RTP
+#ifndef LIBBSP_ARM_TMS570_RTP
+#define LIBBSP_ARM_TMS570_RTP
#include <bsp/utility.h>
@@ -66,9 +66,9 @@ typedef struct{
} tms570_rtp_t;
-/*---------------------TMS570_RTPGLBCTRL---------------------*/
+/*---------------------TMS570_RTP_GLBCTRL---------------------*/
/* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */
-#define TMS570_RTP_GLBCTRL_TEST BSP_FLD32(24)
+#define TMS570_RTP_GLBCTRL_TEST BSP_BIT32(24)
/* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */
#define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18)
@@ -81,10 +81,10 @@ typedef struct{
#define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
/* field: DDM_RW - */
-#define TMS570_RTP_GLBCTRL_DDM_RW BSP_FLD32(11)
+#define TMS570_RTP_GLBCTRL_DDM_RW BSP_BIT32(11)
/* field: TM_DDM - Trace Mode or Direct Data Mode */
-#define TMS570_RTP_GLBCTRL_TM_DDM BSP_FLD32(10)
+#define TMS570_RTP_GLBCTRL_TM_DDM BSP_BIT32(10)
/* field: PW - Port width. This bit field configures the RTP to the desired port width. */
#define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9)
@@ -92,16 +92,16 @@ typedef struct{
#define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: RESET - This bit resets the state machine and the registers to their reset value. */
-#define TMS570_RTP_GLBCTRL_RESET BSP_FLD32(7)
+#define TMS570_RTP_GLBCTRL_RESET BSP_BIT32(7)
/* field: CONTCLK - Continuous RTPCLK enable. */
-#define TMS570_RTP_GLBCTRL_CONTCLK BSP_FLD32(6)
+#define TMS570_RTP_GLBCTRL_CONTCLK BSP_BIT32(6)
/* field: HOVF - Halt on overflow. */
-#define TMS570_RTP_GLBCTRL_HOVF BSP_FLD32(5)
+#define TMS570_RTP_GLBCTRL_HOVF BSP_BIT32(5)
/* field: INV_RGN - Trace inside or outside of defined trace regions. */
-#define TMS570_RTP_GLBCTRL_INV_RGN BSP_FLD32(4)
+#define TMS570_RTP_GLBCTRL_INV_RGN BSP_BIT32(4)
/* field: ON_OFF - ON/Off switch. */
#define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
@@ -109,122 +109,119 @@ typedef struct{
#define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_RTPTRENA----------------------*/
+/*----------------------TMS570_RTP_TRENA----------------------*/
/* field: ENA4 - Enable tracing for peripherals. */
-#define TMS570_RTP_TRENA_ENA4 BSP_FLD32(24)
+#define TMS570_RTP_TRENA_ENA4 BSP_BIT32(24)
/* field: ENA2 - Enable tracing for RAM block 2. */
-#define TMS570_RTP_TRENA_ENA2 BSP_FLD32(8)
+#define TMS570_RTP_TRENA_ENA2 BSP_BIT32(8)
/* field: ENA1 - */
-#define TMS570_RTP_TRENA_ENA1 BSP_FLD32(0)
+#define TMS570_RTP_TRENA_ENA1 BSP_BIT32(0)
-/*-----------------------TMS570_RTPGSR-----------------------*/
+/*-----------------------TMS570_RTP_GSR-----------------------*/
/* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */
-#define TMS570_RTP_GSR_EMPTYSER BSP_FLD32(12)
+#define TMS570_RTP_GSR_EMPTYSER BSP_BIT32(12)
/* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTYPER BSP_FLD32(11)
+#define TMS570_RTP_GSR_EMPTYPER BSP_BIT32(11)
/* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTY2 BSP_FLD32(9)
+#define TMS570_RTP_GSR_EMPTY2 BSP_BIT32(9)
/* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */
-#define TMS570_RTP_GSR_EMPTY1 BSP_FLD32(8)
+#define TMS570_RTP_GSR_EMPTY1 BSP_BIT32(8)
/* field: OVFPER - Overflow peripheral FIFO. */
-#define TMS570_RTP_GSR_OVFPER BSP_FLD32(3)
+#define TMS570_RTP_GSR_OVFPER BSP_BIT32(3)
/* field: OVF2 - Overflow RAM block 2 FIFO. */
-#define TMS570_RTP_GSR_OVF2 BSP_FLD32(1)
+#define TMS570_RTP_GSR_OVF2 BSP_BIT32(1)
/* field: OVF1 - Overflow RAM block 1 FIFO. */
-#define TMS570_RTP_GSR_OVF1 BSP_FLD32(0)
+#define TMS570_RTP_GSR_OVF1 BSP_BIT32(0)
-/*---------------------TMS570_RTPRAM1REG1---------------------*/
+/*--------------------TMS570_RTP_RAM1REGx--------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_RAM1REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_RAM1REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_RAM1REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM1REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
-#define TMS570_RTP_RAM1REG1_RW BSP_FLD32(28)
+#define TMS570_RTP_RAM1REGx_RW BSP_BIT32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_RAM1REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM1REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_RAM1REG1_STARTADDR(val) BSP_FLD32(val,0, 17)
-#define TMS570_RTP_RAM1REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
-#define TMS570_RTP_RAM1REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_RTP_RAM1REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
-/*---------------------TMS570_RTPRAM2REG1---------------------*/
+/*--------------------TMS570_RTP_RAM2REGx--------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_RAM2REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_RAM2REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_RAM2REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM2REGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
-#define TMS570_RTP_RAM2REG1_RW BSP_FLD32(28)
+#define TMS570_RTP_RAM2REGx_RW BSP_BIT32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_RAM2REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM2REGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_RAM2REG1_STARTADDR(val) BSP_FLD32(val,0, 23)
-#define TMS570_RTP_RAM2REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
-#define TMS570_RTP_RAM2REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_RAM2REGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*---------------------TMS570_RTPPERREG1---------------------*/
+/*---------------------TMS570_RTP_PERREGx---------------------*/
/* field: CPU_DMA - CPU and/or other master access. */
-#define TMS570_RTP_PERREG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
-#define TMS570_RTP_PERREG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
-#define TMS570_RTP_PERREG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_PERREGx_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
/* field: RW - Read/Write. */
-#define TMS570_RTP_PERREG1_RW BSP_FLD32(28)
+#define TMS570_RTP_PERREGx_RW BSP_BIT32(28)
/* field: BLOCKSIZE - These bits define the length of the trace region. */
-#define TMS570_RTP_PERREG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
-#define TMS570_RTP_PERREG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
-#define TMS570_RTP_PERREG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_PERREGx_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
-#define TMS570_RTP_PERREG1_STARTADDR(val) BSP_FLD32(val,0, 23)
-#define TMS570_RTP_PERREG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
-#define TMS570_RTP_PERREG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_PERREGx_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*-----------------------TMS570_RTPDDMW-----------------------*/
+/*----------------------TMS570_RTP_DDMW----------------------*/
/* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */
-#define TMS570_RTP_DDMW_DATA(val) BSP_FLD32(val,0, 31)
-#define TMS570_RTP_DDMW_DATA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_RTP_DDMW_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*-----------------------TMS570_RTPPC0-----------------------*/
+/*-----------------------TMS570_RTP_PCx-----------------------*/
/* field: ENAFUNC - Functional mode of RTPENA pin. */
-#define TMS570_RTP_PC0_ENAFUNC BSP_FLD32(18)
+#define TMS570_RTP_PCx_ENAFUNC BSP_BIT32(18)
/* field: CLKFUNC - Functional mode of RTPCLK pin. */
-#define TMS570_RTP_PC0_CLKFUNC BSP_FLD32(17)
+#define TMS570_RTP_PCx_CLKFUNC BSP_BIT32(17)
/* field: SYNCFUNC - Functional mode of RTPSYNC pin. */
-#define TMS570_RTP_PC0_SYNCFUNC BSP_FLD32(16)
+#define TMS570_RTP_PCx_SYNCFUNC BSP_BIT32(16)
/* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */
-#define TMS570_RTP_PC0_DATAFUNC(val) BSP_FLD32(val,0, 15)
-#define TMS570_RTP_PC0_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
-#define TMS570_RTP_PC0_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC(val) BSP_FLD32(val,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_RTP_PCx_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-#endif /* LIBBSP_ARM_tms570_RTP */
+#endif /* LIBBSP_ARM_TMS570_RTP */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
index e4e4eb3..6b954f7 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_SCI
-#define LIBBSP_ARM_tms570_SCI
+#ifndef LIBBSP_ARM_TMS570_SCI
+#define LIBBSP_ARM_TMS570_SCI
#include <bsp/utility.h>
@@ -71,358 +71,358 @@ typedef struct{
} tms570_sci_t;
-/*-----------------------TMS570_SCIGCR0-----------------------*/
+/*----------------------TMS570_SCI_GCR0----------------------*/
/* field: Reserved - Read returns 0. Writes have no effect. */
#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
/* field: RESET - This bit resets the SCI module. */
-#define TMS570_SCI_GCR0_RESET BSP_FLD32(0)
+#define TMS570_SCI_GCR0_RESET BSP_BIT32(0)
-/*-----------------------TMS570_SCIGCR1-----------------------*/
+/*----------------------TMS570_SCI_GCR1----------------------*/
/* field: TXENA - Transmit enable. */
-#define TMS570_SCI_GCR1_TXENA BSP_FLD32(25)
+#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25)
/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
-#define TMS570_SCI_GCR1_RXENA BSP_FLD32(24)
+#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24)
/* field: CONT - Continue on suspend. */
-#define TMS570_SCI_GCR1_CONT BSP_FLD32(17)
+#define TMS570_SCI_GCR1_CONT BSP_BIT32(17)
/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
-#define TMS570_SCI_GCR1_LOOP_BACK BSP_FLD32(16)
+#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16)
/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
-#define TMS570_SCI_GCR1_POWERDOWN BSP_FLD32(9)
+#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9)
/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
-#define TMS570_SCI_GCR1_SLEEP BSP_FLD32(8)
+#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8)
/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
-#define TMS570_SCI_GCR1_SWnRST BSP_FLD32(7)
+#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7)
/* field: CLOCK - CLOCK */
-#define TMS570_SCI_GCR1_CLOCK BSP_FLD32(5)
+#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5)
/* field: STOP - SCI number of stop bits per frame. */
-#define TMS570_SCI_GCR1_STOP BSP_FLD32(4)
+#define TMS570_SCI_GCR1_STOP BSP_BIT32(4)
/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
-#define TMS570_SCI_GCR1_PARITY BSP_FLD32(3)
+#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3)
/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
-#define TMS570_SCI_GCR1_PARITY_ENA BSP_FLD32(2)
+#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2)
/* field: TIMING_MODE - SCI timing mode bit. */
-#define TMS570_SCI_GCR1_TIMING_MODE BSP_FLD32(1)
+#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1)
/* field: COMM_MODE - SCI communication mode bit. */
-#define TMS570_SCI_GCR1_COMM_MODE BSP_FLD32(0)
+#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0)
-/*-----------------------TMS570_SCIGCR2-----------------------*/
+/*----------------------TMS570_SCI_GCR2----------------------*/
/* field: CC - Compare checksum. LIN mode only. */
-#define TMS570_SCI_GCR2_CC BSP_FLD32(17)
+#define TMS570_SCI_GCR2_CC BSP_BIT32(17)
/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
-#define TMS570_SCI_GCR2_SC BSP_FLD32(16)
+#define TMS570_SCI_GCR2_SC BSP_BIT32(16)
/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
-#define TMS570_SCI_GCR2_GEN_WU BSP_FLD32(8)
+#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8)
/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
-#define TMS570_SCI_GCR2_POWERDOWN BSP_FLD32(0)
+#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0)
-/*----------------------TMS570_SCISETINT----------------------*/
+/*---------------------TMS570_SCI_SETINT---------------------*/
/* field: SET_FE_INT - */
-#define TMS570_SCI_SETINT_SET_FE_INT BSP_FLD32(26)
+#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26)
/* field: SET_OE_INT - SET OE INT */
-#define TMS570_SCI_SETINT_SET_OE_INT BSP_FLD32(25)
+#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25)
/* field: SET_PE_INT - Set parity interrupt. */
-#define TMS570_SCI_SETINT_SET_PE_INT BSP_FLD32(24)
+#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24)
/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
-#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
/* field: SET_RX_DMA - SET RX DMA */
-#define TMS570_SCI_SETINT_SET_RX_DMA BSP_FLD32(17)
+#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17)
/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
-#define TMS570_SCI_SETINT_SET_TX_DMA BSP_FLD32(16)
+#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16)
/* field: SET_RX_INT - SET RX INT */
-#define TMS570_SCI_SETINT_SET_RX_INT BSP_FLD32(9)
+#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9)
/* field: SET_TX_INT - Set transmitter interrupt. */
-#define TMS570_SCI_SETINT_SET_TX_INT BSP_FLD32(8)
+#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8)
/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
-#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
-#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0)
-/*---------------------TMS570_SCICLEARINT---------------------*/
+/*--------------------TMS570_SCI_CLEARINT--------------------*/
/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26)
/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25)
/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24)
/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
/* field: CLR_TX_DMA - CLR TX DMA */
-#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9)
/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8)
/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
-#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
-/*--------------------TMS570_SCISETINTLVL--------------------*/
+/*--------------------TMS570_SCI_SETINTLVL--------------------*/
/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
-#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
-#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
-#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
-/*-------------------TMS570_SCICLEARINTLVL-------------------*/
+/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/
/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
-#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
/* field: CLR_PE_INT_LVL - */
-#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
-#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
-#define TMS570_SCI_CLEARINTLVL_8 BSP_FLD32(8)
+#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8)
/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
-#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
-/*-----------------------TMS570_SCIFLR-----------------------*/
+/*-----------------------TMS570_SCI_FLR-----------------------*/
/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
-#define TMS570_SCI_FLR_FE BSP_FLD32(26)
+#define TMS570_SCI_FLR_FE BSP_BIT32(26)
/* field: OE - Overrun error flag. */
-#define TMS570_SCI_FLR_OE BSP_FLD32(25)
+#define TMS570_SCI_FLR_OE BSP_BIT32(25)
/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
-#define TMS570_SCI_FLR_PE BSP_FLD32(24)
+#define TMS570_SCI_FLR_PE BSP_BIT32(24)
/* field: RXWAKE - Receiver wakeup detect flag. */
-#define TMS570_SCI_FLR_RXWAKE BSP_FLD32(12)
+#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12)
/* field: TX_EMPTY - Transmitter empty flag. */
-#define TMS570_SCI_FLR_TX_EMPTY BSP_FLD32(11)
+#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11)
/* field: TXWAKE - Transmitter wakeup method select. */
-#define TMS570_SCI_FLR_TXWAKE BSP_FLD32(10)
+#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10)
/* field: RXRDY - Receiver ready flag. */
-#define TMS570_SCI_FLR_RXRDY BSP_FLD32(9)
+#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9)
/* field: TXRDY - Transmitter buffer register ready flag. */
-#define TMS570_SCI_FLR_TXRDY BSP_FLD32(8)
+#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8)
/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
-#define TMS570_SCI_FLR_BUSY BSP_FLD32(3)
+#define TMS570_SCI_FLR_BUSY BSP_BIT32(3)
/* field: IDLE - SCI receiver in idle state. */
-#define TMS570_SCI_FLR_IDLE BSP_FLD32(2)
+#define TMS570_SCI_FLR_IDLE BSP_BIT32(2)
/* field: WAKEUP - Wakeup flag. */
-#define TMS570_SCI_FLR_WAKEUP BSP_FLD32(1)
+#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1)
/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
-#define TMS570_SCI_FLR_BRKDT BSP_FLD32(0)
+#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0)
-/*---------------------TMS570_SCIINTVECT0---------------------*/
+/*--------------------TMS570_SCI_INTVECT0--------------------*/
/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SCIINTVECT1---------------------*/
+/*--------------------TMS570_SCI_INTVECT1--------------------*/
/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_SCIFORMAT----------------------*/
+/*---------------------TMS570_SCI_FORMAT---------------------*/
/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*-----------------------TMS570_SCIBRS-----------------------*/
+/*-----------------------TMS570_SCI_BRS-----------------------*/
/* field: BAUD - SCI 24-bit baud selection. */
#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
-/*------------------------TMS570_SCIED------------------------*/
+/*-----------------------TMS570_SCI_ED-----------------------*/
/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------------TMS570_SCIRD------------------------*/
+/*-----------------------TMS570_SCI_RD-----------------------*/
/* field: RD - Receiver data. */
#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*------------------------TMS570_SCITD------------------------*/
+/*-----------------------TMS570_SCI_TD-----------------------*/
/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SCIPIO0-----------------------*/
+/*----------------------TMS570_SCI_PIO0----------------------*/
/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
-#define TMS570_SCI_PIO0_TX_FUNC BSP_FLD32(2)
+#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2)
/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
-#define TMS570_SCI_PIO0_RX_FUNC BSP_FLD32(1)
+#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO1-----------------------*/
+/*----------------------TMS570_SCI_PIO1----------------------*/
/* field: TX_DIR - Transmit pin direction. */
-#define TMS570_SCI_PIO1_TX_DIR BSP_FLD32(2)
+#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2)
/* field: RX_DIR - Receive pin direction. */
-#define TMS570_SCI_PIO1_RX_DIR BSP_FLD32(1)
+#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO2-----------------------*/
+/*----------------------TMS570_SCI_PIO2----------------------*/
/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
-#define TMS570_SCI_PIO2_TX_IN BSP_FLD32(2)
+#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2)
/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
-#define TMS570_SCI_PIO2_RX_IN BSP_FLD32(1)
+#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO3-----------------------*/
+/*----------------------TMS570_SCI_PIO3----------------------*/
/* field: TX_OUT - Transmit pin out. */
-#define TMS570_SCI_PIO3_TX_OUT BSP_FLD32(2)
+#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2)
/* field: RX_OUT - Receive pin out. */
-#define TMS570_SCI_PIO3_RX_OUT BSP_FLD32(1)
+#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO4-----------------------*/
+/*----------------------TMS570_SCI_PIO4----------------------*/
/* field: TX_SET - Transmit pin set. */
-#define TMS570_SCI_PIO4_TX_SET BSP_FLD32(2)
+#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2)
/* field: RX_SET - Receive pin set. */
-#define TMS570_SCI_PIO4_RX_SET BSP_FLD32(1)
+#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO5-----------------------*/
+/*----------------------TMS570_SCI_PIO5----------------------*/
/* field: TX_CLR - Transmit pin clear. */
-#define TMS570_SCI_PIO5_TX_CLR BSP_FLD32(2)
+#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2)
/* field: RX_CLR - Receive pin clear. */
-#define TMS570_SCI_PIO5_RX_CLR BSP_FLD32(1)
+#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO6-----------------------*/
+/*----------------------TMS570_SCI_PIO6----------------------*/
/* field: TX_PDR - Transmit pin open drain enable. */
-#define TMS570_SCI_PIO6_TX_PDR BSP_FLD32(2)
+#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2)
/* field: RX_PDR - Receive pin open drain enable. */
-#define TMS570_SCI_PIO6_RX_PDR BSP_FLD32(1)
+#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO7-----------------------*/
+/*----------------------TMS570_SCI_PIO7----------------------*/
/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
-#define TMS570_SCI_PIO7_TX_PD BSP_FLD32(2)
+#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2)
/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
-#define TMS570_SCI_PIO7_RX_PD BSP_FLD32(1)
+#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1)
-/*-----------------------TMS570_SCIPIO8-----------------------*/
+/*----------------------TMS570_SCI_PIO8----------------------*/
/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
-#define TMS570_SCI_PIO8_TX_PSL BSP_FLD32(2)
+#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2)
/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
-#define TMS570_SCI_PIO8_RX_PSL BSP_FLD32(1)
+#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1)
-/*--------------------TMS570_SCIIODFTCTRL--------------------*/
+/*--------------------TMS570_SCI_IODFTCTRL--------------------*/
/* field: FEN - Frame error enable. This bit is used to create a frame error. */
-#define TMS570_SCI_IODFTCTRL_FEN BSP_FLD32(26)
+#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26)
/* field: PEN - Parity error enable. This bit is used to create a parity error. */
-#define TMS570_SCI_IODFTCTRL_PEN BSP_FLD32(25)
+#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25)
/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
-#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
/* field: PIN_SAMPLE_MASK - Pin sample mask. */
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
@@ -440,11 +440,11 @@ typedef struct{
#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
-#define TMS570_SCI_IODFTCTRL_LPBENA BSP_FLD32(1)
+#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1)
/* field: RXPENA - Module analog loopback through receive pin enable. */
-#define TMS570_SCI_IODFTCTRL_RXPENA BSP_FLD32(0)
+#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_SCI */
+#endif /* LIBBSP_ARM_TMS570_SCI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
index a92c0a8..35335c6 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_SPI
-#define LIBBSP_ARM_tms570_SPI
+#ifndef LIBBSP_ARM_TMS570_SPI
+#define LIBBSP_ARM_TMS570_SPI
#include <bsp/utility.h>
@@ -95,92 +95,92 @@ typedef struct{
} tms570_spi_t;
-/*-----------------------TMS570_SPIGCR0-----------------------*/
+/*----------------------TMS570_SPI_GCR0----------------------*/
/* field: nRESET - This is the local reset control for the module. */
-#define TMS570_SPI_GCR0_nRESET BSP_FLD32(0)
+#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0)
-/*-----------------------TMS570_SPIGCR1-----------------------*/
+/*----------------------TMS570_SPI_GCR1----------------------*/
/* field: SPIEN - SPI enable. This bit enables SPI transfers. */
-#define TMS570_SPI_GCR1_SPIEN BSP_FLD32(24)
+#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24)
/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
-#define TMS570_SPI_GCR1_LOOPBACK BSP_FLD32(16)
+#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16)
/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
-#define TMS570_SPI_GCR1_POWERDOWN BSP_FLD32(8)
+#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8)
/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
-#define TMS570_SPI_GCR1_CLKMOD BSP_FLD32(1)
+#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1)
/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
-#define TMS570_SPI_GCR1_MASTER BSP_FLD32(0)
+#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0)
-/*-----------------------TMS570_SPIINT0-----------------------*/
+/*----------------------TMS570_SPI_INT0----------------------*/
/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
-#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_FLD32(24)
+#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24)
/* field: DMAREQEN - DMA request enable. */
-#define TMS570_SPI_INT0_DMAREQEN BSP_FLD32(16)
+#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16)
-/*-----------------------TMS570_SPILVL-----------------------*/
+/*-----------------------TMS570_SPI_LVL-----------------------*/
/* field: TXINTLVL - Transmit interrupt level. */
-#define TMS570_SPI_LVL_TXINTLVL BSP_FLD32(9)
+#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9)
/* field: RXINTLVL - Receive interrupt level. */
-#define TMS570_SPI_LVL_RXINTLVL BSP_FLD32(8)
+#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8)
/* field: RXOVRNINTLVL - Receive overrun interrupt level. */
-#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_FLD32(6)
+#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6)
/* field: BITERRLVL - Bit error interrupt level. */
-#define TMS570_SPI_LVL_BITERRLVL BSP_FLD32(4)
+#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4)
/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
-#define TMS570_SPI_LVL_DESYNCLVL BSP_FLD32(3)
+#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3)
/* field: PARERRLVL - Parity error interrupt level. */
-#define TMS570_SPI_LVL_PARERRLVL BSP_FLD32(2)
+#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2)
/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
-#define TMS570_SPI_LVL_TIMEOUTLVL BSP_FLD32(1)
+#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1)
/* field: DLENERRLVL - Data length error interrupt level (line) select. */
-#define TMS570_SPI_LVL_DLENERRLVL BSP_FLD32(0)
+#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0)
-/*-----------------------TMS570_SPIFLG-----------------------*/
+/*-----------------------TMS570_SPI_FLG-----------------------*/
/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
-#define TMS570_SPI_FLG_BUFINITACTIVE BSP_FLD32(24)
+#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24)
/* field: TXINTFLG - Transmitter-empty interrupt flag. */
-#define TMS570_SPI_FLG_TXINTFLG BSP_FLD32(9)
+#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9)
/* field: RXINTFLG - Receiver-full interrupt flag. */
-#define TMS570_SPI_FLG_RXINTFLG BSP_FLD32(8)
+#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8)
/* field: RXOVRNINTFLG - Receiver overrun flag. */
-#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_FLD32(6)
+#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6)
/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
-#define TMS570_SPI_FLG_BITERRFLG BSP_FLD32(4)
+#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4)
/* field: DESYNCFLG - Desynchronization of slave device. */
-#define TMS570_SPI_FLG_DESYNCFLG BSP_FLD32(3)
+#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3)
/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
-#define TMS570_SPI_FLG_PARITYERRFLG BSP_FLD32(2)
+#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2)
/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
-#define TMS570_SPI_FLG_TIMEOUTFLG BSP_FLD32(1)
+#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1)
/* field: DLENERRFLG - Data-length error flag. */
-#define TMS570_SPI_FLG_DLENERRFLG BSP_FLD32(0)
+#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0)
-/*-----------------------TMS570_SPIPC0-----------------------*/
+/*-----------------------TMS570_SPI_PC0-----------------------*/
/* field: SOMIFUN - Slave out, master in function. */
#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -192,16 +192,16 @@ typedef struct{
#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIFUN0 - SOMIFUN0 */
-#define TMS570_SPI_PC0_SOMIFUN0 BSP_FLD32(11)
+#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11)
/* field: SIMOFUN0 - Slave in, master out function. */
-#define TMS570_SPI_PC0_SIMOFUN0 BSP_FLD32(10)
+#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10)
/* field: CLKFUN - CLKFUN */
-#define TMS570_SPI_PC0_CLKFUN BSP_FLD32(9)
+#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9)
/* field: ENAFUN - SPIENA function. */
-#define TMS570_SPI_PC0_ENAFUN BSP_FLD32(8)
+#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8)
/* field: SCSFUN - SPISCSx function. */
#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
@@ -209,7 +209,7 @@ typedef struct{
#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC1-----------------------*/
+/*-----------------------TMS570_SPI_PC1-----------------------*/
/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -221,16 +221,16 @@ typedef struct{
#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIDIR0 - PISOMI0 direction. */
-#define TMS570_SPI_PC1_SOMIDIR0 BSP_FLD32(11)
+#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11)
/* field: SIMODIR0 - SPISIMO0 direction. */
-#define TMS570_SPI_PC1_SIMODIR0 BSP_FLD32(10)
+#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10)
/* field: CLKDIR - SPICLK direction. */
-#define TMS570_SPI_PC1_CLKDIR BSP_FLD32(9)
+#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9)
/* field: ENADIR - SPIENA direction. */
-#define TMS570_SPI_PC1_ENADIR BSP_FLD32(8)
+#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8)
/* field: SCSDIR - SPISCSx direction. */
#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
@@ -238,7 +238,7 @@ typedef struct{
#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC2-----------------------*/
+/*-----------------------TMS570_SPI_PC2-----------------------*/
/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -250,16 +250,16 @@ typedef struct{
#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
-#define TMS570_SPI_PC2_SOMIDIN0 BSP_FLD32(11)
+#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11)
/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
-#define TMS570_SPI_PC2_SIMODIN0 BSP_FLD32(10)
+#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10)
/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
-#define TMS570_SPI_PC2_CLKDIN BSP_FLD32(9)
+#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9)
/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
-#define TMS570_SPI_PC2_ENADIN BSP_FLD32(8)
+#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8)
/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
@@ -267,7 +267,7 @@ typedef struct{
#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC3-----------------------*/
+/*-----------------------TMS570_SPI_PC3-----------------------*/
/* field: SOMIDOUT - SPISOMIx data out write. */
#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -279,16 +279,16 @@ typedef struct{
#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIDOUT0 - SPISOMI0 data out write. */
-#define TMS570_SPI_PC3_SOMIDOUT0 BSP_FLD32(11)
+#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11)
/* field: SIMODOUT0 - SPISIMO0 data out write. */
-#define TMS570_SPI_PC3_SIMODOUT0 BSP_FLD32(10)
+#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10)
/* field: CLKDOUT - SPICLK data out write. */
-#define TMS570_SPI_PC3_CLKDOUT BSP_FLD32(9)
+#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9)
/* field: ENADOUT - SPIENA data out write. */
-#define TMS570_SPI_PC3_ENADOUT BSP_FLD32(8)
+#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8)
/* field: SCSDOUT - SPISCSx data out write. */
#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
@@ -296,7 +296,7 @@ typedef struct{
#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC4-----------------------*/
+/*-----------------------TMS570_SPI_PC4-----------------------*/
/* field: SOMISET - SPISOMIx data out set. */
#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -308,16 +308,16 @@ typedef struct{
#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMISET0 - SPISOMI0 data out set. */
-#define TMS570_SPI_PC4_SOMISET0 BSP_FLD32(11)
+#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11)
/* field: SIMOSET0 - purpose */
-#define TMS570_SPI_PC4_SIMOSET0 BSP_FLD32(10)
+#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10)
/* field: CLKSET - SPICLK data out set. */
-#define TMS570_SPI_PC4_CLKSET BSP_FLD32(9)
+#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9)
/* field: ENASET - SPIENA data out set. */
-#define TMS570_SPI_PC4_ENASET BSP_FLD32(8)
+#define TMS570_SPI_PC4_ENASET BSP_BIT32(8)
/* field: SCSSET - SPISCSx data out set. */
#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
@@ -325,7 +325,7 @@ typedef struct{
#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC5-----------------------*/
+/*-----------------------TMS570_SPI_PC5-----------------------*/
/* field: SOMICLR - SPISOMIx data out clear. */
#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -337,16 +337,16 @@ typedef struct{
#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMICLR0 - SPISOMI0 data out cleart. */
-#define TMS570_SPI_PC5_SOMICLR0 BSP_FLD32(11)
+#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11)
/* field: SIMOCLR0 - SPISIMO0 data out clear. */
-#define TMS570_SPI_PC5_SIMOCLR0 BSP_FLD32(10)
+#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10)
/* field: CLKCLR - SPICLK data out clear. */
-#define TMS570_SPI_PC5_CLKCLR BSP_FLD32(9)
+#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9)
/* field: ENACLR - SPIENA data out clear. */
-#define TMS570_SPI_PC5_ENACLR BSP_FLD32(8)
+#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8)
/* field: SCSCLR - SPISCSx data out clear. */
#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
@@ -354,7 +354,7 @@ typedef struct{
#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC6-----------------------*/
+/*-----------------------TMS570_SPI_PC6-----------------------*/
/* field: SOMIPDR - SPISOMIx open drain enable. */
#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -366,16 +366,16 @@ typedef struct{
#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIPDR0 - SOMI0 open-drain enable. */
-#define TMS570_SPI_PC6_SOMIPDR0 BSP_FLD32(11)
+#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11)
/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
-#define TMS570_SPI_PC6_SIMOPDR0 BSP_FLD32(10)
+#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10)
/* field: CLKPDR - CLK open drain enable. */
-#define TMS570_SPI_PC6_CLKPDR BSP_FLD32(9)
+#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9)
/* field: ENAPDR - SPIENA pin open drain enable. */
-#define TMS570_SPI_PC6_ENAPDR BSP_FLD32(8)
+#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8)
/* field: SCSPDR - SPISCSx open drain enable. */
#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
@@ -383,7 +383,7 @@ typedef struct{
#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC7-----------------------*/
+/*-----------------------TMS570_SPI_PC7-----------------------*/
/* field: SOMIDIS - SOMIx pull control enable/disable. */
#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -395,16 +395,16 @@ typedef struct{
#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
-#define TMS570_SPI_PC7_SOMIPDIS0 BSP_FLD32(11)
+#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11)
/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
-#define TMS570_SPI_PC7_SIMOPDIS0 BSP_FLD32(10)
+#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10)
/* field: CLKPDIS - CLK pull control enable/disable. */
-#define TMS570_SPI_PC7_CLKPDIS BSP_FLD32(9)
+#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9)
/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
-#define TMS570_SPI_PC7_ENAPDIS BSP_FLD32(8)
+#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8)
/* field: SCSPDIS - SCSx pull control enable/disable. */
#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
@@ -412,7 +412,7 @@ typedef struct{
#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIPC8-----------------------*/
+/*-----------------------TMS570_SPI_PC8-----------------------*/
/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -424,16 +424,16 @@ typedef struct{
#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
-#define TMS570_SPI_PC8_SOMIPSEL0 BSP_FLD32(11)
+#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11)
/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
-#define TMS570_SPI_PC8_SIMOPSEL0 BSP_FLD32(10)
+#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10)
/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
-#define TMS570_SPI_PC8_CLKPSEL BSP_FLD32(9)
+#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9)
/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
-#define TMS570_SPI_PC8_ENAPSEL BSP_FLD32(8)
+#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8)
/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
@@ -441,19 +441,19 @@ typedef struct{
#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIDAT0-----------------------*/
+/*----------------------TMS570_SPI_DAT0----------------------*/
/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_SPIDAT1-----------------------*/
+/*----------------------TMS570_SPI_DAT1----------------------*/
/* field: CSHOLD - Chip select hold mode. */
-#define TMS570_SPI_DAT1_CSHOLD BSP_FLD32(28)
+#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28)
/* field: WDEL - Enable the delay counter at the end of the current transaction. */
-#define TMS570_SPI_DAT1_WDEL BSP_FLD32(26)
+#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26)
/* field: DFSEL - Data word format select */
#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
@@ -471,30 +471,30 @@ typedef struct{
#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_SPIBUF-----------------------*/
+/*-----------------------TMS570_SPI_BUF-----------------------*/
/* field: RXEMPTY - Receive data buffer empty. */
-#define TMS570_SPI_BUF_RXEMPTY BSP_FLD32(31)
+#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31)
/* field: RXOVR - Receive data buffer overrun. */
-#define TMS570_SPI_BUF_RXOVR BSP_FLD32(30)
+#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30)
/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
-#define TMS570_SPI_BUF_TXFULL BSP_FLD32(29)
+#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29)
/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
-#define TMS570_SPI_BUF_BITERR BSP_FLD32(28)
+#define TMS570_SPI_BUF_BITERR BSP_BIT32(28)
/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
-#define TMS570_SPI_BUF_DESYNC BSP_FLD32(27)
+#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27)
/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
-#define TMS570_SPI_BUF_PARITYERR BSP_FLD32(26)
+#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26)
/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
-#define TMS570_SPI_BUF_TIMEOUT BSP_FLD32(25)
+#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25)
/* field: DLENERR - Data length error flag. */
-#define TMS570_SPI_BUF_DLENERR BSP_FLD32(24)
+#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24)
/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
@@ -507,14 +507,14 @@ typedef struct{
#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-----------------------TMS570_SPIEMU-----------------------*/
+/*-----------------------TMS570_SPI_EMU-----------------------*/
/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*----------------------TMS570_SPIDELAY----------------------*/
+/*----------------------TMS570_SPI_DELAY----------------------*/
/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
@@ -536,77 +536,77 @@ typedef struct{
#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIDEF-----------------------*/
+/*-----------------------TMS570_SPI_DEF-----------------------*/
/* field: CDEF - Chip select default pattern. Master-mode only. */
#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*-----------------------TMS570_SPIFMT0-----------------------*/
+/*----------------------TMS570_SPI_FMTx----------------------*/
/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
-#define TMS570_SPI_FMT0_WDELAY(val) BSP_FLD32(val,24, 31)
-#define TMS570_SPI_FMT0_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
-#define TMS570_SPI_FMT0_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
-#define TMS570_SPI_FMT0_PARPOL BSP_FLD32(23)
+#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23)
/* field: PARITYENA - Parity enable for data format x. */
-#define TMS570_SPI_FMT0_PARITYENA BSP_FLD32(22)
+#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22)
/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
-#define TMS570_SPI_FMT0_WAITENA BSP_FLD32(21)
+#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21)
/* field: SHIFTDIR - Shift direction for data format x. */
-#define TMS570_SPI_FMT0_SHIFTDIR BSP_FLD32(20)
+#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20)
/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
-#define TMS570_SPI_FMT0_HDUPLEX_ENAx BSP_FLD32(19)
+#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19)
/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
-#define TMS570_SPI_FMT0_DIS_CS_TIMERS BSP_FLD32(18)
+#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18)
/* field: POLARITY - POLARITY */
-#define TMS570_SPI_FMT0_POLARITY BSP_FLD32(17)
+#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17)
/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
-#define TMS570_SPI_FMT0_PHASE BSP_FLD32(16)
+#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16)
/* field: PRESCALE - SPI data format x prescaler. */
-#define TMS570_SPI_FMT0_PRESCALE(val) BSP_FLD32(val,8, 15)
-#define TMS570_SPI_FMT0_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_SPI_FMT0_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
-#define TMS570_SPI_FMT0_CHARLEN(val) BSP_FLD32(val,0, 4)
-#define TMS570_SPI_FMT0_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
-#define TMS570_SPI_FMT0_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*---------------------TMS570_SPIINTVECT0---------------------*/
+/*--------------------TMS570_SPI_INTVECT0--------------------*/
/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
-#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_FLD32(0)
+#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0)
-/*---------------------TMS570_SPIINTVECT1---------------------*/
+/*--------------------TMS570_SPI_INTVECT1--------------------*/
/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
-#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_FLD32(0)
+#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0)
-/*----------------------TMS570_SPIPMCTRL----------------------*/
+/*---------------------TMS570_SPI_PMCTRL---------------------*/
/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_FLD32(29)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29)
/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
@@ -619,7 +619,7 @@ typedef struct{
#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_FLD32(21)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21)
/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
@@ -632,7 +632,7 @@ typedef struct{
#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_FLD32(13)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13)
/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
@@ -645,7 +645,7 @@ typedef struct{
#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
-#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_FLD32(5)
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5)
/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
@@ -658,15 +658,15 @@ typedef struct{
#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_SPIMIBSPIE---------------------*/
+/*---------------------TMS570_SPI_MIBSPIE---------------------*/
/* field: RXRAM_ACCESS - Receive-RAM access control. */
-#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_FLD32(16)
+#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16)
/* field: MSPIENA - Multi-buffer mode enable. */
-#define TMS570_SPI_MIBSPIE_MSPIENA BSP_FLD32(0)
+#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0)
-/*---------------------TMS570_SPITGITENST---------------------*/
+/*--------------------TMS570_SPI_TGITENST--------------------*/
/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -678,7 +678,7 @@ typedef struct{
#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPITGITENCR---------------------*/
+/*--------------------TMS570_SPI_TGITENCR--------------------*/
/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -690,7 +690,7 @@ typedef struct{
#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPITGITLVST---------------------*/
+/*--------------------TMS570_SPI_TGITLVST--------------------*/
/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -702,7 +702,7 @@ typedef struct{
#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPITGITLVCR---------------------*/
+/*--------------------TMS570_SPI_TGITLVCR--------------------*/
/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -714,7 +714,7 @@ typedef struct{
#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPITGINTFLG---------------------*/
+/*--------------------TMS570_SPI_TGINTFLG--------------------*/
/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -726,12 +726,12 @@ typedef struct{
#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPITICKCNT---------------------*/
+/*---------------------TMS570_SPI_TICKCNT---------------------*/
/* field: TICKENA - Tick counter enable. */
-#define TMS570_SPI_TICKCNT_TICKENA BSP_FLD32(31)
+#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31)
/* field: RELOAD - Pre-load the tick counter. */
-#define TMS570_SPI_TICKCNT_RELOAD BSP_FLD32(30)
+#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30)
/* field: CLKCTRL - Tick counter clock source control. */
#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
@@ -744,7 +744,7 @@ typedef struct{
#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SPILTGPEND---------------------*/
+/*---------------------TMS570_SPI_LTGPEND---------------------*/
/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
@@ -756,23 +756,23 @@ typedef struct{
#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
-/*----------------------TMS570_SPITGCTRL----------------------*/
+/*---------------------TMS570_SPI_TGCTRL---------------------*/
/* field: TGENA - TGx enable. */
-#define TMS570_SPI_TGCTRL_TGENA BSP_FLD32(31)
+#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31)
/* field: ONESHOTx - Single transfer for TGx. */
-#define TMS570_SPI_TGCTRL_ONESHOTx BSP_FLD32(30)
+#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30)
/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
-#define TMS570_SPI_TGCTRL_PRSTx BSP_FLD32(29)
+#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29)
/* field: TGTDx - TG triggered. */
-#define TMS570_SPI_TGCTRL_TGTDx BSP_FLD32(28)
+#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28)
-/*---------------------TMS570_SPIDMACTRL---------------------*/
+/*---------------------TMS570_SPI_DMACTRL---------------------*/
/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
-#define TMS570_SPI_DMACTRL_ONESHOT BSP_FLD32(31)
+#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31)
/* field: BUFIDx - Buffer utilized for DMA transfer. */
#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
@@ -790,13 +790,13 @@ typedef struct{
#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: RXDMAENAx - Receive data DMA channel enable. */
-#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_FLD32(15)
+#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15)
/* field: TXDAMENAx - Transmit data DMA channel enable. */
-#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_FLD32(14)
+#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14)
/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
-#define TMS570_SPI_DMACTRL_NOBRKx BSP_FLD32(13)
+#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13)
/* field: ICOUNTx - Initial count of DMA transfers. */
#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
@@ -804,7 +804,7 @@ typedef struct{
#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
-#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_FLD32(6)
+#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6)
/* field: COUNTx - Actual number of remaining DMA transfers. */
#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
@@ -812,7 +812,7 @@ typedef struct{
#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
-/*---------------------TMS570_SPIDMACOUNT---------------------*/
+/*--------------------TMS570_SPI_DMACOUNT--------------------*/
/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
@@ -824,14 +824,14 @@ typedef struct{
#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_SPIDMACNTLEN--------------------*/
+/*--------------------TMS570_SPI_DMACNTLEN--------------------*/
/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
-#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_FLD32(0)
+#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0)
-/*---------------------TMS570_SPIUERRCTRL---------------------*/
+/*--------------------TMS570_SPI_UERRCTRL--------------------*/
/* field: PTESTEN - Parity memory test enable. */
-#define TMS570_SPI_UERRCTRL_PTESTEN BSP_FLD32(8)
+#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8)
/* field: EDEN - Error detection enable. These bits enable parity error detection. */
#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
@@ -839,53 +839,53 @@ typedef struct{
#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SPIUERRSTAT---------------------*/
+/*--------------------TMS570_SPI_UERRSTAT--------------------*/
/* field: EDFLG1 - RXRAM. */
-#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_FLD32(1)
+#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1)
/* field: EDFLG0 - Uncorrectable parity error detection flag. */
-#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_FLD32(0)
+#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0)
-/*--------------------TMS570_SPIUERRADDRRX--------------------*/
+/*-------------------TMS570_SPI_UERRADDRRX-------------------*/
/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*--------------------TMS570_SPIUERRADDRTX--------------------*/
+/*-------------------TMS570_SPI_UERRADDRTX-------------------*/
/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*-----------------TMS570_SPIRXOVRN_BUF_ADDR-----------------*/
+/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/
/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
-/*-------------------TMS570_SPIIOLPBKTSTCR-------------------*/
+/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/
/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
-#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_FLD32(24)
+#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24)
/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_FLD32(20)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20)
/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_FLD32(19)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19)
/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_FLD32(18)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18)
/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_FLD32(17)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17)
/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_FLD32(16)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16)
/* field: IOLPBKSTENA - Module I/O loopback test enable key. */
#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
@@ -898,21 +898,21 @@ typedef struct{
#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
-#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_FLD32(2)
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2)
/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
-#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_FLD32(1)
+#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1)
/* field: RXP_ENA - Enable analog loopback through the receive pin. */
-#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_FLD32(0)
+#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0)
-/*------------------TMS570_SPIEXT_PRESCALE1------------------*/
-/* field: EPRESCALE_FMT1 - EPRESCALE_FMT1. Extended Prescale value for SPIFMT1. */
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1(val) BSP_FLD32(val,16, 26)
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_GET(reg) BSP_FLD32GET(reg,16, 26)
-#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
+/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/
+/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26)
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26)
+#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
-#endif /* LIBBSP_ARM_tms570_SPI */
+#endif /* LIBBSP_ARM_TMS570_SPI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
index a841ca5..e935f45 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_STC
-#define LIBBSP_ARM_tms570_STC
+#ifndef LIBBSP_ARM_TMS570_STC
+#define LIBBSP_ARM_TMS570_STC
#include <bsp/utility.h>
@@ -61,122 +61,92 @@ typedef struct{
} tms570_stc_t;
-/*---------------------TMS570_STCSTCGCR0---------------------*/
+/*---------------------TMS570_STC_STCGCR0---------------------*/
/* field: INTCOUNT - Number of intervals of self-test run */
#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
/* field: RS_CNT - Restart or Continue */
-#define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0)
+#define TMS570_STC_STCGCR0_RS_CNT BSP_BIT32(0)
-/*---------------------TMS570_STCSTCGCR1---------------------*/
+/*---------------------TMS570_STC_STCGCR1---------------------*/
/* field: STC_ENA - Self-test run enable key */
#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_STCSTCTPR----------------------*/
+/*---------------------TMS570_STC_STCTPR---------------------*/
/* field: RTOD - Self-test timeout count preload */
-#define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_STCSTC_CADDR--------------------*/
+/*--------------------TMS570_STC_STC_CADDR--------------------*/
/* field: ADDR - Current ROM Address */
-#define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_STCSTCCICR---------------------*/
+/*---------------------TMS570_STC_STCCICR---------------------*/
/* field: N - Interval Number */
#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_STCSTCGSTAT---------------------*/
+/*--------------------TMS570_STC_STCGSTAT--------------------*/
/* field: TEST_FAIL - Test Fail */
-#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1)
+#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_BIT32(1)
/* field: TEST_DONE - Test Done */
-#define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0)
+#define TMS570_STC_STCGSTAT_TEST_DONE BSP_BIT32(0)
-/*---------------------TMS570_STCSTCFSTAT---------------------*/
+/*--------------------TMS570_STC_STCFSTAT--------------------*/
/* field: TO_ERR - Timeout Error */
-#define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2)
+#define TMS570_STC_STCFSTAT_TO_ERR BSP_BIT32(2)
/* field: CPU2_FAIL - CPU2 failure info */
-#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1)
+#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_BIT32(1)
/* field: CPU1_FAIL - CPU1 failure info */
-#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0)
+#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_BIT32(0)
-/*------------------TMS570_STCCPU1_CURMISR3------------------*/
+/*------------------TMS570_STC_CPU1_CURMISR3------------------*/
/* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_STCCPU1_CURMISR2------------------*/
+/*------------------TMS570_STC_CPU1_CURMISR2------------------*/
/* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_STCCPU1_CURMISR1------------------*/
+/*------------------TMS570_STC_CPU1_CURMISR1------------------*/
/* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_STCCPU1_CURMISR0------------------*/
+/*------------------TMS570_STC_CPU1_CURMISR0------------------*/
/* field: MISR - MISR data from CPU1 */
-#define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_STCCPU2_CURMISR3------------------*/
+/*------------------TMS570_STC_CPU2_CURMISR3------------------*/
/* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_STCCPU2_CURMISR2------------------*/
+/*------------------TMS570_STC_CPU2_CURMISR2------------------*/
/* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*------------------TMS570_STCCPU2_CURMISR1------------------*/
+/*------------------TMS570_STC_CPU2_CURMISR1------------------*/
/* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*------------------TMS570_STCCPU2_CURMISR0------------------*/
+/*------------------TMS570_STC_CPU2_CURMISR0------------------*/
/* field: MISR - MISR data from CPU2 */
-#define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
-#define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_STCSTCSCSCR---------------------*/
+/*--------------------TMS570_STC_STCSCSCR--------------------*/
/* field: FAULT_INS - Enable / Disable fault insertion. */
-#define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4)
+#define TMS570_STC_STCSCSCR_FAULT_INS BSP_BIT32(4)
/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
@@ -185,4 +155,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_STC */
+#endif /* LIBBSP_ARM_TMS570_STC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
index 88fe860..e191970 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_SYS1
-#define LIBBSP_ARM_tms570_SYS1
+#ifndef LIBBSP_ARM_TMS570_SYS1
+#define LIBBSP_ARM_TMS570_SYS1
#include <bsp/utility.h>
@@ -105,12 +105,12 @@ typedef struct{
} tms570_sys1_t;
-/*---------------------TMS570_SYS1SYSPC1---------------------*/
+/*---------------------TMS570_SYS1_SYSPCx---------------------*/
/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
-#define TMS570_SYS1_SYSPC1_ECPCLKFUN BSP_FLD32(0)
+#define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0)
-/*----------------------TMS570_SYS1CSDIS----------------------*/
+/*---------------------TMS570_SYS1_CSDIS---------------------*/
/* field: CLKSROFF - Clock source[7-3] off. */
#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7)
#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -122,7 +122,7 @@ typedef struct{
#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*--------------------TMS570_SYS1CSDISSET--------------------*/
+/*--------------------TMS570_SYS1_CSDISSET--------------------*/
/* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */
#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -134,7 +134,7 @@ typedef struct{
#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*--------------------TMS570_SYS1CSDISCLR--------------------*/
+/*--------------------TMS570_SYS1_CSDISCLR--------------------*/
/* field: CLRCLKSR_OFF - Enables clock source[7-3]. */
#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7)
#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -146,17 +146,17 @@ typedef struct{
#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*----------------------TMS570_SYS1CDDIS----------------------*/
+/*---------------------TMS570_SYS1_CDDIS---------------------*/
/* field: VCLKAOFF - VCLKA[4-3] domain off. */
#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11)
#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
/* field: VCLK3OFF - VCLK3 domain off. */
-#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8)
/* field: RTICLK1OFF - RTICLK1 domain off. */
-#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6)
/* field: VCLKAOFF - VCLKA[2-1] domain off. */
#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5)
@@ -164,84 +164,84 @@ typedef struct{
#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
/* field: VCLK2OFF - VCLK2 domain off. */
-#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3)
/* field: VCLKPOFF - VCLK_periph domain off. */
-#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2)
/* field: HCLKOFF - HCLK and VCLK_sys domains off. */
-#define TMS570_SYS1_CDDIS_HCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1)
/* field: GCLKOFF - GCLK domain off. */
-#define TMS570_SYS1_CDDIS_GCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0)
-/*--------------------TMS570_SYS1CDDISSET--------------------*/
+/*--------------------TMS570_SYS1_CDDISSET--------------------*/
/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
/* field: SETVCLK3OFF - Set VCLK3 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8)
/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
-#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6)
/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
-#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_FLD32(5)
+#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5)
/* field: SETVCLKA1OFF - Set VCLKA1 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_FLD32(4)
+#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4)
/* field: SETVCLK2OFF - Set VCLK2 domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3)
/* field: SETVCLKPOFF - Set VCLK_periph domain. */
-#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2)
/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
-#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1)
/* field: SETGCLKOFF - Set GCLK domain. */
-#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0)
-/*--------------------TMS570_SYS1CDDISCLR--------------------*/
+/*--------------------TMS570_SYS1_CDDISCLR--------------------*/
/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
/* field: Reserved - Reserved */
-#define TMS570_SYS1_CDDISCLR_Reserved BSP_FLD32(9)
+#define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9)
/* field: CLRVCLK3OFF - Clear VCLK3 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_FLD32(8)
+#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8)
/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_FLD32(6)
+#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6)
/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_FLD32(5)
+#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5)
/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_FLD32(4)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4)
/* field: CLRVCLK2OFF - Clear VCLK2 domain. */
-#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_FLD32(3)
+#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3)
/* field: CLRVCLKPOFF - CLRVCLKPOFF */
-#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_FLD32(2)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2)
/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
-#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_FLD32(1)
+#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1)
/* field: CLRGCLKOFF - Clear GCLK domain. */
-#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_FLD32(0)
+#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0)
-/*---------------------TMS570_SYS1GHVSRC---------------------*/
+/*---------------------TMS570_SYS1_GHVSRC---------------------*/
/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -258,7 +258,7 @@ typedef struct{
#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_SYS1VCLKASRC--------------------*/
+/*--------------------TMS570_SYS1_VCLKASRC--------------------*/
/* field: VCLKA2S - Peripheral asynchronous clock2 source. */
#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
@@ -270,7 +270,7 @@ typedef struct{
#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS1RCLKSRC---------------------*/
+/*--------------------TMS570_SYS1_RCLKSRC--------------------*/
/* field: RTI1DIV - RTI clock1 Divider. */
#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -282,7 +282,7 @@ typedef struct{
#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS1CSVSTAT---------------------*/
+/*--------------------TMS570_SYS1_CSVSTAT--------------------*/
/* field: CLKSRV - Clock source[7-0] valid. */
#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
@@ -294,7 +294,7 @@ typedef struct{
#define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_SYS1MSTGCR---------------------*/
+/*---------------------TMS570_SYS1_MSTGCR---------------------*/
/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
@@ -306,38 +306,32 @@ typedef struct{
#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_SYS1MINITGCR--------------------*/
+/*--------------------TMS570_SYS1_MINITGCR--------------------*/
/* field: MINITGENA - Memory hardware initialization global enable key. */
#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS1MSIENA---------------------*/
+/*---------------------TMS570_SYS1_MSIENA---------------------*/
/* field: MSIENA - PBIST controller and memory initialization enable register. */
-#define TMS570_SYS1_MSIENA_MSIENA(val) BSP_FLD32(val,0, 31)
-#define TMS570_SYS1_MSIENA_MSIENA_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_MSIENA_MSIENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_SYS1MSTCGSTAT--------------------*/
+/*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/
/* field: MINIDONE - Memory hardware initialization complete status. */
-#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_FLD32(8)
+#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8)
/* field: MSTDONE - Memory self-test run complete status. */
-#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_FLD32(0)
+#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0)
-/*--------------------TMS570_SYS1MINISTAT--------------------*/
+/*--------------------TMS570_SYS1_MINISTAT--------------------*/
/* field: MIDONE - Memory hardware initialization status bit. */
-#define TMS570_SYS1_MINISTAT_MIDONE(val) BSP_FLD32(val,0, 31)
-#define TMS570_SYS1_MINISTAT_MIDONE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_MINISTAT_MIDONE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*---------------------TMS570_SYS1PLLCTL1---------------------*/
+/*--------------------TMS570_SYS1_PLLCTL1--------------------*/
/* field: ROS - Reset on PLL Slip */
-#define TMS570_SYS1_PLLCTL1_ROS BSP_FLD32(31)
+#define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
/* field: MASK_SLIP - Mask detection of PLL slip */
#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
@@ -350,7 +344,7 @@ typedef struct{
#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
/* field: ROF - Reset on Oscillator Fail */
-#define TMS570_SYS1_PLLCTL1_ROF BSP_FLD32(23)
+#define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23)
/* field: REFCLKDIV - Reference Clock Divider */
#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
@@ -363,9 +357,9 @@ typedef struct{
#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SYS1PLLCTL2---------------------*/
+/*--------------------TMS570_SYS1_PLLCTL2--------------------*/
/* field: FMENA - Frequency Modulation Enable. */
-#define TMS570_SYS1_PLLCTL2_FMENA BSP_FLD32(31)
+#define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31)
/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
@@ -388,12 +382,12 @@ typedef struct{
#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
-/*---------------------TMS570_SYS1SYSPC10---------------------*/
+/*--------------------TMS570_SYS1_SYSPC10--------------------*/
/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
-#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_FLD32(0)
+#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
-/*---------------------TMS570_SYS1DIEIDL---------------------*/
+/*---------------------TMS570_SYS1_DIEIDL---------------------*/
/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
@@ -415,19 +409,19 @@ typedef struct{
#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_SYS1DIEIDH---------------------*/
+/*---------------------TMS570_SYS1_DIEIDH---------------------*/
/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
-/*--------------------TMS570_SYS1LPOMONCTL--------------------*/
+/*-------------------TMS570_SYS1_LPOMONCTL-------------------*/
/* field: BIAS_ENABLE - Bias enable. */
-#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
-#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
/* field: HFTRIM - High frequency oscillator trim value. */
#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
@@ -435,15 +429,15 @@ typedef struct{
#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
-/*---------------------TMS570_SYS1CLKTEST---------------------*/
+/*--------------------TMS570_SYS1_CLKTEST--------------------*/
/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
-#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
/* field: RANGEDETCTRL - Range detection control. */
-#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
-#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
@@ -461,7 +455,7 @@ typedef struct{
#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_SYS1DFTCTRLREG1-------------------*/
+/*------------------TMS570_SYS1_DFTCTRLREG1------------------*/
/* field: DFTWRITE - DFT logic access. */
#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
@@ -478,7 +472,7 @@ typedef struct{
#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_SYS1DFTCTRLREG2-------------------*/
+/*------------------TMS570_SYS1_DFTCTRLREG2------------------*/
/* field: IMPDF - DFT Implementation defined bits. */
#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
@@ -490,9 +484,9 @@ typedef struct{
#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS1GPREG1---------------------*/
+/*---------------------TMS570_SYS1_GPREG1---------------------*/
/* field: EMIF_FUNC - Enable EMIF functions to be output. */
-#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_FLD32(31)
+#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31)
/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
@@ -510,56 +504,53 @@ typedef struct{
#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_SYS1IMPFASTS--------------------*/
+/*--------------------TMS570_SYS1_IMPFASTS--------------------*/
/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
-#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_FLD32(0)
+#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0)
-/*--------------------TMS570_SYS1IMPFTADD--------------------*/
+/*--------------------TMS570_SYS1_IMPFTADD--------------------*/
/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
-#define TMS570_SYS1_IMPFTADD_IMPFTADD(val) BSP_FLD32(val,0, 31)
-#define TMS570_SYS1_IMPFTADD_IMPFTADD_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS1_IMPFTADD_IMPFTADD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_SYS1SSIR1----------------------*/
+/*---------------------TMS570_SYS1_SSIRx---------------------*/
/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
-#define TMS570_SYS1_SSIR1_SSKEY1(val) BSP_FLD32(val,8, 15)
-#define TMS570_SYS1_SSIR1_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
-#define TMS570_SYS1_SSIR1_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
-#define TMS570_SYS1_SSIR1_SSDATA1(val) BSP_FLD32(val,0, 7)
-#define TMS570_SYS1_SSIR1_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
-#define TMS570_SYS1_SSIR1_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_SYS1RAMGCR---------------------*/
+/*---------------------TMS570_SYS1_RAMGCR---------------------*/
/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
-#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_FLD32(2)
+#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2)
/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
-#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_FLD32(0)
+#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0)
-/*---------------------TMS570_SYS1BMMCR1---------------------*/
+/*---------------------TMS570_SYS1_BMMCR1---------------------*/
/* field: MEMSW - Memory swap key. */
#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_SYS1CPURSTCR--------------------*/
+/*--------------------TMS570_SYS1_CPURSTCR--------------------*/
/* field: CPU_RESET - CPU Reset. */
-#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_FLD32(0)
+#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0)
-/*---------------------TMS570_SYS1CLKCNTL---------------------*/
+/*--------------------TMS570_SYS1_CLKCNTL--------------------*/
/* field: VCLK2R - VBUS clock2 ratio. */
#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
@@ -571,15 +562,15 @@ typedef struct{
#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: PENA - Peripheral enable bit. */
-#define TMS570_SYS1_CLKCNTL_PENA BSP_FLD32(8)
+#define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8)
-/*---------------------TMS570_SYS1ECPCNTL---------------------*/
+/*--------------------TMS570_SYS1_ECPCNTL--------------------*/
/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
-#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_FLD32(24)
+#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24)
/* field: ECPCOS - ECP continue on suspend. */
-#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_FLD32(23)
+#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23)
/* field: ECPINSEL - Select ECP input clock source. */
#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
@@ -592,64 +583,64 @@ typedef struct{
#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*---------------------TMS570_SYS1DEVCR1---------------------*/
+/*---------------------TMS570_SYS1_DEVCR1---------------------*/
/* field: DEVPARSEL - Device parity select bit key. */
#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS1SYSECR---------------------*/
+/*---------------------TMS570_SYS1_SYSECR---------------------*/
/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
-/*---------------------TMS570_SYS1SYSESR---------------------*/
+/*---------------------TMS570_SYS1_SYSESR---------------------*/
/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
-#define TMS570_SYS1_SYSESR_PORST BSP_FLD32(15)
+#define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15)
/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
-#define TMS570_SYS1_SYSESR_OSCRST BSP_FLD32(14)
+#define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14)
/* field: WDRST - Watchdog reset flag. */
-#define TMS570_SYS1_SYSESR_WDRST BSP_FLD32(13)
+#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
-#define TMS570_SYS1_SYSESR_CPURST BSP_FLD32(5)
+#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
-#define TMS570_SYS1_SYSESR_SWRST BSP_FLD32(4)
+#define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4)
/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
-#define TMS570_SYS1_SYSESR_EXTRST BSP_FLD32(3)
+#define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3)
/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
-#define TMS570_SYS1_SYSESR_MPMODE BSP_FLD32(0)
+#define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0)
-/*---------------------TMS570_SYS1SYSTASR---------------------*/
+/*--------------------TMS570_SYS1_SYSTASR--------------------*/
/* field: EFUSE_Abort - Test Abort status flag. */
#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
-/*---------------------TMS570_SYS1GLBSTAT---------------------*/
+/*--------------------TMS570_SYS1_GLBSTAT--------------------*/
/* field: FBSLIP - PLL over cycle slip detection. */
-#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_FLD32(9)
+#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9)
/* field: RFSLIP - PLL under cycle slip detection. */
-#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_FLD32(8)
+#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8)
/* field: OSCFAIL - Oscillator fail flag bit. */
-#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_FLD32(0)
+#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0)
-/*----------------------TMS570_SYS1DEVID----------------------*/
+/*---------------------TMS570_SYS1_DEVID---------------------*/
/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
-#define TMS570_SYS1_DEVID_CP15 BSP_FLD32(31)
+#define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31)
/* field: TECH - These bits define the process technology by which the device was manufactured. */
#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
@@ -657,10 +648,10 @@ typedef struct{
#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
-#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_FLD32(12)
+#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12)
/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
-#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_FLD32(11)
+#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11)
/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
@@ -668,7 +659,7 @@ typedef struct{
#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
-#define TMS570_SYS1_DEVID_RAM_ECC BSP_FLD32(8)
+#define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8)
/* field: VERSION - Version. These bits provide the revision of the device. */
#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
@@ -681,7 +672,7 @@ typedef struct{
#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
-/*---------------------TMS570_SYS1SSIVEC---------------------*/
+/*---------------------TMS570_SYS1_SSIVEC---------------------*/
/* field: SSIDATA - System software interrupt data key. */
#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
@@ -693,7 +684,7 @@ typedef struct{
#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_SYS1SSIF----------------------*/
+/*----------------------TMS570_SYS1_SSIF----------------------*/
/* field: SSI_FLAG - System software interrupt flag[4-1]. */
#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
@@ -701,4 +692,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_SYS1 */
+#endif /* LIBBSP_ARM_TMS570_SYS1 */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
index f936661..29ec5a1 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_SYS2
-#define LIBBSP_ARM_tms570_SYS2
+#ifndef LIBBSP_ARM_TMS570_SYS2
+#define LIBBSP_ARM_TMS570_SYS2
#include <bsp/utility.h>
@@ -61,7 +61,7 @@ typedef struct{
} tms570_sys2_t;
-/*---------------------TMS570_SYS2PLLCTL3---------------------*/
+/*--------------------TMS570_SYS2_PLLCTL3--------------------*/
/* field: ODPLL2 - Internal PLL Output Divider */
#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
@@ -83,19 +83,19 @@ typedef struct{
#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_SYS2STCCLKDIV--------------------*/
+/*-------------------TMS570_SYS2_STCCLKDIV-------------------*/
/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
-/*---------------------TMS570_SYS2ECPCNTL---------------------*/
+/*--------------------TMS570_SYS2_ECPCNTL--------------------*/
/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
-#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24)
+#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_BIT32(24)
/* field: ECPCOS - ECP continue on suspend. */
-#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23)
+#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_BIT32(23)
/* field: ECPINSEL - Select ECP input clock source. */
#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
@@ -108,21 +108,21 @@ typedef struct{
#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_SYS2CLK2CNTRL--------------------*/
+/*-------------------TMS570_SYS2_CLK2CNTRL-------------------*/
/* field: VCLK3R - VBUS clock3 ratio. */
#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*--------------------TMS570_SYS2VCLKACON1--------------------*/
+/*-------------------TMS570_SYS2_VCLKACON1-------------------*/
/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
-#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20)
+#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_BIT32(20)
/* field: VCLKA4S - Peripheral asynchronous clock4 source. */
#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
@@ -135,7 +135,7 @@ typedef struct{
#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
-#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4)
+#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_BIT32(4)
/* field: VCLKA3S - Peripheral asynchronous clock3 source. */
#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
@@ -143,7 +143,7 @@ typedef struct{
#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*---------------------TMS570_SYS2CLKSLIP---------------------*/
+/*--------------------TMS570_SYS2_CLKSLIP--------------------*/
/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
@@ -155,19 +155,16 @@ typedef struct{
#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_SYS2EFC_CTLREG-------------------*/
+/*-------------------TMS570_SYS2_EFC_CTLREG-------------------*/
/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-------------------TMS570_SYS2DIEDL_REG0-------------------*/
+/*-----------------------TMS570_SYS2_x-----------------------*/
/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
-#define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31)
-#define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-#endif /* LIBBSP_ARM_tms570_SYS2 */
+#endif /* LIBBSP_ARM_TMS570_SYS2 */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
index e71dd52..5304504 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_TCR
-#define LIBBSP_ARM_tms570_TCR
+#ifndef LIBBSP_ARM_TMS570_TCR
+#define LIBBSP_ARM_TMS570_TCR
#include <bsp/utility.h>
@@ -47,21 +47,21 @@ typedef struct{
} tms570_tcr_t;
-/*-----------------------TMS570_TCRTCR-----------------------*/
+/*-----------------------TMS570_TCR_TCR-----------------------*/
/* field: STXR - Set Transmit Request. */
-#define TMS570_TCR_TCR_STXR BSP_FLD32(18)
+#define TMS570_TCR_TCR_STXR BSP_BIT32(18)
/* field: THTSM - Transfer Header to System Memory. */
-#define TMS570_TCR_TCR_THTSM BSP_FLD32(17)
+#define TMS570_TCR_TCR_THTSM BSP_BIT32(17)
/* field: TPTSM - Transfer Payload to System Memory. */
-#define TMS570_TCR_TCR_TPTSM BSP_FLD32(16)
+#define TMS570_TCR_TCR_TPTSM BSP_BIT32(16)
/* field: THTCC - Transfer Header to Communication Controller. */
-#define TMS570_TCR_TCR_THTCC BSP_FLD32(15)
+#define TMS570_TCR_TCR_THTCC BSP_BIT32(15)
/* field: TPTCC - Transfer Payload to Communication Controller. */
-#define TMS570_TCR_TCR_TPTCC BSP_FLD32(14)
+#define TMS570_TCR_TCR_TPTCC BSP_BIT32(14)
/* field: TSO - Transfer Start Offset. */
#define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13)
@@ -69,16 +69,16 @@ typedef struct{
#define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
-/*--------------------TMS570_TCRTCR_Parity--------------------*/
+/*-------------------TMS570_TCR_TCR_Parity-------------------*/
/* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */
-#define TMS570_TCR_TCR_Parity_PAB2 BSP_FLD32(16)
+#define TMS570_TCR_TCR_Parity_PAB2 BSP_BIT32(16)
/* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */
-#define TMS570_TCR_TCR_Parity_PAB1 BSP_FLD32(8)
+#define TMS570_TCR_TCR_Parity_PAB1 BSP_BIT32(8)
/* field: PAB0 - Parity Bit for Byte 0. */
-#define TMS570_TCR_TCR_Parity_PAB0 BSP_FLD32(0)
+#define TMS570_TCR_TCR_Parity_PAB0 BSP_BIT32(0)
-#endif /* LIBBSP_ARM_tms570_TCR */
+#endif /* LIBBSP_ARM_TMS570_TCR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
index 9092bfe..1a48848 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_TCRAM
-#define LIBBSP_ARM_tms570_TCRAM
+#ifndef LIBBSP_ARM_TMS570_TCRAM
+#define LIBBSP_ARM_TMS570_TCRAM
#include <bsp/utility.h>
@@ -58,9 +58,9 @@ typedef struct{
} tms570_tcram_t;
-/*--------------------TMS570_TCRAMRAMCTRL--------------------*/
+/*--------------------TMS570_TCRAM_RAMCTRL--------------------*/
/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
-#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_FLD32(30)
+#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_BIT32(30)
/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
@@ -73,7 +73,7 @@ typedef struct{
#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
/* field: ECC_WR_EN - ECC Memory Write Enable. */
-#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_FLD32(8)
+#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_BIT32(8)
/* field: ECC_DETECT_EN - ECC Detect Enable. */
#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
@@ -81,62 +81,62 @@ typedef struct{
#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*------------------TMS570_TCRAMRAMTHRESHOLD------------------*/
+/*-----------------TMS570_TCRAM_RAMTHRESHOLD-----------------*/
/* field: THRESHOLD - Single-bit Error Threshold Count. */
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*--------------------TMS570_TCRAMRAMOCCUR--------------------*/
+/*-------------------TMS570_TCRAM_RAMOCCUR-------------------*/
/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_TCRAMRAMINTCTRL-------------------*/
+/*------------------TMS570_TCRAM_RAMINTCTRL------------------*/
/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
-#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_FLD32(0)
+#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_BIT32(0)
-/*------------------TMS570_TCRAMRAMERRSTATUS------------------*/
+/*-----------------TMS570_TCRAM_RAMERRSTATUS-----------------*/
/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
-#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_FLD32(9)
+#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_BIT32(9)
/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
-#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_FLD32(8)
+#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_BIT32(8)
/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
-#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_FLD32(5)
+#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_BIT32(5)
/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
-#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_FLD32(4)
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_BIT32(4)
/* field: ADDR_DEC_FAIL - Address decode failed. */
-#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_FLD32(2)
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_BIT32(2)
/* field: SERR - Single Error Status. */
-#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_FLD32(0)
+#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_BIT32(0)
-/*------------------TMS570_TCRAMRAMSERRADDR------------------*/
+/*------------------TMS570_TCRAM_RAMSERRADDR------------------*/
/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
-/*------------------TMS570_TCRAMRAMUERRADDR------------------*/
+/*------------------TMS570_TCRAM_RAMUERRADDR------------------*/
/* field: UNCORRECTABLE - address parity error. */
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
-/*--------------------TMS570_TCRAMRAMTEST--------------------*/
+/*--------------------TMS570_TCRAM_RAMTEST--------------------*/
/* field: TRIGGER - Test Trigger. */
-#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_FLD32(8)
+#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_BIT32(8)
/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
@@ -149,9 +149,9 @@ typedef struct{
#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*-----------------TMS570_TCRAMRAMADDRDECVECT-----------------*/
+/*----------------TMS570_TCRAM_RAMADDRDECVECT----------------*/
/* field: ECC_SELECT - ECC Select. */
-#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_FLD32(26)
+#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_BIT32(26)
/* field: RAM_CHIP_SELECT - RAM Chip Select. */
#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
@@ -159,7 +159,7 @@ typedef struct{
#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
-/*-------------------TMS570_TCRAMRAMPERADDR-------------------*/
+/*------------------TMS570_TCRAM_RAMPERADDR------------------*/
/* field: ADDRESS_PARITY - Parity Error Address. */
#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
@@ -167,4 +167,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_TCRAM */
+#endif /* LIBBSP_ARM_TMS570_TCRAM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
index a52c376..d0347a4 100644
--- a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
@@ -36,8 +36,8 @@
* of the authors and should not be interpreted as representing official policies,
* either expressed or implied, of the FreeBSD Project.
*/
-#ifndef LIBBSP_ARM_tms570_VIM
-#define LIBBSP_ARM_tms570_VIM
+#ifndef LIBBSP_ARM_TMS570_VIM
+#define LIBBSP_ARM_TMS570_VIM
#include <bsp/utility.h>
@@ -70,14 +70,14 @@ typedef struct{
} tms570_vim_t;
-/*----------------------TMS570_VIMPARFLG----------------------*/
+/*---------------------TMS570_VIM_PARFLG---------------------*/
/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
-#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
+#define TMS570_VIM_PARFLG_PARFLG BSP_BIT32(0)
-/*----------------------TMS570_VIMPARCTL----------------------*/
+/*---------------------TMS570_VIM_PARCTL---------------------*/
/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
-#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
+#define TMS570_VIM_PARCTL_TEST BSP_BIT32(8)
/* field: PARENA - VIM parity enable. */
#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
@@ -85,7 +85,7 @@ typedef struct{
#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
-/*----------------------TMS570_VIMADDERR----------------------*/
+/*---------------------TMS570_VIM_ADDERR---------------------*/
/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
@@ -102,84 +102,57 @@ typedef struct{
#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
-/*---------------------TMS570_VIMFBPARERR---------------------*/
+/*--------------------TMS570_VIM_FBPARERR--------------------*/
/* field: FBPARERR - Fall back address parity error. */
-#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*---------------------TMS570_VIMIRQINDEX---------------------*/
+/*--------------------TMS570_VIM_IRQINDEX--------------------*/
/* field: IRQINDEX - IRQ index vector. */
#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*---------------------TMS570_VIMFIQINDEX---------------------*/
+/*--------------------TMS570_VIM_FIQINDEX--------------------*/
/* field: FIQINDEX - FIQ index offset vector. */
#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
-/*----------------------TMS570_VIMFIRQPR----------------------*/
+/*---------------------TMS570_VIM_FIRQPR---------------------*/
/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_VIMINTREQ----------------------*/
+/*---------------------TMS570_VIM_INTREQ---------------------*/
/* field: INTREQx - Pending interrupt bits. 96 bit register. */
-#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_VIMREQENASET--------------------*/
+/*--------------------TMS570_VIM_REQENASET--------------------*/
/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_VIMREQENACLR--------------------*/
+/*--------------------TMS570_VIM_REQENACLR--------------------*/
/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
-#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_VIMWAKEENASET--------------------*/
+/*-------------------TMS570_VIM_WAKEENASET-------------------*/
/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
-#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_VIMWAKEENACLR--------------------*/
+/*-------------------TMS570_VIM_WAKEENACLR-------------------*/
/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*--------------------TMS570_VIMIRQVECREG--------------------*/
+/*--------------------TMS570_VIM_IRQVECREG--------------------*/
/* field: IRQVECREG - IRQ interrupt vector register. */
-#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+/* Whole 32 bits */
-
-/*--------------------TMS570_VIMFIQVECREG--------------------*/
+/*--------------------TMS570_VIM_FIQVECREG--------------------*/
/* field: FIQVECREG - FIQ interrupt vector register. */
-#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
-#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
-#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
-
+/* Whole 32 bits */
-/*----------------------TMS570_VIMCAPEVT----------------------*/
+/*---------------------TMS570_VIM_CAPEVT---------------------*/
/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
@@ -191,7 +164,7 @@ typedef struct{
#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
-/*---------------------TMS570_VIMCHANCTRL---------------------*/
+/*--------------------TMS570_VIM_CHANCTRL--------------------*/
/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
@@ -214,4 +187,4 @@ typedef struct{
-#endif /* LIBBSP_ARM_tms570_VIM */
+#endif /* LIBBSP_ARM_TMS570_VIM */
--
1.9.1
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