[PATCH 2/3] bsp/tms570: New/generated header files for TMS570 SoC peripherals registers.
Premysl Houdek
kom541000 at gmail.com
Thu Jul 16 12:14:31 UTC 2015
The header files are generated by script make_header.py.
Current script's version can be found at:
https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python
Registers offsets and fields have been extracted from reference manual.
Signed-off-by: Premysl Houdek <kom541000 at gmail.com>
---
c/src/lib/libbsp/arm/tms570/Makefile.am | 39 +
.../libbsp/arm/tms570/include/ti_herc/reg_adc.h | 626 ++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h | 72 ++
.../libbsp/arm/tms570/include/ti_herc/reg_crc.h | 427 +++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_dcan.h | 962 +++++++++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_dcc.h | 183 ++++
.../libbsp/arm/tms570/include/ti_herc/reg_dma.h | 732 ++++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_dmm.h | 560 ++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_efuse.h | 132 +++
.../libbsp/arm/tms570/include/ti_herc/reg_emac.h | 239 +++++
.../libbsp/arm/tms570/include/ti_herc/reg_emacm.h | 922 ++++++++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_emif.h | 471 ++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_esm.h | 215 +++++
.../libbsp/arm/tms570/include/ti_herc/reg_flash.h | 687 +++++++++++++++
.../arm/tms570/include/ti_herc/reg_flex_ray.h | 801 +++++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_gio.h | 324 +++++++
.../libbsp/arm/tms570/include/ti_herc/reg_htu.h | 351 ++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_i2c.h | 363 ++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_iomm.h | 244 ++++++
.../libbsp/arm/tms570/include/ti_herc/reg_lin.h | 594 +++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_mdio.h | 239 +++++
.../libbsp/arm/tms570/include/ti_herc/reg_n2het.h | 377 ++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_pbist.h | 213 +++++
.../libbsp/arm/tms570/include/ti_herc/reg_pcr.h | 150 ++++
.../libbsp/arm/tms570/include/ti_herc/reg_pll.h | 304 +++++++
.../libbsp/arm/tms570/include/ti_herc/reg_pmm.h | 258 ++++++
.../libbsp/arm/tms570/include/ti_herc/reg_pom.h | 336 +++++++
.../libbsp/arm/tms570/include/ti_herc/reg_rti.h | 407 +++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_rtp.h | 230 +++++
.../libbsp/arm/tms570/include/ti_herc/reg_sci.h | 450 ++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_spi.h | 918 ++++++++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_stc.h | 188 ++++
.../libbsp/arm/tms570/include/ti_herc/reg_sys.h | 704 +++++++++++++++
.../libbsp/arm/tms570/include/ti_herc/reg_sys2.h | 173 ++++
.../libbsp/arm/tms570/include/ti_herc/reg_tcr.h | 84 ++
.../libbsp/arm/tms570/include/ti_herc/reg_tcram.h | 170 ++++
.../libbsp/arm/tms570/include/ti_herc/reg_vim.h | 217 +++++
37 files changed, 14362 insertions(+)
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
create mode 100644 c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
diff --git a/c/src/lib/libbsp/arm/tms570/Makefile.am b/c/src/lib/libbsp/arm/tms570/Makefile.am
index 6cad609..b9c7fd4 100644
--- a/c/src/lib/libbsp/arm/tms570/Makefile.am
+++ b/c/src/lib/libbsp/arm/tms570/Makefile.am
@@ -11,6 +11,8 @@ include $(top_srcdir)/../../../../automake/compile.am
include_bspdir = $(includedir)/bsp
+include_bsp_ti_herculesdir = $(includedir)/bsp/ti_herc
+
dist_project_lib_DATA = bsp_specs
# ----------------------------
@@ -40,6 +42,43 @@ include_bsp_HEADERS += include/tms570-pom.h
include_bsp_HEADERS += include/tms570-sci-driver.h
include_bsp_HEADERS += include/system-clocks.h
+include_bsp_ti_hercules_HEADERS = include/ti_herc/reg_adc.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_ccmsr.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_crc.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcan.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dcc.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dma.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_dmm.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_efuse.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emac.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emacm.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_emif.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_esm.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_flash.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_flex_ray.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_gio.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_htu.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_i2c.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_iomm.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_lin.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_mdio.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_n2het.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pbist.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pll.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pmm.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_rti.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_rtp.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sci.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_tcr.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_tcram.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_vim.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pom.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_spi.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_stc.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sys.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_sys2.h
+include_bsp_ti_hercules_HEADERS += include/ti_herc/reg_pcr.h
+
include_HEADERS += ../../shared/include/tm27.h
# ----------------------------
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
new file mode 100644
index 0000000..9bd9434
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_adc.h
@@ -0,0 +1,626 @@
+/* The header file is generated by make_header.py from ADC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_ADC
+#define LIBBSP_ARM_tms570_ADC
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t BUF0; /*Group 0-2 result buffer 0 register*/
+ uint32_t BUF1; /*Group 0-2 result buffer 1 register*/
+ uint32_t BUF2; /*Group 0-2 result buffer 2 register*/
+ uint32_t BUF3; /*Group 0-2 result buffer 3 register*/
+ uint32_t BUF4; /*Group 0-2 result buffer 4 register*/
+ uint32_t BUF5; /*Group 0-2 result buffer 5 register*/
+ uint32_t BUF6; /*Group 0-2 result buffer 6 register*/
+ uint32_t BUF7; /*Group 0-2 result buffer 7 register*/
+} tms570_gxbuf_t;
+
+typedef struct{
+ uint32_t RSTCR; /*ADC Reset Control Register*/
+ uint32_t OPMODECR; /*ADC Operating Mode Control Register*/
+ uint32_t CLOCKCR; /*ADC Clock Control Register*/
+ uint32_t CALCR; /*ADC Calibration Mode Control Register*/
+ uint32_t GxMODECR[3]; /*ADC Event Group Operating Mode Control Register*/
+ uint32_t EVSRC; /*ADC Trigger Source Select Register*/
+ uint32_t G1SRC; /*ADC Group1 Trigger Source Select Register*/
+ uint32_t G2SRC; /*ADC Group2 Trigger Source Select Register*/
+ uint32_t GxINTENA[3]; /*ADC Event Interrupt Enable Control Register*/
+ uint32_t GxINTFLG[3]; /*ADC Event Group Interrupt Flag Register*/
+ uint32_t GxINTCR[3]; /*ADC Event Group Threshold Interrupt Control Register*/
+ uint32_t EVDMACR; /*ADC Event Group DMA Control Register*/
+ uint32_t G1DMACR; /*ADC Group1 DMA Control Register*/
+ uint32_t G2DMACR; /*ADC Group2 DMA Control Register*/
+ uint32_t BNDCR; /*ADC Results Memory Configuration Register*/
+ uint32_t BNDEND; /*ADC Results Memory Size Configuration Register*/
+ uint32_t EVSAMP; /*ADC Event Group Sampling Time Configuration Register*/
+ uint32_t G1SAMP; /*ADC Group1 Sampling Time Configuration Register()*/
+ uint32_t G2SAMP; /*ADC Group2 Sampling Time Configuration Register*/
+ uint32_t EVSR; /*ADC Event Group Status Register*/
+ uint32_t G1SR; /*ADC Group1 Status Register*/
+ uint32_t G2SR; /*ADC Group2 Status Register*/
+ uint32_t GxSEL[3]; /*ADC Event Group Channel Select Register*/
+ uint32_t CALR; /*ADC Calibration and Error Offset Correction Register*/
+ uint32_t SMSTATE; /*ADC State Machine Status Register*/
+ uint32_t LASTCONV; /*ADC Channel Last Conversion Value Register*/
+ tms570_gxbuf_t GxBUF[3]; /*ADC Event Group Results Emulation FIFO Register*/
+ uint32_t EVEMUBUFFER; /*ADC Event Group Results Emulation FIFO Register*/
+ uint32_t G1EMUBUFFER; /*ADC Group1 Results Emulation FIFO Register*/
+ uint32_t G2EMUBUFFER; /*ADC Group2 Results Emulation FIFO Register*/
+ uint32_t EVTDIR; /*ADC ADEVT Pin Direction Control Register*/
+ uint32_t EVTOUT; /*ADC ADEVT Pin Output Value Control Register*/
+ uint32_t EVTIN; /*ADC ADEVT Pin Input Value Register*/
+ uint32_t EVTSET; /*ADC ADEVT Pin Set Register*/
+ uint32_t EVTCLR; /*ADC ADEVT Pin Clear Register*/
+ uint32_t EVTPDR; /*ADC ADEVT Pin Open Drain Enable Register*/
+ uint32_t EVTPDIS; /*ADC ADEVT Pin Pull Control Disable Register*/
+ uint32_t EVTPSEL; /*ADC ADEVT Pin Pull Control Select Register*/
+ uint32_t EVSAMPDISEN; /*ADC Event Group Sample Cap Discharge Control Register*/
+ uint32_t G1SAMPDISEN; /*ADC Group1 Sample Cap Discharge Control Register*/
+ uint32_t G2SAMPDISEN; /*ADC Group2 Sample Cap Discharge Control Register*/
+ uint32_t MAGINTCR1; /*ADC Magnitude Compare Interrupt Control Register 2*/
+ uint32_t MAGINT1MASK; /*ADC Magnitude Compare Mask Register 0*/
+ uint32_t MAGINTCR2; /*ADC Magnitude Compare Interrupt Control Register 2*/
+ uint32_t MAGINT2MASK; /*ADC Magnitude Compare Mask Register 0*/
+ uint32_t MAGINTCR3; /*ADC Magnitude Compare Interrupt Control Register 2*/
+ uint32_t MAGINT3MASK; /*ADC Magnitude Compare Mask Register 0*/
+ uint8_t reserved1 [24];
+ uint32_t MAGTHRINTENASET; /*ADC Magnitude Compare Interrupt Enable Set Register*/
+ uint32_t MAGTHRINTENACLR; /*ADC Magnitude Compare Interrupt Enable Clear Register*/
+ uint32_t MAGTHRINTFLG; /*ADC Magnitude Compare Interrupt Flag Register*/
+ uint32_t MAGTHRINTOFFSET; /*ADC Magnitude Compare Interrupt Offset Register*/
+ uint32_t GxFIFORESETCR[3]; /*ADC Event Group FIFO Reset Control Register*/
+ uint32_t EVRAMWRADDR; /*ADC Event Group RAM Write Address Register*/
+ uint32_t G1RAMWRADDR; /*ADC Group1 RAM Write Address Register*/
+ uint32_t G2RAMWRADDR; /*ADC Group2 RAM Write Address Register*/
+ uint32_t PARCR; /*ADC Parity Control Register*/
+ uint32_t PARADDR; /*ADC Parity Error Address Register*/
+ uint32_t PWRUPDLYCTRL; /*ADC Power-Up Delay Control Register*/
+} tms570_adc_t;
+
+
+/*-----------------------TMS570_ADCBUF0-----------------------*/
+/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
+#define TMS570_ADC_BUF0_G2_EMPTY_10bit_mode BSP_FLD32(15)
+
+/* field: G2_CHID_10bit_mode - Group2 Channel Id. */
+#define TMS570_ADC_BUF0_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
+#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
+#define TMS570_ADC_BUF0_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
+
+/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
+#define TMS570_ADC_BUF0_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_BUF0_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_BUF0_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
+#define TMS570_ADC_BUF0_G2_EMPTY_12bit_mode BSP_FLD32(31)
+
+/* field: G2_CHID_12bit_mode - Group2 Channel Id. */
+#define TMS570_ADC_BUF0_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
+#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_ADC_BUF0_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
+#define TMS570_ADC_BUF0_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_BUF0_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_BUF0_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*----------------------TMS570_ADCRSTCR----------------------*/
+/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
+#define TMS570_ADC_RSTCR_RESET BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCOPMODECR---------------------*/
+/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
+#define TMS570_ADC_OPMODECR_10_12_BIT BSP_FLD32(31)
+
+
+/*---------------------TMS570_ADCCLOCKCR---------------------*/
+/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
+#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
+#define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*----------------------TMS570_ADCCALCR----------------------*/
+/* field: SELF_TEST - ADC Self Test Enable. */
+#define TMS570_ADC_CALCR_SELF_TEST BSP_FLD32(24)
+
+/* field: CAL_ST - ADC Calibration Conversion Start. */
+#define TMS570_ADC_CALCR_CAL_ST BSP_FLD32(16)
+
+/* field: BRIDGE_EN - Bridge Enable. */
+#define TMS570_ADC_CALCR_BRIDGE_EN BSP_FLD32(9)
+
+/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
+#define TMS570_ADC_CALCR_HILO BSP_FLD32(8)
+
+/* field: CAL_EN - ADC Calibration Enable. */
+#define TMS570_ADC_CALCR_CAL_EN BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCGxMODECR---------------------*/
+/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
+#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_FLD32(16)
+
+/* field: EV_DATA_FMT - Event Group Read Data Format. */
+#define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
+#define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+
+/*----------------------TMS570_ADCEVSRC----------------------*/
+/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
+#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_FLD32(4)
+
+/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
+#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_FLD32(3)
+
+/* field: EV_SRC - Event Group Trigger Source. */
+#define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_ADCG1SRC----------------------*/
+/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
+#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_FLD32(4)
+
+/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
+#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_FLD32(3)
+
+/* field: G1_SRC - Group1 Trigger Source. */
+#define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_ADCG2SRC----------------------*/
+/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
+#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_FLD32(4)
+
+/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
+#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_FLD32(3)
+
+/* field: G2_SRC - Group2 Trigger Source. */
+#define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*---------------------TMS570_ADCGxINTENA---------------------*/
+/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
+#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_FLD32(3)
+
+/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
+#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_FLD32(1)
+
+/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
+#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCGxINTFLG---------------------*/
+/* field: EV_END - Event Group Conversion End. */
+#define TMS570_ADC_GxINTFLG_EV_END BSP_FLD32(3)
+
+/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
+#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_FLD32(2)
+
+/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
+#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_FLD32(1)
+
+/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
+#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCGxINTCR---------------------*/
+/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
+#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
+#define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
+#define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15)
+
+/* field: EV_THR - Event Group Threshold Counter. */
+#define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8)
+#define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*---------------------TMS570_ADCEVDMACR---------------------*/
+/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
+#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
+#define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
+#define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
+
+/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
+#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_FLD32(3)
+
+/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
+#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_FLD32(2)
+
+/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
+#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCG1DMACR---------------------*/
+/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
+#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
+#define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
+#define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
+
+/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
+#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_FLD32(3)
+
+/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
+#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_FLD32(2)
+
+/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
+#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCG2DMACR---------------------*/
+/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
+#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
+#define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
+#define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
+
+/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
+#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_FLD32(3)
+
+/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
+#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_FLD32(2)
+
+/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
+#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCBNDCR----------------------*/
+/* field: BNDA - Buffer Boundary A. */
+#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
+#define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
+#define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
+
+/* field: BNDB - Buffer Boundary B. */
+#define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8)
+#define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*----------------------TMS570_ADCBNDEND----------------------*/
+/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
+#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_FLD32(16)
+
+/* field: BNDEND - Buffer Boundary End. */
+#define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_ADCEVSAMP----------------------*/
+/* field: EV_ACQ - Event Group Acquisition Time. */
+#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*----------------------TMS570_ADCG1SAMP----------------------*/
+/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
+#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*----------------------TMS570_ADCG2SAMP----------------------*/
+/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
+#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*-----------------------TMS570_ADCEVSR-----------------------*/
+/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
+#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_FLD32(3)
+
+/* field: EV_BUSY - Event Group Conversion Busy. */
+#define TMS570_ADC_EVSR_EV_BUSY BSP_FLD32(2)
+
+/* field: EV_STOP - Event Group Conversion Stopped. */
+#define TMS570_ADC_EVSR_EV_STOP BSP_FLD32(1)
+
+/* field: EV_END - Event Group Conversions Ended. */
+#define TMS570_ADC_EVSR_EV_END BSP_FLD32(0)
+
+
+/*-----------------------TMS570_ADCG1SR-----------------------*/
+/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
+#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_FLD32(3)
+
+/* field: G1_BUSY - Group1 Conversion Busy. */
+#define TMS570_ADC_G1SR_G1_BUSY BSP_FLD32(2)
+
+/* field: G1_STOP - Group1 Conversion Stopped. */
+#define TMS570_ADC_G1SR_G1_STOP BSP_FLD32(1)
+
+/* field: G1_END - Group1 Conversions Ended. */
+#define TMS570_ADC_G1SR_G1_END BSP_FLD32(0)
+
+
+/*-----------------------TMS570_ADCG2SR-----------------------*/
+/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
+#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_FLD32(3)
+
+/* field: G2_BUSY - Group2 Conversion Busy. */
+#define TMS570_ADC_G2SR_G2_BUSY BSP_FLD32(2)
+
+/* field: G2_STOP - Group2 Conversion Stopped. */
+#define TMS570_ADC_G2SR_G2_STOP BSP_FLD32(1)
+
+/* field: G2_END - Group2 Conversions Ended. */
+#define TMS570_ADC_G2SR_G2_END BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCGxSEL----------------------*/
+/* field: EV_SEL - Event Group channels selected. */
+#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
+#define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_ADCCALR-----------------------*/
+/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
+#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
+#define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*---------------------TMS570_ADCSMSTATE---------------------*/
+/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
+#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
+#define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*---------------------TMS570_ADCLASTCONV---------------------*/
+/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
+#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
+#define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*----------------------TMS570_ADCGxBUF----------------------*/
+/* field: ADEVT_DIR - ADEVT Pin Direction. */
+#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCEVEMUBUFFER-------------------*/
+/* field: ADEVT_DIR - ADEVT Pin Direction. */
+#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCG1EMUBUFFER-------------------*/
+/* field: ADEVT_DIR - ADEVT Pin Direction. */
+#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCG2EMUBUFFER-------------------*/
+/* field: ADEVT_DIR - ADEVT Pin Direction. */
+#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTDIR----------------------*/
+/* field: ADEVT_DIR - ADEVT Pin Direction. */
+#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTOUT----------------------*/
+/* field: ADEVT_OUT - ADEVT Pin Output Value. */
+#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTIN----------------------*/
+/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
+#define TMS570_ADC_EVTIN_ADEVT_IN BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTSET----------------------*/
+/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
+#define TMS570_ADC_EVTSET_ADEVT_SET BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTCLR----------------------*/
+/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
+#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_FLD32(0)
+
+
+/*----------------------TMS570_ADCEVTPDR----------------------*/
+/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
+#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCEVTPDIS---------------------*/
+/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
+#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_FLD32(0)
+
+
+/*---------------------TMS570_ADCEVTPSEL---------------------*/
+/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
+#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCEVSAMPDISEN-------------------*/
+/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
+#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCG1SAMPDISEN-------------------*/
+/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
+#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCG2SAMPDISEN-------------------*/
+/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
+#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_FLD32(0)
+
+
+/*--------------------TMS570_ADCMAGINTCR1--------------------*/
+/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
+#define TMS570_ADC_MAGINTCR1_MAG_CHID2(val) BSP_FLD32(val,26, 30)
+#define TMS570_ADC_MAGINTCR1_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
+#define TMS570_ADC_MAGINTCR1_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
+
+/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
+#define TMS570_ADC_MAGINTCR1_MAG_THR2(val) BSP_FLD32(val,16, 25)
+#define TMS570_ADC_MAGINTCR1_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
+#define TMS570_ADC_MAGINTCR1_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
+
+/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
+#define TMS570_ADC_MAGINTCR1_COMP_CHID2(val) BSP_FLD32(val,8, 12)
+#define TMS570_ADC_MAGINTCR1_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_ADC_MAGINTCR1_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+
+/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
+#define TMS570_ADC_MAGINTCR1_CHN_THR_COMP2 BSP_FLD32(1)
+
+/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
+#define TMS570_ADC_MAGINTCR1_CMP_GE_LT2 BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCMAGINT1MASK-------------------*/
+/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
+#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_MAGINT1MASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*-----------------TMS570_ADCMAGTHRINTENASET-----------------*/
+/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
+#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------TMS570_ADCMAGTHRINTENACLR-----------------*/
+/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
+#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-------------------TMS570_ADCMAGTHRINTFLG-------------------*/
+/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
+#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
+#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------TMS570_ADCMAGTHRINTOFFSET-----------------*/
+/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
+#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
+#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_ADCGxFIFORESETCR------------------*/
+/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
+#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_FLD32(0)
+
+
+/*-------------------TMS570_ADCEVRAMWRADDR-------------------*/
+/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
+#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
+#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*-------------------TMS570_ADCG1RAMWRADDR-------------------*/
+/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
+#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
+#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*-------------------TMS570_ADCG2RAMWRADDR-------------------*/
+/* field: G2_RAM_ADDR - Group2 results memory write pointer. */
+#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
+#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*----------------------TMS570_ADCPARCR----------------------*/
+/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
+#define TMS570_ADC_PARCR_TEST BSP_FLD32(8)
+
+/* field: PARITY_ENA - PARITY ENA */
+#define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_ADCPARADDR---------------------*/
+/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
+#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
+#define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
+#define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
+
+
+/*-------------------TMS570_ADCPWRUPDLYCTRL-------------------*/
+/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
+#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
+#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+
+#endif /* LIBBSP_ARM_tms570_ADC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
new file mode 100644
index 0000000..30e5c9b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_ccmsr.h
@@ -0,0 +1,72 @@
+/* The header file is generated by make_header.py from CCMSR.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_CCMSR
+#define LIBBSP_ARM_tms570_CCMSR
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t CCMSR; /*CCM-R4F Status Register*/
+ uint32_t CCMKEYR; /*CCM-R4F Key Register*/
+} tms570_ccmsr_t;
+
+
+/*---------------------TMS570_CCMSRCCMSR---------------------*/
+/* field: CMPE - Compare Error */
+#define TMS570_CCMSR_CCMSR_CMPE BSP_FLD32(16)
+
+/* field: STC - Self-test Complete */
+#define TMS570_CCMSR_CCMSR_STC BSP_FLD32(8)
+
+/* field: STET - Self-test Error Type */
+#define TMS570_CCMSR_CCMSR_STET BSP_FLD32(1)
+
+/* field: STE - Self-test Error */
+#define TMS570_CCMSR_CCMSR_STE BSP_FLD32(0)
+
+
+/*--------------------TMS570_CCMSRCCMKEYR--------------------*/
+/* field: MKEY - Mode Key */
+#define TMS570_CCMSR_CCMKEYR_MKEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_CCMSR_CCMKEYR_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_CCMSR_CCMKEYR_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+
+#endif /* LIBBSP_ARM_tms570_CCMSR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
new file mode 100644
index 0000000..8798c12
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_crc.h
@@ -0,0 +1,427 @@
+/* The header file is generated by make_header.py from CRC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_CRC
+#define LIBBSP_ARM_tms570_CRC
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t CTRL0; /*CRC Global Control Register*/
+ uint8_t reserved1 [4];
+ uint32_t CTRL1; /*CRC Global Control Register 1*/
+ uint8_t reserved2 [4];
+ uint32_t CTRL2; /*CRC Global Control Register 2*/
+ uint8_t reserved3 [4];
+ uint32_t INTS; /*CRC Interrupt Enable Set Register*/
+ uint8_t reserved4 [4];
+ uint32_t INTR; /*CRC Interrupt Enable Reset Register*/
+ uint8_t reserved5 [4];
+ uint32_t STATUS; /*CRC Interrupt Status Register*/
+ uint8_t reserved6 [4];
+ uint32_t INT_OFFS_REG; /*CRC Interrupt Offset Register*/
+ uint8_t reserved7 [4];
+ uint32_t BUSY; /*CRC Busy Register*/
+ uint8_t reserved8 [4];
+ uint32_t PCOUNT_REG1; /*CRC Channel 1 Pattern Counter Preload Register*/
+ uint32_t SCOUNT_REG1; /*CRC Channel 1 Sector Counter Preload Register*/
+ uint32_t CURSEC_REG1; /*CRC Channel 1 Current Sector Register*/
+ uint32_t WDTOPLD1; /*CRC Channel 1 Watchdog Timeout Preload Register*/
+ uint32_t BCTOPLD1; /*CRC Channel 1 Block Complete Timeout Preload Register*/
+ uint8_t reserved9 [12];
+ uint32_t PSA_SIGREGL1; /*Channel 1 PSA Signature Low Register*/
+ uint32_t PSA_SIGREGH1; /*Channel 1 PSA Signature High Register*/
+ uint32_t REGL1; /*Channel 1 CRC Value Low Register*/
+ uint32_t REGH1; /*Channel 1 CRC Value High Register*/
+ uint32_t PSA_SECSIGREGL1; /*Channel 1 PSA Sector Signature Low Register*/
+ uint32_t PSA_SECSIGREGH1; /*Channel 1 PSA Sector Signature High Register*/
+ uint32_t RAW_DATAREGL1; /*Channel 1 Raw Data Low Register*/
+ uint32_t RAW_DATAREGH1; /*Channel 1 Raw Data High Register*/
+ uint32_t PCOUNT_REG2; /*CRC Channel 2 Pattern Counter Preload Register*/
+ uint32_t SCOUNT_REG2; /*CRC Channel 2 Sector Counter Preload Register*/
+ uint32_t CURSEC_REG2; /*CRC Current Sector Register 2*/
+ uint32_t WDTOPLD2; /*CRC Channel 2 Watchdog Timeout Preload Register A*/
+ uint32_t BCTOPLD2; /*CRC Channel 2 Block Complete Timeout Preload Register B*/
+ uint8_t reserved10 [12];
+ uint32_t PSA_SIGREGL2; /*Channel 2 PSA Signature Low Register*/
+ uint32_t PSA_SIGREGH2; /*Channel 2 PSA Signature High Register*/
+ uint32_t REGL2; /*Channel 2 CRC Value Low Register*/
+ uint32_t REGH2; /*Channel 2 CRC Value High Register*/
+ uint32_t PSA_SECSIGREGL2; /*Channel 2 PSA Sector Signature Low Register*/
+ uint32_t PSA_SECSIGREGH2; /*Channel 2 PSA Sector Signature High Register*/
+ uint32_t RAW_DATAREGL2; /*Channel 2 Raw Data Low Register*/
+ uint32_t RAW_DATAREGH2; /*Channel 2 Raw Data High Register*/
+ uint8_t reserved11 [128];
+ uint32_t BUS_SEL; /*Data Bus Selection Register*/
+} tms570_crc_t;
+
+
+/*----------------------TMS570_CRCCTRL0----------------------*/
+/* field: CH2_PSA_SWREST - Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
+#define TMS570_CRC_CTRL0_CH2_PSA_SWREST BSP_FLD32(8)
+
+/* field: CH1_PSA_SWREST - Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. */
+#define TMS570_CRC_CTRL0_CH1_PSA_SWREST BSP_FLD32(0)
+
+
+/*----------------------TMS570_CRCCTRL1----------------------*/
+/* field: PWDN - Power Down. */
+#define TMS570_CRC_CTRL1_PWDN BSP_FLD32(0)
+
+
+/*----------------------TMS570_CRCCTRL2----------------------*/
+/* field: CH2_MODE - Channel 2 Mode Selection */
+#define TMS570_CRC_CTRL2_CH2_MODE(val) BSP_FLD32(val,8, 9)
+#define TMS570_CRC_CTRL2_CH2_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_CRC_CTRL2_CH2_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: CH1_TRACEEN - Channel 1 Data Trace Enable. When set, the channel is put into data trace mode. */
+#define TMS570_CRC_CTRL2_CH1_TRACEEN BSP_FLD32(4)
+
+/* field: CH1_MODE - Channel 1 Mode Selection */
+#define TMS570_CRC_CTRL2_CH1_MODE(val) BSP_FLD32(val,0, 1)
+#define TMS570_CRC_CTRL2_CH1_MODE_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_CRC_CTRL2_CH1_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*-----------------------TMS570_CRCINTS-----------------------*/
+/* field: CH2_TIMEOUTENS - Channel 2 Timeout Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH2_TIMEOUTENS BSP_FLD32(12)
+
+/* field: CH2_UNDERENS - Channel 2 Underrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH2_UNDERENS BSP_FLD32(11)
+
+/* field: CH2_OVERENS - Channel 2 Overrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH2_OVERENS BSP_FLD32(10)
+
+/* field: CH2_CRCFAILENS - Channel 2 CRC Fail Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH2_CRCFAILENS BSP_FLD32(9)
+
+/* field: CH2_CCITENS - Channel 2 Compression Complete Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH2_CCITENS BSP_FLD32(8)
+
+/* field: CH1_TIMEOUTENS - Channel 1 Timeout Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH1_TIMEOUTENS BSP_FLD32(4)
+
+/* field: CH1_UNDERENS - Channel 1 Underrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH1_UNDERENS BSP_FLD32(3)
+
+/* field: CH1_OVERENS - CH1_OVERENS Channel 1 Overrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH1_OVERENS BSP_FLD32(2)
+
+/* field: CH1_CRCFAILENS - Channel 1 CRC Fail Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH1_CRCFAILENS BSP_FLD32(1)
+
+/* field: CH1_CCITENS - Channel 1 Compression Complete Interrupt Enable Bit. */
+#define TMS570_CRC_INTS_CH1_CCITENS BSP_FLD32(0)
+
+
+/*-----------------------TMS570_CRCINTR-----------------------*/
+/* field: CH2_TIMEOUTENR - Channel 2 Timeout Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH2_TIMEOUTENR BSP_FLD32(12)
+
+/* field: CH2_UNDERENR - Channel 2 Underrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH2_UNDERENR BSP_FLD32(11)
+
+/* field: CH2_OVERENR - Channel 2 Overrun Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH2_OVERENR BSP_FLD32(10)
+
+/* field: CH2_CRCFAILENR - Channel 2 CRC Fail Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH2_CRCFAILENR BSP_FLD32(9)
+
+/* field: CH2_CCITENR - Channel 2 Compression Complete Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH2_CCITENR BSP_FLD32(8)
+
+/* field: CH1_TIMEOUTENR - Channel 1 Timeout Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH1_TIMEOUTENR BSP_FLD32(4)
+
+/* field: CH1_UNDERENR - interrupt. Writing a zero has no effect. */
+#define TMS570_CRC_INTR_CH1_UNDERENR BSP_FLD32(3)
+
+/* field: CH1_OVERENR - CH1_OVERENR */
+#define TMS570_CRC_INTR_CH1_OVERENR BSP_FLD32(2)
+
+/* field: CH1_CRCFAILENR - Channel 1 CRC Fail Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH1_CRCFAILENR BSP_FLD32(1)
+
+/* field: CH1_CCITENR - Channel 1 Compression Complete Interrupt Enable Bit. */
+#define TMS570_CRC_INTR_CH1_CCITENR BSP_FLD32(0)
+
+
+/*----------------------TMS570_CRCSTATUS----------------------*/
+/* field: CH2_TIMEOUT - Channel 2 CRC Timeout Status Flag. This bit is cleared by writing a '1' to it only. */
+#define TMS570_CRC_STATUS_CH2_TIMEOUT BSP_FLD32(12)
+
+/* field: CH2_UNDER - Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a '1' to it only. */
+#define TMS570_CRC_STATUS_CH2_UNDER BSP_FLD32(11)
+
+/* field: CH2_OVER - Channel 2 CRC Overrun Status Flag. This bit is cleared by writing a '1' to it only. */
+#define TMS570_CRC_STATUS_CH2_OVER BSP_FLD32(10)
+
+/* field: CH2_CRCFAIL - Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a '1' to it only. */
+#define TMS570_CRC_STATUS_CH2_CRCFAIL BSP_FLD32(9)
+
+/* field: CH2_CCIT - Channel 2 CRC Pattern Compression Complete Status Flag. */
+#define TMS570_CRC_STATUS_CH2_CCIT BSP_FLD32(8)
+
+/* field: CH1_TIMEOUT - Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). */
+#define TMS570_CRC_STATUS_CH1_TIMEOUT BSP_FLD32(4)
+
+/* field: CH1_UNDER - Channel 1 Underrun Interrupt Enable Bit. */
+#define TMS570_CRC_STATUS_CH1_UNDER BSP_FLD32(3)
+
+/* field: CH1_OVER - Channel 1 Overrun Interrupt Enable Bit. Writing a one to this bit disable the overrun interrupt. */
+#define TMS570_CRC_STATUS_CH1_OVER BSP_FLD32(2)
+
+/* field: CH1_CRCFAIL - Channel 1 CRC Fail Interrupt Enable Bit. */
+#define TMS570_CRC_STATUS_CH1_CRCFAIL BSP_FLD32(1)
+
+/* field: CH1_CCIT - Channel 1 CRC Pattern Compression Complete Status Flag. */
+#define TMS570_CRC_STATUS_CH1_CCIT BSP_FLD32(0)
+
+
+/*-------------------TMS570_CRCINT_OFFS_REG-------------------*/
+/* field: OFSTREG - CRC Interrupt Offset. This register indicates the highest priority pending interrupt vector address. */
+#define TMS570_CRC_INT_OFFS_REG_OFSTREG(val) BSP_FLD32(val,0, 7)
+#define TMS570_CRC_INT_OFFS_REG_OFSTREG_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_CRC_INT_OFFS_REG_OFSTREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_CRCBUSY-----------------------*/
+/* field: CH2_BUSY - CH2_BUSY. */
+#define TMS570_CRC_BUSY_CH2_BUSY BSP_FLD32(8)
+
+/* field: CH1_BUSY - CH1_BUSY. */
+#define TMS570_CRC_BUSY_CH1_BUSY BSP_FLD32(0)
+
+
+/*-------------------TMS570_CRCPCOUNT_REG1-------------------*/
+/* field: CRC_PAT_COUNT1 - Channel 1 Pattern Counter Preload Register. */
+#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1(val) BSP_FLD32(val,0, 19)
+#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_CRC_PCOUNT_REG1_CRC_PAT_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*-------------------TMS570_CRCSCOUNT_REG1-------------------*/
+/* field: CRC_SEC_COUNT1 - Channel 1 Sector Counter Preload Register. */
+#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1(val) BSP_FLD32(val,0, 15)
+#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_CRC_SCOUNT_REG1_CRC_SEC_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_CRCCURSEC_REG1-------------------*/
+/* field: CRC_CURSEC1 - Channel 1 Current Sector ID Register. */
+#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1(val) BSP_FLD32(val,0, 15)
+#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_CRC_CURSEC_REG1_CRC_CURSEC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_CRCWDTOPLD1---------------------*/
+/* field: CRC_WDTOPLD1 - CRC_WDTOPLD1 */
+#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1(val) BSP_FLD32(val,0, 23)
+#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_CRC_WDTOPLD1_CRC_WDTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*---------------------TMS570_CRCBCTOPLD1---------------------*/
+/* field: CRC_BCTOPLD1 - Channel 1 Block Complete Timeout Counter Preload Register. */
+#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1(val) BSP_FLD32(val,0, 23)
+#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_CRC_BCTOPLD1_CRC_BCTOPLD1_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*-------------------TMS570_CRCPSA_SIGREGL1-------------------*/
+/* field: PSASIG1 - Channel 1 PSA Signature Low Register. */
+#define TMS570_CRC_PSA_SIGREGL1_PSASIG1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SIGREGL1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_CRCPSA_SIGREGH1-------------------*/
+/* field: PSASIG1 - register. */
+#define TMS570_CRC_PSA_SIGREGH1_PSASIG1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SIGREGH1_PSASIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_CRCREGL1----------------------*/
+/* field: CRC1 - Channel 1 CRC Value Low Register. */
+#define TMS570_CRC_REGL1_CRC1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_REGL1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_REGL1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_CRCREGH1----------------------*/
+/* field: CRC1 - Channel 1 CRC Value Low Register. */
+#define TMS570_CRC_REGH1_CRC1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_REGH1_CRC1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_REGH1_CRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------TMS570_CRCPSA_SECSIGREGL1-----------------*/
+/* field: PSASECSIG1 - Channel 1 PSA Sector Signature Low Register. */
+#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGL1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------TMS570_CRCPSA_SECSIGREGH1-----------------*/
+/* field: PSASECSIG1 - Channel 1 PSA Sector Signature High Register. */
+#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGH1_PSASECSIG1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_CRCRAW_DATAREGL1------------------*/
+/* field: RAW_DATA1 - hannel 1 Raw Data Low Register.This register contains bits 31:0 of the uncompressed raw data. */
+#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_RAW_DATAREGL1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_CRCRAW_DATAREGH1------------------*/
+/* field: RAW_DATA1 - Channel 1 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data. */
+#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_RAW_DATAREGH1_RAW_DATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_CRCPCOUNT_REG2-------------------*/
+/* field: CRC_PAT_COUNT2 - Channel 2 Pattern Counter Preload Register. */
+#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2(val) BSP_FLD32(val,0, 19)
+#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_CRC_PCOUNT_REG2_CRC_PAT_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*-------------------TMS570_CRCSCOUNT_REG2-------------------*/
+/* field: CRC_SEC_COUNT2 - Channel 2 Sector Counter Preload Register. */
+#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2(val) BSP_FLD32(val,0, 15)
+#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_CRC_SCOUNT_REG2_CRC_SEC_COUNT2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_CRCCURSEC_REG2-------------------*/
+/* field: CRC_CURSEC2 - Channel 2 Current Sector ID Register. */
+#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2(val) BSP_FLD32(val,0, 15)
+#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_CRC_CURSEC_REG2_CRC_CURSEC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_CRCWDTOPLD2---------------------*/
+/* field: CRC_WDTOPLD2 - Channel 2 Watchdog Timeout Counter Preload Register. */
+#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2(val) BSP_FLD32(val,0, 23)
+#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_CRC_WDTOPLD2_CRC_WDTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*---------------------TMS570_CRCBCTOPLD2---------------------*/
+/* field: CRC_BCTOPLD2 - Channel 2 Block Complete Timeout Counter Preload Register. */
+#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2(val) BSP_FLD32(val,0, 23)
+#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_CRC_BCTOPLD2_CRC_BCTOPLD2_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*-------------------TMS570_CRCPSA_SIGREGL2-------------------*/
+/* field: PSASIG2 - Channel 2 PSA Signature Low Register. */
+#define TMS570_CRC_PSA_SIGREGL2_PSASIG2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SIGREGL2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_CRCPSA_SIGREGH2-------------------*/
+/* field: PSASIG2 - Channel 2 PSA Signature High Register. */
+#define TMS570_CRC_PSA_SIGREGH2_PSASIG2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SIGREGH2_PSASIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_CRCREGL2----------------------*/
+/* field: CRC2 - stored at CRC2[31:0] register. */
+#define TMS570_CRC_REGL2_CRC2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_REGL2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_REGL2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_CRCREGH2----------------------*/
+/* field: CRC2 - Channel 2 CRC Value High Register. */
+#define TMS570_CRC_REGH2_CRC2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_REGH2_CRC2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_REGH2_CRC2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------TMS570_CRCPSA_SECSIGREGL2-----------------*/
+/* field: PSASECSIG2 - Channel 2 PSA Sector Signature Low Register. */
+#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGL2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------TMS570_CRCPSA_SECSIGREGH2-----------------*/
+/* field: PSASECSIG2 - Channel 2 PSA Sector Signature High Register. */
+#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_PSA_SECSIGREGH2_PSASECSIG2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_CRCRAW_DATAREGL2------------------*/
+/* field: RAW_DATA2 - Channel 2 Raw Data Low Register. This register contains bits 31:0 of the uncompressed raw data.. */
+#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_RAW_DATAREGL2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_CRCRAW_DATAREGH2------------------*/
+/* field: RAW_DATA2 - Channel 2 Raw Data High Register. This register contains bits 63:32 of the uncompressed raw data.. */
+#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2(val) BSP_FLD32(val,0, 31)
+#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_CRC_RAW_DATAREGH2_RAW_DATA2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_CRCBUS_SEL---------------------*/
+/* field: MEn - Enable/disables the tracing of Peripheral Bus Master */
+#define TMS570_CRC_BUS_SEL_MEn BSP_FLD32(2)
+
+/* field: DTCMEn - Enable/disables the tracing of data TCM */
+#define TMS570_CRC_BUS_SEL_DTCMEn BSP_FLD32(1)
+
+/* field: ITCMEn - Enable/disables the tracing of instruction TCM */
+#define TMS570_CRC_BUS_SEL_ITCMEn BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_CRC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
new file mode 100644
index 0000000..80d372e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcan.h
@@ -0,0 +1,962 @@
+/* The header file is generated by make_header.py from DCAN.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_DCAN
+#define LIBBSP_ARM_tms570_DCAN
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t CTL; /*CAN Control Register*/
+ uint32_t ES; /*Error and Status Register*/
+ uint32_t ERRC; /*Error Counter Register*/
+ uint32_t BTR; /*Bit Timing Register*/
+ uint32_t INT; /*Interrupt Register*/
+ uint32_t TEST; /*Test Register*/
+ uint8_t reserved1 [4];
+ uint32_t PERR; /*Parity Error Code Register*/
+ uint8_t reserved2 [96];
+ uint32_t ABOTR; /*Auto-Bus-On Time Register*/
+ uint32_t TXRQX; /*Transmission Request X Register*/
+ uint32_t TXRQx[4]; /*Transmission Request Register*/
+ uint32_t NWDATX; /*New Data X Register*/
+ uint32_t NWDATx[4]; /*New Data Register*/
+ uint32_t INTPNDX; /*Interrupt Pending X Register*/
+ uint32_t INTPNDx[4]; /*Interrupt Pending Register*/
+ uint32_t MSGVALX; /*Message Valid X Register*/
+ uint32_t MSGVALx[4]; /*Message Valid Register*/
+ uint8_t reserved3 [4];
+ uint32_t INTMUXx[4]; /*Interrupt Multiplexer Register*/
+ uint8_t reserved4 [24];
+ uint32_t IF1CMD; /*IF1 Command Register*/
+ uint32_t IF1MSK; /*IF1 Mask Register*/
+ uint32_t IF1ARB; /*IF1 Arbitration Register*/
+ uint32_t IF1MCTL; /*IF1 Message Control Register*/
+ uint32_t IF1DATA; /*IF1 Data A Register*/
+ uint32_t IF1DATB; /*IF1 Data B Register*/
+ uint8_t reserved5 [8];
+ uint32_t IF2CMD; /*IF2 Command Register*/
+ uint32_t IF2MSK; /*IF2 Mask Register*/
+ uint32_t IF2ARB; /*IF2 Arbitration Register*/
+ uint32_t IF2MCTL; /*IF2 Message Control Register*/
+ uint32_t IF2DATA; /*IF2 Data A Register*/
+ uint32_t IF2DATB; /*IF2 Data B Register*/
+ uint8_t reserved6 [8];
+ uint32_t IF3OBS; /*IF3 Observation Register*/
+ uint32_t IF3MSK; /*IF3 Mask Register*/
+ uint32_t IF3ARB; /*IF3 Arbitration Register*/
+ uint32_t IF3MCTL; /*IF3 Message Control Register*/
+ uint32_t IF3DATA; /*IF3 Data A Register*/
+ uint32_t IF3DATB; /*IF3 Data B Register*/
+ uint8_t reserved7 [8];
+ uint32_t IF3UEy[4]; /*IF3 Update Enable Register*/
+ uint8_t reserved8 [112];
+ uint32_t TIOC; /*CAN TX IO Control Register*/
+ uint32_t RIOC; /*CAN RX IO Control Register*/
+} tms570_dcan_t;
+
+
+/*-----------------------TMS570_DCANCTL-----------------------*/
+/* field: WUBA - Automatic wake up on bus activity when in local power down mode */
+#define TMS570_DCAN_CTL_WUBA BSP_FLD32(25)
+
+/* field: PDR - Request for local low power down mode */
+#define TMS570_DCAN_CTL_PDR BSP_FLD32(24)
+
+/* field: DE3 - Enable DMA request line for IF3 */
+#define TMS570_DCAN_CTL_DE3 BSP_FLD32(20)
+
+/* field: DE2 - Enable DMA request line for IF2 */
+#define TMS570_DCAN_CTL_DE2 BSP_FLD32(19)
+
+/* field: DE1 - Enable DMA request line for IF1 */
+#define TMS570_DCAN_CTL_DE1 BSP_FLD32(18)
+
+/* field: IE1 - Interrupt line 1 Enable */
+#define TMS570_DCAN_CTL_IE1 BSP_FLD32(17)
+
+/* field: InitDbg - Internal Init state while debug access */
+#define TMS570_DCAN_CTL_InitDbg BSP_FLD32(16)
+
+/* field: SWR - SW Reset Enable */
+#define TMS570_DCAN_CTL_SWR BSP_FLD32(15)
+
+/* field: PMD - Parity on/off */
+#define TMS570_DCAN_CTL_PMD(val) BSP_FLD32(val,10, 13)
+#define TMS570_DCAN_CTL_PMD_GET(reg) BSP_FLD32GET(reg,10, 13)
+#define TMS570_DCAN_CTL_PMD_SET(reg,val) BSP_FLD32SET(reg, val,10, 13)
+
+/* field: ABO - Auto-Bus-On Enable */
+#define TMS570_DCAN_CTL_ABO BSP_FLD32(9)
+
+/* field: IDS - Interruption Debug Support Enable */
+#define TMS570_DCAN_CTL_IDS BSP_FLD32(8)
+
+/* field: Test - Test Mode Enable */
+#define TMS570_DCAN_CTL_Test BSP_FLD32(7)
+
+/* field: CCE - Configuration Change Enable */
+#define TMS570_DCAN_CTL_CCE BSP_FLD32(6)
+
+/* field: DAR - Disable Automatic Retransmission */
+#define TMS570_DCAN_CTL_DAR BSP_FLD32(5)
+
+/* field: EIE - Error Interrupt Enable */
+#define TMS570_DCAN_CTL_EIE BSP_FLD32(3)
+
+/* field: SIE - Status Change Interrupt Enable */
+#define TMS570_DCAN_CTL_SIE BSP_FLD32(2)
+
+/* field: IE0 - Interrupt line 0 Enable */
+#define TMS570_DCAN_CTL_IE0 BSP_FLD32(1)
+
+/* field: Init - Initialization */
+#define TMS570_DCAN_CTL_Init BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DCANES-----------------------*/
+/* field: PDA - Local power down mode acknowledge */
+#define TMS570_DCAN_ES_PDA BSP_FLD32(10)
+
+/* field: WakeUp_Pnd - Wake Up Pending */
+#define TMS570_DCAN_ES_WakeUp_Pnd BSP_FLD32(9)
+
+/* field: PER - Parity Error Detected */
+#define TMS570_DCAN_ES_PER BSP_FLD32(8)
+
+/* field: BOff - Bus-Off State */
+#define TMS570_DCAN_ES_BOff BSP_FLD32(7)
+
+/* field: EWarn - Warning State */
+#define TMS570_DCAN_ES_EWarn BSP_FLD32(6)
+
+/* field: EPass - Error Passive State */
+#define TMS570_DCAN_ES_EPass BSP_FLD32(5)
+
+/* field: RxOK - Received a message successfully */
+#define TMS570_DCAN_ES_RxOK BSP_FLD32(4)
+
+/* field: TxOK - Transmitted a message successfully */
+#define TMS570_DCAN_ES_TxOK BSP_FLD32(3)
+
+/* field: LEC - Last Error Code */
+#define TMS570_DCAN_ES_LEC(val) BSP_FLD32(val,0, 2)
+#define TMS570_DCAN_ES_LEC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_DCAN_ES_LEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_DCANERRC----------------------*/
+/* field: RP - Receive Error Passive */
+#define TMS570_DCAN_ERRC_RP BSP_FLD32(15)
+
+/* field: REC - Receive Error Counter. Actual state of the Receive Error Counter. (values from 0 to 255). */
+#define TMS570_DCAN_ERRC_REC(val) BSP_FLD32(val,8, 14)
+#define TMS570_DCAN_ERRC_REC_GET(reg) BSP_FLD32GET(reg,8, 14)
+#define TMS570_DCAN_ERRC_REC_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
+
+/* field: TEC - Transmit Error Counter. Actual state of the Transmit Error Counter. (values from 0 to 255). */
+#define TMS570_DCAN_ERRC_TEC(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_ERRC_TEC_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_ERRC_TEC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_DCANBTR-----------------------*/
+/* field: BRPE - Baud Rate Prescaler Extension. */
+#define TMS570_DCAN_BTR_BRPE(val) BSP_FLD32(val,16, 19)
+#define TMS570_DCAN_BTR_BRPE_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_DCAN_BTR_BRPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: TSeg2 - Time segment after the sample point */
+#define TMS570_DCAN_BTR_TSeg2(val) BSP_FLD32(val,12, 14)
+#define TMS570_DCAN_BTR_TSeg2_GET(reg) BSP_FLD32GET(reg,12, 14)
+#define TMS570_DCAN_BTR_TSeg2_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
+
+/* field: TSeg1 - Time segment before the sample point */
+#define TMS570_DCAN_BTR_TSeg1(val) BSP_FLD32(val,8, 11)
+#define TMS570_DCAN_BTR_TSeg1_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_DCAN_BTR_TSeg1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: SJW - Synchronization Jump Width */
+#define TMS570_DCAN_BTR_SJW(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCAN_BTR_SJW_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCAN_BTR_SJW_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: BRP - Baud Rate Prescaler */
+#define TMS570_DCAN_BTR_BRP(val) BSP_FLD32(val,0, 5)
+#define TMS570_DCAN_BTR_BRP_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DCAN_BTR_BRP_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------------TMS570_DCANINT-----------------------*/
+/* field: Int1ID - Interrupt 1 Identifier (indicates the message object with the highest pending interrupt) */
+#define TMS570_DCAN_INT_Int1ID(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_INT_Int1ID_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_INT_Int1ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Int0ID - Interrupt Identifier (the number here indicates the source of the interrupt) */
+#define TMS570_DCAN_INT_Int0ID(val) BSP_FLD32(val,0, 15)
+#define TMS570_DCAN_INT_Int0ID_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DCAN_INT_Int0ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_DCANTEST----------------------*/
+/* field: RDA - RAM Direct Access Enable */
+#define TMS570_DCAN_TEST_RDA BSP_FLD32(9)
+
+/* field: EXL - External Loop Back Mode */
+#define TMS570_DCAN_TEST_EXL BSP_FLD32(8)
+
+/* field: Rx - Receive Pin. Monitors the actual value of the CAN_RX pin. */
+#define TMS570_DCAN_TEST_Rx BSP_FLD32(7)
+
+/* field: Tx - Control of CAN_TX pin */
+#define TMS570_DCAN_TEST_Tx(val) BSP_FLD32(val,5, 6)
+#define TMS570_DCAN_TEST_Tx_GET(reg) BSP_FLD32GET(reg,5, 6)
+#define TMS570_DCAN_TEST_Tx_SET(reg,val) BSP_FLD32SET(reg, val,5, 6)
+
+/* field: LBack - Loop Back Mode */
+#define TMS570_DCAN_TEST_LBack BSP_FLD32(4)
+
+/* field: Silent - Silent Mode */
+#define TMS570_DCAN_TEST_Silent BSP_FLD32(3)
+
+
+/*----------------------TMS570_DCANPERR----------------------*/
+/* field: Word_Number - Word number where parity error has been detected */
+#define TMS570_DCAN_PERR_Word_Number(val) BSP_FLD32(val,8, 10)
+#define TMS570_DCAN_PERR_Word_Number_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_DCAN_PERR_Word_Number_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: Message_Number - */
+#define TMS570_DCAN_PERR_Message_Number(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_PERR_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_PERR_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_DCANABOTR----------------------*/
+/* field: ABO_Time - Number of VBUS clock cycles before a Bus-Off recovery sequence is */
+#define TMS570_DCAN_ABOTR_ABO_Time(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_ABOTR_ABO_Time_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_ABOTR_ABO_Time_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DCANTXRQX----------------------*/
+/* field: TxRqstReg8 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg8(val) BSP_FLD32(val,14, 15)
+#define TMS570_DCAN_TXRQX_TxRqstReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_DCAN_TXRQX_TxRqstReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+/* field: TxRqstReg7 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg7(val) BSP_FLD32(val,12, 13)
+#define TMS570_DCAN_TXRQX_TxRqstReg7_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_DCAN_TXRQX_TxRqstReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: TxRqstReg6 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg6(val) BSP_FLD32(val,10, 11)
+#define TMS570_DCAN_TXRQX_TxRqstReg6_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_DCAN_TXRQX_TxRqstReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: TxRqstReg5 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg5(val) BSP_FLD32(val,8, 9)
+#define TMS570_DCAN_TXRQX_TxRqstReg5_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_DCAN_TXRQX_TxRqstReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: TxRqstReg4 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg4(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCAN_TXRQX_TxRqstReg4_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCAN_TXRQX_TxRqstReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: TxRqstReg3 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg3(val) BSP_FLD32(val,4, 5)
+#define TMS570_DCAN_TXRQX_TxRqstReg3_GET(reg) BSP_FLD32GET(reg,4, 5)
+#define TMS570_DCAN_TXRQX_TxRqstReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
+
+/* field: TxRqstReg2 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg2(val) BSP_FLD32(val,2, 3)
+#define TMS570_DCAN_TXRQX_TxRqstReg2_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_DCAN_TXRQX_TxRqstReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: TxRqstReg1 - TxRqstReg8 */
+#define TMS570_DCAN_TXRQX_TxRqstReg1(val) BSP_FLD32(val,0, 1)
+#define TMS570_DCAN_TXRQX_TxRqstReg1_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_DCAN_TXRQX_TxRqstReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*----------------------TMS570_DCANTXRQx----------------------*/
+/* field: TxRqsX - Transmission Request Bits (for all message objects) */
+#define TMS570_DCAN_TXRQx_TxRqsX(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_TXRQx_TxRqsX_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_TXRQx_TxRqsX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_DCANNWDATX---------------------*/
+/* field: NewDatReg8 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg8(val) BSP_FLD32(val,14, 15)
+#define TMS570_DCAN_NWDATX_NewDatReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_DCAN_NWDATX_NewDatReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+/* field: NewDatReg7 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg7(val) BSP_FLD32(val,12, 13)
+#define TMS570_DCAN_NWDATX_NewDatReg7_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_DCAN_NWDATX_NewDatReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: NewDatReg6 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg6(val) BSP_FLD32(val,10, 11)
+#define TMS570_DCAN_NWDATX_NewDatReg6_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_DCAN_NWDATX_NewDatReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: NewDatReg5 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg5(val) BSP_FLD32(val,8, 9)
+#define TMS570_DCAN_NWDATX_NewDatReg5_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_DCAN_NWDATX_NewDatReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: NewDatReg4 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg4(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCAN_NWDATX_NewDatReg4_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCAN_NWDATX_NewDatReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: NewDatReg3 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg3(val) BSP_FLD32(val,4, 5)
+#define TMS570_DCAN_NWDATX_NewDatReg3_GET(reg) BSP_FLD32GET(reg,4, 5)
+#define TMS570_DCAN_NWDATX_NewDatReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
+
+/* field: NewDatReg2 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg2(val) BSP_FLD32(val,2, 3)
+#define TMS570_DCAN_NWDATX_NewDatReg2_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_DCAN_NWDATX_NewDatReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: NewDatReg1 - TxRqstReg8 */
+#define TMS570_DCAN_NWDATX_NewDatReg1(val) BSP_FLD32(val,0, 1)
+#define TMS570_DCAN_NWDATX_NewDatReg1_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_DCAN_NWDATX_NewDatReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_DCANNWDATx---------------------*/
+/* field: NewDatX - New Data Bits (for all message objects) */
+#define TMS570_DCAN_NWDATx_NewDatX(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_NWDATx_NewDatX_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_NWDATx_NewDatX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_DCANINTPNDX---------------------*/
+/* field: IntPndReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg8(val) BSP_FLD32(val,14, 15)
+#define TMS570_DCAN_INTPNDX_IntPndReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_DCAN_INTPNDX_IntPndReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+/* field: IntPndReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg7(val) BSP_FLD32(val,12, 13)
+#define TMS570_DCAN_INTPNDX_IntPndReg7_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_DCAN_INTPNDX_IntPndReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: IntPndReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg6(val) BSP_FLD32(val,10, 11)
+#define TMS570_DCAN_INTPNDX_IntPndReg6_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_DCAN_INTPNDX_IntPndReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: IntPndReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg5(val) BSP_FLD32(val,8, 9)
+#define TMS570_DCAN_INTPNDX_IntPndReg5_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_DCAN_INTPNDX_IntPndReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: IntPndReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg4(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCAN_INTPNDX_IntPndReg4_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCAN_INTPNDX_IntPndReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: IntPndReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg3(val) BSP_FLD32(val,4, 5)
+#define TMS570_DCAN_INTPNDX_IntPndReg3_GET(reg) BSP_FLD32GET(reg,4, 5)
+#define TMS570_DCAN_INTPNDX_IntPndReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
+
+/* field: IntPndReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg2(val) BSP_FLD32(val,2, 3)
+#define TMS570_DCAN_INTPNDX_IntPndReg2_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_DCAN_INTPNDX_IntPndReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: IntPndReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Interrupt Pending X Register will be set. */
+#define TMS570_DCAN_INTPNDX_IntPndReg1(val) BSP_FLD32(val,0, 1)
+#define TMS570_DCAN_INTPNDX_IntPndReg1_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_DCAN_INTPNDX_IntPndReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_DCANINTPNDx---------------------*/
+/* field: IntPndX - Interrupt Pending Bits (for all message objects) */
+#define TMS570_DCAN_INTPNDx_IntPndX(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_INTPNDx_IntPndX_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_INTPNDx_IntPndX_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_DCANMSGVALX---------------------*/
+/* field: MsgValReg8 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg8(val) BSP_FLD32(val,14, 15)
+#define TMS570_DCAN_MSGVALX_MsgValReg8_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_DCAN_MSGVALX_MsgValReg8_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+/* field: MsgValReg7 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg7(val) BSP_FLD32(val,12, 13)
+#define TMS570_DCAN_MSGVALX_MsgValReg7_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_DCAN_MSGVALX_MsgValReg7_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: MsgValReg6 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg6(val) BSP_FLD32(val,10, 11)
+#define TMS570_DCAN_MSGVALX_MsgValReg6_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_DCAN_MSGVALX_MsgValReg6_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: MsgValReg5 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg5(val) BSP_FLD32(val,8, 9)
+#define TMS570_DCAN_MSGVALX_MsgValReg5_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_DCAN_MSGVALX_MsgValReg5_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: MsgValReg4 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg4(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCAN_MSGVALX_MsgValReg4_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCAN_MSGVALX_MsgValReg4_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: MsgValReg3 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg3(val) BSP_FLD32(val,4, 5)
+#define TMS570_DCAN_MSGVALX_MsgValReg3_GET(reg) BSP_FLD32GET(reg,4, 5)
+#define TMS570_DCAN_MSGVALX_MsgValReg3_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
+
+/* field: MsgValReg2 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg2(val) BSP_FLD32(val,2, 3)
+#define TMS570_DCAN_MSGVALX_MsgValReg2_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_DCAN_MSGVALX_MsgValReg2_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: MsgValReg1 - If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the Message Valid X Register will be set. */
+#define TMS570_DCAN_MSGVALX_MsgValReg1(val) BSP_FLD32(val,0, 1)
+#define TMS570_DCAN_MSGVALX_MsgValReg1_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_DCAN_MSGVALX_MsgValReg1_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_DCANMSGVALx---------------------*/
+/* field: MsgVal1To32 - Message Valid Bits (for all message objects) */
+#define TMS570_DCAN_MSGVALx_MsgVal1To32(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_MSGVALx_MsgVal1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_MSGVALx_MsgVal1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_DCANINTMUXx---------------------*/
+/* field: IntMux1To32 - Multiplexes IntPnd value to either DCAN0INT or DCAN1INT interrupt lines. */
+#define TMS570_DCAN_INTMUXx_IntMux1To32(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_INTMUXx_IntMux1To32_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_INTMUXx_IntMux1To32_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_DCANIF1CMD---------------------*/
+/* field: WR_RD - Write/Read */
+#define TMS570_DCAN_IF1CMD_WR_RD BSP_FLD32(23)
+
+/* field: Mask - Access Mask bits */
+#define TMS570_DCAN_IF1CMD_Mask BSP_FLD32(22)
+
+/* field: Arb - Access Arbitration bits */
+#define TMS570_DCAN_IF1CMD_Arb BSP_FLD32(21)
+
+/* field: Control - Access Control bits */
+#define TMS570_DCAN_IF1CMD_Control BSP_FLD32(20)
+
+/* field: ClrIntPnd - Clear Interrupt Pending bit */
+#define TMS570_DCAN_IF1CMD_ClrIntPnd BSP_FLD32(19)
+
+/* field: TxRqst_NewDat - Access Transmission Request bit */
+#define TMS570_DCAN_IF1CMD_TxRqst_NewDat BSP_FLD32(18)
+
+/* field: Data_A - Access Data Bytes 0-3 */
+#define TMS570_DCAN_IF1CMD_Data_A BSP_FLD32(17)
+
+/* field: Data_B - Access Data Bytes 4-7 */
+#define TMS570_DCAN_IF1CMD_Data_B BSP_FLD32(16)
+
+/* field: Busy - Busy flag */
+#define TMS570_DCAN_IF1CMD_Busy BSP_FLD32(15)
+
+/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
+#define TMS570_DCAN_IF1CMD_DMA_Active BSP_FLD32(14)
+
+/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
+#define TMS570_DCAN_IF1CMD_Message_Number(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF1CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF1CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_DCANIF1MSK---------------------*/
+/* field: MXtd - Mask Extended Identifier */
+#define TMS570_DCAN_IF1MSK_MXtd BSP_FLD32(31)
+
+/* field: MDir - Mask Message Direction */
+#define TMS570_DCAN_IF1MSK_MDir BSP_FLD32(30)
+
+/* field: Msk - Identifier Mask */
+#define TMS570_DCAN_IF1MSK_Msk(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF1MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF1MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF1ARB---------------------*/
+/* field: MsgVal - Message Valid */
+#define TMS570_DCAN_IF1ARB_MsgVal BSP_FLD32(31)
+
+/* field: Xtd - Extended Identifier */
+#define TMS570_DCAN_IF1ARB_Xtd BSP_FLD32(30)
+
+/* field: Dir - Message direction */
+#define TMS570_DCAN_IF1ARB_Dir BSP_FLD32(29)
+
+/* field: ID - Message Identifier */
+#define TMS570_DCAN_IF1ARB_ID(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF1ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF1ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF1MCTL---------------------*/
+/* field: NewDat - New Data */
+#define TMS570_DCAN_IF1MCTL_NewDat BSP_FLD32(15)
+
+/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
+#define TMS570_DCAN_IF1MCTL_MsgLst BSP_FLD32(14)
+
+/* field: IntPnd - Interrupt Pending */
+#define TMS570_DCAN_IF1MCTL_IntPnd BSP_FLD32(13)
+
+/* field: UMask - Use Acceptance Mask */
+#define TMS570_DCAN_IF1MCTL_UMask BSP_FLD32(12)
+
+/* field: TxIE - Transmit Interrupt Enable */
+#define TMS570_DCAN_IF1MCTL_TxIE BSP_FLD32(11)
+
+/* field: RxIE - Receive Interrupt Enable */
+#define TMS570_DCAN_IF1MCTL_RxIE BSP_FLD32(10)
+
+/* field: RmtEn - Remote Enable */
+#define TMS570_DCAN_IF1MCTL_RmtEn BSP_FLD32(9)
+
+/* field: TxRqst - Transmit Request */
+#define TMS570_DCAN_IF1MCTL_TxRqst BSP_FLD32(8)
+
+/* field: EoB - Data Frame has 0-8 data bits */
+#define TMS570_DCAN_IF1MCTL_EoB BSP_FLD32(7)
+
+/* field: DLC - Data Length Code */
+#define TMS570_DCAN_IF1MCTL_DLC(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCAN_IF1MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCAN_IF1MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_DCANIF1DATA---------------------*/
+/* field: Data0 - Data 0 */
+#define TMS570_DCAN_IF1DATA_Data0(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF1DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF1DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data1 - Data 1 */
+#define TMS570_DCAN_IF1DATA_Data1(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF1DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF1DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data2 - Data 2 */
+#define TMS570_DCAN_IF1DATA_Data2(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF1DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF1DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data3 - Data 3 */
+#define TMS570_DCAN_IF1DATA_Data3(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF1DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF1DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF1DATB---------------------*/
+/* field: Data4 - Data 4 */
+#define TMS570_DCAN_IF1DATB_Data4(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF1DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF1DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data5 - Data 5 */
+#define TMS570_DCAN_IF1DATB_Data5(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF1DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF1DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data6 - Data 6 */
+#define TMS570_DCAN_IF1DATB_Data6(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF1DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF1DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data7 - Data 7 */
+#define TMS570_DCAN_IF1DATB_Data7(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF1DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF1DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF2CMD---------------------*/
+/* field: WR_RD - Write/Read */
+#define TMS570_DCAN_IF2CMD_WR_RD BSP_FLD32(23)
+
+/* field: Mask - Access Mask bits */
+#define TMS570_DCAN_IF2CMD_Mask BSP_FLD32(22)
+
+/* field: Arb - Access Arbitration bits */
+#define TMS570_DCAN_IF2CMD_Arb BSP_FLD32(21)
+
+/* field: Control - Access Control bits */
+#define TMS570_DCAN_IF2CMD_Control BSP_FLD32(20)
+
+/* field: ClrIntPnd - Clear Interrupt Pending bit */
+#define TMS570_DCAN_IF2CMD_ClrIntPnd BSP_FLD32(19)
+
+/* field: TxRqst_NewDat - Access Transmission Request bit */
+#define TMS570_DCAN_IF2CMD_TxRqst_NewDat BSP_FLD32(18)
+
+/* field: Data_A - Access Data Bytes 0-3 */
+#define TMS570_DCAN_IF2CMD_Data_A BSP_FLD32(17)
+
+/* field: Data_B - Access Data Bytes 4-7 */
+#define TMS570_DCAN_IF2CMD_Data_B BSP_FLD32(16)
+
+/* field: Busy - Busy flag */
+#define TMS570_DCAN_IF2CMD_Busy BSP_FLD32(15)
+
+/* field: DMA_Active - Activation of DMA feature for subsequent internal IF1/IF2 update */
+#define TMS570_DCAN_IF2CMD_DMA_Active BSP_FLD32(14)
+
+/* field: Message_Number - Number of message object in Message RAM that is used for data transfer */
+#define TMS570_DCAN_IF2CMD_Message_Number(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF2CMD_Message_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF2CMD_Message_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_DCANIF2MSK---------------------*/
+/* field: MXtd - Mask Extended Identifier */
+#define TMS570_DCAN_IF2MSK_MXtd BSP_FLD32(31)
+
+/* field: MDir - Mask Message Direction */
+#define TMS570_DCAN_IF2MSK_MDir BSP_FLD32(30)
+
+/* field: Msk - Identifier Mask */
+#define TMS570_DCAN_IF2MSK_Msk(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF2MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF2MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF2ARB---------------------*/
+/* field: MsgVal - Message Valid */
+#define TMS570_DCAN_IF2ARB_MsgVal BSP_FLD32(31)
+
+/* field: Xtd - Extended Identifier */
+#define TMS570_DCAN_IF2ARB_Xtd BSP_FLD32(30)
+
+/* field: Dir - Message direction */
+#define TMS570_DCAN_IF2ARB_Dir BSP_FLD32(29)
+
+/* field: ID - Message Identifier */
+#define TMS570_DCAN_IF2ARB_ID(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF2ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF2ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF2MCTL---------------------*/
+/* field: NewDat - New Data */
+#define TMS570_DCAN_IF2MCTL_NewDat BSP_FLD32(15)
+
+/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
+#define TMS570_DCAN_IF2MCTL_MsgLst BSP_FLD32(14)
+
+/* field: IntPnd - Interrupt Pending */
+#define TMS570_DCAN_IF2MCTL_IntPnd BSP_FLD32(13)
+
+/* field: UMask - Use Acceptance Mask */
+#define TMS570_DCAN_IF2MCTL_UMask BSP_FLD32(12)
+
+/* field: TxIE - Transmit Interrupt Enable */
+#define TMS570_DCAN_IF2MCTL_TxIE BSP_FLD32(11)
+
+/* field: RxIE - Receive Interrupt Enable */
+#define TMS570_DCAN_IF2MCTL_RxIE BSP_FLD32(10)
+
+/* field: RmtEn - Remote Enable */
+#define TMS570_DCAN_IF2MCTL_RmtEn BSP_FLD32(9)
+
+/* field: TxRqst - Transmit Request */
+#define TMS570_DCAN_IF2MCTL_TxRqst BSP_FLD32(8)
+
+/* field: EoB - Data Frame has 0-8 data bits */
+#define TMS570_DCAN_IF2MCTL_EoB BSP_FLD32(7)
+
+/* field: DLC - Data Length Code */
+#define TMS570_DCAN_IF2MCTL_DLC(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCAN_IF2MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCAN_IF2MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_DCANIF2DATA---------------------*/
+/* field: Data0 - Data 0 */
+#define TMS570_DCAN_IF2DATA_Data0(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF2DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF2DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data1 - Data 1 */
+#define TMS570_DCAN_IF2DATA_Data1(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF2DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF2DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data2 - Data 2 */
+#define TMS570_DCAN_IF2DATA_Data2(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF2DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF2DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data3 - Data 3 */
+#define TMS570_DCAN_IF2DATA_Data3(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF2DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF2DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF2DATB---------------------*/
+/* field: Data4 - Data 4 */
+#define TMS570_DCAN_IF2DATB_Data4(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF2DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF2DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data5 - Data 5 */
+#define TMS570_DCAN_IF2DATB_Data5(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF2DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF2DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data6 - Data 6 */
+#define TMS570_DCAN_IF2DATB_Data6(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF2DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF2DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data7 - Data 7 */
+#define TMS570_DCAN_IF2DATB_Data7(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF2DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF2DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF3OBS---------------------*/
+/* field: IF3_Upd - IF3 Update Data */
+#define TMS570_DCAN_IF3OBS_IF3_Upd BSP_FLD32(15)
+
+/* field: IF3_SDB - IF3 Status of Data B read access */
+#define TMS570_DCAN_IF3OBS_IF3_SDB BSP_FLD32(12)
+
+/* field: IF3_SDA - IF3 Status of Data A read access */
+#define TMS570_DCAN_IF3OBS_IF3_SDA BSP_FLD32(11)
+
+/* field: IF3_SC - IF3 Status of Control bits read access */
+#define TMS570_DCAN_IF3OBS_IF3_SC BSP_FLD32(10)
+
+/* field: IF3_SA - IF3 Status of Arbitration data read access */
+#define TMS570_DCAN_IF3OBS_IF3_SA BSP_FLD32(9)
+
+/* field: IF3_SM - IF3 Status of Mask data read access */
+#define TMS570_DCAN_IF3OBS_IF3_SM BSP_FLD32(8)
+
+/* field: Data_B - Data B read observation */
+#define TMS570_DCAN_IF3OBS_Data_B BSP_FLD32(4)
+
+/* field: Data_A - Data A read observation */
+#define TMS570_DCAN_IF3OBS_Data_A BSP_FLD32(3)
+
+/* field: Ctrl - Ctrl read observation */
+#define TMS570_DCAN_IF3OBS_Ctrl BSP_FLD32(2)
+
+/* field: Arb - Arbitration data read observation */
+#define TMS570_DCAN_IF3OBS_Arb BSP_FLD32(1)
+
+/* field: Mask - Mask data read observation */
+#define TMS570_DCAN_IF3OBS_Mask BSP_FLD32(0)
+
+
+/*---------------------TMS570_DCANIF3MSK---------------------*/
+/* field: MXtd - Mask Extended Identifier */
+#define TMS570_DCAN_IF3MSK_MXtd BSP_FLD32(31)
+
+/* field: MDir - Mask Message Direction */
+#define TMS570_DCAN_IF3MSK_MDir BSP_FLD32(30)
+
+/* field: Msk - Identifier Mask */
+#define TMS570_DCAN_IF3MSK_Msk(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF3MSK_Msk_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF3MSK_Msk_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF3ARB---------------------*/
+/* field: MsgVal - Message Valid */
+#define TMS570_DCAN_IF3ARB_MsgVal BSP_FLD32(31)
+
+/* field: Xtd - Extended Identifier */
+#define TMS570_DCAN_IF3ARB_Xtd BSP_FLD32(30)
+
+/* field: Dir - Message direction */
+#define TMS570_DCAN_IF3ARB_Dir BSP_FLD32(29)
+
+/* field: ID - Message Identifier */
+#define TMS570_DCAN_IF3ARB_ID(val) BSP_FLD32(val,0, 28)
+#define TMS570_DCAN_IF3ARB_ID_GET(reg) BSP_FLD32GET(reg,0, 28)
+#define TMS570_DCAN_IF3ARB_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 28)
+
+
+/*---------------------TMS570_DCANIF3MCTL---------------------*/
+/* field: NewDat - New Data */
+#define TMS570_DCAN_IF3MCTL_NewDat BSP_FLD32(15)
+
+/* field: MsgLst - Message Lost (only valid for message objects with direction = receive) */
+#define TMS570_DCAN_IF3MCTL_MsgLst BSP_FLD32(14)
+
+/* field: IntPnd - Interrupt Pending */
+#define TMS570_DCAN_IF3MCTL_IntPnd BSP_FLD32(13)
+
+/* field: UMask - Use Acceptance Mask */
+#define TMS570_DCAN_IF3MCTL_UMask BSP_FLD32(12)
+
+/* field: TxIE - Transmit Interrupt Enable */
+#define TMS570_DCAN_IF3MCTL_TxIE BSP_FLD32(11)
+
+/* field: RxIE - Receive Interrupt Enable */
+#define TMS570_DCAN_IF3MCTL_RxIE BSP_FLD32(10)
+
+/* field: RmtEn - Remote Enable */
+#define TMS570_DCAN_IF3MCTL_RmtEn BSP_FLD32(9)
+
+/* field: TxRqst - TxRqst */
+#define TMS570_DCAN_IF3MCTL_TxRqst BSP_FLD32(8)
+
+/* field: EoB - End of Block */
+#define TMS570_DCAN_IF3MCTL_EoB BSP_FLD32(7)
+
+/* field: DLC - Data Length Code */
+#define TMS570_DCAN_IF3MCTL_DLC(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCAN_IF3MCTL_DLC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCAN_IF3MCTL_DLC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_DCANIF3DATA---------------------*/
+/* field: Data0 - Data 0 */
+#define TMS570_DCAN_IF3DATA_Data0(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF3DATA_Data0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF3DATA_Data0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data1 - Data 1 */
+#define TMS570_DCAN_IF3DATA_Data1(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF3DATA_Data1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF3DATA_Data1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data2 - Data 2 */
+#define TMS570_DCAN_IF3DATA_Data2(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF3DATA_Data2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF3DATA_Data2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data3 - Data 3 */
+#define TMS570_DCAN_IF3DATA_Data3(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF3DATA_Data3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF3DATA_Data3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF3DATB---------------------*/
+/* field: Data4 - Data 4 */
+#define TMS570_DCAN_IF3DATB_Data4(val) BSP_FLD32(val,0, 7)
+#define TMS570_DCAN_IF3DATB_Data4_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_DCAN_IF3DATB_Data4_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+/* field: Data5 - Data 5 */
+#define TMS570_DCAN_IF3DATB_Data5(val) BSP_FLD32(val,8, 15)
+#define TMS570_DCAN_IF3DATB_Data5_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_DCAN_IF3DATB_Data5_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: Data6 - Data 6 */
+#define TMS570_DCAN_IF3DATB_Data6(val) BSP_FLD32(val,16, 23)
+#define TMS570_DCAN_IF3DATB_Data6_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_DCAN_IF3DATB_Data6_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: Data7 - Data 7 */
+#define TMS570_DCAN_IF3DATB_Data7(val) BSP_FLD32(val,24, 31)
+#define TMS570_DCAN_IF3DATB_Data7_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_DCAN_IF3DATB_Data7_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+
+/*---------------------TMS570_DCANIF3UEy---------------------*/
+/* field: IF3UpdEn - IF3 Update Enabled (for all message objects) */
+#define TMS570_DCAN_IF3UEy_IF3UpdEn(val) BSP_FLD32(val,0, 31)
+#define TMS570_DCAN_IF3UEy_IF3UpdEn_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DCAN_IF3UEy_IF3UpdEn_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DCANTIOC----------------------*/
+/* field: PU - CAN_TX Pullup/Pulldown select. This bit is only active when CAN_TX is configured to be an input. */
+#define TMS570_DCAN_TIOC_PU BSP_FLD32(18)
+
+/* field: PD - CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input. */
+#define TMS570_DCAN_TIOC_PD BSP_FLD32(17)
+
+/* field: OD - CAN_TX open drain enable. */
+#define TMS570_DCAN_TIOC_OD BSP_FLD32(16)
+
+/* field: Func - CAN_TX function. This bit changes the function of the CAN_TX pin. */
+#define TMS570_DCAN_TIOC_Func BSP_FLD32(3)
+
+/* field: Dir - CAN_TX data direction. */
+#define TMS570_DCAN_TIOC_Dir BSP_FLD32(2)
+
+/* field: Out - CAN_TX data out write. */
+#define TMS570_DCAN_TIOC_Out BSP_FLD32(1)
+
+
+/*----------------------TMS570_DCANRIOC----------------------*/
+/* field: PU - CAN_RX Pullup/Pulldown select. This bit is only active when CAN_RX is configured to be an input. */
+#define TMS570_DCAN_RIOC_PU BSP_FLD32(18)
+
+/* field: PD - CAN_RX pull disable. This bit is only active when CAN_RX is configured to be an input. */
+#define TMS570_DCAN_RIOC_PD BSP_FLD32(17)
+
+/* field: OD - CAN_RX open drain enable. */
+#define TMS570_DCAN_RIOC_OD BSP_FLD32(16)
+
+/* field: Func - CAN_RX function. This bit changes the function of the CAN_RX pin. */
+#define TMS570_DCAN_RIOC_Func BSP_FLD32(3)
+
+/* field: Dir - CAN_RX data direction. */
+#define TMS570_DCAN_RIOC_Dir BSP_FLD32(2)
+
+/* field: Out - CAN_RX data out write. */
+#define TMS570_DCAN_RIOC_Out BSP_FLD32(1)
+
+/* field: In - CAN_RX data in. */
+#define TMS570_DCAN_RIOC_In BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_DCAN */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
new file mode 100644
index 0000000..73b9232
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dcc.h
@@ -0,0 +1,183 @@
+/* The header file is generated by make_header.py from DCC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_DCC
+#define LIBBSP_ARM_tms570_DCC
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GCTRL; /*DCC Global Control Register*/
+ uint32_t REV; /*DCC Revision Id Register*/
+ uint32_t CNT0SEED; /*DCC Counter0 Seed Register*/
+ uint32_t VALID0SEED; /*DCC Valid0 Seed Register*/
+ uint32_t CNT1SEED; /*DCC Counter1 Seed Register*/
+ uint32_t STAT; /*DCC Status Register*/
+ uint32_t CNT0; /*DCC Counter0 Value Register*/
+ uint32_t VALID0; /*DCC Valid0 Value Register*/
+ uint32_t CNT1; /*DCC Counter1 Value Register*/
+ uint32_t CNT1CLKSRC; /*DCC Counter1 Clock Source Selection Register*/
+ uint32_t CNT0CLKSRC; /*DCC Counter0 Clock Source Selection Register*/
+} tms570_dcc_t;
+
+
+/*----------------------TMS570_DCCGCTRL----------------------*/
+/* field: DONE_INT_ENA - Done Interrupt Enable. */
+#define TMS570_DCC_GCTRL_DONE_INT_ENA(val) BSP_FLD32(val,12, 15)
+#define TMS570_DCC_GCTRL_DONE_INT_ENA_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_DCC_GCTRL_DONE_INT_ENA_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: SINGLE_SHOT - Single-Shot Mode Enable. */
+#define TMS570_DCC_GCTRL_SINGLE_SHOT(val) BSP_FLD32(val,8, 11)
+#define TMS570_DCC_GCTRL_SINGLE_SHOT_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_DCC_GCTRL_SINGLE_SHOT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: ERR_ENA - Error Interrupt Enable. */
+#define TMS570_DCC_GCTRL_ERR_ENA(val) BSP_FLD32(val,4, 7)
+#define TMS570_DCC_GCTRL_ERR_ENA_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_DCC_GCTRL_ERR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: DCC_ENA - DCC Enable. */
+#define TMS570_DCC_GCTRL_DCC_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCC_GCTRL_DCC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCC_GCTRL_DCC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_DCCREV-----------------------*/
+/* field: SCHEME - Reads return 01, writes have no effect. */
+#define TMS570_DCC_REV_SCHEME(val) BSP_FLD32(val,30, 31)
+#define TMS570_DCC_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
+#define TMS570_DCC_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
+
+/* field: FUNC - Functional release number. Reads return 0x000, writes have no effect. */
+#define TMS570_DCC_REV_FUNC(val) BSP_FLD32(val,16, 27)
+#define TMS570_DCC_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27)
+#define TMS570_DCC_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
+
+/* field: RTL - Design release number. Reads return 0x00, writes have no effect. */
+#define TMS570_DCC_REV_RTL(val) BSP_FLD32(val,11, 15)
+#define TMS570_DCC_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
+#define TMS570_DCC_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
+
+/* field: MAJOR - Major revision number. Reads return 0x2, writes have no effect. */
+#define TMS570_DCC_REV_MAJOR(val) BSP_FLD32(val,8, 10)
+#define TMS570_DCC_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_DCC_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CUSTOM - Custom version number. Reads return 0x0, writes have no effect. */
+#define TMS570_DCC_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
+#define TMS570_DCC_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DCC_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: MINOR - Minor revision number. Reads return 0x4, writes have no effect. */
+#define TMS570_DCC_REV_MINOR(val) BSP_FLD32(val,0, 5)
+#define TMS570_DCC_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DCC_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*---------------------TMS570_DCCCNT0SEED---------------------*/
+/* field: COUNT0_SEED - Seed value for DCC Counter0. */
+#define TMS570_DCC_CNT0SEED_COUNT0_SEED(val) BSP_FLD32(val,0, 19)
+#define TMS570_DCC_CNT0SEED_COUNT0_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_DCC_CNT0SEED_COUNT0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*--------------------TMS570_DCCVALID0SEED--------------------*/
+/* field: VALID0_SEED - XXX */
+#define TMS570_DCC_VALID0SEED_VALID0_SEED(val) BSP_FLD32(val,0, 15)
+#define TMS570_DCC_VALID0SEED_VALID0_SEED_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DCC_VALID0SEED_VALID0_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DCCCNT1SEED---------------------*/
+/* field: COUNT1_SEED - Seed value for DCC Counter1. */
+#define TMS570_DCC_CNT1SEED_COUNT1_SEED(val) BSP_FLD32(val,0, 19)
+#define TMS570_DCC_CNT1SEED_COUNT1_SEED_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_DCC_CNT1SEED_COUNT1_SEED_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*-----------------------TMS570_DCCSTAT-----------------------*/
+/* field: DONE_FLG - Single-Shot Sequence Done flag. */
+#define TMS570_DCC_STAT_DONE_FLG BSP_FLD32(1)
+
+/* field: ERR_FLG - Error flag. Indicates that a DCC error has occurred. */
+#define TMS570_DCC_STAT_ERR_FLG BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DCCCNT0-----------------------*/
+/* field: COUNT0 - Current value of DCC Counter0. */
+#define TMS570_DCC_CNT0_COUNT0(val) BSP_FLD32(val,0, 19)
+#define TMS570_DCC_CNT0_COUNT0_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_DCC_CNT0_COUNT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*----------------------TMS570_DCCVALID0----------------------*/
+/* field: VALID0 - Current value for DCC Valid0. */
+#define TMS570_DCC_VALID0_VALID0(val) BSP_FLD32(val,0, 15)
+#define TMS570_DCC_VALID0_VALID0_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DCC_VALID0_VALID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_DCCCNT1-----------------------*/
+/* field: COUNT1 - Current value for DCC Counter1. */
+#define TMS570_DCC_CNT1_COUNT1(val) BSP_FLD32(val,0, 19)
+#define TMS570_DCC_CNT1_COUNT1_GET(reg) BSP_FLD32GET(reg,0, 19)
+#define TMS570_DCC_CNT1_COUNT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 19)
+
+
+/*--------------------TMS570_DCCCNT1CLKSRC--------------------*/
+/* field: KEY - Key to enable clock source selection for Counter1. */
+#define TMS570_DCC_CNT1CLKSRC_KEY(val) BSP_FLD32(val,12, 15)
+#define TMS570_DCC_CNT1CLKSRC_KEY_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_DCC_CNT1CLKSRC_KEY_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: CNT1_CLKSRC - Clock Source for Counter1 when KEY is programmed to be 0xA. */
+#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCC_CNT1CLKSRC_CNT1_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_DCCCNT0CLKSRC--------------------*/
+/* field: CNT0_CLKSRC - Clock Source for Counter0 */
+#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC(val) BSP_FLD32(val,0, 3)
+#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DCC_CNT0CLKSRC_CNT0_CLKSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+
+#endif /* LIBBSP_ARM_tms570_DCC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
new file mode 100644
index 0000000..acef5a0
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dma.h
@@ -0,0 +1,732 @@
+/* The header file is generated by make_header.py from DMA.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_DMA
+#define LIBBSP_ARM_tms570_DMA
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t STARTADD; /*DMA Memory Protection Region start Address Register*/
+ uint32_t ENDADD; /*DMA Memory Protection Region End Address Register*/
+} tms570_memory_prot_t;
+
+typedef struct{
+ uint32_t GCTRL; /*Global Control Register*/
+ uint32_t PEND; /*Channel Pending Register*/
+ uint8_t reserved1 [4];
+ uint32_t DMASTAT; /*DMA Status Register*/
+ uint8_t reserved2 [4];
+ uint32_t HWCHENAS; /*HW Channel Enable Set and Status Register*/
+ uint8_t reserved3 [4];
+ uint32_t HWCHENAR; /*HW Channel Enable Reset and Status Register*/
+ uint8_t reserved4 [4];
+ uint32_t SWCHENAS; /*SW Channel Enable Set and Status Register*/
+ uint8_t reserved5 [4];
+ uint32_t SWCHENAR; /*SW Channel Enable Reset and Status Register*/
+ uint8_t reserved6 [4];
+ uint32_t CHPRIOS; /*Channel Priority Set Register*/
+ uint8_t reserved7 [4];
+ uint32_t CHPRIOR; /*Channel Priority Reset Register*/
+ uint8_t reserved8 [4];
+ uint32_t GCHIENAS; /*Global Channel Interrupt Enable Set Register*/
+ uint8_t reserved9 [4];
+ uint32_t GCHIENAR; /*Global Channel Interrupt Enable Reset Register*/
+ uint8_t reserved10 [4];
+ uint32_t DREQASI[4]; /*DMA Request Assignment Register 0*/
+ uint8_t reserved11 [48];
+ uint32_t PAR0; /*Port Assignment Register 0*/
+ uint32_t PAR1; /*Port Assignment Register 1*/
+ uint8_t reserved12 [24];
+ uint32_t FTCMAP; /*FTC Interrupt Mapping Register*/
+ uint8_t reserved13 [4];
+ uint32_t LFSMAP; /*LFS Interrupt Mapping Register*/
+ uint8_t reserved14 [4];
+ uint32_t HBCMAP; /*HBC Interrupt Mapping Register*/
+ uint8_t reserved15 [4];
+ uint32_t BTCMAP; /*BTC Interrupt Mapping Register*/
+ uint8_t reserved16 [4];
+ uint32_t BERMAP; /*BER Interrupt Mapping Register*/
+ uint8_t reserved17 [4];
+ uint32_t FTCINTENAS; /*FTC Interrupt Enable Set*/
+ uint8_t reserved18 [4];
+ uint32_t FTCINTENAR; /*FTC Interrupt Enable Reset*/
+ uint8_t reserved19 [4];
+ uint32_t LFSINTENAS; /*LFS Interrupt Enable Set*/
+ uint8_t reserved20 [4];
+ uint32_t LFSINTENAR; /*LFS Interrupt Enable Reset*/
+ uint8_t reserved21 [4];
+ uint32_t HBCINTENAS; /*HBC Interrupt Enable Set*/
+ uint8_t reserved22 [4];
+ uint32_t HBCINTENAR; /*HBC Interrupt Enable Reset*/
+ uint8_t reserved23 [4];
+ uint32_t BTCINTENAS; /*BTC Interrupt Enable Set*/
+ uint8_t reserved24 [4];
+ uint32_t BTCINTENAR; /*BTC Interrupt Enable Reset*/
+ uint8_t reserved25 [4];
+ uint32_t GINTFLAG; /*Global Interrupt Flag Register*/
+ uint8_t reserved26 [4];
+ uint32_t FTCFLAG; /*FTC Interrupt Flag Register*/
+ uint8_t reserved27 [4];
+ uint32_t LFSFLAG; /*LFS Interrupt Flag Register*/
+ uint8_t reserved28 [4];
+ uint32_t HBCFLAG; /*HBC Interrupt Flag Register*/
+ uint8_t reserved29 [4];
+ uint32_t BTCFLAG; /*BTC Interrupt Flag Register*/
+ uint8_t reserved30 [4];
+ uint32_t BERFLAG; /*BER Interrupt Flag Register*/
+ uint8_t reserved31 [4];
+ uint32_t FTCAOFFSET; /*FTCA Interrupt Channel Offset Register*/
+ uint32_t LFSAOFFSET; /*LFSA Interrupt Channel Offset Register*/
+ uint32_t HBCAOFFSET; /*HBCA Interrupt Channel Offset Register*/
+ uint32_t BTCAOFFSET; /*BTCA Interrupt Channel Offset Register*/
+ uint32_t BERAOFFSET; /*BERA Interrupt Channel Offset Register*/
+ uint32_t FTCBOFFSET; /*FTCB Interrupt Channel Offset Register*/
+ uint32_t LFSBOFFSET; /*LFSB Interrupt Channel Offset Register*/
+ uint32_t HBCBOFFSET; /*HBCB Interrupt Channel Offset Register*/
+ uint32_t BTCBOFFSET; /*BTCB Interrupt Channel Offset Register*/
+ uint32_t BERBOFFSET; /*BERB Interrupt Channel Offset Register*/
+ uint8_t reserved32 [4];
+ uint32_t PTCRL; /*Port Control Register*/
+ uint32_t RTCTRL; /*RAM Test Control Register*/
+ uint32_t DCTRL; /*Debug Control*/
+ uint32_t WPR; /*Watch Point Register*/
+ uint32_t WMR; /*Watch Mask Register*/
+ uint8_t reserved33 [12];
+ uint32_t PBACSADDR; /*Port B Active Channel Source Address Register*/
+ uint32_t PBACDADDR; /*Port B Active Channel Destination Address Register*/
+ uint32_t PBACTC; /*Port B Active Channel Transfer Count Register*/
+ uint8_t reserved34 [4];
+ uint32_t DMAPCR; /*Parity Control Register*/
+ uint32_t DMAPAR; /*DMA Parity Error Address Register*/
+ uint32_t DMAMPCTRL; /*DMA Memory Protection Control Register*/
+ uint32_t DMAMPST; /*DMA Memory Protection Status Register*/
+ tms570_memory_prot_t DMAMPROS[4];/*DMA Memory Protection Regions*/
+} tms570_dma_t;
+
+
+/*---------------------TMS570_DMASTARTADD---------------------*/
+/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
+#define TMS570_DMA_STARTADD_STARTADDRESS(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_STARTADD_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_STARTADD_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DMAENDADD----------------------*/
+/* field: ENDADDRESS - End Address defines the address at which the region ends. */
+#define TMS570_DMA_ENDADD_ENDADDRESS(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_ENDADD_ENDADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_ENDADD_ENDADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DMAGCTRL----------------------*/
+/* field: DMA_EN - DMA enable bit. */
+#define TMS570_DMA_GCTRL_DMA_EN BSP_FLD32(16)
+
+/* field: BUS_BUSY - This bit indicates status of DMA external AHB bus status. */
+#define TMS570_DMA_GCTRL_BUS_BUSY BSP_FLD32(14)
+
+/* field: DEBUG_MODE - Debug Mode. */
+#define TMS570_DMA_GCTRL_DEBUG_MODE(val) BSP_FLD32(val,8, 9)
+#define TMS570_DMA_GCTRL_DEBUG_MODE_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_DMA_GCTRL_DEBUG_MODE_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: DMA_RES - DMA software reset */
+#define TMS570_DMA_GCTRL_DMA_RES BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMAPEND-----------------------*/
+/* field: PEND - Channel pending register. */
+#define TMS570_DMA_PEND_PEND(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_PEND_PEND_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_PEND_PEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMADMASTAT---------------------*/
+/* field: STCH - Status of DMA channels. */
+#define TMS570_DMA_DMASTAT_STCH(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_DMASTAT_STCH_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_DMASTAT_STCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAHWCHENAS---------------------*/
+/* field: HWCHENA - Hardware channel enable bit. */
+#define TMS570_DMA_HWCHENAS_HWCHENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HWCHENAS_HWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HWCHENAS_HWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAHWCHENAR---------------------*/
+/* field: HWCHDIS - HW channel disable bit. */
+#define TMS570_DMA_HWCHENAR_HWCHDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HWCHENAR_HWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HWCHENAR_HWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMASWCHENAS---------------------*/
+/* field: SWCHENA - SW channel enable bit. */
+#define TMS570_DMA_SWCHENAS_SWCHENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_SWCHENAS_SWCHENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_SWCHENAS_SWCHENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMASWCHENAR---------------------*/
+/* field: SWCHDIS - SW channel disable bit. */
+#define TMS570_DMA_SWCHENAR_SWCHDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_SWCHENAR_SWCHDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_SWCHENAR_SWCHDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMACHPRIOS---------------------*/
+/* field: CPS - Channel priority set bit. */
+#define TMS570_DMA_CHPRIOS_CPS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_CHPRIOS_CPS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_CHPRIOS_CPS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMACHPRIOR---------------------*/
+/* field: CPR - Channel priority reset bit. */
+#define TMS570_DMA_CHPRIOR_CPR(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_CHPRIOR_CPR_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_CHPRIOR_CPR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAGCHIENAS---------------------*/
+/* field: GCHIE - Global channel interrupt enable bit. */
+#define TMS570_DMA_GCHIENAS_GCHIE(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_GCHIENAS_GCHIE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_GCHIENAS_GCHIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAGCHIENAR---------------------*/
+/* field: GCHID - Global channel interrupt disable bit. */
+#define TMS570_DMA_GCHIENAR_GCHID(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_GCHIENAR_GCHID_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_GCHIENAR_GCHID_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMADREQASI---------------------*/
+/* field: CH0ASI - Channel 0 assignment. This bit field chooses the DMA request assignment for channel 0. */
+#define TMS570_DMA_DREQASI_CH0ASI(val) BSP_FLD32(val,24, 29)
+#define TMS570_DMA_DREQASI_CH0ASI_GET(reg) BSP_FLD32GET(reg,24, 29)
+#define TMS570_DMA_DREQASI_CH0ASI_SET(reg,val) BSP_FLD32SET(reg, val,24, 29)
+
+/* field: CH1ASI - Channel 1 assignment. This bit field chooses the DMA request assignment for channel 1. */
+#define TMS570_DMA_DREQASI_CH1ASI(val) BSP_FLD32(val,16, 21)
+#define TMS570_DMA_DREQASI_CH1ASI_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_DMA_DREQASI_CH1ASI_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: CH2ASI - Channel 2 assignment. This bit field chooses the DMA request assignment for channel 2. */
+#define TMS570_DMA_DREQASI_CH2ASI(val) BSP_FLD32(val,8, 13)
+#define TMS570_DMA_DREQASI_CH2ASI_GET(reg) BSP_FLD32GET(reg,8, 13)
+#define TMS570_DMA_DREQASI_CH2ASI_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
+
+/* field: CH3ASI - Channel 3 assignment. This bit field chooses the DMA request assignment for channel 3. */
+#define TMS570_DMA_DREQASI_CH3ASI(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_DREQASI_CH3ASI_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_DREQASI_CH3ASI_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------------TMS570_DMAPAR0-----------------------*/
+/* field: CH0PA - These bit fields determine to which port channel 0 is assigned. */
+#define TMS570_DMA_PAR0_CH0PA(val) BSP_FLD32(val,28, 30)
+#define TMS570_DMA_PAR0_CH0PA_GET(reg) BSP_FLD32GET(reg,28, 30)
+#define TMS570_DMA_PAR0_CH0PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
+
+/* field: CH1PA - These bit fields determine to which port channel 1 is assigned. */
+#define TMS570_DMA_PAR0_CH1PA(val) BSP_FLD32(val,24, 26)
+#define TMS570_DMA_PAR0_CH1PA_GET(reg) BSP_FLD32GET(reg,24, 26)
+#define TMS570_DMA_PAR0_CH1PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
+
+/* field: CH2PA - These bit fields determine to which port channel 2 is assigned. */
+#define TMS570_DMA_PAR0_CH2PA(val) BSP_FLD32(val,20, 22)
+#define TMS570_DMA_PAR0_CH2PA_GET(reg) BSP_FLD32GET(reg,20, 22)
+#define TMS570_DMA_PAR0_CH2PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
+
+/* field: CH3PA - These bit fields determine to which port channel 3 is assigned. */
+#define TMS570_DMA_PAR0_CH3PA(val) BSP_FLD32(val,16, 18)
+#define TMS570_DMA_PAR0_CH3PA_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_DMA_PAR0_CH3PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: CH4PA - These bit fields determine to which port channel 4 is assigned. */
+#define TMS570_DMA_PAR0_CH4PA(val) BSP_FLD32(val,12, 14)
+#define TMS570_DMA_PAR0_CH4PA_GET(reg) BSP_FLD32GET(reg,12, 14)
+#define TMS570_DMA_PAR0_CH4PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
+
+/* field: CH5PA - These bit fields determine to which port channel 5 is assigned. */
+#define TMS570_DMA_PAR0_CH5PA(val) BSP_FLD32(val,8, 10)
+#define TMS570_DMA_PAR0_CH5PA_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_DMA_PAR0_CH5PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CH6PA - These bit fields determine to which port channel 6 is assigned. */
+#define TMS570_DMA_PAR0_CH6PA(val) BSP_FLD32(val,4, 6)
+#define TMS570_DMA_PAR0_CH6PA_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_DMA_PAR0_CH6PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: CH7PA - These bit fields determine to which port channel 7 is assigned. */
+#define TMS570_DMA_PAR0_CH7PA(val) BSP_FLD32(val,0, 2)
+#define TMS570_DMA_PAR0_CH7PA_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_DMA_PAR0_CH7PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_DMAPAR1-----------------------*/
+/* field: CH8PA - These bit fields determine to which port channel 8 is assigned. */
+#define TMS570_DMA_PAR1_CH8PA(val) BSP_FLD32(val,28, 30)
+#define TMS570_DMA_PAR1_CH8PA_GET(reg) BSP_FLD32GET(reg,28, 30)
+#define TMS570_DMA_PAR1_CH8PA_SET(reg,val) BSP_FLD32SET(reg, val,28, 30)
+
+/* field: CH9PA - These bit fields determine to which port channel 9 is assigned. */
+#define TMS570_DMA_PAR1_CH9PA(val) BSP_FLD32(val,24, 26)
+#define TMS570_DMA_PAR1_CH9PA_GET(reg) BSP_FLD32GET(reg,24, 26)
+#define TMS570_DMA_PAR1_CH9PA_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
+
+/* field: CH10PA - These bit fields determine to which port channel 10 is assigned. */
+#define TMS570_DMA_PAR1_CH10PA(val) BSP_FLD32(val,20, 22)
+#define TMS570_DMA_PAR1_CH10PA_GET(reg) BSP_FLD32GET(reg,20, 22)
+#define TMS570_DMA_PAR1_CH10PA_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
+
+/* field: CH11PA - These bit fields determine to which port channel 11 is assigned. */
+#define TMS570_DMA_PAR1_CH11PA(val) BSP_FLD32(val,16, 18)
+#define TMS570_DMA_PAR1_CH11PA_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_DMA_PAR1_CH11PA_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: CH12PA - These bit fields determine to which port channel 12 is assigned. */
+#define TMS570_DMA_PAR1_CH12PA(val) BSP_FLD32(val,12, 14)
+#define TMS570_DMA_PAR1_CH12PA_GET(reg) BSP_FLD32GET(reg,12, 14)
+#define TMS570_DMA_PAR1_CH12PA_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
+
+/* field: CH13PA - These bit fields determine to which port channel 13 is assigned. */
+#define TMS570_DMA_PAR1_CH13PA(val) BSP_FLD32(val,8, 10)
+#define TMS570_DMA_PAR1_CH13PA_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_DMA_PAR1_CH13PA_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CH14PA - These bit fields determine to which port channel 14 is assigned. */
+#define TMS570_DMA_PAR1_CH14PA(val) BSP_FLD32(val,4, 6)
+#define TMS570_DMA_PAR1_CH14PA_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_DMA_PAR1_CH14PA_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: CH15PA - These bit fields determine to which port channel 15 is assigned. */
+#define TMS570_DMA_PAR1_CH15PA(val) BSP_FLD32(val,0, 2)
+#define TMS570_DMA_PAR1_CH15PA_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_DMA_PAR1_CH15PA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_DMAFTCMAP----------------------*/
+/* field: FTCAB - Frame transfer complete (FTC) interrupt to Group A or Group B. */
+#define TMS570_DMA_FTCMAP_FTCAB(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_FTCMAP_FTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_FTCMAP_FTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_DMALFSMAP----------------------*/
+/* field: LFSAB - Last frame started (LFS) interrupt to Group A or Group B. */
+#define TMS570_DMA_LFSMAP_LFSAB(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_LFSMAP_LFSAB_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_LFSMAP_LFSAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_DMAHBCMAP----------------------*/
+/* field: HBCAB - Half block complete (HBC) interrupt to Group A or Group B. */
+#define TMS570_DMA_HBCMAP_HBCAB(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HBCMAP_HBCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HBCMAP_HBCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_DMABTCMAP----------------------*/
+/* field: BTCAB - Block transfer complete (BTC) interrupt to Group A or Group B */
+#define TMS570_DMA_BTCMAP_BTCAB(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BTCMAP_BTCAB_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BTCMAP_BTCAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_DMABERMAP----------------------*/
+/* field: BERAB - Bus error (BER) interrupt to Group A or Group B. */
+#define TMS570_DMA_BERMAP_BERAB(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BERMAP_BERAB_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BERMAP_BERAB_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMAFTCINTENAS--------------------*/
+/* field: FTCINTENA - Frame transfer complete (FTC) interrupt enable. */
+#define TMS570_DMA_FTCINTENAS_FTCINTENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_FTCINTENAS_FTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_FTCINTENAS_FTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMAFTCINTENAR--------------------*/
+/* field: FTCINTDIS - Frame transfer complete (FTC) interrupt disable. */
+#define TMS570_DMA_FTCINTENAR_FTCINTDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_FTCINTENAR_FTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_FTCINTENAR_FTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMALFSINTENAS--------------------*/
+/* field: LFSINTENA - Last frame started (LFS) interrupt enable. */
+#define TMS570_DMA_LFSINTENAS_LFSINTENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_LFSINTENAS_LFSINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_LFSINTENAS_LFSINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMALFSINTENAR--------------------*/
+/* field: LFSINTDIS - Last frame started (LFS) interrupt disable. */
+#define TMS570_DMA_LFSINTENAR_LFSINTDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_LFSINTENAR_LFSINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_LFSINTENAR_LFSINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMAHBCINTENAS--------------------*/
+/* field: HBCINTENA - Half block complete (HBC) interrupt enable. */
+#define TMS570_DMA_HBCINTENAS_HBCINTENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HBCINTENAS_HBCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HBCINTENAS_HBCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMAHBCINTENAR--------------------*/
+/* field: HBCINTDIS - Half block complete (HBC) interrupt disable. */
+#define TMS570_DMA_HBCINTENAR_HBCINTDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HBCINTENAR_HBCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HBCINTENAR_HBCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMABTCINTENAS--------------------*/
+/* field: BTCINTENA - Block transfer complete (BTC) interrupt enable. */
+#define TMS570_DMA_BTCINTENAS_BTCINTENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BTCINTENAS_BTCINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BTCINTENAS_BTCINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMABTCINTENAR--------------------*/
+/* field: BTCINTDIS - Block transfer complete (BTC) interurpt disable. */
+#define TMS570_DMA_BTCINTENAR_BTCINTDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BTCINTENAR_BTCINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BTCINTENAR_BTCINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAGINTFLAG---------------------*/
+/* field: GINT - Global interrupt flags. */
+#define TMS570_DMA_GINTFLAG_GINT(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_GINTFLAG_GINT_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_GINTFLAG_GINT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAFTCFLAG---------------------*/
+/* field: FTCI - Frame transfer complete (FTC) flags. */
+#define TMS570_DMA_FTCFLAG_FTCI(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_FTCFLAG_FTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_FTCFLAG_FTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMALFSFLAG---------------------*/
+/* field: LFSI - Last frame started (LFS) flags. */
+#define TMS570_DMA_LFSFLAG_LFSI(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_LFSFLAG_LFSI_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_LFSFLAG_LFSI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMAHBCFLAG---------------------*/
+/* field: HBCI - Half block transfer (HBC) complete flags. */
+#define TMS570_DMA_HBCFLAG_HBCI(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_HBCFLAG_HBCI_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_HBCFLAG_HBCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMABTCFLAG---------------------*/
+/* field: BTCI - Block transfer complete (BTC) flags. */
+#define TMS570_DMA_BTCFLAG_BTCI(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BTCFLAG_BTCI_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BTCFLAG_BTCI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_DMABERFLAG---------------------*/
+/* field: BERI - Bus error (BER) flags. */
+#define TMS570_DMA_BERFLAG_BERI(val) BSP_FLD32(val,0, 15)
+#define TMS570_DMA_BERFLAG_BERI_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_DMA_BERFLAG_BERI_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_DMAFTCAOFFSET--------------------*/
+/* field: sbz - These bits should always be programmed as zero. */
+#define TMS570_DMA_FTCAOFFSET_sbz(val) BSP_FLD32(val,6, 7)
+#define TMS570_DMA_FTCAOFFSET_sbz_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_DMA_FTCAOFFSET_sbz_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: FTCA - Channel causing FTC interrupt Group A. */
+#define TMS570_DMA_FTCAOFFSET_FTCA(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_FTCAOFFSET_FTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_FTCAOFFSET_FTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMALFSAOFFSET--------------------*/
+/* field: LFSA - Channel causing LFS interrupt Group A. */
+#define TMS570_DMA_LFSAOFFSET_LFSA(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_LFSAOFFSET_LFSA_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_LFSAOFFSET_LFSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMAHBCAOFFSET--------------------*/
+/* field: HBCA - Channel causing HBC interrupt Group A. */
+#define TMS570_DMA_HBCAOFFSET_HBCA(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_HBCAOFFSET_HBCA_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_HBCAOFFSET_HBCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMABTCAOFFSET--------------------*/
+/* field: BTCA - Channel causing BTC interrupt Group A. */
+#define TMS570_DMA_BTCAOFFSET_BTCA(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_BTCAOFFSET_BTCA_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_BTCAOFFSET_BTCA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMABERAOFFSET--------------------*/
+/* field: BERA - Channel causing BER interrupt Group A. */
+#define TMS570_DMA_BERAOFFSET_BERA(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_BERAOFFSET_BERA_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_BERAOFFSET_BERA_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMAFTCBOFFSET--------------------*/
+/* field: FTCB - Channel causing FTC interrupt Group B. */
+#define TMS570_DMA_FTCBOFFSET_FTCB(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_FTCBOFFSET_FTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_FTCBOFFSET_FTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMALFSBOFFSET--------------------*/
+/* field: LFSB - Channel causing LFS interrupt Group B. */
+#define TMS570_DMA_LFSBOFFSET_LFSB(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_LFSBOFFSET_LFSB_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_LFSBOFFSET_LFSB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMAHBCBOFFSET--------------------*/
+/* field: HBCB - Channel causing HBC interrupt Group B. */
+#define TMS570_DMA_HBCBOFFSET_HBCB(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_HBCBOFFSET_HBCB_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_HBCBOFFSET_HBCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMABTCBOFFSET--------------------*/
+/* field: BTCB - interrupt for Group B if the corresponding interrupt enable is set. */
+#define TMS570_DMA_BTCBOFFSET_BTCB(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_BTCBOFFSET_BTCB_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_BTCBOFFSET_BTCB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*--------------------TMS570_DMABERBOFFSET--------------------*/
+/* field: BERB - Channel causing BER interrupt Group B. */
+#define TMS570_DMA_BERBOFFSET_BERB(val) BSP_FLD32(val,0, 5)
+#define TMS570_DMA_BERBOFFSET_BERB_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_DMA_BERBOFFSET_BERB_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*----------------------TMS570_DMAPTCRL----------------------*/
+/* field: PENDB - Transfers pending for Port B. This flag determines if transfers are ongoing on port B. */
+#define TMS570_DMA_PTCRL_PENDB BSP_FLD32(24)
+
+/* field: BYB - Bypass FIFO B. */
+#define TMS570_DMA_PTCRL_BYB BSP_FLD32(18)
+
+/* field: PSFRHQPB - Priority scheme fix or rotate for high priority queue of Port B. */
+#define TMS570_DMA_PTCRL_PSFRHQPB BSP_FLD32(17)
+
+/* field: PSFRLQPB - Priority scheme fix or rotate for low priority queue of Port B. */
+#define TMS570_DMA_PTCRL_PSFRLQPB BSP_FLD32(16)
+
+
+/*----------------------TMS570_DMARTCTRL----------------------*/
+/* field: RTC - RAM Test Control. */
+#define TMS570_DMA_RTCTRL_RTC BSP_FLD32(0)
+
+
+/*----------------------TMS570_DMADCTRL----------------------*/
+/* field: CHNUM - Channel Number. */
+#define TMS570_DMA_DCTRL_CHNUM(val) BSP_FLD32(val,24, 28)
+#define TMS570_DMA_DCTRL_CHNUM_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_DMA_DCTRL_CHNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: DMADBGS - DMA debug status. */
+#define TMS570_DMA_DCTRL_DMADBGS BSP_FLD32(16)
+
+/* field: DBGEN - Debug Enable. */
+#define TMS570_DMA_DCTRL_DBGEN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMAWPR-----------------------*/
+/* field: WP - Watch point. */
+#define TMS570_DMA_WPR_WP(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_DMAWMR-----------------------*/
+/* field: WM - Watch mask. */
+#define TMS570_DMA_WMR_WM(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_DMAPBACSADDR--------------------*/
+/* field: PBACSA - Port B Active Channel Source Address. */
+#define TMS570_DMA_PBACSADDR_PBACSA(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_PBACSADDR_PBACSA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_PBACSADDR_PBACSA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_DMAPBACDADDR--------------------*/
+/* field: PBACDA - address of the active channel as broadcasted in Section 16.3.1.3 for Port B. */
+#define TMS570_DMA_PBACDADDR_PBACDA(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_PBACDADDR_PBACDA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_PBACDADDR_PBACDA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DMAPBACTC----------------------*/
+/* field: PBFTCOUNT - Port B active channel frame count. */
+#define TMS570_DMA_PBACTC_PBFTCOUNT(val) BSP_FLD32(val,16, 28)
+#define TMS570_DMA_PBACTC_PBFTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 28)
+#define TMS570_DMA_PBACTC_PBFTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 28)
+
+/* field: PBETCOUNT - Port B active channel element count. */
+#define TMS570_DMA_PBACTC_PBETCOUNT(val) BSP_FLD32(val,0, 12)
+#define TMS570_DMA_PBACTC_PBETCOUNT_GET(reg) BSP_FLD32GET(reg,0, 12)
+#define TMS570_DMA_PBACTC_PBETCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
+
+
+/*----------------------TMS570_DMADMAPCR----------------------*/
+/* field: ERRA - Error action. */
+#define TMS570_DMA_DMAPCR_ERRA BSP_FLD32(16)
+
+/* field: TEST - When this bit is set, the parity bits are memory mapped to make them accessible by the CPU. */
+#define TMS570_DMA_DMAPCR_TEST BSP_FLD32(8)
+
+/* field: PARITY_ENA - Parity error detection enable. */
+#define TMS570_DMA_DMAPCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMA_DMAPCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMA_DMAPCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_DMADMAPAR----------------------*/
+/* field: EDFLAG - Parity Error Detection Flag. */
+#define TMS570_DMA_DMAPAR_EDFLAG BSP_FLD32(24)
+
+/* field: ERRORADDRESS - Error address. These bits hold the address of the first parity error generated in the RAM. */
+#define TMS570_DMA_DMAPAR_ERRORADDRESS(val) BSP_FLD32(val,0, 11)
+#define TMS570_DMA_DMAPAR_ERRORADDRESS_GET(reg) BSP_FLD32GET(reg,0, 11)
+#define TMS570_DMA_DMAPAR_ERRORADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
+
+
+/*--------------------TMS570_DMADMAMPCTRL--------------------*/
+/* field: INT3AB - Interrupt assignment of region 3 to Group A or Group B. */
+#define TMS570_DMA_DMAMPCTRL_INT3AB BSP_FLD32(28)
+
+/* field: INT3ENA - Interrupt enable of region 3. */
+#define TMS570_DMA_DMAMPCTRL_INT3ENA BSP_FLD32(27)
+
+/* field: REG3AP - Region 3 access permission. */
+#define TMS570_DMA_DMAMPCTRL_REG3AP(val) BSP_FLD32(val,25, 26)
+#define TMS570_DMA_DMAMPCTRL_REG3AP_GET(reg) BSP_FLD32GET(reg,25, 26)
+#define TMS570_DMA_DMAMPCTRL_REG3AP_SET(reg,val) BSP_FLD32SET(reg, val,25, 26)
+
+/* field: REG3ENA - Region 3 enable. */
+#define TMS570_DMA_DMAMPCTRL_REG3ENA BSP_FLD32(24)
+
+/* field: INT2AB - Interrupt assignment of region 2 to Group A or Group B. */
+#define TMS570_DMA_DMAMPCTRL_INT2AB BSP_FLD32(20)
+
+/* field: INT2ENA - Interrupt enable of region 2. */
+#define TMS570_DMA_DMAMPCTRL_INT2ENA BSP_FLD32(19)
+
+/* field: REG2AP - Region 2 access permission. These bits determine the access permission for region 2. */
+#define TMS570_DMA_DMAMPCTRL_REG2AP(val) BSP_FLD32(val,17, 18)
+#define TMS570_DMA_DMAMPCTRL_REG2AP_GET(reg) BSP_FLD32GET(reg,17, 18)
+#define TMS570_DMA_DMAMPCTRL_REG2AP_SET(reg,val) BSP_FLD32SET(reg, val,17, 18)
+
+/* field: REG2ENA - Region 2 enable. */
+#define TMS570_DMA_DMAMPCTRL_REG2ENA BSP_FLD32(16)
+
+/* field: INT1AB - Interrupt assignment of region 1 to Group A or Group B. */
+#define TMS570_DMA_DMAMPCTRL_INT1AB BSP_FLD32(12)
+
+/* field: INT1ENA - Interrupt enable of region 1. */
+#define TMS570_DMA_DMAMPCTRL_INT1ENA BSP_FLD32(11)
+
+/* field: REG1AP - Region 1 access permission. */
+#define TMS570_DMA_DMAMPCTRL_REG1AP(val) BSP_FLD32(val,9, 10)
+#define TMS570_DMA_DMAMPCTRL_REG1AP_GET(reg) BSP_FLD32GET(reg,9, 10)
+#define TMS570_DMA_DMAMPCTRL_REG1AP_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
+
+/* field: REG1ENA - Region 1 enable. */
+#define TMS570_DMA_DMAMPCTRL_REG1ENA BSP_FLD32(8)
+
+/* field: INT0AB - Interrupt assignment of region 0 to Group A or Group B. */
+#define TMS570_DMA_DMAMPCTRL_INT0AB BSP_FLD32(4)
+
+/* field: INT0ENA - Interrupt enable of region 0. */
+#define TMS570_DMA_DMAMPCTRL_INT0ENA BSP_FLD32(3)
+
+/* field: REG0AP - Region 0 access permission. These bits determine the access permission for region 0. */
+#define TMS570_DMA_DMAMPCTRL_REG0AP(val) BSP_FLD32(val,1, 2)
+#define TMS570_DMA_DMAMPCTRL_REG0AP_GET(reg) BSP_FLD32GET(reg,1, 2)
+#define TMS570_DMA_DMAMPCTRL_REG0AP_SET(reg,val) BSP_FLD32SET(reg, val,1, 2)
+
+/* field: REG0ENA - Region 0 enable. */
+#define TMS570_DMA_DMAMPCTRL_REG0ENA BSP_FLD32(0)
+
+
+/*---------------------TMS570_DMADMAMPST---------------------*/
+/* field: REG3FT - Region 3 fault. */
+#define TMS570_DMA_DMAMPST_REG3FT BSP_FLD32(24)
+
+/* field: REG2FT - Region 2 fault. */
+#define TMS570_DMA_DMAMPST_REG2FT BSP_FLD32(16)
+
+/* field: REG1FT - Region 1 fault. */
+#define TMS570_DMA_DMAMPST_REG1FT BSP_FLD32(8)
+
+/* field: REG0FT - Region 0 fault. */
+#define TMS570_DMA_DMAMPST_REG0FT BSP_FLD32(0)
+
+
+/*---------------------TMS570_DMADMAMPROS---------------------*/
+/* field: STARTADDRESS - Start Address defines the address at which the region begins. */
+#define TMS570_DMA_DMAMPROS_STARTADDRESS(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMA_DMAMPROS_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMA_DMAMPROS_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_DMA */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
new file mode 100644
index 0000000..1d45ac7
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_dmm.h
@@ -0,0 +1,560 @@
+/* The header file is generated by make_header.py from DMM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_DMM
+#define LIBBSP_ARM_tms570_DMM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GLBCTRL; /*DMM Global Control Register*/
+ uint32_t INTSET; /*DMM Interrupt Set Register*/
+ uint32_t INTCLR; /*DMM Interrupt Clear Register*/
+ uint32_t INTLVL; /*DMM Interrupt Level Register*/
+ uint32_t INTFLG; /*DMM Interrupt Flag Register*/
+ uint32_t OFF1; /*DMM Interrupt Offset 1 Register*/
+ uint32_t OFF2; /*DMM Interrupt Offset 2 Register*/
+ uint32_t DDMDEST; /*DMM Direct Data Mode Destination Register*/
+ uint32_t DDMBL; /*DMM Direct Data Mode Blocksize Register*/
+ uint32_t DDMPT; /*DMM Direct Data Mode Pointer Register*/
+ uint32_t INTPT; /*DMM Direct Data Mode Interrupt Pointer Register*/
+ uint32_t DEST0REG1; /*DMM Destination 0 Region 1*/
+ uint32_t DEST0BL1; /*DMM Destination 0 Blocksize 1*/
+ uint32_t DEST0REG2; /*DMM Destination 0 Region 2*/
+ uint32_t DEST0BL2; /*DMM Destination 0 Blocksize 2*/
+ uint32_t DEST1REG1; /*DMM Destination 1 Region 1*/
+ uint32_t DEST1BL1; /*DMM Destination 1 Blocksize 1*/
+ uint32_t DEST1REG2; /*DMM Destination 1 Region 2*/
+ uint32_t DEST1BL2; /*DMM Destination 1 Blocksize 2*/
+ uint32_t DEST2REG1; /*DMM Destination 2 Region 1*/
+ uint32_t DEST2BL1; /*DMM Destination 2 Blocksize 1*/
+ uint32_t DEST2REG2; /*DMM Destination 2 Region 2*/
+ uint32_t DEST2BL2; /*DMM Destination 2 Blocksize 2*/
+ uint32_t DEST3REG1; /*DMM Destination 3 Region 1*/
+ uint32_t DEST3BL1; /*DMM Destination 3 Blocksize 1*/
+ uint32_t DEST3REG2; /*DMM Destination 3 Region 2*/
+ uint32_t DEST3BL2; /*DMM Destination 3 Blocksize 2*/
+ uint32_t PC0; /*DMM Pin Control 0*/
+ uint32_t PC1; /*DMM Pin Control 1*/
+ uint32_t PC2; /*DMM Pin Control 2*/
+ uint32_t PC3; /*DMM Pin Control 3*/
+ uint32_t PC4; /*DMM Pin Control 4*/
+ uint32_t PC5; /*DMM Pin Control 5*/
+ uint32_t PC6; /*DMM Pin Control 6*/
+ uint32_t PC7; /*DMM Pin Control 7*/
+ uint32_t PC8; /*DMM Pin Control 8*/
+} tms570_dmm_t;
+
+
+/*---------------------TMS570_DMMGLBCTRL---------------------*/
+/* field: BUSY - Busy indicator. */
+#define TMS570_DMM_GLBCTRL_BUSY BSP_FLD32(24)
+
+/* field: CONTCLK - Continuous DMMCLK input. */
+#define TMS570_DMM_GLBCTRL_CONTCLK BSP_FLD32(18)
+
+/* field: COS - Continue on suspend. Influences behavior of module while in debug mode. */
+#define TMS570_DMM_GLBCTRL_COS BSP_FLD32(17)
+
+/* field: RESET - Reset. */
+#define TMS570_DMM_GLBCTRL_RESET BSP_FLD32(16)
+
+/* field: DDM_WIDTH - Packet Width in direct data mode. */
+#define TMS570_DMM_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,9, 10)
+#define TMS570_DMM_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,9, 10)
+#define TMS570_DMM_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
+
+/* field: TM_DMM - Packet Format. */
+#define TMS570_DMM_GLBCTRL_TM_DMM BSP_FLD32(8)
+
+/* field: ON_OFF - Switch module on or off */
+#define TMS570_DMM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_DMMINTSET----------------------*/
+/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
+#define TMS570_DMM_INTSET_PROG_BUFF BSP_FLD32(17)
+
+/* field: EO_BUFF - EO_BUFF */
+#define TMS570_DMM_INTSET_EO_BUFF BSP_FLD32(16)
+
+/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST3REG2 BSP_FLD32(15)
+
+/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST3REG1 BSP_FLD32(14)
+
+/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST2REG2 BSP_FLD32(13)
+
+/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST2REG1 BSP_FLD32(12)
+
+/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST1REG2 BSP_FLD32(11)
+
+/* field: DEST1REG1 - DEST1REG1 */
+#define TMS570_DMM_INTSET_DEST1REG1 BSP_FLD32(10)
+
+/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST0REG2 BSP_FLD32(9)
+
+/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST0REG1 BSP_FLD32(8)
+
+/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
+#define TMS570_DMM_INTSET_BUSERROR BSP_FLD32(7)
+
+/* field: BUFF_OVF - Buffer Overflow. */
+#define TMS570_DMM_INTSET_BUFF_OVF BSP_FLD32(6)
+
+/* field: SRC_OVF - Source Overflow. */
+#define TMS570_DMM_INTSET_SRC_OVF BSP_FLD32(5)
+
+/* field: DEST3_ERR - Destination 3 Error. */
+#define TMS570_DMM_INTSET_DEST3_ERR BSP_FLD32(4)
+
+/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST2_ERR BSP_FLD32(3)
+
+/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST1_ERR BSP_FLD32(2)
+
+/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
+#define TMS570_DMM_INTSET_DEST0_ERR BSP_FLD32(1)
+
+/* field: PACKET_ERR_INT - Packet Error. */
+#define TMS570_DMM_INTSET_PACKET_ERR_INT BSP_FLD32(0)
+
+
+/*----------------------TMS570_DMMINTCLR----------------------*/
+/* field: PROG_BUFF - Programmable Buffer Interrupt Set. */
+#define TMS570_DMM_INTCLR_PROG_BUFF BSP_FLD32(17)
+
+/* field: EO_BUFF - End of Buffer Interrupt Set. */
+#define TMS570_DMM_INTCLR_EO_BUFF BSP_FLD32(16)
+
+/* field: DEST3REG2 - was accessed at the startaddress of Destination 3 Region 2. */
+#define TMS570_DMM_INTCLR_DEST3REG2 BSP_FLD32(15)
+
+/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST3REG1 BSP_FLD32(14)
+
+/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST2REG2 BSP_FLD32(13)
+
+/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST2REG1 BSP_FLD32(12)
+
+/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST1REG2 BSP_FLD32(11)
+
+/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST1REG1 BSP_FLD32(10)
+
+/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST0REG2 BSP_FLD32(9)
+
+/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST0REG1 BSP_FLD32(8)
+
+/* field: BUSERROR - Bus Error Response for errors generated when doing internal bus transfers. */
+#define TMS570_DMM_INTCLR_BUSERROR BSP_FLD32(7)
+
+/* field: BUFF_OVF - Buffer Overflow. */
+#define TMS570_DMM_INTCLR_BUFF_OVF BSP_FLD32(6)
+
+/* field: SRC_OVF - Source Overflow. */
+#define TMS570_DMM_INTCLR_SRC_OVF BSP_FLD32(5)
+
+/* field: DEST3_ERR - Destination 3 Error. */
+#define TMS570_DMM_INTCLR_DEST3_ERR BSP_FLD32(4)
+
+/* field: DEST2_ERR - Destination 2 Error Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST2_ERR BSP_FLD32(3)
+
+/* field: DEST1_ERR - Destination 1 Error Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST1_ERR BSP_FLD32(2)
+
+/* field: DEST0_ERR - Destination 0 Error Interrupt Set. */
+#define TMS570_DMM_INTCLR_DEST0_ERR BSP_FLD32(1)
+
+/* field: PACKET_ERR_INT - Packet Error. */
+#define TMS570_DMM_INTCLR_PACKET_ERR_INT BSP_FLD32(0)
+
+
+/*----------------------TMS570_DMMINTLVL----------------------*/
+/* field: PROG_BUFF - Programmable Buffer Interrupt Level */
+#define TMS570_DMM_INTLVL_PROG_BUFF BSP_FLD32(17)
+
+/* field: EO_BUFF - End of Buffer Interrupt Level */
+#define TMS570_DMM_INTLVL_EO_BUFF BSP_FLD32(16)
+
+/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST3REG2 BSP_FLD32(15)
+
+/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST3REG1 BSP_FLD32(14)
+
+/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST2REG2 BSP_FLD32(13)
+
+/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST2REG1 BSP_FLD32(12)
+
+/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST1REG2 BSP_FLD32(11)
+
+/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST1REG1 BSP_FLD32(10)
+
+/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST0REG2 BSP_FLD32(9)
+
+/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST0REG1 BSP_FLD32(8)
+
+/* field: BUSERROR - BMM Bus Error Response */
+#define TMS570_DMM_INTLVL_BUSERROR BSP_FLD32(7)
+
+/* field: BUFF_OVF - Write Buffer Overflow Interrupt Level */
+#define TMS570_DMM_INTLVL_BUFF_OVF BSP_FLD32(6)
+
+/* field: SRC_OVF - Source Overflow Interrupt Level */
+#define TMS570_DMM_INTLVL_SRC_OVF BSP_FLD32(5)
+
+/* field: DEST3_ERR - Destination 3 Error Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST3_ERR BSP_FLD32(4)
+
+/* field: DEST2_ERR - Destination 2 Error Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST2_ERR BSP_FLD32(3)
+
+/* field: DEST1_ERR - Destination 1 Error Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST1_ERR BSP_FLD32(2)
+
+/* field: DEST0_ERR - Destination 0 Error Interrupt Level */
+#define TMS570_DMM_INTLVL_DEST0_ERR BSP_FLD32(1)
+
+/* field: PACKET_ERR_INT - Packet Error Interrupt Level */
+#define TMS570_DMM_INTLVL_PACKET_ERR_INT BSP_FLD32(0)
+
+
+/*----------------------TMS570_DMMINTFLG----------------------*/
+/* field: PROG_BUFF - Programmable Buffer Interrupt Flag */
+#define TMS570_DMM_INTFLG_PROG_BUFF BSP_FLD32(17)
+
+/* field: EO_BUFF - End of Buffer Interrupt Flag */
+#define TMS570_DMM_INTFLG_EO_BUFF BSP_FLD32(16)
+
+/* field: DEST3REG2 - Destination 3 Region 2 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST3REG2 BSP_FLD32(15)
+
+/* field: DEST3REG1 - Destination 3 Region 1 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST3REG1 BSP_FLD32(14)
+
+/* field: DEST2REG2 - Destination 2 Region 2 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST2REG2 BSP_FLD32(13)
+
+/* field: DEST2REG1 - Destination 2 Region 1 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST2REG1 BSP_FLD32(12)
+
+/* field: DEST1REG2 - Destination 1 Region 2 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST1REG2 BSP_FLD32(11)
+
+/* field: DEST1REG1 - Destination 1 Region 1 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST1REG1 BSP_FLD32(10)
+
+/* field: DEST0REG2 - Destination 0 Region 2 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST0REG2 BSP_FLD32(9)
+
+/* field: DEST0REG1 - Destination 0 Region 1 Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST0REG1 BSP_FLD32(8)
+
+/* field: BUSERROR - BMM Bus Error Response. */
+#define TMS570_DMM_INTFLG_BUSERROR BSP_FLD32(7)
+
+/* field: BUFF_OVF - Write Buffer Overflow Interrupt Flag */
+#define TMS570_DMM_INTFLG_BUFF_OVF BSP_FLD32(6)
+
+/* field: SRC_OVF - Source Overflow Interrupt Flag */
+#define TMS570_DMM_INTFLG_SRC_OVF BSP_FLD32(5)
+
+/* field: DEST3_ERR - Destination 3 Error Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST3_ERR BSP_FLD32(4)
+
+/* field: DEST2_ERR - Destination 2 Error Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST2_ERR BSP_FLD32(3)
+
+/* field: DEST1_ERR - Destination 1 Error Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST1_ERR BSP_FLD32(2)
+
+/* field: DEST0_ERR - Destination 0 Error Interrupt Flag */
+#define TMS570_DMM_INTFLG_DEST0_ERR BSP_FLD32(1)
+
+/* field: PACKET_ERR_INT - Packet Error Interrupt Flag */
+#define TMS570_DMM_INTFLG_PACKET_ERR_INT BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMOFF1-----------------------*/
+/* field: OFFSET - User and privilege mode (read): */
+#define TMS570_DMM_OFF1_OFFSET(val) BSP_FLD32(val,0, 4)
+#define TMS570_DMM_OFF1_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_DMM_OFF1_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*-----------------------TMS570_DMMOFF2-----------------------*/
+/* field: OFFSET - User and privilege mode (read): */
+#define TMS570_DMM_OFF2_OFFSET(val) BSP_FLD32(val,0, 4)
+#define TMS570_DMM_OFF2_OFFSET_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_DMM_OFF2_OFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*---------------------TMS570_DMMDDMDEST---------------------*/
+/* field: STARTADDR - These bits define the starting address of the buffer. */
+#define TMS570_DMM_DDMDEST_STARTADDR(val) BSP_FLD32(val,0, 31)
+#define TMS570_DMM_DDMDEST_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_DMM_DDMDEST_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_DMMDDMBL----------------------*/
+/* field: BLOCKSIZE - These bits define the size of the buffer region */
+#define TMS570_DMM_DDMBL_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DDMBL_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DDMBL_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_DMMDDMPT----------------------*/
+/* field: POINTER - These bits hold the pointer to the next entry to be written in the buffer. */
+#define TMS570_DMM_DDMPT_POINTER(val) BSP_FLD32(val,0, 14)
+#define TMS570_DMM_DDMPT_POINTER_GET(reg) BSP_FLD32GET(reg,0, 14)
+#define TMS570_DMM_DDMPT_POINTER_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
+
+
+/*----------------------TMS570_DMMINTPT----------------------*/
+/* field: INTPT - Interrupt Pointer. When the buffer pointer (Section 30.3. */
+#define TMS570_DMM_INTPT_INTPT(val) BSP_FLD32(val,0, 14)
+#define TMS570_DMM_INTPT_INTPT_GET(reg) BSP_FLD32GET(reg,0, 14)
+#define TMS570_DMM_INTPT_INTPT_SET(reg,val) BSP_FLD32SET(reg, val,0, 14)
+
+
+/*--------------------TMS570_DMMDEST0REG1--------------------*/
+/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
+#define TMS570_DMM_DEST0REG1_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DEST0REG1_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DEST0REG1_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+
+/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
+#define TMS570_DMM_DEST0REG1_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DEST0REG1_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DEST0REG1_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+
+
+/*---------------------TMS570_DMMDEST0BL1---------------------*/
+/* field: BLOCKSIZE - These bits define the length of the buffer region. */
+#define TMS570_DMM_DEST0BL1_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DEST0BL1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DEST0BL1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_DMMDEST0REG2--------------------*/
+/* field: BASEADDR - These bits define the base address of the 256kB region where the buffer is located. */
+#define TMS570_DMM_DEST0REG2_BASEADDR(val) BSP_FLD32(val,18, 31)
+#define TMS570_DMM_DEST0REG2_BASEADDR_GET(reg) BSP_FLD32GET(reg,18, 31)
+#define TMS570_DMM_DEST0REG2_BASEADDR_SET(reg,val) BSP_FLD32SET(reg, val,18, 31)
+
+/* field: BLOCKADDR - These bits define the starting address of the buffer in the 256kB page. */
+#define TMS570_DMM_DEST0REG2_BLOCKADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_DMM_DEST0REG2_BLOCKADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_DMM_DEST0REG2_BLOCKADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+
+
+/*---------------------TMS570_DMMDEST0BL2---------------------*/
+/* field: BLOCKSIZE - These bits define the length of the buffer region. */
+#define TMS570_DMM_DEST0BL2_BLOCKSIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_DMM_DEST0BL2_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_DMM_DEST0BL2_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_DMMPC0-----------------------*/
+/* field: ENAFUNC - Functional mode of DMMENA pin. */
+#define TMS570_DMM_PC0_ENAFUNC BSP_FLD32(18)
+
+/* field: DATAxFUNC - Functional mode of DMMDATA[x] pin. */
+#define TMS570_DMM_PC0_DATAxFUNC(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC0_DATAxFUNC_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC0_DATAxFUNC_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKFUNC - Functional mode of DMMCLK pin. */
+#define TMS570_DMM_PC0_CLKFUNC BSP_FLD32(1)
+
+/* field: SYNCFUNC - Functional mode of DMMSYNC pin. */
+#define TMS570_DMM_PC0_SYNCFUNC BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC1-----------------------*/
+/* field: ENADIR - Direction of DMMENA pin. */
+#define TMS570_DMM_PC1_ENADIR BSP_FLD32(18)
+
+/* field: DATAxDIR - Direction of DMMDATA[x] pin. */
+#define TMS570_DMM_PC1_DATAxDIR(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC1_DATAxDIR_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC1_DATAxDIR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKDIR - Direction of DMMCLK pin. */
+#define TMS570_DMM_PC1_CLKDIR BSP_FLD32(1)
+
+/* field: SYNCDIR - Direction of DMMSYNC pin. */
+#define TMS570_DMM_PC1_SYNCDIR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC2-----------------------*/
+/* field: ENAIN - DMMENA input. This bit reflects the state of the pin in all modes. */
+#define TMS570_DMM_PC2_ENAIN BSP_FLD32(18)
+
+/* field: DATAxIN - DMMDATA[x] input. This bit reflects the state of the pin in all modes. */
+#define TMS570_DMM_PC2_DATAxIN(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC2_DATAxIN_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC2_DATAxIN_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKIN - DMMCLK input. This bit reflects the state of the pin in all modes. */
+#define TMS570_DMM_PC2_CLKIN BSP_FLD32(1)
+
+/* field: SYNCIN - DMMSYNC input. */
+#define TMS570_DMM_PC2_SYNCIN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC3-----------------------*/
+/* field: ENAOUT - Output state of DMMENA pin. */
+#define TMS570_DMM_PC3_ENAOUT BSP_FLD32(18)
+
+/* field: DATAxOUT - Output state of DMMDATA[x] pin. This bit sets the pin to logic low or high level. */
+#define TMS570_DMM_PC3_DATAxOUT(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC3_DATAxOUT_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC3_DATAxOUT_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKOUT - Output state of DMMCLK pin. */
+#define TMS570_DMM_PC3_CLKOUT BSP_FLD32(1)
+
+/* field: SYNCOUT - Output state of DMMSYNC pin. This bit sets the pin to logic low or high level. */
+#define TMS570_DMM_PC3_SYNCOUT BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC4-----------------------*/
+/* field: ENASET - control register bit to 1 regardless of the current value in the ENAOUT bit. */
+#define TMS570_DMM_PC4_ENASET BSP_FLD32(18)
+
+/* field: DATAxSET - Sets output state of DMMDATA[x] pin to logic high. */
+#define TMS570_DMM_PC4_DATAxSET(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC4_DATAxSET_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC4_DATAxSET_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKSET - Sets output state of DMMCLK pin to logic high. */
+#define TMS570_DMM_PC4_CLKSET BSP_FLD32(1)
+
+/* field: SYNCSET - Sets output state of DMMSYNC pin logic high. */
+#define TMS570_DMM_PC4_SYNCSET BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC5-----------------------*/
+/* field: ENACLR - Sets output state of DMMENA pin to logic low. */
+#define TMS570_DMM_PC5_ENACLR BSP_FLD32(18)
+
+/* field: DATAxCLR - Sets output state of DMMDATA[x] pin to logic low. */
+#define TMS570_DMM_PC5_DATAxCLR(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC5_DATAxCLR_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC5_DATAxCLR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKCLR - Sets output state of DMMCLK pin to logic low. */
+#define TMS570_DMM_PC5_CLKCLR BSP_FLD32(1)
+
+/* field: SYNCCLR - Sets output state of DMMSYNC pin to logic low. */
+#define TMS570_DMM_PC5_SYNCCLR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC6-----------------------*/
+/* field: ENAPDR - Open Drain enable. */
+#define TMS570_DMM_PC6_ENAPDR BSP_FLD32(18)
+
+/* field: DATAxPDR - Open Drain enable. */
+#define TMS570_DMM_PC6_DATAxPDR(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC6_DATAxPDR_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC6_DATAxPDR_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKPDR - Open Drain enable. */
+#define TMS570_DMM_PC6_CLKPDR BSP_FLD32(1)
+
+/* field: SYNCPDR - Open Drain enable. */
+#define TMS570_DMM_PC6_SYNCPDR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC7-----------------------*/
+/* field: ENAPDIS - Pull disable. */
+#define TMS570_DMM_PC7_ENAPDIS BSP_FLD32(18)
+
+/* field: DATAxPDIS - Pull disable. */
+#define TMS570_DMM_PC7_DATAxPDIS(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC7_DATAxPDIS_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC7_DATAxPDIS_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKPDIS - Pull disable. */
+#define TMS570_DMM_PC7_CLKPDIS BSP_FLD32(1)
+
+/* field: SYNCPDIS - Pull disable. */
+#define TMS570_DMM_PC7_SYNCPDIS BSP_FLD32(0)
+
+
+/*-----------------------TMS570_DMMPC8-----------------------*/
+/* field: ENAPSEL - Pull disable. */
+#define TMS570_DMM_PC8_ENAPSEL BSP_FLD32(18)
+
+/* field: DATAxPSEL - Pull disable. */
+#define TMS570_DMM_PC8_DATAxPSEL(val) BSP_FLD32(val,2, 17)
+#define TMS570_DMM_PC8_DATAxPSEL_GET(reg) BSP_FLD32GET(reg,2, 17)
+#define TMS570_DMM_PC8_DATAxPSEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 17)
+
+/* field: CLKPSEL - Pull disable. */
+#define TMS570_DMM_PC8_CLKPSEL BSP_FLD32(1)
+
+/* field: SYNCPSEL - Pull disable. */
+#define TMS570_DMM_PC8_SYNCPSEL BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_DMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
new file mode 100644
index 0000000..190536c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_efuse.h
@@ -0,0 +1,132 @@
+/* The header file is generated by make_header.py from EFUSE.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_EFUSE
+#define LIBBSP_ARM_tms570_EFUSE
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t EFCBOUND; /*EFC Boundary Control Register*/
+ uint8_t reserved1 [12];
+ uint32_t EFCPINS; /*EFC Pins Register*/
+ uint8_t reserved2 [12];
+ uint32_t EFC_ERR_STAT; /*EFC Error Status Register*/
+ uint8_t reserved3 [8];
+ uint32_t EFC_ST_CY; /*EFC Self Test Cycles Register*/
+ uint32_t EFC_ST_SIG; /*EFC Self Test Signature Register*/
+} tms570_efuse_t;
+
+
+/*--------------------TMS570_EFUSEEFCBOUND--------------------*/
+/* field: EFC_Self_Test_Error - This bit drives the self test error signal when bit 17 (Self Test Error OE) is high. */
+#define TMS570_EFUSE_EFCBOUND_EFC_Self_Test_Error BSP_FLD32(21)
+
+/* field: EFC_Single_Bit_Error - This bit drives the single bit error signal when bit 16 (Single bit Error OE) is high. */
+#define TMS570_EFUSE_EFCBOUND_EFC_Single_Bit_Error BSP_FLD32(20)
+
+/* field: EFC_Instruction_Error - This bit drives the instruction error signal when bit 15 (Instruction Error OE) is high. */
+#define TMS570_EFUSE_EFCBOUND_EFC_Instruction_Error BSP_FLD32(19)
+
+/* field: EFC_Autoload_Error - This bit drives the Autoload Error signal when bit 14 (Autoload Error OE) is high. */
+#define TMS570_EFUSE_EFCBOUND_EFC_Autoload_Error BSP_FLD32(18)
+
+/* field: Self_Test_Error_OE - The Self Test Error Output Enable bit determines if the EFC Self Test signal comes from the */
+#define TMS570_EFUSE_EFCBOUND_Self_Test_Error_OE BSP_FLD32(17)
+
+/* field: Single_Bit_Error_OE - The single bit error output enable signal determines if the EFC Single Bit Error signal comes */
+#define TMS570_EFUSE_EFCBOUND_Single_Bit_Error_OE BSP_FLD32(16)
+
+/* field: Instruction_Error_OE - comes from the eFuse controller or from bit 19 of the boundary register. */
+#define TMS570_EFUSE_EFCBOUND_Instruction_Error_OE BSP_FLD32(15)
+
+/* field: Autoload_Error_OE - The autoload error output enable signal determines if the EFC Autoload Error signal comes */
+#define TMS570_EFUSE_EFCBOUND_Autoload_Error_OE BSP_FLD32(14)
+
+/* field: EFC_ECC_Selftest - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
+#define TMS570_EFUSE_EFCBOUND_EFC_ECC_Selftest BSP_FLD32(13)
+
+/* field: Input_Enable - The eFuse Controller ECC Selftest Enable bit starts the selftest of the ECC logic if the four */
+#define TMS570_EFUSE_EFCBOUND_Input_Enable(val) BSP_FLD32(val,0, 3)
+#define TMS570_EFUSE_EFCBOUND_Input_Enable_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_EFUSE_EFCBOUND_Input_Enable_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_EFUSEEFCPINS--------------------*/
+/* field: EFC_Selftest_Done - This bit can be polled to determine when the EFC ECC selftest is complete */
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Done BSP_FLD32(15)
+
+/* field: EFC_Selftest_Error - This bit indicates the pass/fail status of the EFC ECC Selftest once the EFC Selftest Done */
+#define TMS570_EFUSE_EFCPINS_EFC_Selftest_Error BSP_FLD32(14)
+
+/* field: EFC_Single_Bit_Error - This bit indicates if a single bit error was corrected by the ECC logic during the autoload */
+#define TMS570_EFUSE_EFCPINS_EFC_Single_Bit_Error BSP_FLD32(12)
+
+/* field: EFC_Instruction_Error - This bit indicates an error occured during a factory test or program operation. */
+#define TMS570_EFUSE_EFCPINS_EFC_Instruction_Error BSP_FLD32(11)
+
+/* field: EFC_Autoload_Error - This bit indicates that some non-correctable error occurred during the autoload sequence */
+#define TMS570_EFUSE_EFCPINS_EFC_Autoload_Error BSP_FLD32(10)
+
+
+/*------------------TMS570_EFUSEEFC_ERR_STAT------------------*/
+/* field: Instruc_Done - Instruction done. */
+#define TMS570_EFUSE_EFC_ERR_STAT_Instruc_Done BSP_FLD32(5)
+
+/* field: Error_Code - The error status of the last instruction executed by the eFuse Controller */
+#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code(val) BSP_FLD32(val,0, 4)
+#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EFUSE_EFC_ERR_STAT_Error_Code_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*-------------------TMS570_EFUSEEFC_ST_CY-------------------*/
+/* field: Cycles - This register is used to determine the number of cycles to run the eFuse controller ECC logic self test. */
+#define TMS570_EFUSE_EFC_ST_CY_Cycles(val) BSP_FLD32(val,0, 31)
+#define TMS570_EFUSE_EFC_ST_CY_Cycles_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EFUSE_EFC_ST_CY_Cycles_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_EFUSEEFC_ST_SIG-------------------*/
+/* field: Signature - This register is used to hold the expected signature for the eFuse ECC logic self test. */
+#define TMS570_EFUSE_EFC_ST_SIG_Signature(val) BSP_FLD32(val,0, 31)
+#define TMS570_EFUSE_EFC_ST_SIG_Signature_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EFUSE_EFC_ST_SIG_Signature_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_EFUSE */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
new file mode 100644
index 0000000..5783e99
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emac.h
@@ -0,0 +1,239 @@
+/* The header file is generated by make_header.py from EMAC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_EMAC
+#define LIBBSP_ARM_tms570_EMAC
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t REVID; /*MDIO Revision ID Register*/
+ uint32_t CONTROL; /*MDIO Control Register*/
+ uint32_t ALIVE; /*PHY Alive Status register*/
+ uint32_t LINK; /*PHY Link Status Register*/
+ uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/
+ uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/
+ uint8_t reserved1 [8];
+ uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/
+ uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/
+ uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/
+ uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/
+ uint8_t reserved2 [80];
+ uint32_t USERACCESS0; /*MDIO User Access Register 0*/
+ uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/
+ uint32_t USERACCESS1; /*MDIO User Access Register 1*/
+ uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/
+} tms570_emac_t;
+
+
+/*----------------------TMS570_EMACREVID----------------------*/
+/* field: REV - Identifies the MDIO Module revision. */
+#define TMS570_EMAC_REVID_REV(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMAC_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMAC_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_EMACCONTROL---------------------*/
+/* field: IDLE - State machine IDLE status bit. */
+#define TMS570_EMAC_CONTROL_IDLE BSP_FLD32(31)
+
+/* field: ENABLE - State machine enable control bit. */
+#define TMS570_EMAC_CONTROL_ENABLE BSP_FLD32(30)
+
+/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
+#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
+#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_EMAC_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: PREAMBLE - Preamble disable */
+#define TMS570_EMAC_CONTROL_PREAMBLE BSP_FLD32(20)
+
+/* field: FAULT - Fault indicator. */
+#define TMS570_EMAC_CONTROL_FAULT BSP_FLD32(19)
+
+/* field: FAULTENB - Fault detect enable. */
+#define TMS570_EMAC_CONTROL_FAULTENB BSP_FLD32(18)
+
+/* field: CLKDIV - Clock Divider bits. */
+#define TMS570_EMAC_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMAC_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMAC_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_EMACALIVE----------------------*/
+/* field: ALIVE - MDIO Alive bits. */
+#define TMS570_EMAC_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMAC_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMAC_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_EMACLINK----------------------*/
+/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
+#define TMS570_EMAC_LINK_LINK(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMAC_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMAC_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_EMACLINKINTRAW-------------------*/
+/* field: USERPHY1 - MDIO Link change event, raw value. */
+#define TMS570_EMAC_LINKINTRAW_USERPHY1 BSP_FLD32(1)
+
+/* field: USERPHY0 - MDIO Link change event, raw value. */
+#define TMS570_EMAC_LINKINTRAW_USERPHY0 BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACLINKINTMASKED------------------*/
+/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
+#define TMS570_EMAC_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
+
+/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
+#define TMS570_EMAC_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACUSERINTRAW-------------------*/
+/* field: USERACCESS1 - MDIO User command complete event bit. */
+#define TMS570_EMAC_USERINTRAW_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO User command complete event bit. */
+#define TMS570_EMAC_USERINTRAW_USERACCESS0 BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACUSERINTMASKED------------------*/
+/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
+#define TMS570_EMAC_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
+#define TMS570_EMAC_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACUSERINTMASKSET-----------------*/
+/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
+#define TMS570_EMAC_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
+#define TMS570_EMAC_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
+
+
+/*----------------TMS570_EMACUSERINTMASKCLEAR----------------*/
+/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
+#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
+#define TMS570_EMAC_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACUSERACCESS0-------------------*/
+/* field: GO - Go bit. */
+#define TMS570_EMAC_USERACCESS0_GO BSP_FLD32(31)
+
+/* field: WRITE - Write enable bit. */
+#define TMS570_EMAC_USERACCESS0_WRITE BSP_FLD32(30)
+
+/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
+#define TMS570_EMAC_USERACCESS0_ACK BSP_FLD32(29)
+
+/* field: REGADR - Register address bits. */
+#define TMS570_EMAC_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
+#define TMS570_EMAC_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
+#define TMS570_EMAC_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
+
+/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
+#define TMS570_EMAC_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20)
+#define TMS570_EMAC_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_EMAC_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: DATA - User data bits. */
+#define TMS570_EMAC_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMAC_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMAC_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_EMACUSERPHYSEL0-------------------*/
+/* field: LINKSEL - Link status determination select bit. */
+#define TMS570_EMAC_USERPHYSEL0_LINKSEL BSP_FLD32(7)
+
+/* field: LINKINTENB - Link change interrupt enable. */
+#define TMS570_EMAC_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
+
+/* field: PHYADRMON - PHY address whose link status is to be monitored. */
+#define TMS570_EMAC_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
+#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EMAC_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*-------------------TMS570_EMACUSERACCESS1-------------------*/
+/* field: GO - Go bit. */
+#define TMS570_EMAC_USERACCESS1_GO BSP_FLD32(31)
+
+/* field: WRITE - Write enable bit. */
+#define TMS570_EMAC_USERACCESS1_WRITE BSP_FLD32(30)
+
+/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
+#define TMS570_EMAC_USERACCESS1_ACK BSP_FLD32(29)
+
+/* field: REGADR - Register address bits. */
+#define TMS570_EMAC_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
+#define TMS570_EMAC_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
+#define TMS570_EMAC_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
+
+/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
+#define TMS570_EMAC_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20)
+#define TMS570_EMAC_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_EMAC_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: DATA - User data bits. */
+#define TMS570_EMAC_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMAC_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMAC_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_EMACUSERPHYSEL1-------------------*/
+/* field: LINKSEL - Link status determination select bit. */
+#define TMS570_EMAC_USERPHYSEL1_LINKSEL BSP_FLD32(7)
+
+/* field: LINKINTENB - Link change interrupt enable. */
+#define TMS570_EMAC_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
+
+/* field: PHYADRMON - PHY address whose link status is to be monitored. */
+#define TMS570_EMAC_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
+#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EMAC_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+
+#endif /* LIBBSP_ARM_tms570_EMAC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
new file mode 100644
index 0000000..18cc7a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emacm.h
@@ -0,0 +1,922 @@
+/* The header file is generated by make_header.py from EMACM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_EMACM
+#define LIBBSP_ARM_tms570_EMACM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t TXREVID; /*Transmit Revision ID Register*/
+ uint32_t TXCONTROL; /*Transmit Control Register*/
+ uint32_t TXTEARDOWN; /*Transmit Teardown Register*/
+ uint8_t reserved1 [4];
+ uint32_t RXREVID; /*Receive Revision ID Register*/
+ uint32_t RXCONTROL; /*Receive Control Register*/
+ uint32_t RXTEARDOWN; /*Receive Teardown Register*/
+ uint8_t reserved2 [100];
+ uint32_t TXINTSTATRAW; /*Transmit Interrupt Status (Unmasked) Register*/
+ uint32_t TXINTSTATMASKED; /*Transmit Interrupt Status (Masked) Register*/
+ uint32_t TXINTMASKSET; /*Transmit Interrupt Mask Set Register*/
+ uint32_t TXINTMASKCLEAR; /*Transmit Interrupt Clear Register*/
+ uint32_t MACINVECTOR; /*MAC Input Vector Register*/
+ uint32_t MACEOIVECTOR; /*MAC End Of Interrupt Vector Register*/
+ uint8_t reserved3 [8];
+ uint32_t RXINTSTATRAW; /*Receive Interrupt Status (Unmasked) Register*/
+ uint32_t RXINTSTATMASKED; /*Receive Interrupt Status (Masked) Register*/
+ uint32_t RXINTMASKSET; /*Receive Interrupt Mask Set Register*/
+ uint32_t RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/
+ uint32_t MACINTSTATRAW; /*MAC Interrupt Status (Unmasked) Register*/
+ uint32_t MACINTSTATMASKED; /*MAC Interrupt Status (Masked) Register*/
+ uint32_t MACINTMASKSET; /*MAC Interrupt Mask Set Register*/
+ uint32_t MACINTMASKCLEAR; /*MAC Interrupt Mask Clear Register*/
+ uint8_t reserved4 [64];
+ uint32_t RXMBPENABLE; /*Receive Multicast/Broadcast/Promiscuous Channel Enable*/
+ uint32_t RXUNICASTSET; /*Receive Unicast Enable Set Register*/
+ uint32_t RXUNICASTCLEAR; /*Receive Unicast Clear Register*/
+ uint32_t RXMAXLEN; /*Receive Maximum Length Register*/
+ uint32_t RXBUFFEROFFSET; /*Receive Buffer Offset Register*/
+ uint32_t RXFILTERLOWTHRESH; /*Receive Filter Low Priority Frame Threshold Register*/
+ uint8_t reserved5 [8];
+ uint32_t RXFLOWTHRESH[8]; /*Receive Channel Flow Control Threshold Register*/
+ uint32_t RXFREEBUFFER[8]; /*Receive Channel Free Buffer Count Register*/
+ uint32_t MACCONTROL; /*MAC Control Register*/
+ uint32_t MACSTATUS; /*MAC Status Register*/
+ uint32_t EMCONTROL; /*Emulation Control Register*/
+ uint32_t FIFOCONTROL; /*FIFO Control Register*/
+ uint32_t MACCONFIG; /*MAC Configuration Register*/
+ uint32_t SOFTRESET; /*Soft Reset Register*/
+ uint8_t reserved6 [88];
+ uint32_t MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/
+ uint32_t MACSRCADDRHI; /*MAC Source Address High Bytes Register*/
+ uint32_t MACHASH1; /*MAC Hash Address Register 1*/
+ uint32_t MACHASH2; /*MAC Hash Address Register 2*/
+ uint32_t BOFFTEST; /*Back Off Test Register*/
+ uint32_t TPACETEST; /*Transmit Pacing Algorithm Test Register*/
+ uint32_t RXPAUSE; /*Receive Pause Timer Register*/
+ uint32_t TXPAUSE; /*Transmit Pause Timer Register*/
+ uint8_t reserved7 [784];
+ uint32_t MACADDRLO; /*MAC Address Low Bytes Register*/
+ uint32_t MACADDRHI; /*MAC Address High Bytes Register*/
+ uint32_t MACINDEX; /*MAC Index Register*/
+ uint8_t reserved8 [244];
+ uint32_t TXHDP[8]; /*Transmit Channel DMA Head Descriptor Pointer Register*/
+ uint32_t RXHDP[8]; /*Receive Channel DMA Head Descriptor Pointer Register*/
+ uint32_t TXCP[8]; /*Transmit Channel Completion Pointer Register*/
+ uint32_t RXCP[8]; /*Receive Channel Completion Pointer Register*/
+} tms570_emacm_t;
+
+
+/*--------------------TMS570_EMACMTXREVID--------------------*/
+/* field: TXREV - Transmit module revision */
+#define TMS570_EMACM_TXREVID_TXREV(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_TXREVID_TXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_TXREVID_TXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_EMACMTXCONTROL-------------------*/
+/* field: TXEN - Transmit enable */
+#define TMS570_EMACM_TXCONTROL_TXEN BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACMTXTEARDOWN-------------------*/
+/* field: TXTDNCH - Transmit teardown channel. */
+#define TMS570_EMACM_TXTEARDOWN_TXTDNCH(val) BSP_FLD32(val,0, 2)
+#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_EMACM_TXTEARDOWN_TXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*--------------------TMS570_EMACMRXREVID--------------------*/
+/* field: RXREV - Receive module revision */
+#define TMS570_EMACM_RXREVID_RXREV(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_RXREVID_RXREV_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_RXREVID_RXREV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_EMACMRXCONTROL-------------------*/
+/* field: RXEN - Receive enable */
+#define TMS570_EMACM_RXCONTROL_RXEN BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACMRXTEARDOWN-------------------*/
+/* field: RXTDNCH - Receive teardown channel. */
+#define TMS570_EMACM_RXTEARDOWN_RXTDNCH(val) BSP_FLD32(val,0, 2)
+#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_EMACM_RXTEARDOWN_RXTDNCH_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*------------------TMS570_EMACMTXINTSTATRAW------------------*/
+/* field: TX7PEND - TX7PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX7PEND BSP_FLD32(7)
+
+/* field: TX6PEND - TX6PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX6PEND BSP_FLD32(6)
+
+/* field: TX5PEND - TX5PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX5PEND BSP_FLD32(5)
+
+/* field: TX4PEND - X4PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX4PEND BSP_FLD32(4)
+
+/* field: TX3PEND - TX3PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX3PEND BSP_FLD32(3)
+
+/* field: TX2PEND - TX2PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX2PEND BSP_FLD32(2)
+
+/* field: TX1PEND - TX1PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX1PEND BSP_FLD32(1)
+
+/* field: TX0PEND - TX0PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_TXINTSTATRAW_TX0PEND BSP_FLD32(0)
+
+
+/*----------------TMS570_EMACMTXINTSTATMASKED----------------*/
+/* field: TX7PEND - TX7PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX7PEND BSP_FLD32(7)
+
+/* field: TX6PEND - TX6PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX6PEND BSP_FLD32(6)
+
+/* field: TX5PEND - TX5PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX5PEND BSP_FLD32(5)
+
+/* field: TX4PEND - TX4PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX4PEND BSP_FLD32(4)
+
+/* field: TX3PEND - TX3PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX3PEND BSP_FLD32(3)
+
+/* field: TX2PEND - TX2PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX2PEND BSP_FLD32(2)
+
+/* field: TX1PEND - TX1PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX1PEND BSP_FLD32(1)
+
+/* field: TX0PEND - TX0PEND masked interrupt read */
+#define TMS570_EMACM_TXINTSTATMASKED_TX0PEND BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMTXINTMASKSET------------------*/
+/* field: TX7MASK - Transmit channel 7 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX7MASK BSP_FLD32(7)
+
+/* field: TX6MASK - Transmit channel 6 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX6MASK BSP_FLD32(6)
+
+/* field: TX5MASK - Transmit channel 5 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX5MASK BSP_FLD32(5)
+
+/* field: TX4MASK - Transmit channel 4 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX4MASK BSP_FLD32(4)
+
+/* field: TX3MASK - Transmit channel 3 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX3MASK BSP_FLD32(3)
+
+/* field: TX2MASK - Transmit channel 2 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX2MASK BSP_FLD32(2)
+
+/* field: TX1MASK - Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX1MASK BSP_FLD32(1)
+
+/* field: TX0MASK - Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKSET_TX0MASK BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACMTXINTMASKCLEAR-----------------*/
+/* field: TX7MASK - Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX7MASK BSP_FLD32(7)
+
+/* field: TX6MASK - Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX6MASK BSP_FLD32(6)
+
+/* field: TX5MASK - Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX5MASK BSP_FLD32(5)
+
+/* field: TX4MASK - Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX4MASK BSP_FLD32(4)
+
+/* field: TX3MASK - Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX3MASK BSP_FLD32(3)
+
+/* field: TX2MASK - Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX2MASK BSP_FLD32(2)
+
+/* field: TX1MASK - Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX1MASK BSP_FLD32(1)
+
+/* field: TX0MASK - Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_TXINTMASKCLEAR_TX0MASK BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMMACINVECTOR------------------*/
+/* field: STATPEND - EMAC module statistics interrupt (STATPEND) pending status bit */
+#define TMS570_EMACM_MACINVECTOR_STATPEND BSP_FLD32(27)
+
+/* field: HOSTPEND - EMAC module host error interrupt (HOSTPEND) pending status bit */
+#define TMS570_EMACM_MACINVECTOR_HOSTPEND BSP_FLD32(26)
+
+/* field: LINKINT0 - MDIO module USERPHYSEL0 (LINKINT0) status bit */
+#define TMS570_EMACM_MACINVECTOR_LINKINT0 BSP_FLD32(25)
+
+/* field: USERINT0 - MDIO module USERACCESS0 (USERINT0) status bit */
+#define TMS570_EMACM_MACINVECTOR_USERINT0 BSP_FLD32(24)
+
+/* field: TXPEND - Transmit channels 0-7 interrupt (TXnPEND) pending status. Bit 16 is TX0PEND. */
+#define TMS570_EMACM_MACINVECTOR_TXPEND(val) BSP_FLD32(val,16, 23)
+#define TMS570_EMACM_MACINVECTOR_TXPEND_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_EMACM_MACINVECTOR_TXPEND_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: RXTHRESHPEND - Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. */
+#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACINVECTOR_RXTHRESHPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: RXPEND - Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. */
+#define TMS570_EMACM_MACINVECTOR_RXPEND(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACINVECTOR_RXPEND_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACINVECTOR_RXPEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_EMACMMACEOIVECTOR------------------*/
+/* field: INTVECT - Acknowledge EMAC Control Module Interrupts */
+#define TMS570_EMACM_MACEOIVECTOR_INTVECT(val) BSP_FLD32(val,0, 4)
+#define TMS570_EMACM_MACEOIVECTOR_INTVECT_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EMACM_MACEOIVECTOR_INTVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*------------------TMS570_EMACMRXINTSTATRAW------------------*/
+/* field: RX7THRESHPEND - RX7THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX7THRESHPEND BSP_FLD32(15)
+
+/* field: RX6THRESHPEND - RX6THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX6THRESHPEND BSP_FLD32(14)
+
+/* field: RX5THRESHPEND - RX5THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX5THRESHPEND BSP_FLD32(13)
+
+/* field: RX4THRESHPEND - RX4THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX4THRESHPEND BSP_FLD32(12)
+
+/* field: RX3THRESHPEND - RX3THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX3THRESHPEND BSP_FLD32(11)
+
+/* field: RX2THRESHPEND - RX2THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX2THRESHPEND BSP_FLD32(10)
+
+/* field: RX1THRESHPEND - RX1THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX1THRESHPEND BSP_FLD32(9)
+
+/* field: RX0THRESHPEND - RX0THRESHPEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX0THRESHPEND BSP_FLD32(8)
+
+/* field: RX7PEND - RX7PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX7PEND BSP_FLD32(7)
+
+/* field: RX6PEND - RX6PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX6PEND BSP_FLD32(6)
+
+/* field: RX5PEND - RX5PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX5PEND BSP_FLD32(5)
+
+/* field: RX4PEND - RX4PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX4PEND BSP_FLD32(4)
+
+/* field: RX3PEND - RX3PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX3PEND BSP_FLD32(3)
+
+/* field: RX2PEND - RX2PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX2PEND BSP_FLD32(2)
+
+/* field: RX1PEND - RX1PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX1PEND BSP_FLD32(1)
+
+/* field: RX0PEND - RX0PEND raw interrupt read (before mask) */
+#define TMS570_EMACM_RXINTSTATRAW_RX0PEND BSP_FLD32(0)
+
+
+/*----------------TMS570_EMACMRXINTSTATMASKED----------------*/
+/* field: RX7THRESHPEND - RX7THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX7THRESHPEND BSP_FLD32(15)
+
+/* field: RX6THRESHPEND - RX6THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX6THRESHPEND BSP_FLD32(14)
+
+/* field: RX5THRESHPEND - RX5THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX5THRESHPEND BSP_FLD32(13)
+
+/* field: RX4THRESHPEND - RX4THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX4THRESHPEND BSP_FLD32(12)
+
+/* field: RX3THRESHPEND - RX3THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX3THRESHPEND BSP_FLD32(11)
+
+/* field: RX2THRESHPEND - RX2THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX2THRESHPEND BSP_FLD32(10)
+
+/* field: RX1THRESHPEND - RX1THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX1THRESHPEND BSP_FLD32(9)
+
+/* field: RX0THRESHPEND - RX0THRESHPEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX0THRESHPEND BSP_FLD32(8)
+
+/* field: RX7PEND - RX7PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX7PEND BSP_FLD32(7)
+
+/* field: RX6PEND - RX6PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX6PEND BSP_FLD32(6)
+
+/* field: RX5PEND - RX5PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX5PEND BSP_FLD32(5)
+
+/* field: RX4PEND - RX4PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX4PEND BSP_FLD32(4)
+
+/* field: RX3PEND - RX3PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX3PEND BSP_FLD32(3)
+
+/* field: RX2PEND - RX2PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX2PEND BSP_FLD32(2)
+
+/* field: RX1PEND - RX1PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX1PEND BSP_FLD32(1)
+
+/* field: RX0PEND - RX0PEND masked interrupt read */
+#define TMS570_EMACM_RXINTSTATMASKED_RX0PEND BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMRXINTMASKSET------------------*/
+/* field: RX7THRESHMASK - Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX7THRESHMASK BSP_FLD32(15)
+
+/* field: RX6THRESHMASK - Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX6THRESHMASK BSP_FLD32(14)
+
+/* field: RX5THRESHMASK - Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX5THRESHMASK BSP_FLD32(13)
+
+/* field: RX4THRESHMASK - Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX4THRESHMASK BSP_FLD32(12)
+
+/* field: RX3THRESHMASK - Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX3THRESHMASK BSP_FLD32(11)
+
+/* field: RX2THRESHMASK - Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX2THRESHMASK BSP_FLD32(10)
+
+/* field: RX1THRESHMASK - Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX1THRESHMASK BSP_FLD32(9)
+
+/* field: RX0THRESHMASK - Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX0THRESHMASK BSP_FLD32(8)
+
+/* field: RX7MASK - Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX7MASK BSP_FLD32(7)
+
+/* field: RX6MASK - Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX6MASK BSP_FLD32(6)
+
+/* field: RX5MASK - Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX5MASK BSP_FLD32(5)
+
+/* field: RX4MASK - Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX4MASK BSP_FLD32(4)
+
+/* field: RX3MASK - Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX3MASK BSP_FLD32(3)
+
+/* field: RX2MASK - Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX2MASK BSP_FLD32(2)
+
+/* field: RX1MASK - Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX1MASK BSP_FLD32(1)
+
+/* field: RX0MASK - Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKSET_RX0MASK BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACMRXINTMASKCLEAR-----------------*/
+/* field: RX7THRESHMASK - Receive channel 7 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7THRESHMASK BSP_FLD32(15)
+
+/* field: RX6THRESHMASK - Receive channel 6 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6THRESHMASK BSP_FLD32(14)
+
+/* field: RX5THRESHMASK - Receive channel 5 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5THRESHMASK BSP_FLD32(13)
+
+/* field: RX4THRESHMASK - Receive channel 4 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4THRESHMASK BSP_FLD32(12)
+
+/* field: RX3THRESHMASK - Receive channel 3 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3THRESHMASK BSP_FLD32(11)
+
+/* field: RX2THRESHMASK - Receive channel 2 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2THRESHMASK BSP_FLD32(10)
+
+/* field: RX1THRESHMASK - Receive channel 1 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1THRESHMASK BSP_FLD32(9)
+
+/* field: RX0THRESHMASK - Receive channel 0 threshold mask clear bit. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0THRESHMASK BSP_FLD32(8)
+
+/* field: RX7MASK - Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX7MASK BSP_FLD32(7)
+
+/* field: RX6MASK - Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX6MASK BSP_FLD32(6)
+
+/* field: RX5MASK - Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX5MASK BSP_FLD32(5)
+
+/* field: RX4MASK - Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX4MASK BSP_FLD32(4)
+
+/* field: RX3MASK - Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX3MASK BSP_FLD32(3)
+
+/* field: RX2MASK - Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX2MASK BSP_FLD32(2)
+
+/* field: RX1MASK - Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX1MASK BSP_FLD32(1)
+
+/* field: RX0MASK - Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. */
+#define TMS570_EMACM_RXINTMASKCLEAR_RX0MASK BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACMMACINTSTATRAW-----------------*/
+/* field: HOSTPEND - Host pending interrupt (HOSTPEND); raw interrupt read (before mask). */
+#define TMS570_EMACM_MACINTSTATRAW_HOSTPEND BSP_FLD32(1)
+
+/* field: STATPEND - Statistics pending interrupt (STATPEND); raw interrupt read (before mask). */
+#define TMS570_EMACM_MACINTSTATRAW_STATPEND BSP_FLD32(0)
+
+
+/*----------------TMS570_EMACMMACINTSTATMASKED----------------*/
+/* field: HOSTPEND - Host pending interrupt (HOSTPEND); masked interrupt read. */
+#define TMS570_EMACM_MACINTSTATMASKED_HOSTPEND BSP_FLD32(1)
+
+/* field: STATPEND - Statistics pending interrupt (STATPEND); masked interrupt read. */
+#define TMS570_EMACM_MACINTSTATMASKED_STATPEND BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACMMACINTMASKSET-----------------*/
+/* field: HOSTMASK - Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_MACINTMASKSET_HOSTMASK BSP_FLD32(1)
+
+/* field: STATMASK - Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_MACINTMASKSET_STATMASK BSP_FLD32(0)
+
+
+/*----------------TMS570_EMACMMACINTMASKCLEAR----------------*/
+/* field: HOSTMASK - Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_MACINTMASKCLEAR_HOSTMASK BSP_FLD32(1)
+
+/* field: STATMASK - Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. */
+#define TMS570_EMACM_MACINTMASKCLEAR_STATMASK BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMRXMBPENABLE------------------*/
+/* field: RXPASSCRC - Pass receive CRC enable bit */
+#define TMS570_EMACM_RXMBPENABLE_RXPASSCRC BSP_FLD32(30)
+
+/* field: RXQOSEN - Receive quality of service enable bit */
+#define TMS570_EMACM_RXMBPENABLE_RXQOSEN BSP_FLD32(29)
+
+/* field: RXNOCHAIN - Receive no buffer chaining bit */
+#define TMS570_EMACM_RXMBPENABLE_RXNOCHAIN BSP_FLD32(28)
+
+/* field: RXCMFEN - Receive copy MAC control frames enable bit. */
+#define TMS570_EMACM_RXMBPENABLE_RXCMFEN BSP_FLD32(24)
+
+/* field: RXCSFEN - Receive copy short frames enable bit. */
+#define TMS570_EMACM_RXMBPENABLE_RXCSFEN BSP_FLD32(23)
+
+/* field: RXCEFEN - Receive copy error frames enable bit. */
+#define TMS570_EMACM_RXMBPENABLE_RXCEFEN BSP_FLD32(22)
+
+/* field: RXCAFEN - Receive copy all frames enable bit. */
+#define TMS570_EMACM_RXMBPENABLE_RXCAFEN BSP_FLD32(21)
+
+/* field: RXPROMCH - Receive promiscuous channel select */
+#define TMS570_EMACM_RXMBPENABLE_RXPROMCH(val) BSP_FLD32(val,16, 18)
+#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_EMACM_RXMBPENABLE_RXPROMCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: RXBROADEN - Receive broadcast enable. */
+#define TMS570_EMACM_RXMBPENABLE_RXBROADEN BSP_FLD32(13)
+
+/* field: RXBROADCH - Receive broadcast channel select */
+#define TMS570_EMACM_RXMBPENABLE_RXBROADCH(val) BSP_FLD32(val,8, 10)
+#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_EMACM_RXMBPENABLE_RXBROADCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: RXMULTEN - RX multicast enable. */
+#define TMS570_EMACM_RXMBPENABLE_RXMULTEN BSP_FLD32(5)
+
+
+/*------------------TMS570_EMACMRXUNICASTSET------------------*/
+/* field: RXCH7EN - Receive channel 7 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH7EN BSP_FLD32(7)
+
+/* field: RXCH6EN - Receive channel 6 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH6EN BSP_FLD32(6)
+
+/* field: RXCH5EN - Receive channel 5 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH5EN BSP_FLD32(5)
+
+/* field: RXCH4EN - Receive channel 4 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH4EN BSP_FLD32(4)
+
+/* field: RXCH3EN - Receive channel 3 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH3EN BSP_FLD32(3)
+
+/* field: RXCH2EN - Receive channel 2 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH2EN BSP_FLD32(2)
+
+/* field: RXCH1EN - Receive channel 1 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH1EN BSP_FLD32(1)
+
+/* field: RXCH0EN - Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTSET_RXCH0EN BSP_FLD32(0)
+
+
+/*-----------------TMS570_EMACMRXUNICASTCLEAR-----------------*/
+/* field: RXCH7EN - Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH7EN BSP_FLD32(7)
+
+/* field: RXCH6EN - Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH6EN BSP_FLD32(6)
+
+/* field: RXCH5EN - Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH5EN BSP_FLD32(5)
+
+/* field: RXCH4EN - Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH4EN BSP_FLD32(4)
+
+/* field: RXCH3EN - Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH3EN BSP_FLD32(3)
+
+/* field: RXCH2EN - Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH2EN BSP_FLD32(2)
+
+/* field: RXCH1EN - Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH1EN BSP_FLD32(1)
+
+/* field: RXCH0EN - Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. */
+#define TMS570_EMACM_RXUNICASTCLEAR_RXCH0EN BSP_FLD32(0)
+
+
+/*--------------------TMS570_EMACMRXMAXLEN--------------------*/
+/* field: RXMAXLEN - Receive maximum frame length. These bits determine the maximum length of a received frame. */
+#define TMS570_EMACM_RXMAXLEN_RXMAXLEN(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMACM_RXMAXLEN_RXMAXLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------TMS570_EMACMRXBUFFEROFFSET-----------------*/
+/* field: RXBUFFEROFFSET - Receive buffer offset value. */
+#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMACM_RXBUFFEROFFSET_RXBUFFEROFFSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------TMS570_EMACMRXFILTERLOWTHRESH---------------*/
+/* field: RXFILTERTHRESH - Receive filter low threshold. */
+#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_RXFILTERLOWTHRESH_RXFILTERTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_EMACMRXFLOWTHRESH------------------*/
+/* field: RXnFLOWTHRESH - Receive flow threshold. */
+#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_RXFLOWTHRESH_RXnFLOWTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_EMACMRXFREEBUFFER------------------*/
+/* field: RXnFREEBUF - Receive free buffer count. These bits contain the count of free buffers available. */
+#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMACM_RXFREEBUFFER_RXnFREEBUF_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_EMACMMACCONTROL-------------------*/
+/* field: RMIISPEED - RMII interface transmit and receive speed select. */
+#define TMS570_EMACM_MACCONTROL_RMIISPEED BSP_FLD32(15)
+
+/* field: RXOFFLENBLOCK - Receive offset / length word write block. */
+#define TMS570_EMACM_MACCONTROL_RXOFFLENBLOCK BSP_FLD32(14)
+
+/* field: RXOWNERSHIP - Receive ownership write bit value. */
+#define TMS570_EMACM_MACCONTROL_RXOWNERSHIP BSP_FLD32(13)
+
+/* field: CMDIDLE - Command Idle bit */
+#define TMS570_EMACM_MACCONTROL_CMDIDLE BSP_FLD32(11)
+
+/* field: TXSHORTGAPEN - Transmit Short Gap Enable */
+#define TMS570_EMACM_MACCONTROL_TXSHORTGAPEN BSP_FLD32(10)
+
+/* field: TXPTYPE - Transmit queue priority type */
+#define TMS570_EMACM_MACCONTROL_TXPTYPE BSP_FLD32(9)
+
+/* field: TXPACE - Transmit pacing enable bit */
+#define TMS570_EMACM_MACCONTROL_TXPACE BSP_FLD32(6)
+
+/* field: GMIIEN - GMII enable bit */
+#define TMS570_EMACM_MACCONTROL_GMIIEN BSP_FLD32(5)
+
+/* field: TXFLOWEN - Transmit flow control enable bit. */
+#define TMS570_EMACM_MACCONTROL_TXFLOWEN BSP_FLD32(4)
+
+/* field: RXBUFFERFLOWEN - Receive buffer flow control enable bit */
+#define TMS570_EMACM_MACCONTROL_RXBUFFERFLOWEN BSP_FLD32(3)
+
+/* field: LOOPBACK - Loopback mode. The loopback mode forces internal full-duplex mode regardless of the FULLDUPLEX bit. */
+#define TMS570_EMACM_MACCONTROL_LOOPBACK BSP_FLD32(1)
+
+/* field: FULLDUPLEX - Full duplex mode. */
+#define TMS570_EMACM_MACCONTROL_FULLDUPLEX BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACMMACSTATUS-------------------*/
+/* field: IDLE - EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1. */
+#define TMS570_EMACM_MACSTATUS_IDLE BSP_FLD32(31)
+
+/* field: TXERRCODE - Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors. */
+#define TMS570_EMACM_MACSTATUS_TXERRCODE(val) BSP_FLD32(val,20, 23)
+#define TMS570_EMACM_MACSTATUS_TXERRCODE_GET(reg) BSP_FLD32GET(reg,20, 23)
+#define TMS570_EMACM_MACSTATUS_TXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
+
+/* field: TXERRCH - Transmit host error channel. These bits indicate which transmit channel the host error occurred on. */
+#define TMS570_EMACM_MACSTATUS_TXERRCH(val) BSP_FLD32(val,16, 18)
+#define TMS570_EMACM_MACSTATUS_TXERRCH_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_EMACM_MACSTATUS_TXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: RXERRCODE - Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. */
+#define TMS570_EMACM_MACSTATUS_RXERRCODE(val) BSP_FLD32(val,12, 15)
+#define TMS570_EMACM_MACSTATUS_RXERRCODE_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_EMACM_MACSTATUS_RXERRCODE_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: RXERRCH - Receive host error channel. These bits indicate which receive channel the host error occurred on. */
+#define TMS570_EMACM_MACSTATUS_RXERRCH(val) BSP_FLD32(val,8, 10)
+#define TMS570_EMACM_MACSTATUS_RXERRCH_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_EMACM_MACSTATUS_RXERRCH_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: RXQOSACT - Receive Quality of Service (QOS) active bit. */
+#define TMS570_EMACM_MACSTATUS_RXQOSACT BSP_FLD32(2)
+
+/* field: RXFLOWACT - Receive flow control active bit. */
+#define TMS570_EMACM_MACSTATUS_RXFLOWACT BSP_FLD32(1)
+
+/* field: TXFLOWACT - Transmit flow control active bit. */
+#define TMS570_EMACM_MACSTATUS_TXFLOWACT BSP_FLD32(0)
+
+
+/*-------------------TMS570_EMACMEMCONTROL-------------------*/
+/* field: SOFT - Emulation soft bit. */
+#define TMS570_EMACM_EMCONTROL_SOFT BSP_FLD32(1)
+
+/* field: FREE - Emulation free bit. */
+#define TMS570_EMACM_EMCONTROL_FREE BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMFIFOCONTROL------------------*/
+/* field: TXCELLTHRESH - Transmit FIFO cell threshold. */
+#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH(val) BSP_FLD32(val,0, 1)
+#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_EMACM_FIFOCONTROL_TXCELLTHRESH_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*-------------------TMS570_EMACMMACCONFIG-------------------*/
+/* field: TXCELLDEPTH - Transmit cell depth. These bits indicate the number of cells in the transmit FIFO. */
+#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH(val) BSP_FLD32(val,24, 31)
+#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_EMACM_MACCONFIG_TXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: RXCELLDEPTH - Receive cell depth. These bits indicate the number of cells in the receive FIFO. */
+#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH(val) BSP_FLD32(val,16, 23)
+#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_EMACM_MACCONFIG_RXCELLDEPTH_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: ADDRESSTYPE - Address type */
+#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACCONFIG_ADDRESSTYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: MACCFIG - MAC configuration value */
+#define TMS570_EMACM_MACCONFIG_MACCFIG(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACCONFIG_MACCFIG_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACCONFIG_MACCFIG_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_EMACMSOFTRESET-------------------*/
+/* field: SOFTRESET - Software reset. Writing a 1 to this bit causes the EMAC logic to be reset. */
+#define TMS570_EMACM_SOFTRESET_SOFTRESET BSP_FLD32(0)
+
+
+/*------------------TMS570_EMACMMACSRCADDRLO------------------*/
+/* field: MACSRCADDR0 - MAC source address lower 8-0 bits (byte 0) */
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: MACSRCADDR1 - MAC source address bits 15-8 (byte 1) */
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACSRCADDRLO_MACSRCADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_EMACMMACSRCADDRHI------------------*/
+/* field: MACSRCADDR2 - MAC source address bits 23-16 (byte 2) */
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2(val) BSP_FLD32(val,24, 31)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: MACSRCADDR3 - MAC source address bits 31-24 (byte 3) */
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3(val) BSP_FLD32(val,16, 23)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: MACSRCADDR4 - MAC source address bits 39-32 (byte 4) */
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: MACSRCADDR5 - MAC source address bits 47-40 (byte 5) */
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACSRCADDRHI_MACSRCADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_EMACMMACHASH1--------------------*/
+/* field: MACHASH1 - Least-significant 32 bits of the hash table corresponding to hash values 0 to 31. */
+#define TMS570_EMACM_MACHASH1_MACHASH1(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_MACHASH1_MACHASH1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_MACHASH1_MACHASH1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_EMACMMACHASH2--------------------*/
+/* field: MACHASH2 - Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. */
+#define TMS570_EMACM_MACHASH2_MACHASH2(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_MACHASH2_MACHASH2_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_MACHASH2_MACHASH2_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_EMACMBOFFTEST--------------------*/
+/* field: RNDNUM - Backoff random number generator. */
+#define TMS570_EMACM_BOFFTEST_RNDNUM(val) BSP_FLD32(val,16, 25)
+#define TMS570_EMACM_BOFFTEST_RNDNUM_GET(reg) BSP_FLD32GET(reg,16, 25)
+#define TMS570_EMACM_BOFFTEST_RNDNUM_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
+
+/* field: COLLCOUNT - Collision count. These bits indicate the number of collisions the current frame has experienced. */
+#define TMS570_EMACM_BOFFTEST_COLLCOUNT(val) BSP_FLD32(val,12, 15)
+#define TMS570_EMACM_BOFFTEST_COLLCOUNT_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_EMACM_BOFFTEST_COLLCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: TXBACKOFF - Backoff count. */
+#define TMS570_EMACM_BOFFTEST_TXBACKOFF(val) BSP_FLD32(val,0, 9)
+#define TMS570_EMACM_BOFFTEST_TXBACKOFF_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_EMACM_BOFFTEST_TXBACKOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*-------------------TMS570_EMACMTPACETEST-------------------*/
+/* field: PACEVAL - Pacing register current value. A nonzero value in this field indicates that transmit pacing is active. */
+#define TMS570_EMACM_TPACETEST_PACEVAL(val) BSP_FLD32(val,0, 4)
+#define TMS570_EMACM_TPACETEST_PACEVAL_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EMACM_TPACETEST_PACEVAL_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*--------------------TMS570_EMACMRXPAUSE--------------------*/
+/* field: PAUSETIMER - Receive pause timer value. */
+#define TMS570_EMACM_RXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMACM_RXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMACM_RXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_EMACMTXPAUSE--------------------*/
+/* field: PAUSETIMER - Transmit pause timer value. */
+#define TMS570_EMACM_TXPAUSE_PAUSETIMER(val) BSP_FLD32(val,0, 15)
+#define TMS570_EMACM_TXPAUSE_PAUSETIMER_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_EMACM_TXPAUSE_PAUSETIMER_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_EMACMMACADDRLO-------------------*/
+/* field: VALID - Address valid bit. */
+#define TMS570_EMACM_MACADDRLO_VALID BSP_FLD32(20)
+
+/* field: MATCHFILT - Match or filter bit */
+#define TMS570_EMACM_MACADDRLO_MATCHFILT BSP_FLD32(19)
+
+/* field: CHANNEL - Channel select. Determines which receive channel a valid address match will be transferred to. */
+#define TMS570_EMACM_MACADDRLO_CHANNEL(val) BSP_FLD32(val,16, 18)
+#define TMS570_EMACM_MACADDRLO_CHANNEL_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_EMACM_MACADDRLO_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: MACADDR0 - MAC address lower 8-0 bits (byte 0) */
+#define TMS570_EMACM_MACADDRLO_MACADDR0(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACADDRLO_MACADDR0_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACADDRLO_MACADDR0_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: MACADDR1 - MAC address bits 15-8 (byte 1) */
+#define TMS570_EMACM_MACADDRLO_MACADDR1(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACADDRLO_MACADDR1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACADDRLO_MACADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_EMACMMACADDRHI-------------------*/
+/* field: MACADDR2 - MAC source address bits 23-16 (byte 2) */
+#define TMS570_EMACM_MACADDRHI_MACADDR2(val) BSP_FLD32(val,24, 31)
+#define TMS570_EMACM_MACADDRHI_MACADDR2_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_EMACM_MACADDRHI_MACADDR2_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: MACADDR3 - MAC source address bits 31-24 (byte 3) */
+#define TMS570_EMACM_MACADDRHI_MACADDR3(val) BSP_FLD32(val,16, 23)
+#define TMS570_EMACM_MACADDRHI_MACADDR3_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_EMACM_MACADDRHI_MACADDR3_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: MACADDR4 - MAC source address bits 39-32 (byte 4) */
+#define TMS570_EMACM_MACADDRHI_MACADDR4(val) BSP_FLD32(val,8, 15)
+#define TMS570_EMACM_MACADDRHI_MACADDR4_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_EMACM_MACADDRHI_MACADDR4_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: MACADDR5 - MAC source address bits 47-40 (byte 5). Bit 40 is the group bit. It is forced to 0 and read as 0. */
+#define TMS570_EMACM_MACADDRHI_MACADDR5(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMACM_MACADDRHI_MACADDR5_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMACM_MACADDRHI_MACADDR5_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_EMACMMACINDEX--------------------*/
+/* field: MACINDEX - MAC address index. All eight addresses share the upper 40 bits. */
+#define TMS570_EMACM_MACINDEX_MACINDEX(val) BSP_FLD32(val,0, 2)
+#define TMS570_EMACM_MACINDEX_MACINDEX_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_EMACM_MACINDEX_MACINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*---------------------TMS570_EMACMTXHDP---------------------*/
+/* field: TXnHDP - Transmit channel n DMA Head Descriptor pointer. */
+#define TMS570_EMACM_TXHDP_TXnHDP(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_TXHDP_TXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_TXHDP_TXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_EMACMRXHDP---------------------*/
+/* field: RXnHDP - Receive channel n DMA Head Descriptor pointer. */
+#define TMS570_EMACM_RXHDP_RXnHDP(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_RXHDP_RXnHDP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_RXHDP_RXnHDP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_EMACMTXCP----------------------*/
+/* field: TXnCP - Transmit channel n completion pointer register is written by the host with the buffer descriptor */
+#define TMS570_EMACM_TXCP_TXnCP(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_TXCP_TXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_TXCP_TXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_EMACMRXCP----------------------*/
+/* field: RXnCP - Receive channel n completion pointer register is written by the host with the buffer descriptor */
+#define TMS570_EMACM_RXCP_RXnCP(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMACM_RXCP_RXnCP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMACM_RXCP_RXnCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_EMACM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
new file mode 100644
index 0000000..b4e227b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_emif.h
@@ -0,0 +1,471 @@
+/* The header file is generated by make_header.py from EMIF.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_EMIF
+#define LIBBSP_ARM_tms570_EMIF
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t MIDR; /*Module ID Register*/
+ uint32_t AWCC; /*Asynchronous Wait Cycle Configuration Register*/
+ uint32_t SDCR; /*SDRAM Configuration Register*/
+ uint32_t SDRCR; /*SDRAM Refresh Control Register*/
+ uint32_t CE2CFG; /*Asynchronous 1 Configuration Register*/
+ uint32_t CE3CFG; /*Asynchronous 2 Configuration Register*/
+ uint32_t CE4CFG; /*Asynchronous 3 Configuration Register*/
+ uint32_t CE5CFG; /*Asynchronous 4 Configuration Register*/
+ uint32_t SDTIMR; /*SDRAM Timing Register*/
+ uint8_t reserved1 [24];
+ uint32_t SDSRETR; /*SDRAM Self Refresh Exit Timing Register*/
+ uint32_t INTRAW; /*EMIF Interrupt Raw Register*/
+ uint32_t INTMSK; /*EMIF Interrupt Mask Register*/
+ uint32_t INTMSKSET; /*EMIF Interrupt Mask Set Register*/
+ uint32_t INTMSKCLR; /*EMIF Interrupt Mask Clear Register*/
+ uint8_t reserved2 [24];
+ uint32_t PMCR; /*Page Mode Control Register*/
+} tms570_emif_t;
+
+
+/*----------------------TMS570_EMIFMIDR----------------------*/
+/* field: REV - Module ID of EMIF. See the device-specific data manual. */
+#define TMS570_EMIF_MIDR_REV(val) BSP_FLD32(val,0, 31)
+#define TMS570_EMIF_MIDR_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_EMIF_MIDR_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_EMIFAWCC----------------------*/
+/* field: WP1 - EMIF_nWAIT[1] polarity bit. This bit defines the polarity of the EMIF_nWAIT[1] pin. */
+#define TMS570_EMIF_AWCC_WP1 BSP_FLD32(29)
+
+/* field: WP0 - EMIF_nWAIT[0] polarity bit. This bit defines the polarity of the EMIF_nWAIT[0] pin. */
+#define TMS570_EMIF_AWCC_WP0 BSP_FLD32(28)
+
+/* field: CS5_WAIT - Chip Select 5 WAIT signal selection. */
+#define TMS570_EMIF_AWCC_CS5_WAIT(val) BSP_FLD32(val,22, 23)
+#define TMS570_EMIF_AWCC_CS5_WAIT_GET(reg) BSP_FLD32GET(reg,22, 23)
+#define TMS570_EMIF_AWCC_CS5_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,22, 23)
+
+/* field: CS4_WAIT - Chip Select 4 WAIT signal selection. */
+#define TMS570_EMIF_AWCC_CS4_WAIT(val) BSP_FLD32(val,20, 21)
+#define TMS570_EMIF_AWCC_CS4_WAIT_GET(reg) BSP_FLD32GET(reg,20, 21)
+#define TMS570_EMIF_AWCC_CS4_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,20, 21)
+
+/* field: CS3_WAIT - be used for memory accesses to chip select 3 memory space. */
+#define TMS570_EMIF_AWCC_CS3_WAIT(val) BSP_FLD32(val,18, 19)
+#define TMS570_EMIF_AWCC_CS3_WAIT_GET(reg) BSP_FLD32GET(reg,18, 19)
+#define TMS570_EMIF_AWCC_CS3_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,18, 19)
+
+/* field: CS2_WAIT - Chip Select 2 WAIT signal selection. */
+#define TMS570_EMIF_AWCC_CS2_WAIT(val) BSP_FLD32(val,16, 17)
+#define TMS570_EMIF_AWCC_CS2_WAIT_GET(reg) BSP_FLD32GET(reg,16, 17)
+#define TMS570_EMIF_AWCC_CS2_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
+
+/* field: MAX_EXT_WAIT - Maximum extended wait cycles. */
+#define TMS570_EMIF_AWCC_MAX_EXT_WAIT(val) BSP_FLD32(val,0, 7)
+#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_EMIF_AWCC_MAX_EXT_WAIT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_EMIFSDCR----------------------*/
+/* field: SR - Self-Refresh mode bit. */
+#define TMS570_EMIF_SDCR_SR BSP_FLD32(31)
+
+/* field: PD - Power Down bit. This bit controls entering and exiting of the power-down mode. */
+#define TMS570_EMIF_SDCR_PD BSP_FLD32(30)
+
+/* field: PDWR - Perform refreshes during power down. */
+#define TMS570_EMIF_SDCR_PDWR BSP_FLD32(29)
+
+/* field: NM - Narrow mode bit. This bit defines whether a 16- or 32-bit-wide SDRAM is connected to the EMIF. */
+#define TMS570_EMIF_SDCR_NM BSP_FLD32(14)
+
+/* field: CL - CAS Latency. */
+#define TMS570_EMIF_SDCR_CL(val) BSP_FLD32(val,9, 11)
+#define TMS570_EMIF_SDCR_CL_GET(reg) BSP_FLD32GET(reg,9, 11)
+#define TMS570_EMIF_SDCR_CL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
+
+/* field: BIT11_9LOCK - Bits 11 to 9 lock. CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */
+#define TMS570_EMIF_SDCR_BIT11_9LOCK BSP_FLD32(8)
+
+/* field: IBANK - Internal SDRAM Bank size. */
+#define TMS570_EMIF_SDCR_IBANK(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_SDCR_IBANK_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_SDCR_IBANK_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: PAGESIZE - Page Size. This field defines the internal page size of connected SDRAM devices. */
+#define TMS570_EMIF_SDCR_PAGESIZE(val) BSP_FLD32(val,0, 2)
+#define TMS570_EMIF_SDCR_PAGESIZE_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_EMIF_SDCR_PAGESIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*----------------------TMS570_EMIFSDRCR----------------------*/
+/* field: RR - Refresh Rate. This field is used to define the SDRAM refresh period in terms of EMIF_CLK cycles. */
+#define TMS570_EMIF_SDRCR_RR(val) BSP_FLD32(val,0, 12)
+#define TMS570_EMIF_SDRCR_RR_GET(reg) BSP_FLD32GET(reg,0, 12)
+#define TMS570_EMIF_SDRCR_RR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
+
+
+/*---------------------TMS570_EMIFCE2CFG---------------------*/
+/* field: SS - Select Strobe bit. */
+#define TMS570_EMIF_CE2CFG_SS BSP_FLD32(31)
+
+/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
+#define TMS570_EMIF_CE2CFG_EW BSP_FLD32(30)
+
+/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
+#define TMS570_EMIF_CE2CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
+#define TMS570_EMIF_CE2CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
+
+/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
+#define TMS570_EMIF_CE2CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_EMIF_CE2CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
+#define TMS570_EMIF_CE2CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
+#define TMS570_EMIF_CE2CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
+
+/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
+#define TMS570_EMIF_CE2CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
+#define TMS570_EMIF_CE2CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
+
+/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
+#define TMS570_EMIF_CE2CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
+#define TMS570_EMIF_CE2CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
+
+/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE2CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_CE2CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_CE2CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TA - Minimum Turn-Around time. */
+#define TMS570_EMIF_CE2CFG_TA(val) BSP_FLD32(val,2, 3)
+#define TMS570_EMIF_CE2CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_EMIF_CE2CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
+#define TMS570_EMIF_CE2CFG_ASIZE(val) BSP_FLD32(val,0, 1)
+#define TMS570_EMIF_CE2CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_EMIF_CE2CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_EMIFCE3CFG---------------------*/
+/* field: SS - Select Strobe bit. */
+#define TMS570_EMIF_CE3CFG_SS BSP_FLD32(31)
+
+/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
+#define TMS570_EMIF_CE3CFG_EW BSP_FLD32(30)
+
+/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
+#define TMS570_EMIF_CE3CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
+#define TMS570_EMIF_CE3CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
+
+/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
+#define TMS570_EMIF_CE3CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_EMIF_CE3CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
+#define TMS570_EMIF_CE3CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
+#define TMS570_EMIF_CE3CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
+
+/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
+#define TMS570_EMIF_CE3CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
+#define TMS570_EMIF_CE3CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
+
+/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
+#define TMS570_EMIF_CE3CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
+#define TMS570_EMIF_CE3CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
+
+/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE3CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_CE3CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_CE3CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TA - Minimum Turn-Around time. */
+#define TMS570_EMIF_CE3CFG_TA(val) BSP_FLD32(val,2, 3)
+#define TMS570_EMIF_CE3CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_EMIF_CE3CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
+#define TMS570_EMIF_CE3CFG_ASIZE(val) BSP_FLD32(val,0, 1)
+#define TMS570_EMIF_CE3CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_EMIF_CE3CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_EMIFCE4CFG---------------------*/
+/* field: SS - Select Strobe bit. */
+#define TMS570_EMIF_CE4CFG_SS BSP_FLD32(31)
+
+/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
+#define TMS570_EMIF_CE4CFG_EW BSP_FLD32(30)
+
+/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
+#define TMS570_EMIF_CE4CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
+#define TMS570_EMIF_CE4CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
+
+/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
+#define TMS570_EMIF_CE4CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_EMIF_CE4CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
+#define TMS570_EMIF_CE4CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
+#define TMS570_EMIF_CE4CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
+
+/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
+#define TMS570_EMIF_CE4CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
+#define TMS570_EMIF_CE4CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
+
+/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
+#define TMS570_EMIF_CE4CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
+#define TMS570_EMIF_CE4CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
+
+/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE4CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_CE4CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_CE4CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TA - Minimum Turn-Around time. */
+#define TMS570_EMIF_CE4CFG_TA(val) BSP_FLD32(val,2, 3)
+#define TMS570_EMIF_CE4CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_EMIF_CE4CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
+#define TMS570_EMIF_CE4CFG_ASIZE(val) BSP_FLD32(val,0, 1)
+#define TMS570_EMIF_CE4CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_EMIF_CE4CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_EMIFCE5CFG---------------------*/
+/* field: SS - Select Strobe bit. */
+#define TMS570_EMIF_CE5CFG_SS BSP_FLD32(31)
+
+/* field: EW - Extend Wait bit. This bit defines whether extended wait cycles will be enabled. See Section 17.2.6. */
+#define TMS570_EMIF_CE5CFG_EW BSP_FLD32(30)
+
+/* field: W_SETUP - Write setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_W_SETUP(val) BSP_FLD32(val,26, 29)
+#define TMS570_EMIF_CE5CFG_W_SETUP_GET(reg) BSP_FLD32GET(reg,26, 29)
+#define TMS570_EMIF_CE5CFG_W_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,26, 29)
+
+/* field: W_STROBE - Write strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_W_STROBE(val) BSP_FLD32(val,20, 25)
+#define TMS570_EMIF_CE5CFG_W_STROBE_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_EMIF_CE5CFG_W_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: W_HOLD - Write hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_W_HOLD(val) BSP_FLD32(val,17, 19)
+#define TMS570_EMIF_CE5CFG_W_HOLD_GET(reg) BSP_FLD32GET(reg,17, 19)
+#define TMS570_EMIF_CE5CFG_W_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,17, 19)
+
+/* field: R_SETUP - Read setup width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_R_SETUP(val) BSP_FLD32(val,13, 16)
+#define TMS570_EMIF_CE5CFG_R_SETUP_GET(reg) BSP_FLD32GET(reg,13, 16)
+#define TMS570_EMIF_CE5CFG_R_SETUP_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
+
+/* field: R_STROBE - Read strobe width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_R_STROBE(val) BSP_FLD32(val,7, 12)
+#define TMS570_EMIF_CE5CFG_R_STROBE_GET(reg) BSP_FLD32GET(reg,7, 12)
+#define TMS570_EMIF_CE5CFG_R_STROBE_SET(reg,val) BSP_FLD32SET(reg, val,7, 12)
+
+/* field: R_HOLD - Read hold width in EMIF_CLK cycles, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_R_HOLD(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_CE5CFG_R_HOLD_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_CE5CFG_R_HOLD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TA - and writes, minus one cycle. See Section 17.2.6.3 for details. */
+#define TMS570_EMIF_CE5CFG_TA(val) BSP_FLD32(val,2, 3)
+#define TMS570_EMIF_CE5CFG_TA_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_EMIF_CE5CFG_TA_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: ASIZE - Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. */
+#define TMS570_EMIF_CE5CFG_ASIZE(val) BSP_FLD32(val,0, 1)
+#define TMS570_EMIF_CE5CFG_ASIZE_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_EMIF_CE5CFG_ASIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_EMIFSDTIMR---------------------*/
+/* field: T_RFC - Specifies the Trfc value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_RFC(val) BSP_FLD32(val,27, 31)
+#define TMS570_EMIF_SDTIMR_T_RFC_GET(reg) BSP_FLD32GET(reg,27, 31)
+#define TMS570_EMIF_SDTIMR_T_RFC_SET(reg,val) BSP_FLD32SET(reg, val,27, 31)
+
+/* field: T_RP - Precharge (PRE) to Activate (ACTV) or Refresh (REFR) command, minus 1: */
+#define TMS570_EMIF_SDTIMR_T_RP(val) BSP_FLD32(val,24, 26)
+#define TMS570_EMIF_SDTIMR_T_RP_GET(reg) BSP_FLD32GET(reg,24, 26)
+#define TMS570_EMIF_SDTIMR_T_RP_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
+
+/* field: T_RCD - Specifies the Trcd value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_RCD(val) BSP_FLD32(val,20, 22)
+#define TMS570_EMIF_SDTIMR_T_RCD_GET(reg) BSP_FLD32GET(reg,20, 22)
+#define TMS570_EMIF_SDTIMR_T_RCD_SET(reg,val) BSP_FLD32SET(reg, val,20, 22)
+
+/* field: T_WR - Specifies the Twr value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_WR(val) BSP_FLD32(val,16, 18)
+#define TMS570_EMIF_SDTIMR_T_WR_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_EMIF_SDTIMR_T_WR_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: T_RAS - Specifies the Tras value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_RAS(val) BSP_FLD32(val,12, 15)
+#define TMS570_EMIF_SDTIMR_T_RAS_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_EMIF_SDTIMR_T_RAS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: T_RC - Specifies the Trc value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_RC(val) BSP_FLD32(val,8, 11)
+#define TMS570_EMIF_SDTIMR_T_RC_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_EMIF_SDTIMR_T_RC_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: T_RRD - Specifies the Trrd value of the SDRAM. */
+#define TMS570_EMIF_SDTIMR_T_RRD(val) BSP_FLD32(val,4, 6)
+#define TMS570_EMIF_SDTIMR_T_RRD_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_EMIF_SDTIMR_T_RRD_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+
+/*---------------------TMS570_EMIFSDSRETR---------------------*/
+/* field: T_XS - This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, */
+#define TMS570_EMIF_SDSRETR_T_XS(val) BSP_FLD32(val,0, 4)
+#define TMS570_EMIF_SDSRETR_T_XS_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_EMIF_SDSRETR_T_XS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*---------------------TMS570_EMIFINTRAW---------------------*/
+/* field: WR - Wait Rise. */
+#define TMS570_EMIF_INTRAW_WR BSP_FLD32(2)
+
+/* field: LT - Line Trap. Set to 1 by hardware to indicate illegal memory access type or invalid cache line size. */
+#define TMS570_EMIF_INTRAW_LT BSP_FLD32(1)
+
+/* field: AT - Asynchronous Timeout. */
+#define TMS570_EMIF_INTRAW_AT BSP_FLD32(0)
+
+
+/*---------------------TMS570_EMIFINTMSK---------------------*/
+/* field: WR_MASKED - Wait Rise Masked. */
+#define TMS570_EMIF_INTMSK_WR_MASKED BSP_FLD32(2)
+
+/* field: LT_MASKED - Masked Line Trap. */
+#define TMS570_EMIF_INTMSK_LT_MASKED BSP_FLD32(1)
+
+/* field: AT_MASKED - Asynchronous Timeout Masked. */
+#define TMS570_EMIF_INTMSK_AT_MASKED BSP_FLD32(0)
+
+
+/*--------------------TMS570_EMIFINTMSKSET--------------------*/
+/* field: WR_MASK_SET - Wait Rise Mask Set. This bit determines whether or not the wait rise Interrupt is enabled. */
+#define TMS570_EMIF_INTMSKSET_WR_MASK_SET BSP_FLD32(2)
+
+/* field: LT_MASK_SET - LT_MASK_SET Mask set for LT_MASKED bit in the EMIF interrupt mask register (INTMSK). */
+#define TMS570_EMIF_INTMSKSET_LT_MASK_SET BSP_FLD32(1)
+
+/* field: AT_MASK_SET - Asynchronous Timeout Mask Set. */
+#define TMS570_EMIF_INTMSKSET_AT_MASK_SET BSP_FLD32(0)
+
+
+/*--------------------TMS570_EMIFINTMSKCLR--------------------*/
+/* field: WR_MASK_CLR - Wait Rise Mask Clear. This bit determines whether or not the wait rise interrupt is enabled. */
+#define TMS570_EMIF_INTMSKCLR_WR_MASK_CLR BSP_FLD32(2)
+
+/* field: LT_MASK_CLR - 1 to this bit clears this bit, clears the LT_MASK_SET bit in the EMIF interrupt mask set register */
+#define TMS570_EMIF_INTMSKCLR_LT_MASK_CLR BSP_FLD32(1)
+
+/* field: AT_MASK_CLR - Asynchronous Timeout Mask Clear. */
+#define TMS570_EMIF_INTMSKCLR_AT_MASK_CLR BSP_FLD32(0)
+
+
+/*----------------------TMS570_EMIFPMCR----------------------*/
+/* field: CS5_PG_DEL - Page access delay for NOR Flash connected on CS5. CS5 is not available on this device. */
+#define TMS570_EMIF_PMCR_CS5_PG_DEL(val) BSP_FLD32(val,26, 31)
+#define TMS570_EMIF_PMCR_CS5_PG_DEL_GET(reg) BSP_FLD32GET(reg,26, 31)
+#define TMS570_EMIF_PMCR_CS5_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
+
+/* field: CS5_PG_SIZE - Page Size for NOR Flash connected on CS5. CS5 is not available on this device. */
+#define TMS570_EMIF_PMCR_CS5_PG_SIZE BSP_FLD32(25)
+
+/* field: CS5_PG_MD_EN - Page Mode enable for NOR Flash connected on CS5. CS5 is not available on this device. */
+#define TMS570_EMIF_PMCR_CS5_PG_MD_EN BSP_FLD32(24)
+
+/* field: CS4_PG_DEL - Page access delay for NOR Flash connected on CS4. */
+#define TMS570_EMIF_PMCR_CS4_PG_DEL(val) BSP_FLD32(val,18, 23)
+#define TMS570_EMIF_PMCR_CS4_PG_DEL_GET(reg) BSP_FLD32GET(reg,18, 23)
+#define TMS570_EMIF_PMCR_CS4_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,18, 23)
+
+/* field: CS4_PG_SIZE - Page Size for NOR Flash connected on CS4. */
+#define TMS570_EMIF_PMCR_CS4_PG_SIZE BSP_FLD32(17)
+
+/* field: CS4_PG_MD_EN - Page Mode enable for NOR Flash connected on CS4. */
+#define TMS570_EMIF_PMCR_CS4_PG_MD_EN BSP_FLD32(16)
+
+/* field: CS3_PG_DEL - the page read data to be valid, minus one cycle. This value must not be cleared to 0. */
+#define TMS570_EMIF_PMCR_CS3_PG_DEL(val) BSP_FLD32(val,10, 15)
+#define TMS570_EMIF_PMCR_CS3_PG_DEL_GET(reg) BSP_FLD32GET(reg,10, 15)
+#define TMS570_EMIF_PMCR_CS3_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,10, 15)
+
+/* field: CS3_PG_SIZE - Page Size for NOR Flash connected on CS3. */
+#define TMS570_EMIF_PMCR_CS3_PG_SIZE BSP_FLD32(9)
+
+/* field: CS3_PG_MD_EN - Page Mode enable for NOR Flash connected on CS3. */
+#define TMS570_EMIF_PMCR_CS3_PG_MD_EN BSP_FLD32(8)
+
+/* field: CS2_PG_DEL - Page access delay for NOR Flash connected on CS2. */
+#define TMS570_EMIF_PMCR_CS2_PG_DEL(val) BSP_FLD32(val,2, 7)
+#define TMS570_EMIF_PMCR_CS2_PG_DEL_GET(reg) BSP_FLD32GET(reg,2, 7)
+#define TMS570_EMIF_PMCR_CS2_PG_DEL_SET(reg,val) BSP_FLD32SET(reg, val,2, 7)
+
+/* field: CS2_PG_SIZE - Page Size for NOR Flash connected on CS2. */
+#define TMS570_EMIF_PMCR_CS2_PG_SIZE BSP_FLD32(1)
+
+/* field: CS2_PG_MD_EN - Page Mode enable for NOR Flash connected on CS2. */
+#define TMS570_EMIF_PMCR_CS2_PG_MD_EN BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_EMIF */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
new file mode 100644
index 0000000..5a65bca
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_esm.h
@@ -0,0 +1,215 @@
+/* The header file is generated by make_header.py from ESM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_ESM
+#define LIBBSP_ARM_tms570_ESM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t EEPAPR1; /*ESM Enable ERROR Pin Action/Response Register 1*/
+ uint32_t DEPAPR1; /*ESM Disable ERROR Pin Action/Response Register 1*/
+ uint32_t IESR1; /*ESM Interrupt Enable Set/Status Register 1*/
+ uint32_t IECR1; /*ESM Interrupt Enable Clear/Status Register 1*/
+ uint32_t ILSR1; /*Interrupt Level Set/Status Register 1*/
+ uint32_t ILCR1; /*Interrupt Level Clear/Status Register 1*/
+ uint32_t SR[3]; /*ESM Status Register*/
+ uint32_t EPSR; /*ESM ERROR Pin Status Register*/
+ uint32_t IOFFHR; /*ESM Interrupt Offset High Register*/
+ uint32_t IOFFLR; /*ESM Interrupt Offset Low Register*/
+ uint32_t LTCR; /*ESM Low-Time Counter Register*/
+ uint32_t LTCPR; /*ESM Low-Time Counter Preload Register*/
+ uint32_t EKR; /*ESM Error Key Register*/
+ uint32_t SSR2; /*ESM Status Shadow Register 2*/
+ uint32_t IEPSR4; /*ESM Influence ERROR Pin Set/Status Register 4*/
+ uint32_t IEPCR4; /*ESM Influence ERROR Pin Clear/Status Register 4*/
+ uint32_t IESR4; /*ESM Interrupt Enable Set/Status Register 4*/
+ uint32_t IECR4; /*ESM Interrupt Enable Clear/Status Register 4*/
+ uint32_t ILSR4; /*Interrupt Level Set/Status Register 4*/
+ uint32_t ILCR4; /*Interrupt Level Clear/Status Register 4*/
+ uint32_t SR4; /*ESM Status Register 4*/
+} tms570_esm_t;
+
+
+/*---------------------TMS570_ESMEEPAPR1---------------------*/
+/* field: IEPSET - Enable ERROR Pin Action/Response on Group 1. */
+#define TMS570_ESM_EEPAPR1_IEPSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_EEPAPR1_IEPSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_EEPAPR1_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_ESMDEPAPR1---------------------*/
+/* field: IEPCLR - Disable ERROR Pin Action/Response on Group 1. */
+#define TMS570_ESM_DEPAPR1_IEPCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_DEPAPR1_IEPCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_DEPAPR1_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_ESMIESR1----------------------*/
+/* field: INTENSET - Set interrupt Enable */
+#define TMS570_ESM_IESR1_INTENSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_IESR1_INTENSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_IESR1_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_ESMIECR1----------------------*/
+/* field: INTENCLR - Clear Interrupt Enable */
+#define TMS570_ESM_IECR1_INTENCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_IECR1_INTENCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_IECR1_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_ESMILSR1----------------------*/
+/* field: INTLVLSET - Set Interrupt Priority */
+#define TMS570_ESM_ILSR1_INTLVLSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_ILSR1_INTLVLSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_ILSR1_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_ESMILCR1----------------------*/
+/* field: INTLVLCLR - Clear Interrupt Priority. */
+#define TMS570_ESM_ILCR1_INTLVLCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_ILCR1_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_ILCR1_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------------TMS570_ESMSR------------------------*/
+/* field: ESF - Error Status Flag. Provides status information on a pending error. */
+#define TMS570_ESM_SR_ESF(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_SR_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_SR_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_ESMEPSR-----------------------*/
+/* field: EPSF - ERROR Pin Status Flag. Provides status information for the ERROR Pin. */
+#define TMS570_ESM_EPSR_EPSF BSP_FLD32(0)
+
+
+/*----------------------TMS570_ESMIOFFHR----------------------*/
+/* field: INTOFFH - Offset High Level Interrupt. */
+#define TMS570_ESM_IOFFHR_INTOFFH(val) BSP_FLD32(val,0, 6)
+#define TMS570_ESM_IOFFHR_INTOFFH_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_ESM_IOFFHR_INTOFFH_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*----------------------TMS570_ESMIOFFLR----------------------*/
+/* field: INTOFFL - Offset Low Level Interrupt. */
+#define TMS570_ESM_IOFFLR_INTOFFL(val) BSP_FLD32(val,0, 6)
+#define TMS570_ESM_IOFFLR_INTOFFL_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_ESM_IOFFLR_INTOFFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*-----------------------TMS570_ESMLTCR-----------------------*/
+/* field: LTC - ERROR Pin Low-Time Counter */
+#define TMS570_ESM_LTCR_LTC(val) BSP_FLD32(val,0, 15)
+#define TMS570_ESM_LTCR_LTC_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_ESM_LTCR_LTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_ESMLTCPR----------------------*/
+/* field: LTCP - ERROR Pin Low-Time Counter Pre-load Value */
+#define TMS570_ESM_LTCPR_LTCP(val) BSP_FLD32(val,0, 15)
+#define TMS570_ESM_LTCPR_LTCP_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_ESM_LTCPR_LTCP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_ESMEKR-----------------------*/
+/* field: EKEY - Error Key. The key to reset the ERROR pin or to force an error on the ERROR pin. */
+#define TMS570_ESM_EKR_EKEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_ESM_EKR_EKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_ESM_EKR_EKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_ESMSSR2-----------------------*/
+/* field: ESF - Error Status Flag. Shadow register for status information on pending error. */
+#define TMS570_ESM_SSR2_ESF(val) BSP_FLD32(val,0, 31)
+#define TMS570_ESM_SSR2_ESF_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_ESM_SSR2_ESF_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_ESMIEPSR4----------------------*/
+/* field: IEPSET - Set Influence on ERROR Pin */
+#define TMS570_ESM_IEPSR4_IEPSET(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_IEPSR4_IEPSET_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_IEPSR4_IEPSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*----------------------TMS570_ESMIEPCR4----------------------*/
+/* field: IEPCLR - Clear Influence on ERROR Pin */
+#define TMS570_ESM_IEPCR4_IEPCLR(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_IEPCR4_IEPCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_IEPCR4_IEPCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*----------------------TMS570_ESMIESR4----------------------*/
+/* field: INTENSET - Set Interrupt Enable */
+#define TMS570_ESM_IESR4_INTENSET(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_IESR4_INTENSET_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_IESR4_INTENSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*----------------------TMS570_ESMIECR4----------------------*/
+/* field: INTENCLR - Clear Interrupt Enable */
+#define TMS570_ESM_IECR4_INTENCLR(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_IECR4_INTENCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_IECR4_INTENCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*----------------------TMS570_ESMILSR4----------------------*/
+/* field: INTLVLSET - Set Interrupt Level */
+#define TMS570_ESM_ILSR4_INTLVLSET(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_ILSR4_INTLVLSET_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_ILSR4_INTLVLSET_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*----------------------TMS570_ESMILCR4----------------------*/
+/* field: INTLVLCLR - Clear Interrupt Level */
+#define TMS570_ESM_ILCR4_INTLVLCLR(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_ILCR4_INTLVLCLR_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_ILCR4_INTLVLCLR_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+/*-----------------------TMS570_ESMSR4-----------------------*/
+/* field: ESF - Error Status Flag. Provides status information on a pending error. */
+#define TMS570_ESM_SR4_ESF(val) BSP_FLD32(val,32, 63)
+#define TMS570_ESM_SR4_ESF_GET(reg) BSP_FLD32GET(reg,32, 63)
+#define TMS570_ESM_SR4_ESF_SET(reg,val) BSP_FLD32SET(reg, val,32, 63)
+
+
+
+#endif /* LIBBSP_ARM_tms570_ESM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
new file mode 100644
index 0000000..ac0fc40
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flash.h
@@ -0,0 +1,687 @@
+/* The header file is generated by make_header.py from FLASH.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_FLASH
+#define LIBBSP_ARM_tms570_FLASH
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t FRDCNTL; /*Flash Option Control Register*/
+ uint8_t reserved1 [4];
+ uint32_t FEDACTRL1; /*Flash Error Detection and Correction Control Register 1*/
+ uint32_t FEDACTRL2; /*Flash Error Detection and Correction Control Register 2*/
+ uint32_t FCORERRCNT; /*Flash Correctable Error Count Register*/
+ uint32_t FCORERRADD; /*Flash Correctable Error Address Register*/
+ uint32_t FCORERRPOS; /*Flash Correctable Error Position Register*/
+ uint32_t FEDACSTATUS; /*Flash Error Detection and Correction Status Register*/
+ uint32_t FUNCERRADD; /*Flash Un-Correctable Error Address Register*/
+ uint32_t FEDACSDIS; /*Flash Error Detection and Correction Sector Disable Register*/
+ uint32_t FPRIMADDTAG; /*Flash Primary Address Tag Register*/
+ uint32_t FDUPADDTAG; /*Flash Duplicate Address Tag Register*/
+ uint32_t FBPROT; /*Flash Bank Protection Register*/
+ uint32_t FBSE; /*Flash Bank Sector Enable Register*/
+ uint32_t FBBUSY; /*Flash Bank Busy Register*/
+ uint32_t FBAC; /*Flash Bank Access Control Register*/
+ uint32_t FBFALLBACK; /*Flash Bank Fallback Power Register*/
+ uint32_t FBPRDY; /*Flash Bank/Pump Ready Register*/
+ uint32_t FPAC1; /*Flash Pump Access Control Register 1*/
+ uint32_t FPAC2; /*Flash Pump Access Control Register 2*/
+ uint32_t FMAC; /*Flash Module Access Control Register*/
+ uint32_t FMSTAT; /*Flash Module Status Register*/
+ uint32_t FEMUDMSW; /*EEPROM Emulation Data MSW Register*/
+ uint32_t FEMUDLSW; /*EEPROM Emulation Data LSW Register*/
+ uint32_t FEMUECC; /*EEPROM Emulation ECC Register*/
+ uint8_t reserved2 [4];
+ uint32_t FEMUADDR; /*EEPROM Emulation Address Register*/
+ uint32_t FDIAGCTRL; /*Diagnostic Control Register*/
+ uint32_t FRAWDATAH; /*Uncorrected Raw Data High Register*/
+ uint32_t FRAWDATAL; /*Uncorrected Raw Data Low Register*/
+ uint32_t FRAWECC; /*Uncorrected Raw ECC Register*/
+ uint32_t FPAROVR; /*Parity Override Register*/
+ uint8_t reserved3 [64];
+ uint32_t FEDACSDIS2; /*Flash Error Detection and Correction Sector Disable Register 2*/
+ uint8_t reserved4 [452];
+ uint32_t FSMWRENA; /*FSM Register Write Enable*/
+ uint8_t reserved5 [24];
+ uint32_t FSMSECTOR; /*FSM Sector Register*/
+ uint8_t reserved6 [16];
+ uint32_t EEPROMCONFIG; /*EEPROM Emulation Configuration Register*/
+ uint8_t reserved7 [76];
+ uint32_t EECTRL1; /*EEPROM Emulation Error Detection and Correction Control Register 1*/
+ uint32_t EECTRL2; /*EEPROM Emulation Error Detection and Correction Control Register 2*/
+ uint32_t EECORERRCNT; /*EEPROM Emulation Correctable Error Count Register*/
+ uint32_t EECORERRADD; /*EEPROM Emulation Correctable Error Address Register*/
+ uint32_t EECORERRPOS; /*EEPROM Emulation Correctable Error Bit Position Register*/
+ uint32_t EESTATUS; /*EEPROM Emulation Error Status Register*/
+ uint32_t EEUNCERRADD; /*EEPROM Emulation Un-Correctable Error Address Register*/
+ uint8_t reserved8 [220];
+ uint32_t FCFGBANK; /*Flash Bank Configuration Register*/
+} tms570_flash_t;
+
+
+/*--------------------TMS570_FLASHFRDCNTL--------------------*/
+/* field: RWAIT - Random/data Read Wait State */
+#define TMS570_FLASH_FRDCNTL_RWAIT(val) BSP_FLD32(val,8, 11)
+#define TMS570_FLASH_FRDCNTL_RWAIT_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_FLASH_FRDCNTL_RWAIT_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: ASWSTEN - Address Setup Wait State Enable */
+#define TMS570_FLASH_FRDCNTL_ASWSTEN BSP_FLD32(4)
+
+/* field: ENPIPE - Enable Pipeline Mode */
+#define TMS570_FLASH_FRDCNTL_ENPIPE BSP_FLD32(0)
+
+
+/*-------------------TMS570_FLASHFEDACTRL1-------------------*/
+/* field: SUSP_IGNR - Suspend Ignore. */
+#define TMS570_FLASH_FEDACTRL1_SUSP_IGNR BSP_FLD32(24)
+
+/* field: EDACMODE - Error Correction Mode. */
+#define TMS570_FLASH_FEDACTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_FEDACTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_FEDACTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: EOFEN - Event on Ones Fail Enable */
+#define TMS570_FLASH_FEDACTRL1_EOFEN BSP_FLD32(10)
+
+/* field: EZFEN - Event on Zeros Fail Enable */
+#define TMS570_FLASH_FEDACTRL1_EZFEN BSP_FLD32(9)
+
+/* field: EPEN - Error Profiling Enable. */
+#define TMS570_FLASH_FEDACTRL1_EPEN BSP_FLD32(8)
+
+/* field: EDACEN - Error Detection and Correction Enable */
+#define TMS570_FLASH_FEDACTRL1_EDACEN(val) BSP_FLD32(val,0, 3)
+#define TMS570_FLASH_FEDACTRL1_EDACEN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_FLASH_FEDACTRL1_EDACEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_FLASHFEDACTRL2-------------------*/
+/* field: SEC_THRESHOLD - Single Error Correction Threshold */
+#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_FEDACTRL2_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_FLASHFCORERRCNT-------------------*/
+/* field: FERRCNT - Single Error Correction Count */
+#define TMS570_FLASH_FCORERRCNT_FERRCNT(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_FCORERRCNT_FERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_FCORERRCNT_FERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_FLASHFCORERRADD-------------------*/
+/* field: COR_ERR_ADD - Correctable Error Address */
+#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
+#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
+#define TMS570_FLASH_FCORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31)
+
+/* field: B_OFF - Byte Offset */
+#define TMS570_FLASH_FCORERRADD_B_OFF(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_FCORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_FCORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-------------------TMS570_FLASHFCORERRPOS-------------------*/
+/* field: BUS2 - Bus 2 Error */
+#define TMS570_FLASH_FCORERRPOS_BUS2 BSP_FLD32(9)
+
+/* field: TYPE - ErrorType */
+#define TMS570_FLASH_FCORERRPOS_TYPE BSP_FLD32(8)
+
+/* field: ERR_POS - The bit address of the single bit error */
+#define TMS570_FLASH_FCORERRPOS_ERR_POS(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FCORERRPOS_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FCORERRPOS_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_FLASHFEDACSTATUS------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_FLASH_FEDACSTATUS_Reserved(val) BSP_FLD32(val,26, 31)
+#define TMS570_FLASH_FEDACSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,26, 31)
+#define TMS570_FLASH_FEDACSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,26, 31)
+
+/* field: FSM_DONE - Flash State Machine Done */
+#define TMS570_FLASH_FEDACSTATUS_FSM_DONE BSP_FLD32(24)
+
+/* field: COMB2_MAL_G - Bus 2 Compare Malfunction Flag. */
+#define TMS570_FLASH_FEDACSTATUS_COMB2_MAL_G BSP_FLD32(19)
+
+/* field: ECC_B2_MAL_ - Bus 2 ECC Malfunction Error Flag */
+#define TMS570_FLASH_FEDACSTATUS_ECC_B2_MAL_ BSP_FLD32(18)
+
+/* field: B2_UNC_ERR - Bus 2 uncorrectable error */
+#define TMS570_FLASH_FEDACSTATUS_B2_UNC_ERR BSP_FLD32(17)
+
+/* field: B2_COR_ERR - Bus 2 Correctable Error */
+#define TMS570_FLASH_FEDACSTATUS_B2_COR_ERR BSP_FLD32(16)
+
+/* field: D_UNC_ERR - Diagnostic Uncorrectable Error */
+#define TMS570_FLASH_FEDACSTATUS_D_UNC_ERR BSP_FLD32(12)
+
+/* field: ADD_TAG_ERR - Address Tag Register Error Flag */
+#define TMS570_FLASH_FEDACSTATUS_ADD_TAG_ERR BSP_FLD32(11)
+
+/* field: ADD_PAR_ERR - Address Parity Error Flag */
+#define TMS570_FLASH_FEDACSTATUS_ADD_PAR_ERR BSP_FLD32(10)
+
+/* field: B1_UNC_ERR - Bus 1 Uncorrectable Error Flag */
+#define TMS570_FLASH_FEDACSTATUS_B1_UNC_ERR BSP_FLD32(8)
+
+/* field: D_CORR_ERR - Diagnostic Correctable Error Status Flag */
+#define TMS570_FLASH_FEDACSTATUS_D_CORR_ERR BSP_FLD32(3)
+
+/* field: ERR_ONE_FLG - Error on One Fail Status Flag */
+#define TMS570_FLASH_FEDACSTATUS_ERR_ONE_FLG BSP_FLD32(2)
+
+/* field: ERR_ZERO__FLG - Error on Zero Fail Status Flag */
+#define TMS570_FLASH_FEDACSTATUS_ERR_ZERO__FLG BSP_FLD32(1)
+
+/* field: ERR_PRF_FLG - Error Profiling Status Flag */
+#define TMS570_FLASH_FEDACSTATUS_ERR_PRF_FLG BSP_FLD32(0)
+
+
+/*-------------------TMS570_FLASHFUNCERRADD-------------------*/
+/* field: UNC_ERR_ADD - Un-correctable Error Address */
+#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
+#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
+#define TMS570_FLASH_FUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31)
+
+/* field: B_OFF - Byte offset */
+#define TMS570_FLASH_FUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_FUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_FUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-------------------TMS570_FLASHFEDACSDIS-------------------*/
+/* field: BankID1_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse(val) BSP_FLD32(val,29, 31)
+#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
+#define TMS570_FLASH_FEDACSDIS_BankID1_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
+
+/* field: SectorID1_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse(val) BSP_FLD32(val,24, 27)
+#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_FLASH_FEDACSDIS_SectorID1_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: BankID1 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS_BankID1(val) BSP_FLD32(val,21, 23)
+#define TMS570_FLASH_FEDACSDIS_BankID1_GET(reg) BSP_FLD32GET(reg,21, 23)
+#define TMS570_FLASH_FEDACSDIS_BankID1_SET(reg,val) BSP_FLD32SET(reg, val,21, 23)
+
+/* field: SectorID1 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS_SectorID1(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_FEDACSDIS_SectorID1_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_FEDACSDIS_SectorID1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: BankID0_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse(val) BSP_FLD32(val,13, 15)
+#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15)
+#define TMS570_FLASH_FEDACSDIS_BankID0_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15)
+
+/* field: SectorID0_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse(val) BSP_FLD32(val,8, 11)
+#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_FLASH_FEDACSDIS_SectorID0_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: BankID0 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS_BankID0(val) BSP_FLD32(val,5, 7)
+#define TMS570_FLASH_FEDACSDIS_BankID0_GET(reg) BSP_FLD32GET(reg,5, 7)
+#define TMS570_FLASH_FEDACSDIS_BankID0_SET(reg,val) BSP_FLD32SET(reg, val,5, 7)
+
+/* field: SectorID0 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS_SectorID0(val) BSP_FLD32(val,0, 3)
+#define TMS570_FLASH_FEDACSDIS_SectorID0_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_FLASH_FEDACSDIS_SectorID0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_FLASHFPRIMADDTAG------------------*/
+/* field: PRIM_ADD_TAG - Primary Address Tag Register */
+#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG(val) BSP_FLD32(val,4, 31)
+#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
+#define TMS570_FLASH_FPRIMADDTAG_PRIM_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
+
+/* field: 0 - Always 0000 */
+#define TMS570_FLASH_FPRIMADDTAG_0(val) BSP_FLD32(val,0, 3)
+#define TMS570_FLASH_FPRIMADDTAG_0_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_FLASH_FPRIMADDTAG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_FLASHFDUPADDTAG-------------------*/
+/* field: DUP_ADD_TAG - Primary Address Tag Register */
+#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG(val) BSP_FLD32(val,4, 31)
+#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_GET(reg) BSP_FLD32GET(reg,4, 31)
+#define TMS570_FLASH_FDUPADDTAG_DUP_ADD_TAG_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
+
+
+/*---------------------TMS570_FLASHFBPROT---------------------*/
+/* field: PROTL1DIS - PROTL1DIS: Level 1 Protection Disabled */
+#define TMS570_FLASH_FBPROT_PROTL1DIS BSP_FLD32(0)
+
+
+/*----------------------TMS570_FLASHFBSE----------------------*/
+/* field: BSE - Bank Sector Enable */
+#define TMS570_FLASH_FBSE_BSE(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_FBSE_BSE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_FBSE_BSE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_FLASHFBBUSY---------------------*/
+/* field: BUSY - Bank Busy */
+#define TMS570_FLASH_FBBUSY_BUSY(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FBBUSY_BUSY_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FBBUSY_BUSY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_FLASHFBAC----------------------*/
+/* field: OTPPROTDIS - OTP Sector Protection Disable. */
+#define TMS570_FLASH_FBAC_OTPPROTDIS(val) BSP_FLD32(val,16, 23)
+#define TMS570_FLASH_FBAC_OTPPROTDIS_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_FLASH_FBAC_OTPPROTDIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: 15_8 - BAGP 0-FFh Bank Active Grace Period. */
+#define TMS570_FLASH_FBAC_15_8(val) BSP_FLD32(val,8, 15)
+#define TMS570_FLASH_FBAC_15_8_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_FLASH_FBAC_15_8_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: VREADST - VREAD Setup. */
+#define TMS570_FLASH_FBAC_VREADST(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FBAC_VREADST_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FBAC_VREADST_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_FLASHFBFALLBACK-------------------*/
+/* field: BANKPWR7 - Bank 7 Fallback Power Mode */
+#define TMS570_FLASH_FBFALLBACK_BANKPWR7(val) BSP_FLD32(val,14, 15)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR7_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR7_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+/* field: BANKPWR1 - Bank 1 Fallback Power Mode */
+#define TMS570_FLASH_FBFALLBACK_BANKPWR1(val) BSP_FLD32(val,2, 3)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR1_GET(reg) BSP_FLD32GET(reg,2, 3)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR1_SET(reg,val) BSP_FLD32SET(reg, val,2, 3)
+
+/* field: BANKPWR0 - Bank 0 Fallback Power Mode */
+#define TMS570_FLASH_FBFALLBACK_BANKPWR0(val) BSP_FLD32(val,0, 1)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR0_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_FLASH_FBFALLBACK_BANKPWR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_FLASHFBPRDY---------------------*/
+/* field: BANKBUSY - Bank busy bits (one bit for each bank) */
+#define TMS570_FLASH_FBPRDY_BANKBUSY(val) BSP_FLD32(val,16, 23)
+#define TMS570_FLASH_FBPRDY_BANKBUSY_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_FLASH_FBPRDY_BANKBUSY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: PUMPRDY - Flash pump ready flag */
+#define TMS570_FLASH_FBPRDY_PUMPRDY BSP_FLD32(15)
+
+/* field: BANKRDY - Bank ready bits (one bit for each bank) */
+#define TMS570_FLASH_FBPRDY_BANKRDY(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FBPRDY_BANKRDY_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FBPRDY_BANKRDY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_FLASHFPAC1---------------------*/
+/* field: PSLEEP - Pump Sleep. */
+#define TMS570_FLASH_FPAC1_PSLEEP(val) BSP_FLD32(val,16, 26)
+#define TMS570_FLASH_FPAC1_PSLEEP_GET(reg) BSP_FLD32GET(reg,16, 26)
+#define TMS570_FLASH_FPAC1_PSLEEP_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
+
+/* field: PUMPPWR - Flash Charge Pump Fallback Power Mode */
+#define TMS570_FLASH_FPAC1_PUMPPWR BSP_FLD32(0)
+
+
+/*---------------------TMS570_FLASHFPAC2---------------------*/
+/* field: PAGP - Pump Active Grace Period */
+#define TMS570_FLASH_FPAC2_PAGP(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_FPAC2_PAGP_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_FPAC2_PAGP_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_FLASHFMAC----------------------*/
+/* field: BANK - Bank Enable. */
+#define TMS570_FLASH_FMAC_BANK(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_FMAC_BANK_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_FMAC_BANK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*---------------------TMS570_FLASHFMSTAT---------------------*/
+/* field: ILA - Illegal Address */
+#define TMS570_FLASH_FMSTAT_ILA BSP_FLD32(14)
+
+/* field: PGV - Program Verify */
+#define TMS570_FLASH_FMSTAT_PGV BSP_FLD32(12)
+
+/* field: EV - Erase Verify */
+#define TMS570_FLASH_FMSTAT_EV BSP_FLD32(10)
+
+/* field: BUSY - Busy */
+#define TMS570_FLASH_FMSTAT_BUSY BSP_FLD32(8)
+
+/* field: ERS - Erase Active */
+#define TMS570_FLASH_FMSTAT_ERS BSP_FLD32(7)
+
+/* field: PGM - Program Active */
+#define TMS570_FLASH_FMSTAT_PGM BSP_FLD32(6)
+
+/* field: INVDAT - Invalid Data */
+#define TMS570_FLASH_FMSTAT_INVDAT BSP_FLD32(5)
+
+/* field: CSTAT - Command Status */
+#define TMS570_FLASH_FMSTAT_CSTAT BSP_FLD32(4)
+
+/* field: VOLTSTAT - Core Voltage Status */
+#define TMS570_FLASH_FMSTAT_VOLTSTAT BSP_FLD32(3)
+
+/* field: ESUSP - Erase Suspended */
+#define TMS570_FLASH_FMSTAT_ESUSP BSP_FLD32(2)
+
+/* field: PSUSP - Program Suspended */
+#define TMS570_FLASH_FMSTAT_PSUSP BSP_FLD32(1)
+
+/* field: SLOCK - Sector Lock Status */
+#define TMS570_FLASH_FMSTAT_SLOCK BSP_FLD32(0)
+
+
+/*--------------------TMS570_FLASHFEMUDMSW--------------------*/
+/* field: EMU_DMSW - EEPROM Emulation Most Significant Data Word */
+#define TMS570_FLASH_FEMUDMSW_EMU_DMSW(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLASH_FEMUDMSW_EMU_DMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLASHFEMUDLSW--------------------*/
+/* field: EMU_DLSW - EEPROM Emulation Least Significant Data Word */
+#define TMS570_FLASH_FEMUDLSW_EMU_DLSW(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLASH_FEMUDLSW_EMU_DLSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLASHFEMUECC--------------------*/
+/* field: EMU_ECC - This register can be written by the CPU in any mode. */
+#define TMS570_FLASH_FEMUECC_EMU_ECC(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FEMUECC_EMU_ECC_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FEMUECC_EMU_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_FLASHFEMUADDR--------------------*/
+/* field: EMU_ADDR - EEPROM Emulation Address */
+#define TMS570_FLASH_FEMUADDR_EMU_ADDR(val) BSP_FLD32(val,3, 21)
+#define TMS570_FLASH_FEMUADDR_EMU_ADDR_GET(reg) BSP_FLD32GET(reg,3, 21)
+#define TMS570_FLASH_FEMUADDR_EMU_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,3, 21)
+
+
+/*-------------------TMS570_FLASHFDIAGCTRL-------------------*/
+/* field: DIAG_TRIG - Diagnostic Trigger */
+#define TMS570_FLASH_FDIAGCTRL_DIAG_TRIG BSP_FLD32(24)
+
+/* field: DIAG_EN_KEY - Diagnostic Enable Key */
+#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_EN_KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: DIAG_ECC_SEL - Diagnostic SECDED Select */
+#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL(val) BSP_FLD32(val,12, 14)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_GET(reg) BSP_FLD32GET(reg,12, 14)
+#define TMS570_FLASH_FDIAGCTRL_DIAG_ECC_SEL_SET(reg,val) BSP_FLD32SET(reg, val,12, 14)
+
+
+/*-------------------TMS570_FLASHFRAWDATAH-------------------*/
+/* field: RAW_DATA_ - Uncorrected Raw Data */
+#define TMS570_FLASH_FRAWDATAH_RAW_DATA_(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLASH_FRAWDATAH_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLASH_FRAWDATAH_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLASHFRAWDATAL-------------------*/
+/* field: RAW_DATA_ - Uncorrected Raw Data. Same as FRAW_DATAH but stores lower 32 bits. */
+#define TMS570_FLASH_FRAWDATAL_RAW_DATA_(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLASH_FRAWDATAL_RAW_DATA__GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLASH_FRAWDATAL_RAW_DATA__SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLASHFRAWECC--------------------*/
+/* field: PIPE_BUF - Error came from pipeline buffer hit */
+#define TMS570_FLASH_FRAWECC_PIPE_BUF BSP_FLD32(8)
+
+/* field: RAW_ECC - Uncorrected Raw ECC */
+#define TMS570_FLASH_FRAWECC_RAW_ECC(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FRAWECC_RAW_ECC_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FRAWECC_RAW_ECC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_FLASHFPAROVR--------------------*/
+/* field: BNK_INV_PAR - Buffer Invert Parity */
+#define TMS570_FLASH_FPAROVR_BNK_INV_PAR BSP_FLD32(16)
+
+/* field: BUS_PAR_DIS - Disable Bus Parity */
+#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS(val) BSP_FLD32(val,12, 15)
+#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_GET(reg) BSP_FLD32GET(reg,12, 15)
+#define TMS570_FLASH_FPAROVR_BUS_PAR_DIS_SET(reg,val) BSP_FLD32SET(reg, val,12, 15)
+
+/* field: PAR_OVR_KEY - When this value is 101, the selected ADD_INV_PAR and DAT_INV_PAR fields will become active. */
+#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY(val) BSP_FLD32(val,9, 11)
+#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_GET(reg) BSP_FLD32GET(reg,9, 11)
+#define TMS570_FLASH_FPAROVR_PAR_OVR_KEY_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
+
+/* field: ADD_INV_PAR - Address Odd Parity */
+#define TMS570_FLASH_FPAROVR_ADD_INV_PAR BSP_FLD32(8)
+
+/* field: DAT_INV_PAR - Data Odd Parity */
+#define TMS570_FLASH_FPAROVR_DAT_INV_PAR(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_FPAROVR_DAT_INV_PAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_FLASHFEDACSDIS2-------------------*/
+/* field: BankID3_Inverse - The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse(val) BSP_FLD32(val,29, 31)
+#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_GET(reg) BSP_FLD32GET(reg,29, 31)
+#define TMS570_FLASH_FEDACSDIS2_BankID3_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
+
+/* field: SectorID3_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled. */
+#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse(val) BSP_FLD32(val,24, 27)
+#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_FLASH_FEDACSDIS2_SectorID3_inverse_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: BankID3 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS2_BankID3(val) BSP_FLD32(val,21, 23)
+#define TMS570_FLASH_FEDACSDIS2_BankID3_GET(reg) BSP_FLD32GET(reg,21, 23)
+#define TMS570_FLASH_FEDACSDIS2_BankID3_SET(reg,val) BSP_FLD32SET(reg, val,21, 23)
+
+/* field: SectorID3 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS2_SectorID3(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_FEDACSDIS2_SectorID3_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_FEDACSDIS2_SectorID3_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: BankID2_Inverse - is disabled. The only bank that supports sector disable is bank 7. */
+#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse(val) BSP_FLD32(val,13, 15)
+#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_GET(reg) BSP_FLD32GET(reg,13, 15)
+#define TMS570_FLASH_FEDACSDIS2_BankID2_Inverse_SET(reg,val) BSP_FLD32SET(reg, val,13, 15)
+
+/* field: SectorID2_inverse - The sector ID inverse bits are used with the sector ID bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse(val) BSP_FLD32(val,8, 11)
+#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_FLASH_FEDACSDIS2_SectorID2_inverse_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: BankID2 - The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector */
+#define TMS570_FLASH_FEDACSDIS2_BankID2(val) BSP_FLD32(val,5, 7)
+#define TMS570_FLASH_FEDACSDIS2_BankID2_GET(reg) BSP_FLD32GET(reg,5, 7)
+#define TMS570_FLASH_FEDACSDIS2_BankID2_SET(reg,val) BSP_FLD32SET(reg, val,5, 7)
+
+/* field: SectorID2 - The sector ID bits are used with the sector ID inverse bits to determine which sector is */
+#define TMS570_FLASH_FEDACSDIS2_SectorID2(val) BSP_FLD32(val,0, 3)
+#define TMS570_FLASH_FEDACSDIS2_SectorID2_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_FLASH_FEDACSDIS2_SectorID2_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_FLASHFSMWRENA--------------------*/
+/* field: WR_ENA - Flash State Machine Write Enable */
+#define TMS570_FLASH_FSMWRENA_WR_ENA(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_FSMWRENA_WR_ENA_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_FSMWRENA_WR_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-------------------TMS570_FLASHFSMSECTOR-------------------*/
+/* field: SECT_ERASED - Sectors Erased */
+#define TMS570_FLASH_FSMSECTOR_SECT_ERASED(val) BSP_FLD32(val,16, 31)
+#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_FLASH_FSMSECTOR_SECT_ERASED_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+
+/*------------------TMS570_FLASHEEPROMCONFIG------------------*/
+/* field: EWAIT - EEPROM Wait state Counter */
+#define TMS570_FLASH_EEPROMCONFIG_EWAIT(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_EEPROMCONFIG_EWAIT_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_EEPROMCONFIG_EWAIT_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: AUTOSUSP_EN - Auto Suspend Enable */
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSUSP_EN BSP_FLD32(8)
+
+/* field: AUTOSTART_GRACE - Auto-suspend Startup Grace Period */
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_EEPROMCONFIG_AUTOSTART_GRACE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_FLASHEECTRL1--------------------*/
+/* field: EDACMODE - Error Correction Mode. */
+#define TMS570_FLASH_EECTRL1_EDACMODE(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLASH_EECTRL1_EDACMODE_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLASH_EECTRL1_EDACMODE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: EE_EOFEN - EEPROM Emulation Event on a correctable One's Fail Enable bit */
+#define TMS570_FLASH_EECTRL1_EE_EOFEN BSP_FLD32(10)
+
+/* field: EE_EZFEN - EEPROM Emulation Event on a correctable Zero's Fail Enable bit */
+#define TMS570_FLASH_EECTRL1_EE_EZFEN BSP_FLD32(9)
+
+/* field: EE_EPEN - EEPROM Emulation Error Profiling Enable. */
+#define TMS570_FLASH_EECTRL1_EE_EPEN BSP_FLD32(8)
+
+
+/*--------------------TMS570_FLASHEECTRL2--------------------*/
+/* field: EE_SEC_THRESHOLD - EEPROM Emulation Single Error Correction Threshold */
+#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_EECTRL2_EE_SEC_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*------------------TMS570_FLASHEECORERRCNT------------------*/
+/* field: EE_ERRCNT - Single Error Correction Count */
+#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLASH_EECORERRCNT_EE_ERRCNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*------------------TMS570_FLASHEECORERRADD------------------*/
+/* field: COR_ERR_ADD - Correctable Error Address */
+#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD(val) BSP_FLD32(val,3, 31)
+#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
+#define TMS570_FLASH_EECORERRADD_COR_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31)
+
+/* field: B_OFF - Byte offset */
+#define TMS570_FLASH_EECORERRADD_B_OFF(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_EECORERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_EECORERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*------------------TMS570_FLASHEECORERRPOS------------------*/
+/* field: TYPE - ErrorType */
+#define TMS570_FLASH_EECORERRPOS_TYPE BSP_FLD32(8)
+
+/* field: EE_ERR_POS - The bit address of the single bit error */
+#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLASH_EECORERRPOS_EE_ERR_POS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_FLASHEESTATUS--------------------*/
+/* field: EE_D_UNC_ERR - Diagnostic Mode Uncorrectable Error Status Flag */
+#define TMS570_FLASH_EESTATUS_EE_D_UNC_ERR BSP_FLD32(12)
+
+/* field: EE_UNC_ERR - EEPROM Emulation Uncorrectable Error Flag */
+#define TMS570_FLASH_EESTATUS_EE_UNC_ERR BSP_FLD32(8)
+
+/* field: EE_CMG - EEPROM Emulation Compare Malfunction Good */
+#define TMS570_FLASH_EESTATUS_EE_CMG BSP_FLD32(6)
+
+/* field: EE_CME - . */
+#define TMS570_FLASH_EESTATUS_EE_CME BSP_FLD32(4)
+
+/* field: EE_D_COR_ERR - Diagnostic Correctable Error Flag */
+#define TMS570_FLASH_EESTATUS_EE_D_COR_ERR BSP_FLD32(3)
+
+/* field: EE_ERR_ONE_FLG - Error on One Fail Error Flag */
+#define TMS570_FLASH_EESTATUS_EE_ERR_ONE_FLG BSP_FLD32(2)
+
+/* field: EE_ERR_ZERO_FLG - Error on Zero Fail Error Flag */
+#define TMS570_FLASH_EESTATUS_EE_ERR_ZERO_FLG BSP_FLD32(1)
+
+/* field: EE_ERR_PRF_FLG - Error Profiling Error Flag */
+#define TMS570_FLASH_EESTATUS_EE_ERR_PRF_FLG BSP_FLD32(0)
+
+
+/*------------------TMS570_FLASHEEUNCERRADD------------------*/
+/* field: UNC_ERR_ADD - Un-correctable Error Address */
+#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD(val) BSP_FLD32(val,3, 31)
+#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_GET(reg) BSP_FLD32GET(reg,3, 31)
+#define TMS570_FLASH_EEUNCERRADD_UNC_ERR_ADD_SET(reg,val) BSP_FLD32SET(reg, val,3, 31)
+
+/* field: B_OFF - Byte offset */
+#define TMS570_FLASH_EEUNCERRADD_B_OFF(val) BSP_FLD32(val,0, 2)
+#define TMS570_FLASH_EEUNCERRADD_B_OFF_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_FLASH_EEUNCERRADD_B_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*--------------------TMS570_FLASHFCFGBANK--------------------*/
+/* field: EE_BANK_WIDTH - Bank 7 width (144 bits wide) */
+#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH(val) BSP_FLD32(val,20, 31)
+#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,20, 31)
+#define TMS570_FLASH_FCFGBANK_EE_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,20, 31)
+
+/* field: MAIN_BANK_WIDTH - Width of main flash banks (144 bits wide) */
+#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH(val) BSP_FLD32(val,4, 15)
+#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_GET(reg) BSP_FLD32GET(reg,4, 15)
+#define TMS570_FLASH_FCFGBANK_MAIN_BANK_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,4, 15)
+
+
+
+#endif /* LIBBSP_ARM_tms570_FLASH */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
new file mode 100644
index 0000000..799ad1b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_flex_ray.h
@@ -0,0 +1,801 @@
+/* The header file is generated by make_header.py from FLEX_RAY.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_FLEX_RAY
+#define LIBBSP_ARM_tms570_FLEX_RAY
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GSN0; /*Global Static Number 0*/
+ uint32_t GSN1; /*Global Static Number 1*/
+ uint8_t reserved1 [8];
+ uint32_t GCS; /*Global Control Set*/
+ uint32_t GCR; /*Global Control Reset*/
+ uint32_t TSCB; /*Transfer Status Current Buffer*/
+ uint32_t LTBCC; /*Last Transferred Buffer to Communication Controller*/
+ uint32_t LTBSM; /*Last Transferred Buffer to System Memory*/
+ uint32_t TBA; /*Transfer Base Address*/
+ uint32_t NTBA; /*Next Transfer Base Address*/
+ uint32_t BAMS; /*Base Address of Mirrored Status*/
+ uint32_t SAMP; /*Start Address of Memory Protection*/
+ uint32_t EAMP; /*End Address of Memory Protection*/
+ uint8_t reserved2 [8];
+ uint32_t TSMO1; /*Transfer to System Memory Occurred 1*/
+ uint32_t TSMO2; /*Transfer to System Memory Occurred 2*/
+ uint32_t TSMO3; /*Transfer to System Memory Occurred 3*/
+ uint32_t TSMO4; /*Transfer to System Memory Occurred 4*/
+ uint32_t TCCO1; /*Transfer to Communication Controller Occurred 1*/
+ uint32_t TCCO2; /*Transfer to Communication Controller Occurred 2*/
+ uint32_t TCCO3; /*Transfer to Communication Controller Occurred 3*/
+ uint32_t TCCO4; /*Transfer to Communication Controller Occurred 4*/
+ uint32_t TOOFF; /*Transfer Occurred Offset*/
+ uint8_t reserved3 [12];
+ uint32_t PEADR; /*Parity Error Address*/
+ uint32_t TEIF; /*Transfer Error Interrupt*/
+ uint32_t TEIRES; /*Transfer Error Interrupt Enable Set*/
+ uint32_t TEIRER; /*Transfer Error Interrupt Enable Reset*/
+ uint32_t TTSMS1; /*Trigger Transfer to System Memory Set 1*/
+ uint32_t TTSMR1; /*Trigger Transfer to System Memory Reset 1*/
+ uint32_t TTSMS2; /*Trigger Transfer to System Memory Set 2*/
+ uint32_t TTSMR2; /*Trigger Transfer to System Memory Reset 2*/
+ uint32_t TTSMS3; /*Trigger Transfer to System Memory Set 3*/
+ uint32_t TTSMR3; /*Trigger Transfer to System Memory Reset 3*/
+ uint32_t TTSMS4; /*Trigger Transfer to System Memory Set 4*/
+ uint32_t TTSMR4; /*Trigger Transfer to System Memory Reset 4*/
+ uint32_t TTCCS1; /*Trigger Transfer to Communication Controller Set 1*/
+ uint32_t TTCCR1; /*Trigger Transfer to Communication Controller Reset 1*/
+ uint32_t TTCCS2; /*Trigger Transfer to Communication Controller Set 2*/
+ uint32_t TTCCR2; /*Trigger Transfer to Communication Controller Reset 2*/
+ uint32_t TTCCS3; /*Trigger Transfer to Communication Controller Set 3*/
+ uint32_t TTCCR3; /*Trigger Transfer to Communication Controller Reset 3*/
+ uint32_t TTCCS4; /*Trigger Transfer to Communication Controller Set 4*/
+ uint32_t TTCCR4; /*Trigger Transfer to Communication Controller Reset 4*/
+ uint32_t ETESMS1; /*Enable Transfer on Event to System Memory Set 1*/
+ uint32_t ETESMR1; /*Enable Transfer on Event to System Memory Reset 1*/
+ uint32_t ETESMS2; /*Enable Transfer on Event to System Memory Set 2*/
+ uint32_t ETESMR2; /*Enable Transfer on Event to System Memory Reset 2*/
+ uint32_t ETESMS3; /*Enable Transfer on Event to System Memory Set 3*/
+ uint32_t ETESMR3; /*Enable Transfer on Event to System Memory Reset 3*/
+ uint32_t ETESMS4; /*Enable Transfer on Event to System Memory Set 4*/
+ uint32_t ETESMR4; /*Enable Transfer on Event to System Memory Reset 4*/
+ uint32_t CESMS1; /*Clear on Event to System Memory Set 1*/
+ uint32_t CESMR1; /*Clear on Event to System Memory Reset 1*/
+ uint32_t CESMS2; /*Clear on Event to System Memory Set 2*/
+ uint32_t CESMR2; /*Clear on Event to System Memory Reset 2*/
+ uint32_t CESMS3; /*Clear on Event to System Memory Set 3*/
+ uint32_t CESMR3; /*Clear on Event to System Memory Reset 3*/
+ uint32_t CESMS4; /*Clear on Event to System Memory Set 4*/
+ uint32_t CESMR4; /*Clear on Event to System Memory Reset 4*/
+ uint32_t TSMIES1; /*Transfer to System Memory Interrupt Enable Set 1*/
+ uint32_t TSMIER1; /*Transfer to System Memory Interrupt Enable Reset 1*/
+ uint32_t TSMIES2; /*Transfer to System Memory Interrupt Enable Set 2*/
+ uint32_t TSMIER2; /*Transfer to System Memory Interrupt Enable Reset 2*/
+ uint32_t TSMIES3; /*Transfer to System Memory Interrupt Enable Set 3*/
+ uint32_t TSMIER3; /*Transfer to System Memory Interrupt Enable Reset 3*/
+ uint32_t TSMIES4; /*Transfer to System Memory Interrupt Enable Set 4*/
+ uint32_t TSMIER4; /*Transfer to System Memory Interrupt Enable Reset 4*/
+ uint32_t TCCIES1; /*Transfer to Communication Controller Interrupt Enable Set 1*/
+ uint32_t TCCIER1; /*Transfer to Communication Controller Interrupt Enable Reset 1*/
+ uint32_t TCCIES2; /*Transfer to Communication Controller Interrupt Enable Set 2*/
+ uint32_t TCCIER2; /*Transfer to Communication Controller Interrupt Enable Reset 2*/
+ uint32_t TCCIES3; /*Transfer to Communication Controller Interrupt Enable Set 3*/
+ uint32_t TCCIER3; /*Transfer to Communication Controller Interrupt Enable Reset 3*/
+ uint32_t TCCIES4; /*Transfer to Communication Controller Interrupt Enable Set 4*/
+ uint32_t TCCIER4; /*Transfer to Communication Controller Interrupt Enable Reset 4*/
+} tms570_flex_ray_t;
+
+
+/*--------------------TMS570_FLEX_RAYGSN0--------------------*/
+/* field: Data_A - Data_A(15-0) */
+#define TMS570_FLEX_RAY_GSN0_Data_A(val) BSP_FLD32(val,16, 31)
+#define TMS570_FLEX_RAY_GSN0_Data_A_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_FLEX_RAY_GSN0_Data_A_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: Data_B - (complement of Data_A(15-0)) */
+#define TMS570_FLEX_RAY_GSN0_Data_B(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLEX_RAY_GSN0_Data_B_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLEX_RAY_GSN0_Data_B_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_FLEX_RAYGSN1--------------------*/
+/* field: Data_C - Data_C(15-0) */
+#define TMS570_FLEX_RAY_GSN1_Data_C(val) BSP_FLD32(val,16, 31)
+#define TMS570_FLEX_RAY_GSN1_Data_C_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_FLEX_RAY_GSN1_Data_C_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: Data_D - (complement of Data_C(15-0)) */
+#define TMS570_FLEX_RAY_GSN1_Data_D(val) BSP_FLD32(val,0, 15)
+#define TMS570_FLEX_RAY_GSN1_Data_D_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_FLEX_RAY_GSN1_Data_D_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_FLEX_RAYGCS---------------------*/
+/* field: ENDVBM - Endianness Correction on VBusp Master */
+#define TMS570_FLEX_RAY_GCS_ENDVBM BSP_FLD32(31)
+
+/* field: ENDVBS - Endianness correction on VBusp Slave */
+#define TMS570_FLEX_RAY_GCS_ENDVBS BSP_FLD32(30)
+
+/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
+#define TMS570_FLEX_RAY_GCS_ENDRx(val) BSP_FLD32(val,28, 29)
+#define TMS570_FLEX_RAY_GCS_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29)
+#define TMS570_FLEX_RAY_GCS_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
+
+/* field: ENDHx - Endianness Correction for Header */
+#define TMS570_FLEX_RAY_GCS_ENDHx(val) BSP_FLD32(val,26, 27)
+#define TMS570_FLEX_RAY_GCS_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27)
+#define TMS570_FLEX_RAY_GCS_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27)
+
+/* field: ENDPx - Endianness Correction for Payload */
+#define TMS570_FLEX_RAY_GCS_ENDPx(val) BSP_FLD32(val,24, 25)
+#define TMS570_FLEX_RAY_GCS_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25)
+#define TMS570_FLEX_RAY_GCS_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
+
+/* field: PRIO - Transfer Priority */
+#define TMS570_FLEX_RAY_GCS_PRIO BSP_FLD32(21)
+
+/* field: PEFT - Parity for Test */
+#define TMS570_FLEX_RAY_GCS_PEFT BSP_FLD32(20)
+
+/* field: PELx - Parity Lock */
+#define TMS570_FLEX_RAY_GCS_PELx(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLEX_RAY_GCS_PELx_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLEX_RAY_GCS_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: CETESM - Clear ETESM Register */
+#define TMS570_FLEX_RAY_GCS_CETESM BSP_FLD32(14)
+
+/* field: CTTCC - Clear TTCC Register */
+#define TMS570_FLEX_RAY_GCS_CTTCC BSP_FLD32(13)
+
+/* field: CTTSM - Clear TTSM Register */
+#define TMS570_FLEX_RAY_GCS_CTTSM BSP_FLD32(12)
+
+/* field: ETSM - Enable Transfer Status Mirrored */
+#define TMS570_FLEX_RAY_GCS_ETSM BSP_FLD32(8)
+
+/* field: SILE - Status Interrupt Line Enable */
+#define TMS570_FLEX_RAY_GCS_SILE BSP_FLD32(5)
+
+/* field: EILE - Error Interrupt Line Enable */
+#define TMS570_FLEX_RAY_GCS_EILE BSP_FLD32(4)
+
+/* field: TUH - Transfer Unit Halted */
+#define TMS570_FLEX_RAY_GCS_TUH BSP_FLD32(1)
+
+/* field: TUE - Transfer Unit Enabled */
+#define TMS570_FLEX_RAY_GCS_TUE BSP_FLD32(0)
+
+
+/*---------------------TMS570_FLEX_RAYGCR---------------------*/
+/* field: ENDVBM - Endianness Correction on VBusp Master */
+#define TMS570_FLEX_RAY_GCR_ENDVBM BSP_FLD32(31)
+
+/* field: ENDVBS - Endianness correction on VBusp Slave */
+#define TMS570_FLEX_RAY_GCR_ENDVBS BSP_FLD32(30)
+
+/* field: ENDRx - Endianness Correction for No (header or payload) Data Sink Access */
+#define TMS570_FLEX_RAY_GCR_ENDRx(val) BSP_FLD32(val,28, 29)
+#define TMS570_FLEX_RAY_GCR_ENDRx_GET(reg) BSP_FLD32GET(reg,28, 29)
+#define TMS570_FLEX_RAY_GCR_ENDRx_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
+
+/* field: ENDHx - Endianness Correction for Header */
+#define TMS570_FLEX_RAY_GCR_ENDHx(val) BSP_FLD32(val,26, 27)
+#define TMS570_FLEX_RAY_GCR_ENDHx_GET(reg) BSP_FLD32GET(reg,26, 27)
+#define TMS570_FLEX_RAY_GCR_ENDHx_SET(reg,val) BSP_FLD32SET(reg, val,26, 27)
+
+/* field: ENDPx - Endianness Correction for Payload */
+#define TMS570_FLEX_RAY_GCR_ENDPx(val) BSP_FLD32(val,24, 25)
+#define TMS570_FLEX_RAY_GCR_ENDPx_GET(reg) BSP_FLD32GET(reg,24, 25)
+#define TMS570_FLEX_RAY_GCR_ENDPx_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
+
+/* field: PRIO - Transfer Priority */
+#define TMS570_FLEX_RAY_GCR_PRIO BSP_FLD32(21)
+
+/* field: PEFT - Parity for Test */
+#define TMS570_FLEX_RAY_GCR_PEFT BSP_FLD32(20)
+
+/* field: PELx - Parity Lock */
+#define TMS570_FLEX_RAY_GCR_PELx(val) BSP_FLD32(val,16, 19)
+#define TMS570_FLEX_RAY_GCR_PELx_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_FLEX_RAY_GCR_PELx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: CETESM - Clear ETESM Register */
+#define TMS570_FLEX_RAY_GCR_CETESM BSP_FLD32(14)
+
+/* field: CTTCC - Clear TTCC Register */
+#define TMS570_FLEX_RAY_GCR_CTTCC BSP_FLD32(13)
+
+/* field: CTTSM - Clear TTSM Register */
+#define TMS570_FLEX_RAY_GCR_CTTSM BSP_FLD32(12)
+
+/* field: ETSM - Enable Transfer Status Mirrored */
+#define TMS570_FLEX_RAY_GCR_ETSM BSP_FLD32(8)
+
+/* field: SILE - Status Interrupt Line Enable */
+#define TMS570_FLEX_RAY_GCR_SILE BSP_FLD32(5)
+
+/* field: EILE - Error Interrupt Line Enable */
+#define TMS570_FLEX_RAY_GCR_EILE BSP_FLD32(4)
+
+/* field: TUH - Transfer Unit Halted */
+#define TMS570_FLEX_RAY_GCR_TUH BSP_FLD32(1)
+
+/* field: TUE - Transfer Unit Enabled */
+#define TMS570_FLEX_RAY_GCR_TUE BSP_FLD32(0)
+
+
+/*--------------------TMS570_FLEX_RAYTSCB--------------------*/
+/* field: TSMS - Transfer State Machine Status */
+#define TMS570_FLEX_RAY_TSCB_TSMS(val) BSP_FLD32(val,16, 20)
+#define TMS570_FLEX_RAY_TSCB_TSMS_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_FLEX_RAY_TSCB_TSMS_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: STUH - Status of Transfer Unit State Machine for Halt Detection */
+#define TMS570_FLEX_RAY_TSCB_STUH BSP_FLD32(12)
+
+/* field: IDLE - Detects Transfer State Machine State IDLE */
+#define TMS570_FLEX_RAY_TSCB_IDLE BSP_FLD32(8)
+
+/* field: BN - Buffer Number */
+#define TMS570_FLEX_RAY_TSCB_BN(val) BSP_FLD32(val,0, 6)
+#define TMS570_FLEX_RAY_TSCB_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_FLEX_RAY_TSCB_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*--------------------TMS570_FLEX_RAYLTBCC--------------------*/
+/* field: BN - Buffer number. */
+#define TMS570_FLEX_RAY_LTBCC_BN(val) BSP_FLD32(val,0, 6)
+#define TMS570_FLEX_RAY_LTBCC_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_FLEX_RAY_LTBCC_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*--------------------TMS570_FLEX_RAYLTBSM--------------------*/
+/* field: BN - Buffer number. */
+#define TMS570_FLEX_RAY_LTBSM_BN(val) BSP_FLD32(val,0, 6)
+#define TMS570_FLEX_RAY_LTBSM_BN_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_FLEX_RAY_LTBSM_BN_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*---------------------TMS570_FLEX_RAYTBA---------------------*/
+/* field: TBA - Transfer Base Address. */
+#define TMS570_FLEX_RAY_TBA_TBA(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TBA_TBA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TBA_TBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYNTBA--------------------*/
+/* field: nTBA - nTBA(31-0) */
+#define TMS570_FLEX_RAY_NTBA_nTBA(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_NTBA_nTBA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_NTBA_nTBA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYBAMS--------------------*/
+/* field: BAMS - Base Address of Mirrored Status32-bit base pointer, 2 LSB are not significant (32-bit */
+#define TMS570_FLEX_RAY_BAMS_BAMS(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_BAMS_BAMS_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_BAMS_BAMS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYSAMP--------------------*/
+/* field: SAMP - Start Address Memory Protection. */
+#define TMS570_FLEX_RAY_SAMP_SAMP(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_SAMP_SAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_SAMP_SAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYEAMP--------------------*/
+/* field: EAMP - End Address Memory Protection. */
+#define TMS570_FLEX_RAY_EAMP_EAMP(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_EAMP_EAMP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_EAMP_EAMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTSMO1--------------------*/
+/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
+#define TMS570_FLEX_RAY_TSMO1_TSMO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMO1_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMO1_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTSMO2--------------------*/
+/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
+#define TMS570_FLEX_RAY_TSMO2_TSMO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMO2_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMO2_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTSMO3--------------------*/
+/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
+#define TMS570_FLEX_RAY_TSMO3_TSMO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMO3_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMO3_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTSMO4--------------------*/
+/* field: TSMO1 - Transfer to System Memory Occurred Register 1. */
+#define TMS570_FLEX_RAY_TSMO4_TSMO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMO4_TSMO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMO4_TSMO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTCCO1--------------------*/
+/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
+#define TMS570_FLEX_RAY_TCCO1_TCCO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCO1_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCO1_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTCCO2--------------------*/
+/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
+#define TMS570_FLEX_RAY_TCCO2_TCCO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCO2_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCO2_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTCCO3--------------------*/
+/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
+#define TMS570_FLEX_RAY_TCCO3_TCCO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCO3_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCO3_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTCCO4--------------------*/
+/* field: TCCO1 - Transfer to Communication Controller Occurred Register 1. */
+#define TMS570_FLEX_RAY_TCCO4_TCCO1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCO4_TCCO1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCO4_TCCO1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_FLEX_RAYTOOFF--------------------*/
+/* field: TDIR - Transfer Direction. */
+#define TMS570_FLEX_RAY_TOOFF_TDIR BSP_FLD32(8)
+
+/* field: OFF - Offset Vector */
+#define TMS570_FLEX_RAY_TOOFF_OFF(val) BSP_FLD32(val,0, 7)
+#define TMS570_FLEX_RAY_TOOFF_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_FLEX_RAY_TOOFF_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*--------------------TMS570_FLEX_RAYPEADR--------------------*/
+/* field: ADR - Address of failing TCR location. */
+#define TMS570_FLEX_RAY_PEADR_ADR(val) BSP_FLD32(val,0, 8)
+#define TMS570_FLEX_RAY_PEADR_ADR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_FLEX_RAY_PEADR_ADR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*--------------------TMS570_FLEX_RAYTEIF--------------------*/
+/* field: MPV - Memory Protection Violation. */
+#define TMS570_FLEX_RAY_TEIF_MPV BSP_FLD32(17)
+
+/* field: PE - Parity Error. The flag signals a parity error to the host. */
+#define TMS570_FLEX_RAY_TEIF_PE BSP_FLD32(16)
+
+/* field: RSTAT - Status of VBUS on read transfers. */
+#define TMS570_FLEX_RAY_TEIF_RSTAT(val) BSP_FLD32(val,8, 10)
+#define TMS570_FLEX_RAY_TEIF_RSTAT_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_FLEX_RAY_TEIF_RSTAT_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: WSTAT - Status of VBUS on write transfers. */
+#define TMS570_FLEX_RAY_TEIF_WSTAT(val) BSP_FLD32(val,4, 6)
+#define TMS570_FLEX_RAY_TEIF_WSTAT_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_FLEX_RAY_TEIF_WSTAT_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TNR - Transfer Not Ready. */
+#define TMS570_FLEX_RAY_TEIF_TNR BSP_FLD32(1)
+
+/* field: FAC - Forbidden Access. */
+#define TMS570_FLEX_RAY_TEIF_FAC BSP_FLD32(0)
+
+
+/*-------------------TMS570_FLEX_RAYTEIRES-------------------*/
+/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
+#define TMS570_FLEX_RAY_TEIRES_RSTATE(val) BSP_FLD32(val,8, 10)
+#define TMS570_FLEX_RAY_TEIRES_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_FLEX_RAY_TEIRES_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */
+#define TMS570_FLEX_RAY_TEIRES_WSTATE(val) BSP_FLD32(val,4, 6)
+#define TMS570_FLEX_RAY_TEIRES_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_FLEX_RAY_TEIRES_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TNRE - Transfer Not Ready Enable. */
+#define TMS570_FLEX_RAY_TEIRES_TNRE BSP_FLD32(1)
+
+/* field: FACE - Forbidden Access Enable. */
+#define TMS570_FLEX_RAY_TEIRES_FACE BSP_FLD32(0)
+
+
+/*-------------------TMS570_FLEX_RAYTEIRER-------------------*/
+/* field: RSTATE - Read Error Interrupt Generation (interrupt generation on VBUS read transfer errors). */
+#define TMS570_FLEX_RAY_TEIRER_RSTATE(val) BSP_FLD32(val,8, 10)
+#define TMS570_FLEX_RAY_TEIRER_RSTATE_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_FLEX_RAY_TEIRER_RSTATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: WSTATE - Write Error Interrupt Generation (interrupt generation on VBUS write transfer errors). */
+#define TMS570_FLEX_RAY_TEIRER_WSTATE(val) BSP_FLD32(val,4, 6)
+#define TMS570_FLEX_RAY_TEIRER_WSTATE_GET(reg) BSP_FLD32GET(reg,4, 6)
+#define TMS570_FLEX_RAY_TEIRER_WSTATE_SET(reg,val) BSP_FLD32SET(reg, val,4, 6)
+
+/* field: TNRE - Transfer Not Ready Enable. */
+#define TMS570_FLEX_RAY_TEIRER_TNRE BSP_FLD32(1)
+
+/* field: FACE - Forbidden Access Enable. */
+#define TMS570_FLEX_RAY_TEIRER_FACE BSP_FLD32(0)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMS1-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMS1_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMS1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMR1-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMR1_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMR1_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMS2-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMS2_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMS2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMR2-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMR2_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMR2_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMS3-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMS3_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMS3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMR3-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMR3_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMR3_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMS4-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMS4_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMS4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTSMR4-------------------*/
+/* field: TTSMS1 - Trigger Transfer to System Memory Set 1. */
+#define TMS570_FLEX_RAY_TTSMR4_TTSMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTSMR4_TTSMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCS1-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCS1_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCS1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCR1-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCR1_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCR1_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCS2-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCS2_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCS2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCR2-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCR2_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCR2_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCS3-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCS3_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCS3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCR3-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCR3_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCR3_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCS4-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCS4_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCS4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTTCCR4-------------------*/
+/* field: TTCCS1 - Trigger Transfer to Communication Controller Set 1. */
+#define TMS570_FLEX_RAY_TTCCR4_TTCCS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TTCCR4_TTCCS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMS1-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMS1_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMS1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMR1-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMR1_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMR1_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMS2-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMS2_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMS2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMR2-------------------*/
+/* field: ETESMS1 - message buffers 0 to 31. */
+#define TMS570_FLEX_RAY_ETESMR2_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMR2_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMS3-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMS3_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMS3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMR3-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMR3_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMR3_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMS4-------------------*/
+/* field: ETESMS1 - Enable Transfer on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_ETESMS4_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMS4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYETESMR4-------------------*/
+/* field: ETESMS1 - message buffers 0 to 31. */
+#define TMS570_FLEX_RAY_ETESMR4_ETESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_ETESMR4_ETESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMS1-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMS1_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMS1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMS1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMR1-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMR1_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMR1_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMR1_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMS2-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMS2_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMS2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMS2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMR2-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMR2_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMR2_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMR2_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMS3-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMS3_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMS3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMS3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMR3-------------------*/
+/* field: CESMS1 - CESMS1(31-0) */
+#define TMS570_FLEX_RAY_CESMR3_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMR3_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMR3_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMS4-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMS4_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMS4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMS4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYCESMR4-------------------*/
+/* field: CESMS1 - Clear on Event to System Memory Set 1. */
+#define TMS570_FLEX_RAY_CESMR4_CESMS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_CESMR4_CESMS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_CESMR4_CESMS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIES1-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIES1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIER1-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIER1_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIES2-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIES2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIER2-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIER2_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIES3-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIES3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIER3-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIER3_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIES4-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIES4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTSMIER4-------------------*/
+/* field: TTSMIES1 - Transfer to System Memory Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TSMIER4_TTSMIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIES1-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIES1_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIES1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIER1-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIER1_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIER1_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIES2-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIES2_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIES2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIER2-------------------*/
+/* field: TCCIES1 - to message buffers 0 to 31. */
+#define TMS570_FLEX_RAY_TCCIER2_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIER2_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIES3-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIES3_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIES3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIER3-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIER3_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIER3_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIES4-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIES4_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIES4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_FLEX_RAYTCCIER4-------------------*/
+/* field: TCCIES1 - Transfer to Communication Controller Interrupt Enable Set 1. */
+#define TMS570_FLEX_RAY_TCCIER4_TCCIES1(val) BSP_FLD32(val,0, 31)
+#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_FLEX_RAY_TCCIER4_TCCIES1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_FLEX_RAY */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
new file mode 100644
index 0000000..bc7c857
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_gio.h
@@ -0,0 +1,324 @@
+/* The header file is generated by make_header.py from GIO.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_GIO
+#define LIBBSP_ARM_tms570_GIO
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t DIR; /*GIO Data Direction Register*/
+ uint32_t DIN; /*GIO Data Input Register*/
+ uint32_t DOUT; /*GIO Data Output Register*/
+ uint32_t DSET; /*GIO Data Set Register*/
+ uint32_t DCLR; /*GIO Data Clear Register*/
+ uint32_t PDR; /*GIO Open Drain Register*/
+ uint32_t PULDIS; /*GIO Pull Disable Register*/
+ uint32_t PSL; /*GIO Pull Select Register*/
+} tms570_gio_port_t;
+
+typedef struct{
+ uint32_t GCR0; /*GIO Global Control Register*/
+ uint8_t reserved1 [4];
+ uint32_t INTDET; /*GIO Interrupt Detect Register*/
+ uint32_t POL; /*GIO Interrupt Polarity Register*/
+ uint32_t ENASET; /*GIO Interrupt Enable Set Register*/
+ uint32_t ENACLR; /*GIO Interrupt Enable Clear Register*/
+ uint32_t LVLSET; /*GIO Interrupt Priority Set Register*/
+ uint32_t LVLCLR; /*GIO Interrupt Priority Clear Register*/
+ uint32_t FLG; /*GIO Interrupt Flag Register*/
+ uint32_t OFF1; /*GIO Offset 1 Register*/
+ uint32_t OFF2; /*GIO Offset 2 Register*/
+ uint32_t EMU1; /*GIO Emulation 1 Register*/
+ uint32_t EMU2; /*GIO Emulation 2 Register*/
+ tms570_gio_port_t ports[8]; /*GIO ports*/
+} tms570_gio_t;
+
+
+/*-----------------------TMS570_GIODIR-----------------------*/
+/* field: GIODIR - GIO data direction, pins [7:0] */
+#define TMS570_GIO_DIR_GIODIR(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_DIR_GIODIR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_DIR_GIODIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIODIN-----------------------*/
+/* field: GIODIN - GIO data input, pins [7:0] */
+#define TMS570_GIO_DIN_GIODIN(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_DIN_GIODIN_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_DIN_GIODIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIODOUT-----------------------*/
+/* field: GIODOUT - IO data output, pins[7:0]. */
+#define TMS570_GIO_DOUT_GIODOUT(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_DOUT_GIODOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_DOUT_GIODOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIODSET-----------------------*/
+/* field: GIODSET - GIO data set, pins[7:0]. This bit drives the output of GIO pin high. */
+#define TMS570_GIO_DSET_GIODSET(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_DSET_GIODSET_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_DSET_GIODSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIODCLR-----------------------*/
+/* field: GIODCLR - GIO data clear, pins[7:0]. This bit drives the output of GIO pin low. */
+#define TMS570_GIO_DCLR_GIODCLR(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_DCLR_GIODCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_DCLR_GIODCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOPDR-----------------------*/
+/* field: 7_0 - GIOPDRH GIO open drain, pins[7:0] */
+#define TMS570_GIO_PDR_7_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_PDR_7_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_PDR_7_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_GIOPULDIS----------------------*/
+/* field: GIOPULDIS - GIO pull disable, pins[7:0]. */
+#define TMS570_GIO_PULDIS_GIOPULDIS(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_PULDIS_GIOPULDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_PULDIS_GIOPULDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOPSL-----------------------*/
+/* field: GIOPSL - GIO pull select, pins[7:0] */
+#define TMS570_GIO_PSL_GIOPSL(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_PSL_GIOPSL_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_PSL_GIOPSL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOGCR0-----------------------*/
+/* field: RESET - GIO reset. */
+#define TMS570_GIO_GCR0_RESET BSP_FLD32(0)
+
+
+/*----------------------TMS570_GIOINTDET----------------------*/
+/* field: GIOINTDET_3 - Interrupt detection select for pins GIOD[7:0] */
+#define TMS570_GIO_INTDET_GIOINTDET_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_INTDET_GIOINTDET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_INTDET_GIOINTDET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOINTDET_2 - Interrupt detection select for pins GIOC[7:0] */
+#define TMS570_GIO_INTDET_GIOINTDET_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_INTDET_GIOINTDET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_INTDET_GIOINTDET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOINTDET_1 - Interrupt detection select for pins GIOB[7:0] */
+#define TMS570_GIO_INTDET_GIOINTDET_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_INTDET_GIOINTDET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_INTDET_GIOINTDET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOINTDET_0 - Interrupt detection select for pins GIOA[7:0] */
+#define TMS570_GIO_INTDET_GIOINTDET_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_INTDET_GIOINTDET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_INTDET_GIOINTDET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOPOL-----------------------*/
+/* field: GIOPOL_3 - Interrupt polarity select for pins GIOD[7:0] */
+#define TMS570_GIO_POL_GIOPOL_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_POL_GIOPOL_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_POL_GIOPOL_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOPOL_2 - Interrupt polarity select for pins GIOC[7:0] */
+#define TMS570_GIO_POL_GIOPOL_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_POL_GIOPOL_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_POL_GIOPOL_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOPOL_1 - Interrupt polarity select for pins GIOB[7:0] */
+#define TMS570_GIO_POL_GIOPOL_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_POL_GIOPOL_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_POL_GIOPOL_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOPOL_0 - Interrupt polarity select for pins GIOA[7:0] */
+#define TMS570_GIO_POL_GIOPOL_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_POL_GIOPOL_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_POL_GIOPOL_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_GIOENASET----------------------*/
+/* field: GIOENASET_3 - nterrupt enable for pins GIOD[7:0] */
+#define TMS570_GIO_ENASET_GIOENASET_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_ENASET_GIOENASET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_ENASET_GIOENASET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOENASET_2 - Interrupt enable for pins GIOC[7:0] */
+#define TMS570_GIO_ENASET_GIOENASET_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_ENASET_GIOENASET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_ENASET_GIOENASET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOENASET_1 - Interrupt enable for pins GIOB[7:0] */
+#define TMS570_GIO_ENASET_GIOENASET_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_ENASET_GIOENASET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_ENASET_GIOENASET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOENASET_0 - Interrupt enable for pins GIOA[7:0] */
+#define TMS570_GIO_ENASET_GIOENASET_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_ENASET_GIOENASET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_ENASET_GIOENASET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_GIOENACLR----------------------*/
+/* field: GIOENACLR_3 - Interrupt enable for pins GIOD[7:0] */
+#define TMS570_GIO_ENACLR_GIOENACLR_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_ENACLR_GIOENACLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_ENACLR_GIOENACLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOENACLR_2 - Interrupt enable for pins GIOC[7:0] */
+#define TMS570_GIO_ENACLR_GIOENACLR_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_ENACLR_GIOENACLR_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_ENACLR_GIOENACLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOENACLR_1 - Interrupt enable for pins GIOB[7:0] */
+#define TMS570_GIO_ENACLR_GIOENACLR_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_ENACLR_GIOENACLR_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_ENACLR_GIOENACLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOENACLR_0 - Interrupt enable for pins GIOA[7:0] */
+#define TMS570_GIO_ENACLR_GIOENACLR_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_ENACLR_GIOENACLR_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_ENACLR_GIOENACLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_GIOLVLSET----------------------*/
+/* field: GIOLVLSET_3 - GIO high priority interrupt for pins GIOD[7:0]. */
+#define TMS570_GIO_LVLSET_GIOLVLSET_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_LVLSET_GIOLVLSET_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_LVLSET_GIOLVLSET_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOLVLSET_2 - GIO high priority interrupt for pins GIOC[7:0]. */
+#define TMS570_GIO_LVLSET_GIOLVLSET_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_LVLSET_GIOLVLSET_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_LVLSET_GIOLVLSET_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOLVLSET_1 - GIO high priority interrupt for pins GIOB[7:0]. */
+#define TMS570_GIO_LVLSET_GIOLVLSET_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_LVLSET_GIOLVLSET_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_LVLSET_GIOLVLSET_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOLVLSET_0 - GIO high priority interrupt for pins GIOA[7:0]. */
+#define TMS570_GIO_LVLSET_GIOLVLSET_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_LVLSET_GIOLVLSET_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_LVLSET_GIOLVLSET_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_GIOLVLCLR----------------------*/
+/* field: GIOLVLCLR_3 - GIO low priority interrupt for pins GIOD[7:0] */
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOLVLCLR_2 - GIO low priority interrupt for pins GIOC[7:0] */
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOLVLCLR_1 - GIO low priority interrupt for pins GIOB[7:0] */
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOLVLCLR_0 - GIO low priority interrupt for pins GIOA[7:0] */
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_LVLCLR_GIOLVLCLR_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOFLG-----------------------*/
+/* field: GIOFLG_3 - GIO flag for pins GIOD[7:0]. */
+#define TMS570_GIO_FLG_GIOFLG_3(val) BSP_FLD32(val,24, 31)
+#define TMS570_GIO_FLG_GIOFLG_3_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_GIO_FLG_GIOFLG_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: GIOFLG_2 - GIO flag for pins GIOC[7:0]. */
+#define TMS570_GIO_FLG_GIOFLG_2(val) BSP_FLD32(val,16, 23)
+#define TMS570_GIO_FLG_GIOFLG_2_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_GIO_FLG_GIOFLG_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: GIOFLG_1 - GIO flag for pins GIOB[7:0]. */
+#define TMS570_GIO_FLG_GIOFLG_1(val) BSP_FLD32(val,8, 15)
+#define TMS570_GIO_FLG_GIOFLG_1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_GIO_FLG_GIOFLG_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: GIOFLG_0 - GIO flag for pins GIOA[7:0]. */
+#define TMS570_GIO_FLG_GIOFLG_0(val) BSP_FLD32(val,0, 7)
+#define TMS570_GIO_FLG_GIOFLG_0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_GIO_FLG_GIOFLG_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_GIOOFF1-----------------------*/
+/* field: GIOOFF1 - GIO offset 1. These bits index the currently pending high-priority interrupt. */
+#define TMS570_GIO_OFF1_GIOOFF1(val) BSP_FLD32(val,0, 5)
+#define TMS570_GIO_OFF1_GIOOFF1_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_GIO_OFF1_GIOOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------------TMS570_GIOOFF2-----------------------*/
+/* field: GIOOFF2 - GIO offset 2. These bits index the currently pending low-priority interrupt. */
+#define TMS570_GIO_OFF2_GIOOFF2(val) BSP_FLD32(val,0, 5)
+#define TMS570_GIO_OFF2_GIOOFF2_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_GIO_OFF2_GIOOFF2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------------TMS570_GIOEMU1-----------------------*/
+/* field: GIOEMU1 - GIO offset emulation 1. These bits index the currently pending high-priority interrupt. */
+#define TMS570_GIO_EMU1_GIOEMU1(val) BSP_FLD32(val,0, 5)
+#define TMS570_GIO_EMU1_GIOEMU1_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_GIO_EMU1_GIOEMU1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------------TMS570_GIOEMU2-----------------------*/
+/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
+#define TMS570_GIO_EMU2_GIOEMU2(val) BSP_FLD32(val,0, 5)
+#define TMS570_GIO_EMU2_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_GIO_EMU2_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*----------------------TMS570_GIOports----------------------*/
+/* field: GIOEMU2 - GIO offset emulation 2. These bits index the currently pending low-priority interrupt. */
+#define TMS570_GIO_ports_GIOEMU2(val) BSP_FLD32(val,0, 5)
+#define TMS570_GIO_ports_GIOEMU2_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_GIO_ports_GIOEMU2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+
+#endif /* LIBBSP_ARM_tms570_GIO */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
new file mode 100644
index 0000000..f033303
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_htu.h
@@ -0,0 +1,351 @@
+/* The header file is generated by make_header.py from HTU.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_HTU
+#define LIBBSP_ARM_tms570_HTU
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GC; /*Global Control Register*/
+ uint32_t CPENA; /*Control Packet Enable Register*/
+ uint32_t BUSY0; /*Control Packet Busy Register 0*/
+ uint32_t BUSY1; /*Control Packet Busy Register 1*/
+ uint32_t BUSY2; /*Control Packet Busy Register 2*/
+ uint32_t BUSY3; /*Control Packet Busy Register 3*/
+ uint32_t ACPE; /*Active Control Packet and Error Register*/
+ uint8_t reserved1 [4];
+ uint32_t RLBECTRL; /*Request Lost and Bus Error Control Register*/
+ uint32_t BFINTS; /*Buffer Full Interrupt Enable Set Register*/
+ uint32_t BFINTC; /*Buffer Full Interrupt Enable Clear Register*/
+ uint8_t reserved2 [8];
+ uint32_t INTOFF0; /*Interrupt Offset Register 0*/
+ uint32_t INTOFF1; /*Interrupt Offset Register 1*/
+ uint32_t BIM; /*Buffer Initialization Mode Register*/
+ uint32_t RLOSTFL; /*Request Lost Flag Register*/
+ uint32_t BFINTFL; /*Buffer Full Interrupt Flag Register*/
+ uint32_t BERINTFL; /*BER Interrupt Flag Register*/
+ uint32_t MP1S; /*Memory Protection 1 Start Address Register*/
+ uint32_t MP1E; /*Memory Protection 1 End Address Register*/
+ uint32_t DCTRL; /*Debug Control Register*/
+ uint32_t WPR; /*Watch Point Register*/
+ uint32_t WMR; /*Watch Mask Register*/
+ uint32_t ID; /*Module Identification Register*/
+ uint32_t PCR; /*Parity Control Register*/
+ uint32_t PAR; /*Parity Address Register*/
+ uint8_t reserved3 [4];
+ uint32_t MPCS; /*Memory Protection Control and Status Register*/
+ uint32_t MP0S; /*Memory Protection 0 Start Address Register*/
+ uint32_t MP0E; /*Memory Protection 0 End Address Register*/
+} tms570_htu_t;
+
+
+/*------------------------TMS570_HTUGC------------------------*/
+/* field: VBUSHOLD - Hold the VBUS bus */
+#define TMS570_HTU_GC_VBUSHOLD BSP_FLD32(24)
+
+/* field: HTUEN - Transfer Unit Enable Bit */
+#define TMS570_HTU_GC_HTUEN BSP_FLD32(16)
+
+/* field: DEBM - Debug Mode */
+#define TMS570_HTU_GC_DEBM BSP_FLD32(8)
+
+/* field: HTURES - HTU Software Reset Request */
+#define TMS570_HTU_GC_HTURES BSP_FLD32(0)
+
+
+/*----------------------TMS570_HTUCPENA----------------------*/
+/* field: CPENA - CP Enable Bits */
+#define TMS570_HTU_CPENA_CPENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_CPENA_CPENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_CPENA_CPENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_HTUBUSY0----------------------*/
+/* field: BUSY0A - Busy Flag for CP A of DCP 0 */
+#define TMS570_HTU_BUSY0_BUSY0A BSP_FLD32(24)
+
+/* field: BUSY0B - Busy Flag for CP B of DCP 0 */
+#define TMS570_HTU_BUSY0_BUSY0B BSP_FLD32(16)
+
+/* field: BUSY1A - Busy Flag for CP A of DCP 1 */
+#define TMS570_HTU_BUSY0_BUSY1A BSP_FLD32(8)
+
+/* field: BUSY1B - Busy Flag for CP B of DCP 1 */
+#define TMS570_HTU_BUSY0_BUSY1B BSP_FLD32(0)
+
+
+/*----------------------TMS570_HTUBUSY1----------------------*/
+/* field: BUSY2A - Busy Flag for CP A of DCP 2 */
+#define TMS570_HTU_BUSY1_BUSY2A BSP_FLD32(24)
+
+/* field: BUSY2B - Busy Flag for CP B of DCP 2 */
+#define TMS570_HTU_BUSY1_BUSY2B BSP_FLD32(16)
+
+/* field: BUSY3A - Busy Flag for CP A of DCP 3 */
+#define TMS570_HTU_BUSY1_BUSY3A BSP_FLD32(8)
+
+/* field: BUSY3B - Busy Flag for CP B of DCP 3 */
+#define TMS570_HTU_BUSY1_BUSY3B BSP_FLD32(0)
+
+
+/*----------------------TMS570_HTUBUSY2----------------------*/
+/* field: BUSY4A - Busy Flag for CP A of DCP 4 */
+#define TMS570_HTU_BUSY2_BUSY4A BSP_FLD32(24)
+
+/* field: BUSY4B - Busy Flag for CP B of DCP 4 */
+#define TMS570_HTU_BUSY2_BUSY4B BSP_FLD32(16)
+
+/* field: BUSY5A - Busy Flag for CP A of DCP 5 */
+#define TMS570_HTU_BUSY2_BUSY5A BSP_FLD32(8)
+
+/* field: BUSY5B - Busy Flag for CP B of DCP 5 */
+#define TMS570_HTU_BUSY2_BUSY5B BSP_FLD32(0)
+
+
+/*----------------------TMS570_HTUBUSY3----------------------*/
+/* field: BUSY6A - Busy Flag for CP A of DCP 6 */
+#define TMS570_HTU_BUSY3_BUSY6A BSP_FLD32(24)
+
+/* field: BUSY6B - Busy Flag for CP B of DCP 6 */
+#define TMS570_HTU_BUSY3_BUSY6B BSP_FLD32(16)
+
+/* field: BUSY7A - Busy Flag for CP A of DCP 7 */
+#define TMS570_HTU_BUSY3_BUSY7A BSP_FLD32(8)
+
+/* field: BUSY7B - Busy Flag for CP B of DCP 7 */
+#define TMS570_HTU_BUSY3_BUSY7B BSP_FLD32(0)
+
+
+/*-----------------------TMS570_HTUACPE-----------------------*/
+/* field: ERRF - Error Flag */
+#define TMS570_HTU_ACPE_ERRF BSP_FLD32(31)
+
+
+/*---------------------TMS570_HTURLBECTRL---------------------*/
+/* field: BERINTENA - Bus Error Interrupt Enable Bit */
+#define TMS570_HTU_RLBECTRL_BERINTENA BSP_FLD32(16)
+
+/* field: CORL - Continue On Request Lost Error */
+#define TMS570_HTU_RLBECTRL_CORL BSP_FLD32(8)
+
+/* field: RLINTENA - Request Lost Interrupt Enable Bit */
+#define TMS570_HTU_RLBECTRL_RLINTENA BSP_FLD32(0)
+
+
+/*----------------------TMS570_HTUBFINTS----------------------*/
+/* field: BFINTENA - Bus Full Interrupt Enable Bits. */
+#define TMS570_HTU_BFINTS_BFINTENA(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_BFINTS_BFINTENA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_BFINTS_BFINTENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_HTUBFINTC----------------------*/
+/* field: BFINTDIS - */
+#define TMS570_HTU_BFINTC_BFINTDIS(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_BFINTC_BFINTDIS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_BFINTC_BFINTDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_HTUINTOFF0---------------------*/
+/* field: INTTYPE0 - Interrupt Type of Interrupt Line 0. */
+#define TMS570_HTU_INTOFF0_INTTYPE0(val) BSP_FLD32(val,8, 10)
+#define TMS570_HTU_INTOFF0_INTTYPE0_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_HTU_INTOFF0_INTTYPE0_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CPOFF0 - CP Offset. */
+#define TMS570_HTU_INTOFF0_CPOFF0(val) BSP_FLD32(val,0, 4)
+#define TMS570_HTU_INTOFF0_CPOFF0_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_HTU_INTOFF0_CPOFF0_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*---------------------TMS570_HTUINTOFF1---------------------*/
+/* field: INTTYPE1 - INTTYPE1 Interrupt Type of Interrupt Line 1. */
+#define TMS570_HTU_INTOFF1_INTTYPE1(val) BSP_FLD32(val,8, 10)
+#define TMS570_HTU_INTOFF1_INTTYPE1_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_HTU_INTOFF1_INTTYPE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CPOFF1 - CP Offset. */
+#define TMS570_HTU_INTOFF1_CPOFF1(val) BSP_FLD32(val,0, 4)
+#define TMS570_HTU_INTOFF1_CPOFF1_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_HTU_INTOFF1_CPOFF1_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*-----------------------TMS570_HTUBIM-----------------------*/
+/* field: BIM - Buffer Initialization Mode */
+#define TMS570_HTU_BIM_BIM(val) BSP_FLD32(val,0, 7)
+#define TMS570_HTU_BIM_BIM_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_HTU_BIM_BIM_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_HTURLOSTFL---------------------*/
+/* field: CPRLFL - CP Request Lost Flags */
+#define TMS570_HTU_RLOSTFL_CPRLFL(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_RLOSTFL_CPRLFL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_RLOSTFL_CPRLFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_HTUBFINTFL---------------------*/
+/* field: BFINTFL - Buffer Full Interrupt Flags */
+#define TMS570_HTU_BFINTFL_BFINTFL(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_BFINTFL_BFINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_BFINTFL_BFINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_HTUBERINTFL---------------------*/
+/* field: BERINTFL - Bus Error Interrupt Flags */
+#define TMS570_HTU_BERINTFL_BERINTFL(val) BSP_FLD32(val,0, 15)
+#define TMS570_HTU_BERINTFL_BERINTFL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_HTU_BERINTFL_BERINTFL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_HTUMP1S-----------------------*/
+/* field: STARTADDRESS1 - he start address defines at which main memory address the region begins. */
+#define TMS570_HTU_MP1S_STARTADDRESS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_MP1S_STARTADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_MP1S_STARTADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_HTUMP1E-----------------------*/
+/* field: ENDADDRESS1 - The end address defines at which address the region ends. */
+#define TMS570_HTU_MP1E_ENDADDRESS1(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_MP1E_ENDADDRESS1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_MP1E_ENDADDRESS1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_HTUDCTRL----------------------*/
+/* field: CPNUM - CP Number. These bit fields indicate the CP which should cause the watch point to match. */
+#define TMS570_HTU_DCTRL_CPNUM(val) BSP_FLD32(val,24, 27)
+#define TMS570_HTU_DCTRL_CPNUM_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_HTU_DCTRL_CPNUM_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: HTUDBGS - HTU Debug Status. */
+#define TMS570_HTU_DCTRL_HTUDBGS BSP_FLD32(16)
+
+/* field: DBREN - Debug Request Enable */
+#define TMS570_HTU_DCTRL_DBREN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_HTUWPR-----------------------*/
+/* field: WP - Watch Point Register */
+#define TMS570_HTU_WPR_WP(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_WPR_WP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_WPR_WP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_HTUWMR-----------------------*/
+/* field: WM - Watch Mask Register */
+#define TMS570_HTU_WMR_WM(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_WMR_WM_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_WMR_WM_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------------TMS570_HTUID------------------------*/
+/* field: CLASS - Module Class */
+#define TMS570_HTU_ID_CLASS(val) BSP_FLD32(val,16, 23)
+#define TMS570_HTU_ID_CLASS_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_HTU_ID_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TYPE - Subtype within a Class */
+#define TMS570_HTU_ID_TYPE(val) BSP_FLD32(val,8, 15)
+#define TMS570_HTU_ID_TYPE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_HTU_ID_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: REV - Module Revision Number */
+#define TMS570_HTU_ID_REV(val) BSP_FLD32(val,0, 7)
+#define TMS570_HTU_ID_REV_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_HTU_ID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_HTUPCR-----------------------*/
+/* field: COPE - Continue on Parity Error */
+#define TMS570_HTU_PCR_COPE BSP_FLD32(16)
+
+/* field: TEST - Test. */
+#define TMS570_HTU_PCR_TEST BSP_FLD32(8)
+
+/* field: PARITY_ENA - Enable/Disable Parity Checking. */
+#define TMS570_HTU_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_HTU_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_HTU_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_HTUPAR-----------------------*/
+/* field: PEFT - Parity Error Fault Flag. */
+#define TMS570_HTU_PAR_PEFT BSP_FLD32(16)
+
+/* field: PAOFF - PAOFF */
+#define TMS570_HTU_PAR_PAOFF(val) BSP_FLD32(val,0, 8)
+#define TMS570_HTU_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_HTU_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*-----------------------TMS570_HTUMPCS-----------------------*/
+/* field: CPNUM0 - Control Packet Number for single memory protection region configuration. */
+#define TMS570_HTU_MPCS_CPNUM0(val) BSP_FLD32(val,24, 27)
+#define TMS570_HTU_MPCS_CPNUM0_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_HTU_MPCS_CPNUM0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: MPEFT1 - MPEFT1 */
+#define TMS570_HTU_MPCS_MPEFT1 BSP_FLD32(17)
+
+/* field: MPEFT0 - Memory Protection Error Fault Flag 0. */
+#define TMS570_HTU_MPCS_MPEFT0 BSP_FLD32(16)
+
+/* field: CPNUM1 - Control Packet Number for single memory protection region configuration. */
+#define TMS570_HTU_MPCS_CPNUM1(val) BSP_FLD32(val,8, 11)
+#define TMS570_HTU_MPCS_CPNUM1_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_HTU_MPCS_CPNUM1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+
+/*-----------------------TMS570_HTUMP0S-----------------------*/
+/* field: ISTARTADDRESS0 - The start address defines at which main memory address the region begins. */
+#define TMS570_HTU_MP0S_ISTARTADDRESS0(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_MP0S_ISTARTADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_MP0S_ISTARTADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_HTUMP0E-----------------------*/
+/* field: ENDADDRESS0 - The end address defines at which address the region ends. */
+#define TMS570_HTU_MP0E_ENDADDRESS0(val) BSP_FLD32(val,0, 31)
+#define TMS570_HTU_MP0E_ENDADDRESS0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_HTU_MP0E_ENDADDRESS0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_HTU */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
new file mode 100644
index 0000000..c4441ca
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_i2c.h
@@ -0,0 +1,363 @@
+/* The header file is generated by make_header.py from I2C.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_I2C
+#define LIBBSP_ARM_tms570_I2C
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t OAR; /*I2C Own Address Manager*/
+ uint32_t IMR; /*I2C Interupt Mask Register*/
+ uint32_t STR; /*I2C Status Register*/
+ uint32_t CKL; /*I2C Clock Divider Low Register*/
+ uint32_t CKH; /*I2C Clock Control High Register*/
+ uint32_t CNT; /*I2C Data Count Register*/
+ uint32_t DRR; /*I2C Data Receive Register*/
+ uint32_t SAR; /*I2C Slave Address Register*/
+ uint32_t DXR; /*I2C Data Transmit Register*/
+ uint32_t MDR; /*I2C Mode Register*/
+ uint32_t IVR; /*I2C Interrupt Vector Register*/
+ uint32_t EMDR; /*I2C Extended Mode Register*/
+ uint32_t PSC; /*I2C Prescale Register*/
+ uint32_t PID11; /*I2C Peripheral ID Register 1*/
+ uint32_t PID12; /*I2C Peripheral ID Register 2*/
+ uint32_t DMACR; /*I2C DMA Control Register*/
+ uint8_t reserved1 [8];
+ uint32_t PFNC; /*I2C Pin Function Register*/
+ uint32_t DIR; /*I2C Pin Direction Register*/
+ uint32_t DIN; /*I2C Data Input Register*/
+ uint32_t DOUT; /*I2C Data Output Register*/
+ uint32_t SET; /*I2C Data Set Register*/
+ uint32_t CLR; /*I2C Data Clear Register*/
+ uint32_t PDR; /*I2C Pin Open Drain Register*/
+ uint32_t PDIS; /*I2C Pull Disable Register*/
+ uint32_t PSEL; /*I2C Pull Select Register*/
+ uint32_t pSRS; /*I2C Pins Slew Rate Select Register*/
+} tms570_i2c_t;
+
+
+/*-----------------------TMS570_I2COAR-----------------------*/
+/* field: OA - Own address */
+#define TMS570_I2C_OAR_OA(val) BSP_FLD32(val,0, 9)
+#define TMS570_I2C_OAR_OA_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_I2C_OAR_OA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*-----------------------TMS570_I2CIMR-----------------------*/
+/* field: AASEN - Address As Slave Interrupt Enable */
+#define TMS570_I2C_IMR_AASEN BSP_FLD32(6)
+
+/* field: SCDEN - Stop Condition Interrupt Enable */
+#define TMS570_I2C_IMR_SCDEN BSP_FLD32(5)
+
+/* field: TXRDYEN - Transmit Data Ready Interrupt Enable */
+#define TMS570_I2C_IMR_TXRDYEN BSP_FLD32(4)
+
+/* field: RXRDYEN - Receive Data Ready Interrupt Enable */
+#define TMS570_I2C_IMR_RXRDYEN BSP_FLD32(3)
+
+/* field: ARDYEN - Register Access Ready Interrupt Enable */
+#define TMS570_I2C_IMR_ARDYEN BSP_FLD32(2)
+
+/* field: NACKEN - No Acknowledgement Interrupt Enable */
+#define TMS570_I2C_IMR_NACKEN BSP_FLD32(1)
+
+/* field: ALEN - Arbitration Lost Interrupt Enable */
+#define TMS570_I2C_IMR_ALEN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CSTR-----------------------*/
+/* field: SDIR - Slave direction */
+#define TMS570_I2C_STR_SDIR BSP_FLD32(14)
+
+/* field: NACKSNT - No acknowledge sent */
+#define TMS570_I2C_STR_NACKSNT BSP_FLD32(13)
+
+/* field: BB - Bus busy */
+#define TMS570_I2C_STR_BB BSP_FLD32(12)
+
+/* field: RSFULL - Receiver shift full */
+#define TMS570_I2C_STR_RSFULL BSP_FLD32(11)
+
+/* field: XSMT - XSMT */
+#define TMS570_I2C_STR_XSMT BSP_FLD32(10)
+
+/* field: AAS - Address as slave */
+#define TMS570_I2C_STR_AAS BSP_FLD32(9)
+
+/* field: AD0 - Address zero status */
+#define TMS570_I2C_STR_AD0 BSP_FLD32(8)
+
+/* field: SCD - SCD */
+#define TMS570_I2C_STR_SCD BSP_FLD32(5)
+
+/* field: TXRDY - Transmit data ready interrupt flag */
+#define TMS570_I2C_STR_TXRDY BSP_FLD32(4)
+
+/* field: RXRDY - Receive data ready interrupt flag */
+#define TMS570_I2C_STR_RXRDY BSP_FLD32(3)
+
+/* field: ARDY - Register access ready interrupt flag */
+#define TMS570_I2C_STR_ARDY BSP_FLD32(2)
+
+/* field: NACK - No acknowledgement interrupt */
+#define TMS570_I2C_STR_NACK BSP_FLD32(1)
+
+/* field: AL - Arbitration lost interrupt flag */
+#define TMS570_I2C_STR_AL BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CCKL-----------------------*/
+/* field: CLKL - Low time clock division factor */
+#define TMS570_I2C_CKL_CLKL(val) BSP_FLD32(val,0, 15)
+#define TMS570_I2C_CKL_CLKL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_I2C_CKL_CLKL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_I2CCKH-----------------------*/
+/* field: CLKH - High time clock division factor */
+#define TMS570_I2C_CKH_CLKH(val) BSP_FLD32(val,0, 15)
+#define TMS570_I2C_CKH_CLKH_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_I2C_CKH_CLKH_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_I2CCNT-----------------------*/
+/* field: CNT - Data counter */
+#define TMS570_I2C_CNT_CNT(val) BSP_FLD32(val,0, 15)
+#define TMS570_I2C_CNT_CNT_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_I2C_CNT_CNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_I2CDRR-----------------------*/
+/* field: DATARX - Receive data */
+#define TMS570_I2C_DRR_DATARX(val) BSP_FLD32(val,0, 7)
+#define TMS570_I2C_DRR_DATARX_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_I2C_DRR_DATARX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_I2CSAR-----------------------*/
+/* field: SA - 7- or 10-bit programmable slave address */
+#define TMS570_I2C_SAR_SA(val) BSP_FLD32(val,0, 9)
+#define TMS570_I2C_SAR_SA_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_I2C_SAR_SA_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*-----------------------TMS570_I2CDXR-----------------------*/
+/* field: DATATX - Transmit data */
+#define TMS570_I2C_DXR_DATATX(val) BSP_FLD32(val,0, 7)
+#define TMS570_I2C_DXR_DATATX_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_I2C_DXR_DATATX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_I2CMDR-----------------------*/
+/* field: NACKMOD - No-acknowledge (NACK) mode */
+#define TMS570_I2C_MDR_NACKMOD BSP_FLD32(15)
+
+/* field: FREE - Free running bit */
+#define TMS570_I2C_MDR_FREE BSP_FLD32(14)
+
+/* field: STT - Start condition */
+#define TMS570_I2C_MDR_STT BSP_FLD32(13)
+
+/* field: STP - Stop condition */
+#define TMS570_I2C_MDR_STP BSP_FLD32(11)
+
+/* field: MST - Master/slave mode bit */
+#define TMS570_I2C_MDR_MST BSP_FLD32(10)
+
+/* field: TRX - Transmit/receive bit */
+#define TMS570_I2C_MDR_TRX BSP_FLD32(9)
+
+/* field: XA - Expand address enable bit */
+#define TMS570_I2C_MDR_XA BSP_FLD32(8)
+
+/* field: RM - RM */
+#define TMS570_I2C_MDR_RM BSP_FLD32(7)
+
+/* field: DLB - Digital loop back enable bit */
+#define TMS570_I2C_MDR_DLB BSP_FLD32(6)
+
+/* field: nIRS - I2C reset enable bit */
+#define TMS570_I2C_MDR_nIRS BSP_FLD32(5)
+
+/* field: STB - Start byte mode enable bit (Master mode only) */
+#define TMS570_I2C_MDR_STB BSP_FLD32(4)
+
+/* field: FDF - Free data format enable bit */
+#define TMS570_I2C_MDR_FDF BSP_FLD32(3)
+
+/* field: BC - Bit count */
+#define TMS570_I2C_MDR_BC(val) BSP_FLD32(val,0, 2)
+#define TMS570_I2C_MDR_BC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_I2C_MDR_BC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_I2CIVR-----------------------*/
+/* field: TESTMD - Reserved for internal testing. */
+#define TMS570_I2C_IVR_TESTMD(val) BSP_FLD32(val,8, 11)
+#define TMS570_I2C_IVR_TESTMD_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_I2C_IVR_TESTMD_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: INTCODE - Interrupt Code Bits */
+#define TMS570_I2C_IVR_INTCODE(val) BSP_FLD32(val,0, 2)
+#define TMS570_I2C_IVR_INTCODE_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_I2C_IVR_INTCODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_I2CEMDR-----------------------*/
+/* field: IGNACK - Ignore NACK mode */
+#define TMS570_I2C_EMDR_IGNACK BSP_FLD32(1)
+
+/* field: BCM - Backwards compatibility mode */
+#define TMS570_I2C_EMDR_BCM BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CPSC-----------------------*/
+/* field: PSC - Prescale */
+#define TMS570_I2C_PSC_PSC(val) BSP_FLD32(val,0, 7)
+#define TMS570_I2C_PSC_PSC_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_I2C_PSC_PSC_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_I2CPID11----------------------*/
+/* field: CLASS - Peripheral class */
+#define TMS570_I2C_PID11_CLASS(val) BSP_FLD32(val,8, 15)
+#define TMS570_I2C_PID11_CLASS_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_I2C_PID11_CLASS_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: REVISION - Revision level of the I2C */
+#define TMS570_I2C_PID11_REVISION(val) BSP_FLD32(val,0, 7)
+#define TMS570_I2C_PID11_REVISION_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_I2C_PID11_REVISION_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_I2CPID12----------------------*/
+/* field: TYPE - Peripheral type */
+#define TMS570_I2C_PID12_TYPE(val) BSP_FLD32(val,0, 7)
+#define TMS570_I2C_PID12_TYPE_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_I2C_PID12_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_I2CDMACR----------------------*/
+/* field: TXDMAEN - Transmitter DMA enable */
+#define TMS570_I2C_DMACR_TXDMAEN BSP_FLD32(1)
+
+/* field: RXDMAEN - Receive DMA enable */
+#define TMS570_I2C_DMACR_RXDMAEN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CPFNC-----------------------*/
+/* field: PINFUNC - SDA and SCL Pin Function */
+#define TMS570_I2C_PFNC_PINFUNC BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CDIR-----------------------*/
+/* field: SDADIR - SDA direction */
+#define TMS570_I2C_DIR_SDADIR BSP_FLD32(1)
+
+/* field: SCLDIR - SCL direction */
+#define TMS570_I2C_DIR_SCLDIR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CDIN-----------------------*/
+/* field: SDAIN - Serial data in */
+#define TMS570_I2C_DIN_SDAIN BSP_FLD32(1)
+
+/* field: SCLIN - Serial clock data in */
+#define TMS570_I2C_DIN_SCLIN BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CDOUT-----------------------*/
+/* field: SDAOUT - SDA Data Output */
+#define TMS570_I2C_DOUT_SDAOUT BSP_FLD32(1)
+
+/* field: SCLOUT - SCL Data Output */
+#define TMS570_I2C_DOUT_SCLOUT BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CSET-----------------------*/
+/* field: SDASET - Serial Data Set */
+#define TMS570_I2C_SET_SDASET BSP_FLD32(1)
+
+/* field: SCLSET - Serial Clock Set */
+#define TMS570_I2C_SET_SCLSET BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CCLR-----------------------*/
+/* field: SDACLR - Serial Data Clear */
+#define TMS570_I2C_CLR_SDACLR BSP_FLD32(1)
+
+/* field: SCLCLR - Serial Clock Clear */
+#define TMS570_I2C_CLR_SCLCLR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CPDR-----------------------*/
+/* field: SDAPDR - SDA pin open drain enable */
+#define TMS570_I2C_PDR_SDAPDR BSP_FLD32(1)
+
+/* field: SCLPDR - SCL pin open drain enable */
+#define TMS570_I2C_PDR_SCLPDR BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CPDIS-----------------------*/
+/* field: SDAPDIS - SDA pull disable */
+#define TMS570_I2C_PDIS_SDAPDIS BSP_FLD32(1)
+
+/* field: SCLPDIS - SCL pull disable */
+#define TMS570_I2C_PDIS_SCLPDIS BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CPSEL-----------------------*/
+/* field: SDAPSEL - SDA pull select */
+#define TMS570_I2C_PSEL_SDAPSEL BSP_FLD32(1)
+
+/* field: SCLPSEL - SCL pull select */
+#define TMS570_I2C_PSEL_SCLPSEL BSP_FLD32(0)
+
+
+/*-----------------------TMS570_I2CpSRS-----------------------*/
+/* field: SDASRS - SDA Slew Rate select */
+#define TMS570_I2C_pSRS_SDASRS BSP_FLD32(1)
+
+/* field: SCLSRS - SCL Slew Rate select */
+#define TMS570_I2C_pSRS_SCLSRS BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_I2C */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
new file mode 100644
index 0000000..8a8c05f
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_iomm.h
@@ -0,0 +1,244 @@
+/* The header file is generated by make_header.py from IOMM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_IOMM
+#define LIBBSP_ARM_tms570_IOMM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PINMMR0; /*Pin Multiplexing Control Register 0*/
+ uint32_t PINMMR1; /*Pin Multiplexing Control Register 1*/
+ uint32_t PINMMR2; /*Pin Multiplexing Control Register 2*/
+ uint32_t PINMMR3; /*Pin Multiplexing Control Register 3*/
+ uint32_t PINMMR4; /*Pin Multiplexing Control Register 4*/
+ uint32_t PINMMR5; /*Pin Multiplexing Control Register 5*/
+ uint32_t PINMMR6; /*Pin Multiplexing Control Register 6*/
+ uint32_t PINMMR7; /*Pin Multiplexing Control Register 7*/
+ uint32_t PINMMR8; /*Pin Multiplexing Control Register 8*/
+ uint32_t PINMMR9; /*Pin Multiplexing Control Register 9*/
+ uint32_t PINMMR10; /*Pin Multiplexing Control Register 10*/
+ uint32_t PINMMR11; /*Pin Multiplexing Control Register 11*/
+ uint32_t PINMMR12; /*Pin Multiplexing Control Register 12*/
+ uint32_t PINMMR13; /*Pin Multiplexing Control Register 13*/
+ uint32_t PINMMR14; /*Pin Multiplexing Control Register 14*/
+ uint32_t PINMMR15; /*Pin Multiplexing Control Register 15*/
+ uint32_t PINMMR16; /*Pin Multiplexing Control Register 16*/
+ uint32_t PINMMR17; /*Pin Multiplexing Control Register 17*/
+ uint32_t PINMMR18; /*Pin Multiplexing Control Register 18*/
+ uint32_t PINMMR19; /*Pin Multiplexing Control Register 19*/
+ uint32_t PINMMR20; /*Pin Multiplexing Control Register 20*/
+ uint32_t PINMMR21; /*Pin Multiplexing Control Register 21*/
+ uint32_t PINMMR22; /*Pin Multiplexing Control Register 22*/
+ uint32_t PINMMR23; /*Pin Multiplexing Control Register 23*/
+ uint32_t PINMMR24; /*Pin Multiplexing Control Register 24*/
+ uint32_t PINMMR25; /*Pin Multiplexing Control Register 25*/
+ uint32_t PINMMR26; /*Pin Multiplexing Control Register 26*/
+ uint32_t PINMMR27; /*Pin Multiplexing Control Register 27*/
+ uint32_t PINMMR28; /*Pin Multiplexing Control Register 28*/
+ uint32_t PINMMR29; /*Pin Multiplexing Control Register 29*/
+ uint32_t PINMMR30; /*Pin Multiplexing Control Register 30*/
+} tms570_pinmux_t;
+
+typedef struct{
+ uint32_t REVISION_REG; /*Revision Register*/
+ uint8_t reserved1 [28];
+ uint32_t ENDIAN_REG; /*Device Endianness Register*/
+ uint8_t reserved2 [20];
+ uint32_t KICK_REG0; /*Kicker Register 0*/
+ uint32_t KICK_REG1; /*Kicker Register 1*/
+ uint8_t reserved3 [160];
+ uint32_t ERR_RAW_STATUS_REG;/*Error Raw Status / Set Register*/
+ uint32_t ERR_ENABLED_STATUS_REG;/*Error Enabled Status / Clear Register*/
+ uint32_t ERR_ENABLE_REG; /*Error Signaling Enable Register*/
+ uint32_t ERR_ENABLE_CLR_REG;/*Error Signaling Enable Clear Register*/
+ uint8_t reserved4 [4];
+ uint32_t FAULT_ADDRESS_REG; /*Fault Address Register*/
+ uint32_t FAULT_STATUS_REG; /*Fault Status Register*/
+ uint32_t FAULT_CLEAR_REG; /*Fault Clear Register*/
+ uint8_t reserved5 [16];
+ tms570_pinmux_t PINMUX; /*Pin Multiplexing Control Registers*/
+} tms570_iomm_t;
+
+
+/*---------------------TMS570_IOMMPINMMR0---------------------*/
+/* field: PINMMRx24To31 - Each of these byte-fields control the functionality on a given ball/pin. */
+#define TMS570_IOMM_PINMMR0_PINMMRx24To31(val) BSP_FLD32(val,24, 31)
+#define TMS570_IOMM_PINMMR0_PINMMRx24To31_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_IOMM_PINMMR0_PINMMRx24To31_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: PINMMRx16To23 - Each of these byte-fields control the functionality on a given ball/pin. */
+#define TMS570_IOMM_PINMMR0_PINMMRx16To23(val) BSP_FLD32(val,16, 23)
+#define TMS570_IOMM_PINMMR0_PINMMRx16To23_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_IOMM_PINMMR0_PINMMRx16To23_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: PINMMRx8To16 - Each of these byte-fields control the functionality on a given ball/pin. */
+#define TMS570_IOMM_PINMMR0_PINMMRx8To16(val) BSP_FLD32(val,8, 15)
+#define TMS570_IOMM_PINMMR0_PINMMRx8To16_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_IOMM_PINMMR0_PINMMRx8To16_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: PINMMRx0To7 - Each of these byte-fields control the functionality on a given ball/pin. */
+#define TMS570_IOMM_PINMMR0_PINMMRx0To7(val) BSP_FLD32(val,0, 7)
+#define TMS570_IOMM_PINMMR0_PINMMRx0To7_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_IOMM_PINMMR0_PINMMRx0To7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_IOMMREVISION_REG------------------*/
+/* field: REV_SCHEME - Revision Scheme */
+#define TMS570_IOMM_REVISION_REG_REV_SCHEME(val) BSP_FLD32(val,30, 31)
+#define TMS570_IOMM_REVISION_REG_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
+#define TMS570_IOMM_REVISION_REG_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
+
+/* field: REV_MODULE - Module Id */
+#define TMS570_IOMM_REVISION_REG_REV_MODULE(val) BSP_FLD32(val,16, 27)
+#define TMS570_IOMM_REVISION_REG_REV_MODULE_GET(reg) BSP_FLD32GET(reg,16, 27)
+#define TMS570_IOMM_REVISION_REG_REV_MODULE_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
+
+/* field: REV_RTL - RTL Revision */
+#define TMS570_IOMM_REVISION_REG_REV_RTL(val) BSP_FLD32(val,11, 15)
+#define TMS570_IOMM_REVISION_REG_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
+#define TMS570_IOMM_REVISION_REG_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
+
+/* field: REV_MAJOR - Major Revision */
+#define TMS570_IOMM_REVISION_REG_REV_MAJOR(val) BSP_FLD32(val,8, 10)
+#define TMS570_IOMM_REVISION_REG_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_IOMM_REVISION_REG_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: REV_CUSTOM - REV CUSTOM 0 Custom Revision */
+#define TMS570_IOMM_REVISION_REG_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
+#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_IOMM_REVISION_REG_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: REV_MINOR - Minor Revision */
+#define TMS570_IOMM_REVISION_REG_REV_MINOR(val) BSP_FLD32(val,0, 5)
+#define TMS570_IOMM_REVISION_REG_REV_MINOR_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_IOMM_REVISION_REG_REV_MINOR_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-------------------TMS570_IOMMENDIAN_REG-------------------*/
+/* field: ENDIAN - Device endianness */
+#define TMS570_IOMM_ENDIAN_REG_ENDIAN BSP_FLD32(0)
+
+
+/*--------------------TMS570_IOMMKICK_REG0--------------------*/
+/* field: KICK0 - Kicker 0 Register. */
+#define TMS570_IOMM_KICK_REG0_KICK0(val) BSP_FLD32(val,0, 31)
+#define TMS570_IOMM_KICK_REG0_KICK0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_IOMM_KICK_REG0_KICK0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_IOMMKICK_REG1--------------------*/
+/* field: KICK1 - Kicker 1 Register. */
+#define TMS570_IOMM_KICK_REG1_KICK1(val) BSP_FLD32(val,0, 31)
+#define TMS570_IOMM_KICK_REG1_KICK1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_IOMM_KICK_REG1_KICK1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------TMS570_IOMMERR_RAW_STATUS_REG---------------*/
+/* field: ADDR_ERR - Addressing Error Status and Error Signaling Enable. */
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_ADDR_ERR BSP_FLD32(1)
+
+/* field: PROT_ERR - register inside the IOMM is written in the CPU's user mode of operation. */
+#define TMS570_IOMM_ERR_RAW_STATUS_REG_PROT_ERR BSP_FLD32(0)
+
+
+/*-------------TMS570_IOMMERR_ENABLED_STATUS_REG-------------*/
+/* field: ENABLED_ADDR_ERR - Addressing Error Signaling Enable Status and Status Clear */
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_ADDR_ERR BSP_FLD32(1)
+
+/* field: ENABLED_PROT_ERR - Protection Error Signaling Enable Status and Status Clear */
+#define TMS570_IOMM_ERR_ENABLED_STATUS_REG_ENABLED_PROT_ERR BSP_FLD32(0)
+
+
+/*-----------------TMS570_IOMMERR_ENABLE_REG-----------------*/
+/* field: ADDR_ERR_EN - Addressing Error Signaling Enable */
+#define TMS570_IOMM_ERR_ENABLE_REG_ADDR_ERR_EN BSP_FLD32(1)
+
+/* field: PROT_ERR_EN - Protection ErrorSignaling Enable */
+#define TMS570_IOMM_ERR_ENABLE_REG_PROT_ERR_EN BSP_FLD32(0)
+
+
+/*---------------TMS570_IOMMERR_ENABLE_CLR_REG---------------*/
+/* field: ADDR_ERR_EN_CLR - Addressing Error Signaling Enable Clear */
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_ADDR_ERR_EN_CLR BSP_FLD32(1)
+
+/* field: PROT_ERR_EN_CLR - Protection Error Signaling Enable Clear */
+#define TMS570_IOMM_ERR_ENABLE_CLR_REG_PROT_ERR_EN_CLR BSP_FLD32(0)
+
+
+/*----------------TMS570_IOMMFAULT_ADDRESS_REG----------------*/
+/* field: FAULT_ADDR - Fault Address. */
+#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR(val) BSP_FLD32(val,0, 31)
+#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_IOMM_FAULT_ADDRESS_REG_FAULT_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------TMS570_IOMMFAULT_STATUS_REG----------------*/
+/* field: FAULT_ID - Faulting Transaction ID */
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID(val) BSP_FLD32(val,24, 27)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_ID_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: FAULT_MSTID - ID of Master that initiated the faulting transaction */
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID(val) BSP_FLD32(val,16, 23)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_MSTID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: FAULT_PRIVID - Faulting Privilege ID */
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID(val) BSP_FLD32(val,9, 12)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_GET(reg) BSP_FLD32GET(reg,9, 12)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_PRIVID_SET(reg,val) BSP_FLD32SET(reg, val,9, 12)
+
+/* field: FAULT_TYPE - Type of fault detected */
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE(val) BSP_FLD32(val,0, 5)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_IOMM_FAULT_STATUS_REG_FAULT_TYPE_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*-----------------TMS570_IOMMFAULT_CLEAR_REG-----------------*/
+/* field: FAULT_CLEAR - Fault Clear */
+#define TMS570_IOMM_FAULT_CLEAR_REG_FAULT_CLEAR BSP_FLD32(0)
+
+
+/*---------------------TMS570_IOMMPINMUX---------------------*/
+/* field: FAULT_CLEAR - Fault Clear */
+#define TMS570_IOMM_PINMUX_FAULT_CLEAR BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_IOMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
new file mode 100644
index 0000000..2729b33
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_lin.h
@@ -0,0 +1,594 @@
+/* The header file is generated by make_header.py from LIN.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_LIN
+#define LIBBSP_ARM_tms570_LIN
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GCR0; /*SCI Global Control Register 0*/
+ uint32_t GCR1; /*SCI Global Control Register 1*/
+ uint32_t GCR2; /*SCI Global Control Register 2*/
+ uint32_t SETINT; /*SCI Set Interrupt Register*/
+ uint32_t CLEARINT; /*SCI Clear Interrupt Register*/
+ uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/
+ uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/
+ uint32_t FLR; /*SCI Flags Register*/
+ uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/
+ uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/
+ uint32_t FORMAT; /*SCI Format Control Register*/
+ uint32_t BRS; /*Baud Rate Selection Register*/
+ uint32_t ED; /*Receiver Emulation Data Buffer*/
+ uint32_t RD; /*Receiver Data Buffer*/
+ uint32_t TD; /*Transmit Data Buffer*/
+ uint32_t PIO0; /*SCI Pin I/O Control Register 0*/
+ uint32_t PIO1; /*SCI Pin I/O Control Register 1*/
+ uint32_t PIO2; /*SCI Pin I/O Control Register 2*/
+ uint32_t PIO3; /*SCI Pin I/O Control Register 3*/
+ uint32_t PIO4; /*SCI Pin I/O Control Register 4*/
+ uint32_t PIO5; /*SCI Pin I/O Control Register 5*/
+ uint32_t PIO6; /*SCI Pin I/O Control Register 6*/
+ uint32_t PIO7; /*SCI Pin I/O Control Register 7*/
+ uint32_t PIO8; /*SCI Pin I/O Control Register 8*/
+ uint32_t COMP; /*LIN Compare Register*/
+ uint32_t RD0; /*LIN Receive Buffer 0 Register*/
+ uint32_t RD1; /*LIN Receive Buffer 1 Register*/
+ uint32_t MASK; /*LIN Mask Register*/
+ uint32_t ID; /*LIN Identification Register*/
+ uint32_t TD0; /*LIN Transmit Buffer 0*/
+ uint32_t TD1; /*LIN Transmit Buffer 1*/
+ uint32_t MBRSR; /*Maximum Baud Rate Selection Register*/
+ uint8_t reserved1 [16];
+ uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/
+} tms570_lin_t;
+
+
+/*-----------------------TMS570_LINGCR0-----------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_LIN_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
+#define TMS570_LIN_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
+#define TMS570_LIN_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
+
+/* field: RESET - This bit resets the SCI module. */
+#define TMS570_LIN_GCR0_RESET BSP_FLD32(0)
+
+
+/*-----------------------TMS570_LINGCR1-----------------------*/
+/* field: TXENA - Transmit enable. */
+#define TMS570_LIN_GCR1_TXENA BSP_FLD32(25)
+
+/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
+#define TMS570_LIN_GCR1_RXENA BSP_FLD32(24)
+
+/* field: CONT - Continue on suspend. */
+#define TMS570_LIN_GCR1_CONT BSP_FLD32(17)
+
+/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
+#define TMS570_LIN_GCR1_LOOP_BACK BSP_FLD32(16)
+
+/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
+#define TMS570_LIN_GCR1_POWERDOWN BSP_FLD32(9)
+
+/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
+#define TMS570_LIN_GCR1_SLEEP BSP_FLD32(8)
+
+/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
+#define TMS570_LIN_GCR1_SWnRST BSP_FLD32(7)
+
+/* field: CLOCK - CLOCK */
+#define TMS570_LIN_GCR1_CLOCK BSP_FLD32(5)
+
+/* field: STOP - SCI number of stop bits per frame. */
+#define TMS570_LIN_GCR1_STOP BSP_FLD32(4)
+
+/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
+#define TMS570_LIN_GCR1_PARITY BSP_FLD32(3)
+
+/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
+#define TMS570_LIN_GCR1_PARITY_ENA BSP_FLD32(2)
+
+/* field: TIMING_MODE - SCI timing mode bit. */
+#define TMS570_LIN_GCR1_TIMING_MODE BSP_FLD32(1)
+
+/* field: COMM_MODE - SCI communication mode bit. */
+#define TMS570_LIN_GCR1_COMM_MODE BSP_FLD32(0)
+
+
+/*-----------------------TMS570_LINGCR2-----------------------*/
+/* field: CC - Compare checksum. LIN mode only. */
+#define TMS570_LIN_GCR2_CC BSP_FLD32(17)
+
+/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
+#define TMS570_LIN_GCR2_SC BSP_FLD32(16)
+
+/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
+#define TMS570_LIN_GCR2_GEN_WU BSP_FLD32(8)
+
+/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
+#define TMS570_LIN_GCR2_POWERDOWN BSP_FLD32(0)
+
+
+/*----------------------TMS570_LINSETINT----------------------*/
+/* field: SET_FE_INT - */
+#define TMS570_LIN_SETINT_SET_FE_INT BSP_FLD32(26)
+
+/* field: SET_OE_INT - SET OE INT */
+#define TMS570_LIN_SETINT_SET_OE_INT BSP_FLD32(25)
+
+/* field: SET_PE_INT - Set parity interrupt. */
+#define TMS570_LIN_SETINT_SET_PE_INT BSP_FLD32(24)
+
+/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
+#define TMS570_LIN_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+
+/* field: SET_RX_DMA - SET RX DMA */
+#define TMS570_LIN_SETINT_SET_RX_DMA BSP_FLD32(17)
+
+/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
+#define TMS570_LIN_SETINT_SET_TX_DMA BSP_FLD32(16)
+
+/* field: SET_RX_INT - SET RX INT */
+#define TMS570_LIN_SETINT_SET_RX_INT BSP_FLD32(9)
+
+/* field: SET_TX_INT - Set transmitter interrupt. */
+#define TMS570_LIN_SETINT_SET_TX_INT BSP_FLD32(8)
+
+/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
+#define TMS570_LIN_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+
+/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
+#define TMS570_LIN_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+
+
+/*---------------------TMS570_LINCLEARINT---------------------*/
+/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+
+/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+
+/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+
+/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+
+/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
+#define TMS570_LIN_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+
+/* field: CLR_TX_DMA - CLR TX DMA */
+#define TMS570_LIN_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+
+/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+
+/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+
+/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+
+/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
+#define TMS570_LIN_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+
+
+/*--------------------TMS570_LINSETINTLVL--------------------*/
+/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+
+/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+
+/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+
+/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
+#define TMS570_LIN_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+
+/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+
+/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+
+/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
+#define TMS570_LIN_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+
+/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
+#define TMS570_LIN_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+
+
+/*-------------------TMS570_LINCLEARINTLVL-------------------*/
+/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
+#define TMS570_LIN_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+
+/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+
+/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
+#define TMS570_LIN_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+
+/* field: CLR_PE_INT_LVL - */
+#define TMS570_LIN_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+
+/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+
+/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
+#define TMS570_LIN_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+
+/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
+#define TMS570_LIN_CLEARINTLVL_8 BSP_FLD32(8)
+
+/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
+#define TMS570_LIN_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+
+/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
+#define TMS570_LIN_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+
+
+/*-----------------------TMS570_LINFLR-----------------------*/
+/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
+#define TMS570_LIN_FLR_FE BSP_FLD32(26)
+
+/* field: OE - Overrun error flag. */
+#define TMS570_LIN_FLR_OE BSP_FLD32(25)
+
+/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
+#define TMS570_LIN_FLR_PE BSP_FLD32(24)
+
+/* field: RXWAKE - Receiver wakeup detect flag. */
+#define TMS570_LIN_FLR_RXWAKE BSP_FLD32(12)
+
+/* field: TX_EMPTY - Transmitter empty flag. */
+#define TMS570_LIN_FLR_TX_EMPTY BSP_FLD32(11)
+
+/* field: TXWAKE - Transmitter wakeup method select. */
+#define TMS570_LIN_FLR_TXWAKE BSP_FLD32(10)
+
+/* field: RXRDY - Receiver ready flag. */
+#define TMS570_LIN_FLR_RXRDY BSP_FLD32(9)
+
+/* field: TXRDY - Transmitter buffer register ready flag. */
+#define TMS570_LIN_FLR_TXRDY BSP_FLD32(8)
+
+/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
+#define TMS570_LIN_FLR_BUSY BSP_FLD32(3)
+
+/* field: IDLE - SCI receiver in idle state. */
+#define TMS570_LIN_FLR_IDLE BSP_FLD32(2)
+
+/* field: WAKEUP - Wakeup flag. */
+#define TMS570_LIN_FLR_WAKEUP BSP_FLD32(1)
+
+/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
+#define TMS570_LIN_FLR_BRKDT BSP_FLD32(0)
+
+
+/*---------------------TMS570_LININTVECT0---------------------*/
+/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
+#define TMS570_LIN_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
+#define TMS570_LIN_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_LIN_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_LININTVECT1---------------------*/
+/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
+#define TMS570_LIN_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
+#define TMS570_LIN_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_LIN_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_LINFORMAT----------------------*/
+/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
+#define TMS570_LIN_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
+#define TMS570_LIN_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_LIN_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_LINBRS-----------------------*/
+/* field: BAUD - SCI 24-bit baud selection. */
+#define TMS570_LIN_BRS_BAUD(val) BSP_FLD32(val,0, 23)
+#define TMS570_LIN_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_LIN_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*------------------------TMS570_LINED------------------------*/
+/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
+#define TMS570_LIN_ED_ED(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------------TMS570_LINRD------------------------*/
+/* field: RD - Receiver data. */
+#define TMS570_LIN_RD_RD(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------------TMS570_LINTD------------------------*/
+/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
+#define TMS570_LIN_TD_TD(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_LINPIO0-----------------------*/
+/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
+#define TMS570_LIN_PIO0_TX_FUNC BSP_FLD32(2)
+
+/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
+#define TMS570_LIN_PIO0_RX_FUNC BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO1-----------------------*/
+/* field: TX_DIR - Transmit pin direction. */
+#define TMS570_LIN_PIO1_TX_DIR BSP_FLD32(2)
+
+/* field: RX_DIR - Receive pin direction. */
+#define TMS570_LIN_PIO1_RX_DIR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO2-----------------------*/
+/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
+#define TMS570_LIN_PIO2_TX_IN BSP_FLD32(2)
+
+/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
+#define TMS570_LIN_PIO2_RX_IN BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO3-----------------------*/
+/* field: TX_OUT - Transmit pin out. */
+#define TMS570_LIN_PIO3_TX_OUT BSP_FLD32(2)
+
+/* field: RX_OUT - Receive pin out. */
+#define TMS570_LIN_PIO3_RX_OUT BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO4-----------------------*/
+/* field: TX_SET - Transmit pin set. */
+#define TMS570_LIN_PIO4_TX_SET BSP_FLD32(2)
+
+/* field: RX_SET - Receive pin set. */
+#define TMS570_LIN_PIO4_RX_SET BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO5-----------------------*/
+/* field: TX_CLR - Transmit pin clear. */
+#define TMS570_LIN_PIO5_TX_CLR BSP_FLD32(2)
+
+/* field: RX_CLR - Receive pin clear. */
+#define TMS570_LIN_PIO5_RX_CLR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO6-----------------------*/
+/* field: TX_PDR - Transmit pin open drain enable. */
+#define TMS570_LIN_PIO6_TX_PDR BSP_FLD32(2)
+
+/* field: RX_PDR - Receive pin open drain enable. */
+#define TMS570_LIN_PIO6_RX_PDR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO7-----------------------*/
+/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
+#define TMS570_LIN_PIO7_TX_PD BSP_FLD32(2)
+
+/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
+#define TMS570_LIN_PIO7_RX_PD BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINPIO8-----------------------*/
+/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
+#define TMS570_LIN_PIO8_TX_PSL BSP_FLD32(2)
+
+/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
+#define TMS570_LIN_PIO8_RX_PSL BSP_FLD32(1)
+
+
+/*-----------------------TMS570_LINCOMP-----------------------*/
+/* field: SDEL - 2-bit synch delimiter compare. These bits are effective in LIN mode only. */
+#define TMS570_LIN_COMP_SDEL(val) BSP_FLD32(val,8, 9)
+#define TMS570_LIN_COMP_SDEL_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_LIN_COMP_SDEL_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: SBREAK - Synch break extend. These bits are effective in LIN mode only. */
+#define TMS570_LIN_COMP_SBREAK(val) BSP_FLD32(val,0, 2)
+#define TMS570_LIN_COMP_SBREAK_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_LIN_COMP_SBREAK_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_LINRD0-----------------------*/
+/* field: RD0 - Receive buffer 0. Byte 0 of the response data byte. */
+#define TMS570_LIN_RD0_RD0(val) BSP_FLD32(val,24, 31)
+#define TMS570_LIN_RD0_RD0_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_LIN_RD0_RD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: RD1 - Receive buffer 1. Byte 1 of the response data byte. */
+#define TMS570_LIN_RD0_RD1(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_RD0_RD1_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_RD0_RD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: RD2 - Receive buffer 2. Byte 2 of the response data byte. */
+#define TMS570_LIN_RD0_RD2(val) BSP_FLD32(val,8, 15)
+#define TMS570_LIN_RD0_RD2_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_LIN_RD0_RD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: RD3 - Receive buffer 3. Byte 3 of the response data byte. */
+#define TMS570_LIN_RD0_RD3(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_RD0_RD3_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_RD0_RD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_LINRD1-----------------------*/
+/* field: RD4 - Receive buffer 4. Byte 4 of the response data byte. */
+#define TMS570_LIN_RD1_RD4(val) BSP_FLD32(val,24, 31)
+#define TMS570_LIN_RD1_RD4_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_LIN_RD1_RD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: RD5 - Receive buffer 5. Byte 5 of the response data byte. */
+#define TMS570_LIN_RD1_RD5(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_RD1_RD5_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_RD1_RD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: RD6 - Receive buffer 6. Byte 6 of the response data byte. */
+#define TMS570_LIN_RD1_RD6(val) BSP_FLD32(val,8, 15)
+#define TMS570_LIN_RD1_RD6_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_LIN_RD1_RD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: RD7 - Receive buffer 7. Byte 7 of the response data byte. */
+#define TMS570_LIN_RD1_RD7(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_RD1_RD7_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_RD1_RD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_LINMASK-----------------------*/
+/* field: RX_ID_MASK - Receive ID mask. These bits are effective in LIN mode only. */
+#define TMS570_LIN_MASK_RX_ID_MASK(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_MASK_RX_ID_MASK_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_MASK_RX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TX_ID_MASK - Transmit ID mask. These bits are effective in LIN mode only. */
+#define TMS570_LIN_MASK_TX_ID_MASK(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_MASK_TX_ID_MASK_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_MASK_TX_ID_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------------TMS570_LINID------------------------*/
+/* field: RECEIVED_ID - Received identification. These bits are effective in LIN mode only. */
+#define TMS570_LIN_ID_RECEIVED_ID(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_ID_RECEIVED_ID_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_ID_RECEIVED_ID_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: ID_SLAVETASK_BYTE - ID-SlaveTask Byte. These bits are effective in LIN mode only. */
+#define TMS570_LIN_ID_ID_SLAVETASK_BYTE(val) BSP_FLD32(val,8, 15)
+#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_LIN_ID_ID_SLAVETASK_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: ID_BYTE - ID byte. This field is effective in LIN mode only. This byte is the LIN mode message ID. */
+#define TMS570_LIN_ID_ID_BYTE(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_ID_ID_BYTE_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_ID_ID_BYTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_LINTD0-----------------------*/
+/* field: TD0 - 8-Bit transmit buffer 0. */
+#define TMS570_LIN_TD0_TD0(val) BSP_FLD32(val,24, 31)
+#define TMS570_LIN_TD0_TD0_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_LIN_TD0_TD0_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: TD1 - 8-Bit transmit buffer 1. */
+#define TMS570_LIN_TD0_TD1(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_TD0_TD1_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_TD0_TD1_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TD2 - 8-Bit transmit buffer 2. */
+#define TMS570_LIN_TD0_TD2(val) BSP_FLD32(val,8, 15)
+#define TMS570_LIN_TD0_TD2_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_LIN_TD0_TD2_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: TD3 - 8-Bit transmit buffer 3. */
+#define TMS570_LIN_TD0_TD3(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_TD0_TD3_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_TD0_TD3_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_LINTD1-----------------------*/
+/* field: TD4 - 8-Bit transmit buffer 4. */
+#define TMS570_LIN_TD1_TD4(val) BSP_FLD32(val,24, 31)
+#define TMS570_LIN_TD1_TD4_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_LIN_TD1_TD4_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: TD5 - 8-Bit transmit buffer 5. */
+#define TMS570_LIN_TD1_TD5(val) BSP_FLD32(val,16, 23)
+#define TMS570_LIN_TD1_TD5_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_LIN_TD1_TD5_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TD6 - 8-Bit transmit buffer 6. */
+#define TMS570_LIN_TD1_TD6(val) BSP_FLD32(val,8, 15)
+#define TMS570_LIN_TD1_TD6_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_LIN_TD1_TD6_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: TD7 - 8-Bit transmit buffer 7. */
+#define TMS570_LIN_TD1_TD7(val) BSP_FLD32(val,0, 7)
+#define TMS570_LIN_TD1_TD7_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_LIN_TD1_TD7_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_LINMBRSR----------------------*/
+/* field: MBR - Maximum baud rate prescaler. This bit is effective in LIN mode only. */
+#define TMS570_LIN_MBRSR_MBR(val) BSP_FLD32(val,0, 12)
+#define TMS570_LIN_MBRSR_MBR_GET(reg) BSP_FLD32GET(reg,0, 12)
+#define TMS570_LIN_MBRSR_MBR_SET(reg,val) BSP_FLD32SET(reg, val,0, 12)
+
+
+/*--------------------TMS570_LINIODFTCTRL--------------------*/
+/* field: FEN - Frame error enable. This bit is used to create a frame error. */
+#define TMS570_LIN_IODFTCTRL_FEN BSP_FLD32(26)
+
+/* field: PEN - Parity error enable. This bit is used to create a parity error. */
+#define TMS570_LIN_IODFTCTRL_PEN BSP_FLD32(25)
+
+/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
+#define TMS570_LIN_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+
+/* field: PIN_SAMPLE_MASK - Pin sample mask. */
+#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
+#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20)
+#define TMS570_LIN_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20)
+
+/* field: TX_SHIFT - Transmit shift. */
+#define TMS570_LIN_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18)
+#define TMS570_LIN_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_LIN_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */
+#define TMS570_LIN_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11)
+#define TMS570_LIN_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_LIN_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
+#define TMS570_LIN_IODFTCTRL_LPBENA BSP_FLD32(1)
+
+/* field: RXPENA - Module analog loopback through receive pin enable. */
+#define TMS570_LIN_IODFTCTRL_RXPENA BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_LIN */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
new file mode 100644
index 0000000..33ae386
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_mdio.h
@@ -0,0 +1,239 @@
+/* The header file is generated by make_header.py from MDIO.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_MDIO
+#define LIBBSP_ARM_tms570_MDIO
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t REVID; /*MDIO Revision ID Register*/
+ uint32_t CONTROL; /*MDIO Control Register*/
+ uint32_t ALIVE; /*PHY Alive Status register*/
+ uint32_t LINK; /*PHY Link Status Register*/
+ uint32_t LINKINTRAW; /*MDIO Link Status Change Interrupt (Unmasked) Register*/
+ uint32_t LINKINTMASKED; /*MDIO Link Status Change Interrupt (Masked) Register*/
+ uint8_t reserved1 [8];
+ uint32_t USERINTRAW; /*MDIO User Command Complete Interrupt (Unmasked) Register*/
+ uint32_t USERINTMASKED; /*MDIO User Command Complete Interrupt (Masked) Register*/
+ uint32_t USERINTMASKSET; /*MDIO User Command Complete Interrupt Mask Set Register*/
+ uint32_t USERINTMASKCLEAR; /*MDIO User Command Complete Interrupt Mask Clear Register*/
+ uint8_t reserved2 [80];
+ uint32_t USERACCESS0; /*MDIO User Access Register 0*/
+ uint32_t USERPHYSEL0; /*MDIO User PHY Select Register 0*/
+ uint32_t USERACCESS1; /*MDIO User Access Register 1*/
+ uint32_t USERPHYSEL1; /*MDIO User PHY Select Register 1*/
+} tms570_mdio_t;
+
+
+/*----------------------TMS570_MDIOREVID----------------------*/
+/* field: REV - Identifies the MDIO Module revision. */
+#define TMS570_MDIO_REVID_REV(val) BSP_FLD32(val,0, 31)
+#define TMS570_MDIO_REVID_REV_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_MDIO_REVID_REV_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_MDIOCONTROL---------------------*/
+/* field: IDLE - State machine IDLE status bit. */
+#define TMS570_MDIO_CONTROL_IDLE BSP_FLD32(31)
+
+/* field: ENABLE - State machine enable control bit. */
+#define TMS570_MDIO_CONTROL_ENABLE BSP_FLD32(30)
+
+/* field: HIGHEST_USER_CHANNEL - Highest user channel that is available in the module. It is currently set to 1. */
+#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(val) BSP_FLD32(val,24, 28)
+#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: PREAMBLE - Preamble disable */
+#define TMS570_MDIO_CONTROL_PREAMBLE BSP_FLD32(20)
+
+/* field: FAULT - Fault indicator. */
+#define TMS570_MDIO_CONTROL_FAULT BSP_FLD32(19)
+
+/* field: FAULTENB - Fault detect enable. */
+#define TMS570_MDIO_CONTROL_FAULTENB BSP_FLD32(18)
+
+/* field: CLKDIV - Clock Divider bits. */
+#define TMS570_MDIO_CONTROL_CLKDIV(val) BSP_FLD32(val,0, 15)
+#define TMS570_MDIO_CONTROL_CLKDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_MDIO_CONTROL_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_MDIOALIVE----------------------*/
+/* field: ALIVE - MDIO Alive bits. */
+#define TMS570_MDIO_ALIVE_ALIVE(val) BSP_FLD32(val,0, 31)
+#define TMS570_MDIO_ALIVE_ALIVE_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_MDIO_ALIVE_ALIVE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_MDIOLINK----------------------*/
+/* field: LINK - MDIO Link state bits. This register is updated after a read of the generic status register of a PHY. */
+#define TMS570_MDIO_LINK_LINK(val) BSP_FLD32(val,0, 31)
+#define TMS570_MDIO_LINK_LINK_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_MDIO_LINK_LINK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_MDIOLINKINTRAW-------------------*/
+/* field: USERPHY1 - MDIO Link change event, raw value. */
+#define TMS570_MDIO_LINKINTRAW_USERPHY1 BSP_FLD32(1)
+
+/* field: USERPHY0 - MDIO Link change event, raw value. */
+#define TMS570_MDIO_LINKINTRAW_USERPHY0 BSP_FLD32(0)
+
+
+/*------------------TMS570_MDIOLINKINTMASKED------------------*/
+/* field: USERPHY1 - MDIO Link change interrupt, masked value. */
+#define TMS570_MDIO_LINKINTMASKED_USERPHY1 BSP_FLD32(1)
+
+/* field: USERPHY0 - MDIO Link change interrupt, masked value. */
+#define TMS570_MDIO_LINKINTMASKED_USERPHY0 BSP_FLD32(0)
+
+
+/*-------------------TMS570_MDIOUSERINTRAW-------------------*/
+/* field: USERACCESS1 - MDIO User command complete event bit. */
+#define TMS570_MDIO_USERINTRAW_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO User command complete event bit. */
+#define TMS570_MDIO_USERINTRAW_USERACCESS0 BSP_FLD32(0)
+
+
+/*------------------TMS570_MDIOUSERINTMASKED------------------*/
+/* field: USERACCESS1 - Masked value of MDIO User command complete interrupt. */
+#define TMS570_MDIO_USERINTMASKED_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - Masked value of MDIO User command complete interrupt. */
+#define TMS570_MDIO_USERINTMASKED_USERACCESS0 BSP_FLD32(0)
+
+
+/*-----------------TMS570_MDIOUSERINTMASKSET-----------------*/
+/* field: USERACCESS1 - MDIO user interrupt mask set for USERINTMASKED[1]. */
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO user interrupt mask set for USERINTMASKED[0]. */
+#define TMS570_MDIO_USERINTMASKSET_USERACCESS0 BSP_FLD32(0)
+
+
+/*----------------TMS570_MDIOUSERINTMASKCLEAR----------------*/
+/* field: USERACCESS1 - MDIO user command complete interrupt mask clear for USERINTMASKED[1]. */
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS1 BSP_FLD32(1)
+
+/* field: USERACCESS0 - MDIO user command complete interrupt mask clear for USERINTMASKED[0]. */
+#define TMS570_MDIO_USERINTMASKCLEAR_USERACCESS0 BSP_FLD32(0)
+
+
+/*-------------------TMS570_MDIOUSERACCESS0-------------------*/
+/* field: GO - Go bit. */
+#define TMS570_MDIO_USERACCESS0_GO BSP_FLD32(31)
+
+/* field: WRITE - Write enable bit. */
+#define TMS570_MDIO_USERACCESS0_WRITE BSP_FLD32(30)
+
+/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
+#define TMS570_MDIO_USERACCESS0_ACK BSP_FLD32(29)
+
+/* field: REGADR - Register address bits. */
+#define TMS570_MDIO_USERACCESS0_REGADR(val) BSP_FLD32(val,21, 25)
+#define TMS570_MDIO_USERACCESS0_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
+#define TMS570_MDIO_USERACCESS0_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
+
+/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
+#define TMS570_MDIO_USERACCESS0_PHYADR(val) BSP_FLD32(val,16, 20)
+#define TMS570_MDIO_USERACCESS0_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_MDIO_USERACCESS0_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: DATA - User data bits. */
+#define TMS570_MDIO_USERACCESS0_DATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_MDIO_USERACCESS0_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_MDIO_USERACCESS0_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_MDIOUSERPHYSEL0-------------------*/
+/* field: LINKSEL - Link status determination select bit. */
+#define TMS570_MDIO_USERPHYSEL0_LINKSEL BSP_FLD32(7)
+
+/* field: LINKINTENB - Link change interrupt enable. */
+#define TMS570_MDIO_USERPHYSEL0_LINKINTENB BSP_FLD32(6)
+
+/* field: PHYADRMON - PHY address whose link status is to be monitored. */
+#define TMS570_MDIO_USERPHYSEL0_PHYADRMON(val) BSP_FLD32(val,0, 4)
+#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_MDIO_USERPHYSEL0_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*-------------------TMS570_MDIOUSERACCESS1-------------------*/
+/* field: GO - Go bit. */
+#define TMS570_MDIO_USERACCESS1_GO BSP_FLD32(31)
+
+/* field: WRITE - Write enable bit. */
+#define TMS570_MDIO_USERACCESS1_WRITE BSP_FLD32(30)
+
+/* field: ACK - Acknowledge bit. This bit is set if the PHY acknowledged the read transaction. */
+#define TMS570_MDIO_USERACCESS1_ACK BSP_FLD32(29)
+
+/* field: REGADR - Register address bits. */
+#define TMS570_MDIO_USERACCESS1_REGADR(val) BSP_FLD32(val,21, 25)
+#define TMS570_MDIO_USERACCESS1_REGADR_GET(reg) BSP_FLD32GET(reg,21, 25)
+#define TMS570_MDIO_USERACCESS1_REGADR_SET(reg,val) BSP_FLD32SET(reg, val,21, 25)
+
+/* field: PHYADR - PHY address bits. This field specifies the PHY to be accessed for this transaction. */
+#define TMS570_MDIO_USERACCESS1_PHYADR(val) BSP_FLD32(val,16, 20)
+#define TMS570_MDIO_USERACCESS1_PHYADR_GET(reg) BSP_FLD32GET(reg,16, 20)
+#define TMS570_MDIO_USERACCESS1_PHYADR_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
+
+/* field: DATA - User data bits. */
+#define TMS570_MDIO_USERACCESS1_DATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_MDIO_USERACCESS1_DATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_MDIO_USERACCESS1_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_MDIOUSERPHYSEL1-------------------*/
+/* field: LINKSEL - Link status determination select bit. */
+#define TMS570_MDIO_USERPHYSEL1_LINKSEL BSP_FLD32(7)
+
+/* field: LINKINTENB - Link change interrupt enable. */
+#define TMS570_MDIO_USERPHYSEL1_LINKINTENB BSP_FLD32(6)
+
+/* field: PHYADRMON - PHY address whose link status is to be monitored. */
+#define TMS570_MDIO_USERPHYSEL1_PHYADRMON(val) BSP_FLD32(val,0, 4)
+#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_MDIO_USERPHYSEL1_PHYADRMON_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+
+#endif /* LIBBSP_ARM_tms570_MDIO */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
new file mode 100644
index 0000000..1b3c870
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_n2het.h
@@ -0,0 +1,377 @@
+/* The header file is generated by make_header.py from N2HET.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_NHET
+#define LIBBSP_ARM_tms570_NHET
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GCR; /*Global Configuration Register*/
+ uint32_t PFR; /*Prescale Factor Register*/
+ uint32_t ADDR; /*NHET Current Address Register*/
+ uint32_t OFF1; /*Offset Index Priority Level 1 Register*/
+ uint32_t OFF2; /*Offset Index Priority Level 2 Register*/
+ uint32_t INTENAS; /*Interrupt Enable Set Register*/
+ uint32_t INTENAC; /*Interrupt Enable Clear Register*/
+ uint32_t EXC1; /*Exception Control Register 1*/
+ uint32_t EXC2; /*Exception Control Register 2*/
+ uint32_t PRY; /*Interrupt Priority Register*/
+ uint32_t FLG; /*Interrupt Flag Register*/
+ uint32_t AND; /*AND Share Control Register*/
+ uint8_t reserved1 [4];
+ uint32_t HRSH; /*HR Share Control Register*/
+ uint32_t XOR; /*HR XOR-Share Control Register*/
+ uint32_t REQENS; /*Request Enable Set Register*/
+ uint32_t REQENC; /*Request Enable Clear Register*/
+ uint32_t REQDS; /*Request Destination Select Register*/
+ uint8_t reserved2 [4];
+ uint32_t DIR; /*NHET Direction Register*/
+ uint32_t DIN; /*NHET Data Input Register*/
+ uint32_t DOUT; /*NHET Data Output Register*/
+ uint32_t DSET; /*NHET Data Set Register*/
+ uint32_t DCLR; /*NHET Data Clear Register*/
+ uint32_t PDR; /*NHET Open Drain Register*/
+ uint32_t PULDIS; /*NHET Pull Disable Register*/
+ uint32_t PSL; /*NHET Pull Select Register*/
+ uint8_t reserved3 [8];
+ uint32_t PCR; /*Parity Control Register*/
+ uint32_t PAR; /*Parity Address Register*/
+ uint32_t PPR; /*Parity Pin Register*/
+ uint32_t SFPRLD; /*Suppression Filter Preload Register*/
+ uint32_t SFENA; /*Suppression Filter Enable Register*/
+ uint8_t reserved4 [4];
+ uint32_t LBPSEL; /*Loop Back Pair Select Register*/
+ uint32_t LBPDIR; /*Loop Back Pair Direction Register*/
+ uint32_t PINDIS; /*NHET Pin Disable Register*/
+} tms570_nhet_t;
+
+
+/*-----------------------TMS570_NHETGCR-----------------------*/
+/* field: HET_PIN_ENA - Enables the output buffers of the pin structures depending on the value of nDIS and DIR. */
+#define TMS570_NHET_GCR_HET_PIN_ENA BSP_FLD32(24)
+
+/* field: MP - Master Priority */
+#define TMS570_NHET_GCR_MP(val) BSP_FLD32(val,21, 22)
+#define TMS570_NHET_GCR_MP_GET(reg) BSP_FLD32GET(reg,21, 22)
+#define TMS570_NHET_GCR_MP_SET(reg,val) BSP_FLD32SET(reg, val,21, 22)
+
+/* field: PPF - Protect Program Fields */
+#define TMS570_NHET_GCR_PPF BSP_FLD32(18)
+
+/* field: IS - Ignore Suspend */
+#define TMS570_NHET_GCR_IS BSP_FLD32(17)
+
+/* field: CMS - Clk_master/slave */
+#define TMS570_NHET_GCR_CMS BSP_FLD32(16)
+
+
+/*-----------------------TMS570_NHETPFR-----------------------*/
+/* field: LRPFC - oop Resolution Pre-scale Factor Code */
+#define TMS570_NHET_PFR_LRPFC(val) BSP_FLD32(val,8, 10)
+#define TMS570_NHET_PFR_LRPFC_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_NHET_PFR_LRPFC_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: HRPFC - High Resolution Pre-scale Factor Code */
+#define TMS570_NHET_PFR_HRPFC(val) BSP_FLD32(val,0, 5)
+#define TMS570_NHET_PFR_HRPFC_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_NHET_PFR_HRPFC_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*----------------------TMS570_NHETADDR----------------------*/
+/* field: HETADDR - N2HET Current Address */
+#define TMS570_NHET_ADDR_HETADDR(val) BSP_FLD32(val,0, 8)
+#define TMS570_NHET_ADDR_HETADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_NHET_ADDR_HETADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*----------------------TMS570_NHETOFF1----------------------*/
+/* field: OFFSET1 - HETOFF1[5:0] indexes the currently pending high-priority interrupt. */
+#define TMS570_NHET_OFF1_OFFSET1(val) BSP_FLD32(val,0, 5)
+#define TMS570_NHET_OFF1_OFFSET1_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_NHET_OFF1_OFFSET1_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*----------------------TMS570_NHETOFF2----------------------*/
+/* field: OFFSET2 - HETOFF2[5:0] indexes the currently pending low-priority interrupt. */
+#define TMS570_NHET_OFF2_OFFSET2(val) BSP_FLD32(val,0, 5)
+#define TMS570_NHET_OFF2_OFFSET2_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_NHET_OFF2_OFFSET2_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*---------------------TMS570_NHETINTENAS---------------------*/
+/* field: HETINTENAS - Interrupt Enable Set bits. HETINTENAS is readable and writable in any operation mode. */
+#define TMS570_NHET_INTENAS_HETINTENAS(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_INTENAS_HETINTENAS_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_INTENAS_HETINTENAS_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_NHETINTENAC---------------------*/
+/* field: HETINTENAC - Interrupt Enable Clear bits. HETINTENAC is readable and writable in any operation mode. */
+#define TMS570_NHET_INTENAC_HETINTENAC(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_INTENAC_HETINTENAC_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_INTENAC_HETINTENAC_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_NHETEXC1----------------------*/
+/* field: APCNT_OVRFL_ENA - APCNT Overflow Enable */
+#define TMS570_NHET_EXC1_APCNT_OVRFL_ENA BSP_FLD32(24)
+
+/* field: APCNT_UNRFL_ENA - APCNT Underflow Enable */
+#define TMS570_NHET_EXC1_APCNT_UNRFL_ENA BSP_FLD32(16)
+
+/* field: PRGM_OVRFL_ENA - Program Overflow Enable */
+#define TMS570_NHET_EXC1_PRGM_OVRFL_ENA BSP_FLD32(8)
+
+/* field: APCNT_OVRFL_PRY - APCNT Overflow Exception Interrupt Priority */
+#define TMS570_NHET_EXC1_APCNT_OVRFL_PRY BSP_FLD32(2)
+
+/* field: APCNT_UNRFL_PRY - APCNT Underflow Exception Interrupt Priority */
+#define TMS570_NHET_EXC1_APCNT_UNRFL_PRY BSP_FLD32(1)
+
+/* field: PRGM_OVRFL_PRY - ProgramOverflow Exception Interrupt Priority */
+#define TMS570_NHET_EXC1_PRGM_OVRFL_PRY BSP_FLD32(0)
+
+
+/*----------------------TMS570_NHETEXC2----------------------*/
+/* field: DEBUG_STATUS_FLAG - Debug Status Flag. */
+#define TMS570_NHET_EXC2_DEBUG_STATUS_FLAG BSP_FLD32(8)
+
+/* field: APCNT_OVRFL_FLAG - APCNT Overflow Flag */
+#define TMS570_NHET_EXC2_APCNT_OVRFL_FLAG BSP_FLD32(2)
+
+/* field: APCNT_UNDFL_FLAG - APCNT Underflow Flag */
+#define TMS570_NHET_EXC2_APCNT_UNDFL_FLAG BSP_FLD32(1)
+
+/* field: PRGM_OVERFL_FLAG - Program Overflow Flag */
+#define TMS570_NHET_EXC2_PRGM_OVERFL_FLAG BSP_FLD32(0)
+
+
+/*-----------------------TMS570_NHETPRY-----------------------*/
+/* field: HETPRY - HET Interrupt Priority Level bits */
+#define TMS570_NHET_PRY_HETPRY(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PRY_HETPRY_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PRY_HETPRY_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETFLG-----------------------*/
+/* field: HETFLAG - Interrupt Flag Register Bits */
+#define TMS570_NHET_FLG_HETFLAG(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_FLG_HETFLAG_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_FLG_HETFLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETAND-----------------------*/
+/* field: AND_SHARE - AND Share Enable */
+#define TMS570_NHET_AND_AND_SHARE(val) BSP_FLD32(val,0, 15)
+#define TMS570_NHET_AND_AND_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_NHET_AND_AND_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_NHETHRSH----------------------*/
+/* field: HR_SHARE - HR Share Bits */
+#define TMS570_NHET_HRSH_HR_SHARE(val) BSP_FLD32(val,0, 15)
+#define TMS570_NHET_HRSH_HR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_NHET_HRSH_HR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_NHETXOR-----------------------*/
+/* field: XOR_SHARE - XOR Share Enable */
+#define TMS570_NHET_XOR_XOR_SHARE(val) BSP_FLD32(val,0, 15)
+#define TMS570_NHET_XOR_XOR_SHARE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_NHET_XOR_XOR_SHARE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_NHETREQENS---------------------*/
+/* field: REQ_ENA_n - Request Enable Bits */
+#define TMS570_NHET_REQENS_REQ_ENA_n(val) BSP_FLD32(val,0, 7)
+#define TMS570_NHET_REQENS_REQ_ENA_n_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_NHET_REQENS_REQ_ENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_NHETREQENC---------------------*/
+/* field: REQ_DIS_n - Request Disable Bits */
+#define TMS570_NHET_REQENC_REQ_DIS_n(val) BSP_FLD32(val,0, 7)
+#define TMS570_NHET_REQENC_REQ_DIS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_NHET_REQENC_REQ_DIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_NHETREQDS----------------------*/
+/* field: TDBS_n - HTU, DMA or Both Select Bits */
+#define TMS570_NHET_REQDS_TDBS_n(val) BSP_FLD32(val,16, 23)
+#define TMS570_NHET_REQDS_TDBS_n_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_NHET_REQDS_TDBS_n_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TDS_n - HTU or DMA Select Bits */
+#define TMS570_NHET_REQDS_TDS_n(val) BSP_FLD32(val,0, 7)
+#define TMS570_NHET_REQDS_TDS_n_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_NHET_REQDS_TDS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_NHETDIR-----------------------*/
+/* field: HETDIR_n - Data direction of NHET pins */
+#define TMS570_NHET_DIR_HETDIR_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_DIR_HETDIR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_DIR_HETDIR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETDIN-----------------------*/
+/* field: HETDIN_n - Data input. This bit displays the logic state of the pin. */
+#define TMS570_NHET_DIN_HETDIN_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_DIN_HETDIN_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_DIN_HETDIN_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_NHETDOUT----------------------*/
+/* field: HETDOUT_n - Data out write. Writes to this bit will only take effect when the pin is configured as an output. */
+#define TMS570_NHET_DOUT_HETDOUT_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_DOUT_HETDOUT_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_DOUT_HETDOUT_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_NHETDSET----------------------*/
+/* field: HETDSET_n - This register allows bits of HETDOUT to be set while avoiding the pitfalls of a readmodify- write */
+#define TMS570_NHET_DSET_HETDSET_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_DSET_HETDSET_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_DSET_HETDSET_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_NHETDCLR----------------------*/
+/* field: HETDCLR_n - This register allows bits of HETDOUT to be cleared while avoiding the pitfalls of a read-modifywrite */
+#define TMS570_NHET_DCLR_HETDCLR_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_DCLR_HETDCLR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_DCLR_HETDCLR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETPDR-----------------------*/
+/* field: HETPDR_n - Open drain control for HET[n] pins */
+#define TMS570_NHET_PDR_HETPDR_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PDR_HETPDR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PDR_HETPDR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_NHETPULDIS---------------------*/
+/* field: HETPULDIS_n - Pull disable for N2HET pins */
+#define TMS570_NHET_PULDIS_HETPULDIS_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PULDIS_HETPULDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PULDIS_HETPULDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETPSL-----------------------*/
+/* field: HETPSL_n - Pull select for NHET pins */
+#define TMS570_NHET_PSL_HETPSL_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PSL_HETPSL_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PSL_HETPSL_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_NHETPCR-----------------------*/
+/* field: TEST - Test Bit. */
+#define TMS570_NHET_PCR_TEST BSP_FLD32(8)
+
+/* field: PARITY_ENA - Enable/disable parity checking. */
+#define TMS570_NHET_PCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_NHET_PCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_NHET_PCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_NHETPAR-----------------------*/
+/* field: PAOFF - Parity Error Address Offset. */
+#define TMS570_NHET_PAR_PAOFF(val) BSP_FLD32(val,2, 12)
+#define TMS570_NHET_PAR_PAOFF_GET(reg) BSP_FLD32GET(reg,2, 12)
+#define TMS570_NHET_PAR_PAOFF_SET(reg,val) BSP_FLD32SET(reg, val,2, 12)
+
+
+/*-----------------------TMS570_NHETPPR-----------------------*/
+/* field: HETPPR_n - NHET Parity Pin Select Bits - Allows HET[n] pins to be configured to drive to a known state when */
+#define TMS570_NHET_PPR_HETPPR_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PPR_HETPPR_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PPR_HETPPR_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_NHETSFPRLD---------------------*/
+/* field: CCDIV - Counter Clock Divider */
+#define TMS570_NHET_SFPRLD_CCDIV(val) BSP_FLD32(val,16, 17)
+#define TMS570_NHET_SFPRLD_CCDIV_GET(reg) BSP_FLD32GET(reg,16, 17)
+#define TMS570_NHET_SFPRLD_CCDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
+
+/* field: CPRLD - Counter Preload Value */
+#define TMS570_NHET_SFPRLD_CPRLD(val) BSP_FLD32(val,0, 9)
+#define TMS570_NHET_SFPRLD_CPRLD_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_NHET_SFPRLD_CPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*----------------------TMS570_NHETSFENA----------------------*/
+/* field: HETSFENA_n - Suppression Filter Enable Bits */
+#define TMS570_NHET_SFENA_HETSFENA_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_SFENA_HETSFENA_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_SFENA_HETSFENA_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_NHETLBPSEL---------------------*/
+/* field: LBPTYPE - Loop Back Pair Type Select Bits */
+#define TMS570_NHET_LBPSEL_LBPTYPE(val) BSP_FLD32(val,16, 31)
+#define TMS570_NHET_LBPSEL_LBPTYPE_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_NHET_LBPSEL_LBPTYPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: LBPSEL - Loop Back Pair Select Bits */
+#define TMS570_NHET_LBPSEL_LBPSEL(val) BSP_FLD32(val,0, 15)
+#define TMS570_NHET_LBPSEL_LBPSEL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_NHET_LBPSEL_LBPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_NHETLBPDIR---------------------*/
+/* field: LBPTSTENA - Loopback Test Enable Key */
+#define TMS570_NHET_LBPDIR_LBPTSTENA(val) BSP_FLD32(val,16, 19)
+#define TMS570_NHET_LBPDIR_LBPTSTENA_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_NHET_LBPDIR_LBPTSTENA_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: LBPDIR - Loop Back Pair Direction Bits */
+#define TMS570_NHET_LBPDIR_LBPDIR(val) BSP_FLD32(val,0, 15)
+#define TMS570_NHET_LBPDIR_LBPDIR_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_NHET_LBPDIR_LBPDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_NHETPINDIS---------------------*/
+/* field: HETPINDIS_n - N2HET Pin Disable Bits */
+#define TMS570_NHET_PINDIS_HETPINDIS_n(val) BSP_FLD32(val,0, 31)
+#define TMS570_NHET_PINDIS_HETPINDIS_n_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_NHET_PINDIS_HETPINDIS_n_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_NHET */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
new file mode 100644
index 0000000..9c7441e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pbist.h
@@ -0,0 +1,213 @@
+/* The header file is generated by make_header.py from PBIST.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_PBIST
+#define LIBBSP_ARM_tms570_PBIST
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t DNW[88]; /*Reserved DO NOT WRITE*/
+ uint32_t RAMT; /*RAM Configuration Register*/
+ uint32_t DLR; /*Datalogger Register*/
+ uint8_t reserved1 [24];
+ uint32_t PACT; /*PBIST Activate/ROM Clock Enable Register*/
+ uint32_t PBISTID; /*PBIST ID Register*/
+ uint32_t OVER; /*Override Register*/
+ uint8_t reserved2 [4];
+ uint32_t FSRF0; /*Fail Status Fail Register 0*/
+ uint8_t reserved3 [4];
+ uint32_t FSRC0; /*Fail Status Count Register 0*/
+ uint32_t FSRC1; /*Fail Status Count Register 1*/
+ uint32_t FSRA0; /*Fail Status Address 0 Register*/
+ uint32_t FSRA1; /*Fail Status Address 1 Register*/
+ uint32_t FSRDL0; /*Fail Status Data Register 0*/
+ uint8_t reserved4 [4];
+ uint32_t FSRDL1; /*Fail Status Data Register 1*/
+ uint8_t reserved5 [12];
+ uint32_t ROM; /*ROM Mask Register*/
+ uint32_t ALGO; /*ROM Algorithm Mask Register*/
+ uint32_t RINFOL; /*RAM Info Mask Lower Register*/
+ uint32_t RINFOUL; /*RAM Info Mask Lower Register*/
+} tms570_pbist_t;
+
+
+/*----------------------TMS570_PBISTDNW----------------------*/
+/* field: Reserved - Do not write */
+#define TMS570_PBIST_DNW_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_DNW_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_DNW_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_PBISTRAMT----------------------*/
+/* field: RGS - Ram Group Select. Refer Table 2-5 for information on the RGS value for each memory. */
+#define TMS570_PBIST_RAMT_RGS(val) BSP_FLD32(val,24, 31)
+#define TMS570_PBIST_RAMT_RGS_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_PBIST_RAMT_RGS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: RDS - Return Data Select. Refer Table 2-5 for information on the RDS values for each memory. */
+#define TMS570_PBIST_RAMT_RDS(val) BSP_FLD32(val,16, 23)
+#define TMS570_PBIST_RAMT_RDS_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_PBIST_RAMT_RDS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: DWR - Data Width Register */
+#define TMS570_PBIST_RAMT_DWR(val) BSP_FLD32(val,8, 15)
+#define TMS570_PBIST_RAMT_DWR_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_PBIST_RAMT_DWR_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: SMS - Sense Margin Select Register */
+#define TMS570_PBIST_RAMT_SMS(val) BSP_FLD32(val,6, 7)
+#define TMS570_PBIST_RAMT_SMS_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_PBIST_RAMT_SMS_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: PLS - Pipeline Latency Select */
+#define TMS570_PBIST_RAMT_PLS(val) BSP_FLD32(val,2, 5)
+#define TMS570_PBIST_RAMT_PLS_GET(reg) BSP_FLD32GET(reg,2, 5)
+#define TMS570_PBIST_RAMT_PLS_SET(reg,val) BSP_FLD32SET(reg, val,2, 5)
+
+/* field: RLS - RAM Latency Select */
+#define TMS570_PBIST_RAMT_RLS(val) BSP_FLD32(val,0, 1)
+#define TMS570_PBIST_RAMT_RLS_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PBIST_RAMT_RLS_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*----------------------TMS570_PBISTDLR----------------------*/
+/* field: DLR4 - Config access: setting this bit allows the host processor to configure the PBIST controller registers */
+#define TMS570_PBIST_DLR_DLR4 BSP_FLD32(4)
+
+/* field: DLR2 - ROM-based testing: setting this bit enables the PBIST controller to execute test algorithms that are */
+#define TMS570_PBIST_DLR_DLR2 BSP_FLD32(2)
+
+
+/*----------------------TMS570_PBISTPACT----------------------*/
+/* field: PACT1 - PBIST Activate */
+#define TMS570_PBIST_PACT_PACT1 BSP_FLD32(1)
+
+/* field: PACT0 - ROM Clock Enable Register */
+#define TMS570_PBIST_PACT_PACT0 BSP_FLD32(0)
+
+
+/*--------------------TMS570_PBISTPBISTID--------------------*/
+/* field: PBIST_ID - This is a unique ID assigned to each PBIST controller in a device with multiple PBIST controllers. */
+#define TMS570_PBIST_PBISTID_PBIST_ID(val) BSP_FLD32(val,0, 7)
+#define TMS570_PBIST_PBISTID_PBIST_ID_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_PBIST_PBISTID_PBIST_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_PBISTOVER----------------------*/
+/* field: OVER0 - RINFO Override Bit */
+#define TMS570_PBIST_OVER_OVER0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_PBISTFSRF0---------------------*/
+/* field: FSRF0 - Fail Status 0. */
+#define TMS570_PBIST_FSRF0_FSRF0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_PBISTFSRC0---------------------*/
+/* field: FSRC0 - Fail Status Count 0. Indicates the number of failures on port 0. */
+#define TMS570_PBIST_FSRC0_FSRC0(val) BSP_FLD32(val,0, 7)
+#define TMS570_PBIST_FSRC0_FSRC0_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_PBIST_FSRC0_FSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_PBISTFSRC1---------------------*/
+/* field: FSRC1 - Fail Status Count 1. Indicates the number of failures on port 1. */
+#define TMS570_PBIST_FSRC1_FSRC1(val) BSP_FLD32(val,0, 7)
+#define TMS570_PBIST_FSRC1_FSRC1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_PBIST_FSRC1_FSRC1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_PBISTFSRA0---------------------*/
+/* field: FSRA0 - Fail Status Address 0. Contains the address of the first failure. */
+#define TMS570_PBIST_FSRA0_FSRA0(val) BSP_FLD32(val,0, 15)
+#define TMS570_PBIST_FSRA0_FSRA0_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_PBIST_FSRA0_FSRA0_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_PBISTFSRA1---------------------*/
+/* field: FSRA1 - Fail Status Address 1. Contains the address of the first failure. */
+#define TMS570_PBIST_FSRA1_FSRA1(val) BSP_FLD32(val,0, 15)
+#define TMS570_PBIST_FSRA1_FSRA1_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_PBIST_FSRA1_FSRA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_PBISTFSRDL0---------------------*/
+/* field: FSRDL1 - Failure data on port 1 */
+#define TMS570_PBIST_FSRDL0_FSRDL1(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_FSRDL0_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_FSRDL0_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_PBISTFSRDL1---------------------*/
+/* field: FSRDL1 - Failure data on port 1 */
+#define TMS570_PBIST_FSRDL1_FSRDL1(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_FSRDL1_FSRDL1_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_FSRDL1_FSRDL1_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_PBISTROM----------------------*/
+/* field: ROM - ROM Mask */
+#define TMS570_PBIST_ROM_ROM(val) BSP_FLD32(val,0, 1)
+#define TMS570_PBIST_ROM_ROM_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PBIST_ROM_ROM_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*----------------------TMS570_PBISTALGO----------------------*/
+/* field: ROM_ALG_MASK - Each bit corresponds to a specific algorithm */
+#define TMS570_PBIST_ALGO_ROM_ALG_MASK(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_ALGO_ROM_ALG_MASK_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_ALGO_ROM_ALG_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_PBISTRINFOL---------------------*/
+/* field: RAM_ALG_MASK_LOW - Each bit corresponds to a specific algorithm */
+#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_RINFOL_RAM_ALG_MASK_LOW_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PBISTRINFOUL--------------------*/
+/* field: RAM_ALG_MASK_UP - Each bit corresponds to a specific algorithm */
+#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP(val) BSP_FLD32(val,0, 31)
+#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PBIST_RINFOUL_RAM_ALG_MASK_UP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_PBIST */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
new file mode 100644
index 0000000..99c5ac7
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pcr.h
@@ -0,0 +1,150 @@
+/* The header file is generated by make_header.py from PCR.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_PCR
+#define LIBBSP_ARM_tms570_PCR
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PMPROTSET0; /*Peripheral Memory Protection Set Register 0*/
+ uint32_t PMPROTSET1; /*Peripheral Memory Protection Set Register 1*/
+ uint8_t reserved1 [8];
+ uint32_t PMPROTCLR0; /*Peripheral Memory Protection Clear Register 0*/
+ uint32_t PMPROTCLR1; /*Peripheral Memory Protection Clear Register 1*/
+ uint8_t reserved2 [8];
+ uint32_t PPROTSET0; /*Peripheral Protection Set Register 0*/
+ uint32_t PPROTSET1; /*Peripheral Protection Set Register 1*/
+ uint32_t PPROTSET2; /*Peripheral Protection Set Register 2*/
+ uint32_t PPROTSET3; /*Peripheral Protection Set Register 3*/
+ uint8_t reserved3 [16];
+ uint32_t PPROTCLR0; /*Peripheral Protection Clear Register 0*/
+ uint32_t PPROTCLR1; /*Peripheral Protection Clear Register 1*/
+ uint32_t PPROTCLR2; /*Peripheral Protection Clear Register 2*/
+ uint32_t PPROTCLR3; /*Peripheral Protection Clear Register 3*/
+ uint8_t reserved4 [16];
+ uint32_t PCSPWRDWNSET0; /*Peripheral Memory Power-Down Set Register 0*/
+ uint32_t PCSPWRDWNSET1; /*Peripheral Memory Power-Down Set Register 1*/
+ uint8_t reserved5 [8];
+ uint32_t PCSPWRDWNCLR0; /*Peripheral Memory Power-Down Clear Register 0*/
+ uint32_t PCSPWRDWNCLR1; /*Peripheral Memory Power-Down Clear Register 1*/
+ uint8_t reserved6 [8];
+ uint32_t PSPWRDWNSET0; /*Peripheral Power-Down Set Register 0*/
+ uint32_t PSPWRDWNSET1; /*Peripheral Power-Down Set Register 1*/
+ uint32_t PSPWRDWNSET2; /*Peripheral Power-Down Set Register 2*/
+ uint32_t PSPWRDWNSET3; /*Peripheral Power-Down Set Register 3*/
+ uint8_t reserved7 [16];
+ uint32_t PSPWRDWNCLR0; /*Peripheral Power-Down Clear Register 0*/
+ uint32_t PSPWRDWNCLR1; /*Peripheral Power-Down Clear Register 1*/
+ uint32_t PSPWRDWNCLR2; /*Peripheral Power-Down Clear Register 2*/
+ uint32_t PSPWRDWNCLR3; /*Peripheral Power-Down Clear Register 3*/
+} tms570_pcr_t;
+
+
+/*--------------------TMS570_PCRPMPROTSET0--------------------*/
+/* field: PCSPROTSET - Peripheral memory frame protection set. */
+#define TMS570_PCR_PMPROTSET0_PCSPROTSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PMPROTSET0_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PMPROTSET0_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PCRPMPROTSET1--------------------*/
+/* field: PCSPROTSET - Peripheral memory frame protection set. */
+#define TMS570_PCR_PMPROTSET1_PCSPROTSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PMPROTSET1_PCSPROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PMPROTSET1_PCSPROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PCRPMPROTCLR0--------------------*/
+/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
+#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PMPROTCLR0_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PCRPMPROTCLR1--------------------*/
+/* field: PCSPROTCLR - Peripheral memory frame protection clear. */
+#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PMPROTCLR1_PCSPROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PCRPPROTSET0--------------------*/
+/* field: PROTSET - Peripheral select quadrant protection set. */
+#define TMS570_PCR_PPROTSET0_PROTSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PPROTSET0_PROTSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PPROTSET0_PROTSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_PCRPPROTCLR0--------------------*/
+/* field: PROTCLR - Peripheral select quadrant protection clear. */
+#define TMS570_PCR_PPROTCLR0_PROTCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PPROTCLR0_PROTCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PPROTCLR0_PROTCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_PCRPCSPWRDWNSET0------------------*/
+/* field: PWRDNSET - Peripheral memory clock power-down set. */
+#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PCSPWRDWNSET0_PWRDNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_PCRPCSPWRDWNCLR0------------------*/
+/* field: PWRDNCLR - Peripheral memory clock power-down clear. */
+#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PCSPWRDWNCLR0_PWRDNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_PCRPSPWRDWNSET0-------------------*/
+/* field: PWRDWNSET - Peripheral select quadrant clock power-down set. */
+#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PSPWRDWNSET0_PWRDWNSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_PCRPSPWRDWNCLR0-------------------*/
+/* field: PWRDWNCLR - Peripheral select quadrant clock power-down clear. */
+#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PCR_PSPWRDWNCLR0_PWRDWNCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_PCR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
new file mode 100644
index 0000000..b56ed4e
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pll.h
@@ -0,0 +1,304 @@
+/* The header file is generated by make_header.py from PLL.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_PLL
+#define LIBBSP_ARM_tms570_PLL
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PLLCTL3; /*PLL Control 3 Register*/
+ uint8_t reserved1 [108];
+ uint32_t CLKSLIP; /*PLL Clock Slip Control Register*/
+ uint8_t reserved2 [7600];
+ uint32_t SSWPLL1; /*PLL Modulation Depth Measurement Control Register*/
+ uint32_t SSWPLL2; /*SSW PLL BIST Control Register 2*/
+ uint32_t SSWPLL3; /*SSW PLL BIST Control Register 3*/
+ uint32_t CSDIS; /*Clock Source Disable Register*/
+ uint32_t CSDISSET; /*Clock Source Disable Set Register*/
+ uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
+ uint8_t reserved3 [24];
+ uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
+ uint8_t reserved4 [24];
+ uint32_t PLLCTL1; /*PLL Control 1 Register*/
+ uint32_t PLLCTL2; /*PLL Control 2 Register*/
+ uint8_t reserved5 [16];
+ uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
+ uint32_t CLKTEST; /*Clock Test Register*/
+ uint8_t reserved6 [16];
+ uint32_t GPREG1; /*General Purpose Register*/
+ uint8_t reserved7 [72];
+ uint32_t GLBSTAT; /*Global Status Register*/
+} tms570_pll_t;
+
+
+/*---------------------TMS570_PLLPLLCTL3---------------------*/
+/* field: ODPLL2 - Internal PLL Output Divider */
+#define TMS570_PLL_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
+#define TMS570_PLL_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
+#define TMS570_PLL_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
+
+/* field: PLLDIV2 - PLL2 Output Clock Divider */
+#define TMS570_PLL_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
+#define TMS570_PLL_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_PLL_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: REFCLKDIV2 - Reference Clock Divider */
+#define TMS570_PLL_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
+#define TMS570_PLL_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_PLL_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: PLLMUL2 - PLL2 Multiplication Factor */
+#define TMS570_PLL_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
+#define TMS570_PLL_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_PLL_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_PLLCLKSLIP---------------------*/
+/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
+
+/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PLL_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_PLLSSWPLL1---------------------*/
+/* field: CAPTURE_WINDOW_INDEX - The capture counter present in the PLL wrapper will count the PLL clock edges when */
+#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX(val) BSP_FLD32(val,8, 15)
+#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_PLL_SSWPLL1_CAPTURE_WINDOW_INDEX_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: COUNTER_READ_READY - Counter read ready. */
+#define TMS570_PLL_SSWPLL1_COUNTER_READ_READY BSP_FLD32(6)
+
+/* field: COUNTER_RESET - Counter reset. */
+#define TMS570_PLL_SSWPLL1_COUNTER_RESET BSP_FLD32(5)
+
+/* field: COUNTER_EN - Counter enable. */
+#define TMS570_PLL_SSWPLL1_COUNTER_EN BSP_FLD32(4)
+
+/* field: TAP_COUNTER_DIS - The value in this register is used to program a particular bit in CLKOUT counter. */
+#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS(val) BSP_FLD32(val,1, 3)
+#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_GET(reg) BSP_FLD32GET(reg,1, 3)
+#define TMS570_PLL_SSWPLL1_TAP_COUNTER_DIS_SET(reg,val) BSP_FLD32SET(reg, val,1, 3)
+
+/* field: EXT_COUNTER_EN - Modulation Depth Measurement mode */
+#define TMS570_PLL_SSWPLL1_EXT_COUNTER_EN BSP_FLD32(0)
+
+
+/*---------------------TMS570_PLLSSWPLL2---------------------*/
+/* field: SSW_CAPTURE_COUNT - Capture count. This register returns the value of the capture count. */
+#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
+#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PLL_SSWPLL2_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_PLLSSWPLL3---------------------*/
+/* field: SSW_CAPTURE_COUNT - Value of CLKout count register. */
+#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT(val) BSP_FLD32(val,0, 31)
+#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_PLL_SSWPLL3_SSW_CAPTURE_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_PLLCSDIS----------------------*/
+/* field: CLKSR_7_3_OFF - Clock source[7-3] off. */
+#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_PLL_CSDIS_CLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLKSR_1_0_OFF - Clock source[1-0] off. */
+#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PLL_CSDIS_CLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_PLLCSDISSET---------------------*/
+/* field: SETCLKSR_7_3_OFF - Set clock source[7-3] to the disabled state. */
+#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_PLL_CSDISSET_SETCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: SETCLKSR_1_0_OFF - Set clock source[1-0] to the disabled state. */
+#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PLL_CSDISSET_SETCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_PLLCSDISCLR---------------------*/
+/* field: CLRCLKSR_7_3_OFF - Enables clock source[7-3]. */
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_7_3_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLRCLKSR_1_0_OFF - Enables clock source[1-0]. */
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PLL_CSDISCLR_CLRCLKSR_1_0_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_PLLCSVSTAT---------------------*/
+/* field: CLKSR_7_3V - Clock source[7-0] valid. */
+#define TMS570_PLL_CSVSTAT_CLKSR_7_3V(val) BSP_FLD32(val,3, 7)
+#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_PLL_CSVSTAT_CLKSR_7_3V_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLKSR_1_0V - Clock source[1-0] valid. */
+#define TMS570_PLL_CSVSTAT_CLKSR_1_0V(val) BSP_FLD32(val,0, 1)
+#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PLL_CSVSTAT_CLKSR_1_0V_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_PLLPLLCTL1---------------------*/
+/* field: ROS - Reset on PLL Slip */
+#define TMS570_PLL_PLLCTL1_ROS BSP_FLD32(31)
+
+/* field: MASK_SLIP - Mask detection of PLL slip */
+#define TMS570_PLL_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
+#define TMS570_PLL_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_PLL_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
+/* field: PLLDIV - PLL Output Clock Divider */
+#define TMS570_PLL_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
+#define TMS570_PLL_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_PLL_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: ROF - Reset on Oscillator Fail */
+#define TMS570_PLL_PLLCTL1_ROF BSP_FLD32(23)
+
+/* field: REFCLKDIV - Reference Clock Divider */
+#define TMS570_PLL_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
+#define TMS570_PLL_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_PLL_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: PLLMUL - PLL Multiplication Factor */
+#define TMS570_PLL_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
+#define TMS570_PLL_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_PLL_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_PLLPLLCTL2---------------------*/
+/* field: FMENA - Frequency Modulation Enable. */
+#define TMS570_PLL_PLLCTL2_FMENA BSP_FLD32(31)
+
+/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
+#define TMS570_PLL_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
+#define TMS570_PLL_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
+#define TMS570_PLL_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
+
+/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
+#define TMS570_PLL_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
+#define TMS570_PLL_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
+#define TMS570_PLL_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
+
+/* field: ODPLL - Internal PLL Output Divider. */
+#define TMS570_PLL_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
+#define TMS570_PLL_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
+#define TMS570_PLL_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
+
+/* field: SPR_AMOUNT - Spreading Amount. */
+#define TMS570_PLL_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
+#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_PLL_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*--------------------TMS570_PLLLPOMONCTL--------------------*/
+/* field: BIAS_ENABLE - Bias enable. */
+#define TMS570_PLL_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+
+/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
+#define TMS570_PLL_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+
+/* field: HFTRIM - High frequency oscillator trim value. */
+#define TMS570_PLL_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
+#define TMS570_PLL_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_PLL_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+
+
+/*---------------------TMS570_PLLCLKTEST---------------------*/
+/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
+#define TMS570_PLL_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+
+/* field: RANGEDETCTRL - Range detection control. */
+#define TMS570_PLL_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+
+/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
+#define TMS570_PLL_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+
+/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
+#define TMS570_PLL_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
+#define TMS570_PLL_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PLL_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+
+/*----------------------TMS570_PLLGPREG1----------------------*/
+/* field: EMIF_FUNC - Enable EMIF functions to be output. */
+#define TMS570_PLL_GPREG1_EMIF_FUNC BSP_FLD32(31)
+
+/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
+#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
+#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_PLL_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
+#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
+#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PLL_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
+#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
+#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_PLL_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_PLLGLBSTAT---------------------*/
+/* field: FBSLIP - PLL over cycle slip detection. */
+#define TMS570_PLL_GLBSTAT_FBSLIP BSP_FLD32(9)
+
+/* field: RFSLIP - PLL under cycle slip detection. */
+#define TMS570_PLL_GLBSTAT_RFSLIP BSP_FLD32(8)
+
+/* field: OSCFAIL - Oscillator fail flag bit. */
+#define TMS570_PLL_GLBSTAT_OSCFAIL BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_PLL */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
new file mode 100644
index 0000000..5f70db2
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pmm.h
@@ -0,0 +1,258 @@
+/* The header file is generated by make_header.py from PMM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_PMM
+#define LIBBSP_ARM_tms570_PMM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t LOGICPDPWRCTRL0; /*Logic Power Domain Control Register 0*/
+ uint8_t reserved1 [12];
+ uint32_t MEMPDPWRCTRL0; /*Memory Power Domain Control Register 0*/
+ uint8_t reserved2 [12];
+ uint32_t PDCLKDISREG; /*Power Domain Clock Disable Register*/
+ uint32_t PDCLKDISSETREG; /*Power Domain Clock Disable Set Register*/
+ uint32_t PDCLKDISCLRREG; /*Power Domain Clock Disable Clear Register*/
+ uint8_t reserved3 [20];
+ uint32_t LOGICPDPWRSTAT[4]; /*Logic Power Domain PD2 Power Status Registers*/
+ uint8_t reserved4 [48];
+ uint32_t MEMPDPWRSTAT[3]; /*Memory Power Domain RAM_PD1 Power Status Registers*/
+ uint8_t reserved5 [20];
+ uint32_t GLOBALCTRL1; /*Global Control Register 1*/
+ uint8_t reserved6 [4];
+ uint32_t GLOBALSTAT; /*Global Status Register*/
+ uint32_t PRCKEYREG; /*PSCON Diagnostic Compare Key Register*/
+ uint32_t LPDDCSTAT1; /*LogicPD PSCON Diagnostic Compare Status Register 1*/
+ uint32_t LPDDCSTAT2; /*LogicPD PSCON Diagnostic Compare Status Register 2*/
+ uint32_t MPDDCSTAT1; /*Memory PD PSCON Diagnostic Compare Status Register 1*/
+ uint32_t MPDDCSTAT2; /*Memory PD PSCON Diagnostic Compare Status Register 2*/
+ uint32_t ISODIAGSTAT; /*Isolation Diagnostic Status Register*/
+} tms570_pmm_t;
+
+
+/*-----------------TMS570_PMMLOGICPDPWRCTRL0-----------------*/
+/* field: LOGICPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0(val) BSP_FLD32(val,24, 27)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: LOGICPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1(val) BSP_FLD32(val,16, 19)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: LOGICPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2(val) BSP_FLD32(val,8, 11)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: LOGICPDON3 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3(val) BSP_FLD32(val,0, 3)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PMM_LOGICPDPWRCTRL0_LOGICPDON3_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_PMMMEMPDPWRCTRL0------------------*/
+/* field: MEMPDON0 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0(val) BSP_FLD32(val,24, 27)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON0_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: MEMPDON1 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1(val) BSP_FLD32(val,16, 19)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON1_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: MEMPDON2 - Read in User and Privileged Mode. Write in Privileged Mode only. */
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2(val) BSP_FLD32(val,8, 11)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_PMM_MEMPDPWRCTRL0_MEMPDON2_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+
+/*-------------------TMS570_PMMPDCLKDISREG-------------------*/
+/* field: PDCLK_DIS_3 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[3]. */
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_3 BSP_FLD32(3)
+
+/* field: PDCLK_DIS_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_2 BSP_FLD32(2)
+
+/* field: PDCLK_DIS_1 - ead in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_1 BSP_FLD32(1)
+
+/* field: PDCLK_DIS_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
+#define TMS570_PMM_PDCLKDISREG_PDCLK_DIS_0 BSP_FLD32(0)
+
+
+/*------------------TMS570_PMMPDCLKDISSETREG------------------*/
+/* field: PDCLK_DISSET_3 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[3]. */
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_3 BSP_FLD32(3)
+
+/* field: PDCLK_DISSET_2 - Privileged Mode only. */
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_2 BSP_FLD32(2)
+
+/* field: PDCLK_DISSET_1 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[1]. */
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_1 BSP_FLD32(1)
+
+/* field: PDCLK_DISSET_0 - Read in User and Privileged Mode returns the current value of PDCLK_DISSET[0]. */
+#define TMS570_PMM_PDCLKDISSETREG_PDCLK_DISSET_0 BSP_FLD32(0)
+
+
+/*------------------TMS570_PMMPDCLKDISCLRREG------------------*/
+/* field: PDCLK_DISCLR_3 - PDCLK_DISCLR[3] */
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_3 BSP_FLD32(3)
+
+/* field: PDCLK_DISCLR_2 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[2]. */
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_2 BSP_FLD32(2)
+
+/* field: PDCLK_DISCLR_1 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[1]. */
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_1 BSP_FLD32(1)
+
+/* field: PDCLK_DISCLR_0 - Read in User and Privileged Mode returns the current value of PDCLK_DIS[0]. */
+#define TMS570_PMM_PDCLKDISCLRREG_PDCLK_DISCLR_0 BSP_FLD32(0)
+
+
+/*------------------TMS570_PMMLOGICPDPWRSTAT------------------*/
+/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain PD2. */
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+
+/* field: MEM_IN_TRANS0 - Memory in transition status for power domain PD2. */
+#define TMS570_PMM_LOGICPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+
+/* field: DOMAIN_ON0 - Current state of power domain PD2. */
+#define TMS570_PMM_LOGICPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+
+/* field: LOGICPDPWR_STAT0 - Logic power domain PD2 power state. */
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PMM_LOGICPDPWRSTAT_LOGICPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*-------------------TMS570_PMMMEMPDPWRSTAT-------------------*/
+/* field: LOGIC_IN_TRANS0 - Logic in transition status for power domain RAM_PD1. */
+#define TMS570_PMM_MEMPDPWRSTAT_LOGIC_IN_TRANS0 BSP_FLD32(24)
+
+/* field: MEM_IN_TRANS0 - Memory in transition status for power domain RAM_PD1. */
+#define TMS570_PMM_MEMPDPWRSTAT_MEM_IN_TRANS0 BSP_FLD32(16)
+
+/* field: DOMAIN_ON0 - Current state of power domain RAM_PD1. */
+#define TMS570_PMM_MEMPDPWRSTAT_DOMAIN_ON0 BSP_FLD32(8)
+
+/* field: MEMPDPWR_STAT0 - Memory power domain RAM_PD1 power state. */
+#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0(val) BSP_FLD32(val,0, 1)
+#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_PMM_MEMPDPWRSTAT_MEMPDPWR_STAT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*-------------------TMS570_PMMGLOBALCTRL1-------------------*/
+/* field: PMCTRL_PWRDN - PMC/PSCON Power Down */
+#define TMS570_PMM_GLOBALCTRL1_PMCTRL_PWRDN BSP_FLD32(8)
+
+/* field: AUTO_CLK_WAKE_ENA - Automatic Clock Enable on Wake Up */
+#define TMS570_PMM_GLOBALCTRL1_AUTO_CLK_WAKE_ENA BSP_FLD32(0)
+
+
+/*--------------------TMS570_PMMGLOBALSTAT--------------------*/
+/* field: PMCTRL_IDLE - State of PMC and all PSCONs. */
+#define TMS570_PMM_GLOBALSTAT_PMCTRL_IDLE BSP_FLD32(0)
+
+
+/*--------------------TMS570_PMMPRCKEYREG--------------------*/
+/* field: MKEY - Diagnostic PSCON Mode Key. The mode key is applied to all individual PSCON compare units. */
+#define TMS570_PMM_PRCKEYREG_MKEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_PMM_PRCKEYREG_MKEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PMM_PRCKEYREG_MKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_PMMLPDDCSTAT1--------------------*/
+/* field: LCMPE - Logic Power Domain Compare Error */
+#define TMS570_PMM_LPDDCSTAT1_LCMPE(val) BSP_FLD32(val,16, 19)
+#define TMS570_PMM_LPDDCSTAT1_LCMPE_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PMM_LPDDCSTAT1_LCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: LSTC - Logic Power Domain Self-test Complete */
+#define TMS570_PMM_LPDDCSTAT1_LSTC(val) BSP_FLD32(val,0, 3)
+#define TMS570_PMM_LPDDCSTAT1_LSTC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PMM_LPDDCSTAT1_LSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_PMMLPDDCSTAT2--------------------*/
+/* field: LSTET - Logic Power Domain Self-test Error Type */
+#define TMS570_PMM_LPDDCSTAT2_LSTET(val) BSP_FLD32(val,16, 19)
+#define TMS570_PMM_LPDDCSTAT2_LSTET_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_PMM_LPDDCSTAT2_LSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: LSTE - Logic Power Domain Self-test Error */
+#define TMS570_PMM_LPDDCSTAT2_LSTE(val) BSP_FLD32(val,0, 3)
+#define TMS570_PMM_LPDDCSTAT2_LSTE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PMM_LPDDCSTAT2_LSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_PMMMPDDCSTAT1--------------------*/
+/* field: MCMPE - Memory Power Domain Compare Error */
+#define TMS570_PMM_MPDDCSTAT1_MCMPE(val) BSP_FLD32(val,16, 18)
+#define TMS570_PMM_MPDDCSTAT1_MCMPE_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_PMM_MPDDCSTAT1_MCMPE_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: MSTC - Memory Power Domain Self-test Complete */
+#define TMS570_PMM_MPDDCSTAT1_MSTC(val) BSP_FLD32(val,0, 2)
+#define TMS570_PMM_MPDDCSTAT1_MSTC_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_PMM_MPDDCSTAT1_MSTC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*--------------------TMS570_PMMMPDDCSTAT2--------------------*/
+/* field: MSTET - Memory Power Domain Self-test Error Type */
+#define TMS570_PMM_MPDDCSTAT2_MSTET(val) BSP_FLD32(val,16, 18)
+#define TMS570_PMM_MPDDCSTAT2_MSTET_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_PMM_MPDDCSTAT2_MSTET_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: MSTE - Memory Power Domain Self-test Error */
+#define TMS570_PMM_MPDDCSTAT2_MSTE(val) BSP_FLD32(val,0, 2)
+#define TMS570_PMM_MPDDCSTAT2_MSTE_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_PMM_MPDDCSTAT2_MSTE_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-------------------TMS570_PMMISODIAGSTAT-------------------*/
+/* field: ISO_DIAG - Isolation Diagnostic */
+#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG(val) BSP_FLD32(val,0, 3)
+#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_PMM_ISODIAGSTAT_ISO_DIAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+
+#endif /* LIBBSP_ARM_tms570_PMM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
new file mode 100644
index 0000000..d6616c6
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_pom.h
@@ -0,0 +1,336 @@
+/* The header file is generated by make_header.py from POM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_POM
+#define LIBBSP_ARM_tms570_POM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PROGSTART; /*POM Program Region Start Address Register*/
+ uint32_t OVLSTART; /*POM Overlay Region Start Address Register*/
+ uint32_t REGSIZE; /*POM Region Size Register */
+ uint32_t Reser; /*Reserved*/
+} tms570_pom_region_t;
+
+typedef struct{
+ uint32_t GLBCTRL; /*POM Global Control Register*/
+ uint32_t REV; /*POM Revision ID*/
+ uint32_t CLKCTRL; /*POM Clock Gate Control Register*/
+ uint32_t FLG; /*POM Status Register*/
+ uint8_t reserved1 [496];
+ tms570_pom_region_t REG[32];/*Program Regions*/
+ uint8_t reserved2 [2816];
+ uint32_t ITCTRL; /*POM Integration Control Register*/
+ uint8_t reserved3 [156];
+ uint32_t CLAIMSET; /*POM Claim Set Register*/
+ uint32_t CLAIMCLR; /*POM Claim Clear Register*/
+ uint8_t reserved4 [8];
+ uint32_t LOCKACCESS; /*POM Lock Access Register*/
+ uint32_t LOCKSTATUS; /*POM Lock Status Register*/
+ uint32_t AUTHSTATUS; /*POM Authentication Status Register*/
+ uint8_t reserved5 [12];
+ uint32_t DEVID; /*POM Device ID Register*/
+ uint32_t DEVTYPE; /*POM Device Type Register*/
+ uint32_t PERIPHERALID4; /*POM Peripheral ID 4 Register*/
+ uint32_t PERIPHERALID5; /*POM Peripheral ID 5 Register*/
+ uint32_t PERIPHERALID6; /*POM Peripheral ID 6 Register*/
+ uint32_t PERIPHERALID7; /*POM Peripheral ID 7 Register*/
+ uint32_t PERIPHERALID0; /*POM Peripheral ID 0 Register*/
+ uint32_t PERIPHERALID1; /*POM Peripheral ID 1 Register*/
+ uint32_t PERIPHERALID2; /*POM Peripheral ID 2 Register*/
+ uint32_t PERIPHERALID3; /*POM Peripheral ID 3 Register*/
+ uint32_t COMPONENTID0; /*POM Component ID 0 Register*/
+ uint32_t COMPONENTID1; /*POM Component ID 1 Register*/
+ uint32_t COMPONENTID2; /*POM Component ID 2 Register*/
+ uint32_t COMPONENTID3; /*POM Component ID 3 Register*/
+} tms570_pom_t;
+
+
+/*--------------------TMS570_POMPROGSTART--------------------*/
+/* field: STARTADDRESS - Defines the start address of the program memory region. */
+#define TMS570_POM_PROGSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
+#define TMS570_POM_PROGSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
+#define TMS570_POM_PROGSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
+
+
+/*---------------------TMS570_POMOVLSTART---------------------*/
+/* field: STARTADDRESS - Defines the start address of the overlay memory region. */
+#define TMS570_POM_OVLSTART_STARTADDRESS(val) BSP_FLD32(val,0, 22)
+#define TMS570_POM_OVLSTART_STARTADDRESS_GET(reg) BSP_FLD32GET(reg,0, 22)
+#define TMS570_POM_OVLSTART_STARTADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,0, 22)
+
+
+/*---------------------TMS570_POMREGSIZE---------------------*/
+/* field: SIZE - Region size */
+#define TMS570_POM_REGSIZE_SIZE(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_REGSIZE_SIZE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_REGSIZE_SIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_POMGLBCTRL---------------------*/
+/* field: OTADDR - Overlay target Address. */
+#define TMS570_POM_GLBCTRL_OTADDR(val) BSP_FLD32(val,23, 31)
+#define TMS570_POM_GLBCTRL_OTADDR_GET(reg) BSP_FLD32GET(reg,23, 31)
+#define TMS570_POM_GLBCTRL_OTADDR_SET(reg,val) BSP_FLD32SET(reg, val,23, 31)
+
+/* field: ETO - Enable Timeout. Refer to Section 18.2.2 for more details on the timeout error. */
+#define TMS570_POM_GLBCTRL_ETO(val) BSP_FLD32(val,8, 11)
+#define TMS570_POM_GLBCTRL_ETO_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_POM_GLBCTRL_ETO_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: ON_OFF - Turn functionality of POM on or off. */
+#define TMS570_POM_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------------TMS570_POMREV-----------------------*/
+/* field: SCHEME - Used to distinguish between different ID schemes. */
+#define TMS570_POM_REV_SCHEME(val) BSP_FLD32(val,30, 31)
+#define TMS570_POM_REV_SCHEME_GET(reg) BSP_FLD32GET(reg,30, 31)
+#define TMS570_POM_REV_SCHEME_SET(reg,val) BSP_FLD32SET(reg, val,30, 31)
+
+/* field: FUNC - Indicates the SW compatible module family */
+#define TMS570_POM_REV_FUNC(val) BSP_FLD32(val,16, 27)
+#define TMS570_POM_REV_FUNC_GET(reg) BSP_FLD32GET(reg,16, 27)
+#define TMS570_POM_REV_FUNC_SET(reg,val) BSP_FLD32SET(reg, val,16, 27)
+
+/* field: RTL - RTL version number */
+#define TMS570_POM_REV_RTL(val) BSP_FLD32(val,11, 15)
+#define TMS570_POM_REV_RTL_GET(reg) BSP_FLD32GET(reg,11, 15)
+#define TMS570_POM_REV_RTL_SET(reg,val) BSP_FLD32SET(reg, val,11, 15)
+
+/* field: MAJOR - Major revision number */
+#define TMS570_POM_REV_MAJOR(val) BSP_FLD32(val,8, 10)
+#define TMS570_POM_REV_MAJOR_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_POM_REV_MAJOR_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: CUSTOM - Indicates a device specific implementation */
+#define TMS570_POM_REV_CUSTOM(val) BSP_FLD32(val,6, 7)
+#define TMS570_POM_REV_CUSTOM_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_POM_REV_CUSTOM_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: 5_0 - MINOR 8h Minor revision number */
+#define TMS570_POM_REV_5_0(val) BSP_FLD32(val,0, 5)
+#define TMS570_POM_REV_5_0_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_POM_REV_5_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*---------------------TMS570_POMCLKCTRL---------------------*/
+/* field: CLK_GATE_OFF - Do not modify this bit. Leave it in its reset state. */
+#define TMS570_POM_CLKCTRL_CLK_GATE_OFF BSP_FLD32(0)
+
+
+/*-----------------------TMS570_POMFLG-----------------------*/
+/* field: TO - Timeout. */
+#define TMS570_POM_FLG_TO BSP_FLD32(0)
+
+
+/*----------------------TMS570_POMITCTRL----------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_ITCTRL_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_ITCTRL_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_ITCTRL_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_POMCLAIMSET---------------------*/
+/* field: SET1 - The module is claimed */
+#define TMS570_POM_CLAIMSET_SET1 BSP_FLD32(1)
+
+/* field: SET0 - The module is claimed */
+#define TMS570_POM_CLAIMSET_SET0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_POMCLAIMCLR---------------------*/
+/* field: CLR1 - The module is claimed */
+#define TMS570_POM_CLAIMCLR_CLR1 BSP_FLD32(1)
+
+/* field: CLR0 - The module is claimed */
+#define TMS570_POM_CLAIMCLR_CLR0 BSP_FLD32(0)
+
+
+/*--------------------TMS570_POMLOCKACCESS--------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_LOCKACCESS_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_LOCKACCESS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_LOCKACCESS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_POMLOCKSTATUS--------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_LOCKSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_LOCKSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_LOCKSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_POMAUTHSTATUS--------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_AUTHSTATUS_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_AUTHSTATUS_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_AUTHSTATUS_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_POMDEVID----------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_DEVID_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_DEVID_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_DEVID_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_POMDEVTYPE---------------------*/
+/* field: Sub_Type - Other */
+#define TMS570_POM_DEVTYPE_Sub_Type(val) BSP_FLD32(val,4, 7)
+#define TMS570_POM_DEVTYPE_Sub_Type_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_POM_DEVTYPE_Sub_Type_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: Major_Type - Debug Control */
+#define TMS570_POM_DEVTYPE_Major_Type(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_DEVTYPE_Major_Type_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_DEVTYPE_Major_Type_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_POMPERIPHERALID4------------------*/
+/* field: 4KB_Count - Only 4KB implemented */
+#define TMS570_POM_PERIPHERALID4_4KB_Count(val) BSP_FLD32(val,4, 7)
+#define TMS570_POM_PERIPHERALID4_4KB_Count_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_POM_PERIPHERALID4_4KB_Count_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: JEP_Continuation - JEP106 Code */
+#define TMS570_POM_PERIPHERALID4_JEP_Continuation(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_PERIPHERALID4_JEP_Continuation_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_PERIPHERALID4_JEP_Continuation_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_POMPERIPHERALID5------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_PERIPHERALID5_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_PERIPHERALID5_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_PERIPHERALID5_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_POMPERIPHERALID6------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_PERIPHERALID6_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_PERIPHERALID6_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_PERIPHERALID6_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_POMPERIPHERALID7------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_PERIPHERALID7_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_PERIPHERALID7_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_PERIPHERALID7_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_POMPERIPHERALID0------------------*/
+/* field: Part_Number - Reads 0, since POMREV defines the module */
+#define TMS570_POM_PERIPHERALID0_Part_Number(val) BSP_FLD32(val,0, 7)
+#define TMS570_POM_PERIPHERALID0_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_POM_PERIPHERALID0_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------TMS570_POMPERIPHERALID1------------------*/
+/* field: JEP106_Identity - Part of TI JEDEC number */
+#define TMS570_POM_PERIPHERALID1_JEP106_Identity(val) BSP_FLD32(val,4, 7)
+#define TMS570_POM_PERIPHERALID1_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_POM_PERIPHERALID1_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: Part_Number - Reads 0, since POMREV defines the module */
+#define TMS570_POM_PERIPHERALID1_Part_Number(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_PERIPHERALID1_Part_Number_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_PERIPHERALID1_Part_Number_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_POMPERIPHERALID2------------------*/
+/* field: Revision - Reads 0, since POMREV defines the module */
+#define TMS570_POM_PERIPHERALID2_Revision(val) BSP_FLD32(val,4, 7)
+#define TMS570_POM_PERIPHERALID2_Revision_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_POM_PERIPHERALID2_Revision_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: JEDEC - Indicates JEDEC assigned value */
+#define TMS570_POM_PERIPHERALID2_JEDEC BSP_FLD32(3)
+
+/* field: JEP106_Identity - JEDEC+JEP106 Identity Code (POMPERIPHERALID2)+JEP106 Identity Code */
+#define TMS570_POM_PERIPHERALID2_JEP106_Identity(val) BSP_FLD32(val,0, 2)
+#define TMS570_POM_PERIPHERALID2_JEP106_Identity_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_POM_PERIPHERALID2_JEP106_Identity_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*------------------TMS570_POMPERIPHERALID3------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_POM_PERIPHERALID3_Reserved(val) BSP_FLD32(val,0, 31)
+#define TMS570_POM_PERIPHERALID3_Reserved_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_POM_PERIPHERALID3_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_POMCOMPONENTID0-------------------*/
+/* field: Preamble - Preamble */
+#define TMS570_POM_COMPONENTID0_Preamble(val) BSP_FLD32(val,0, 7)
+#define TMS570_POM_COMPONENTID0_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_POM_COMPONENTID0_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_POMCOMPONENTID1-------------------*/
+/* field: Component_Class - CoreSight Component */
+#define TMS570_POM_COMPONENTID1_Component_Class(val) BSP_FLD32(val,4, 7)
+#define TMS570_POM_COMPONENTID1_Component_Class_GET(reg) BSP_FLD32GET(reg,4, 7)
+#define TMS570_POM_COMPONENTID1_Component_Class_SET(reg,val) BSP_FLD32SET(reg, val,4, 7)
+
+/* field: Preamble - Preamble */
+#define TMS570_POM_COMPONENTID1_Preamble(val) BSP_FLD32(val,0, 3)
+#define TMS570_POM_COMPONENTID1_Preamble_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_POM_COMPONENTID1_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_POMCOMPONENTID2-------------------*/
+/* field: Preamble - Preamble */
+#define TMS570_POM_COMPONENTID2_Preamble(val) BSP_FLD32(val,0, 7)
+#define TMS570_POM_COMPONENTID2_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_POM_COMPONENTID2_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-------------------TMS570_POMCOMPONENTID3-------------------*/
+/* field: Preamble - Preamble */
+#define TMS570_POM_COMPONENTID3_Preamble(val) BSP_FLD32(val,0, 7)
+#define TMS570_POM_COMPONENTID3_Preamble_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_POM_COMPONENTID3_Preamble_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+
+#endif /* LIBBSP_ARM_tms570_POM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
new file mode 100644
index 0000000..b6ebe49
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rti.h
@@ -0,0 +1,407 @@
+/* The header file is generated by make_header.py from RTI.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_RTI
+#define LIBBSP_ARM_tms570_RTI
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t COMPx; /*RTI Compare x Register*/
+ uint32_t UDCPx; /*RTI Update Compare x Register*/
+} tms570_rti_compare_t;
+
+typedef struct{
+ uint32_t FRCx; /*RTI Free Running Counter x Register*/
+ uint32_t UCx; /*RTI Up Counter x Register*/
+ uint32_t CPUCx; /*RTI Compare Up Counter x Register*/
+ uint8_t reserved1 [4];
+ uint32_t CAFRCx; /*RTI Capture Free Running Counter x Register*/
+ uint32_t CAUCx; /*RTI Capture Up Counter x Register*/
+ uint32_t rsvd[2]; /*Reserved*/
+} tms570_rti_counter_t;
+
+typedef struct{
+ uint32_t GCTRL; /*RTI Global Control Register*/
+ uint32_t TBCTRL; /*RTI Timebase Control Register*/
+ uint32_t CAPCTRL; /*RTI Capture Control Register*/
+ uint32_t COMPCTRL; /*RTI Compare Control Register*/
+ tms570_rti_counter_t CNT[2];/*Counters*/
+ tms570_rti_compare_t CMP[4];/*Compares*/
+ uint32_t TBLCOMP; /*RTI Timebase Low Compare Register*/
+ uint32_t TBHCOMP; /*RTI Timebase High Compare Register*/
+ uint8_t reserved2 [8];
+ uint32_t SETINTENA; /*RTI Set Interrupt Enable Register*/
+ uint32_t CLEARINTENA; /*RTI Clear Interrupt Enable Register*/
+ uint32_t INTFLAG; /*RTI Interrupt Flag Register*/
+ uint8_t reserved3 [4];
+ uint32_t DWDCTRL; /*Digital Watchdog Control Register*/
+ uint32_t DWDPRLD; /*Digital Watchdog Preload Register*/
+ uint32_t WDSTATUS; /*Watchdog Status Register*/
+ uint32_t WDKEY; /*RTI Watchdog Key Register*/
+ uint32_t DWDCNTR; /*RTI Digital Watchdog Down Counter Register*/
+ uint32_t WWDRXNCTRL; /*Digital Windowed Watchdog Reaction Control Register*/
+ uint32_t WWDSIZECTRL; /*Digital Windowed Watchdog Window Size Control Register*/
+ uint32_t INTCLRENABLE; /*RTI Compare Interrupt Clear Enable Register*/
+ uint32_t COMP0CLR; /*RTI Compare 0 Clear Register*/
+ uint32_t COMP1CLR; /*RTI Compare 1 Clear Register*/
+ uint32_t COMP2CLR; /*RTI Compare 2 Clear Register*/
+ uint32_t COMP3CLR; /*RTI Compare 3 Clear Register*/
+} tms570_rti_t;
+
+
+/*----------------------TMS570_RTICOMPx----------------------*/
+/* field: COMPx - Compare x. */
+#define TMS570_RTI_COMPx_COMPx(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_COMPx_COMPx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_COMPx_COMPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_RTIUDCPx----------------------*/
+/* field: UDCPx - Update compare x. */
+#define TMS570_RTI_UDCPx_UDCPx(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_UDCPx_UDCPx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_UDCPx_UDCPx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_RTIFRCx-----------------------*/
+/* field: FRC0 - FRC0 */
+#define TMS570_RTI_FRCx_FRC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_FRCx_FRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_FRCx_FRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_RTIUCx-----------------------*/
+/* field: UC0 - Up counter 0. */
+#define TMS570_RTI_UCx_UC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_UCx_UC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_UCx_UC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_RTICPUCx----------------------*/
+/* field: CPUC0 - Compare up counter 0. This register holds the value that is compared with the up counter 0. */
+#define TMS570_RTI_CPUCx_CPUC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_CPUCx_CPUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_CPUCx_CPUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_RTICAFRCx----------------------*/
+/* field: CAFRC0 - Capture free running counter 0. */
+#define TMS570_RTI_CAFRCx_CAFRC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_CAFRCx_CAFRC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_CAFRCx_CAFRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_RTICAUCx----------------------*/
+/* field: CAUC0 - Capture up counter 0. */
+#define TMS570_RTI_CAUCx_CAUC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_CAUCx_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_CAUCx_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_RTIrsvd-----------------------*/
+/* field: CAUC0 - Capture up counter 0. */
+#define TMS570_RTI_rsvd_CAUC0(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_rsvd_CAUC0_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_rsvd_CAUC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_RTIGCTRL----------------------*/
+/* field: NTUSEL - Select NTU signal. */
+#define TMS570_RTI_GCTRL_NTUSEL(val) BSP_FLD32(val,16, 19)
+#define TMS570_RTI_GCTRL_NTUSEL_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_RTI_GCTRL_NTUSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: COS - Continue on suspend. */
+#define TMS570_RTI_GCTRL_COS BSP_FLD32(15)
+
+/* field: CNT1EN - Counter 1 enable. This bit starts and stops counter block 1 (RTIUC1 and RTIFRC1). */
+#define TMS570_RTI_GCTRL_CNT1EN BSP_FLD32(1)
+
+/* field: CNT0EN - Counter 0 enable. This bit starts and stops counter block 0 (RTIUC0 and RTIFRC0). */
+#define TMS570_RTI_GCTRL_CNT0EN BSP_FLD32(0)
+
+
+/*----------------------TMS570_RTITBCTRL----------------------*/
+/* field: INC - Increment free running counter 0. */
+#define TMS570_RTI_TBCTRL_INC BSP_FLD32(1)
+
+/* field: TBEXT - Timebase external. */
+#define TMS570_RTI_TBCTRL_TBEXT BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTICAPCTRL---------------------*/
+/* field: CAPCNTR1 - Capture counter 1. */
+#define TMS570_RTI_CAPCTRL_CAPCNTR1 BSP_FLD32(1)
+
+/* field: CAPCNTR0 - Capture counter 0. */
+#define TMS570_RTI_CAPCTRL_CAPCNTR0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTICOMPCTRL---------------------*/
+/* field: COMPSEL3 - Compare select 3. */
+#define TMS570_RTI_COMPCTRL_COMPSEL3 BSP_FLD32(12)
+
+/* field: COMPSEL2 - Compare select 2. */
+#define TMS570_RTI_COMPCTRL_COMPSEL2 BSP_FLD32(8)
+
+/* field: COMPSEL1 - Compare select 1. */
+#define TMS570_RTI_COMPCTRL_COMPSEL1 BSP_FLD32(4)
+
+/* field: COMPSEL0 - Compare select 0. */
+#define TMS570_RTI_COMPCTRL_COMPSEL0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTITBLCOMP---------------------*/
+/* field: TBLCOMP - Timebase low compare value. */
+#define TMS570_RTI_TBLCOMP_TBLCOMP(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_TBLCOMP_TBLCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_TBLCOMP_TBLCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_RTITBHCOMP---------------------*/
+/* field: TBHCOMP - Timebase high compare value. */
+#define TMS570_RTI_TBHCOMP_TBHCOMP(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_TBHCOMP_TBHCOMP_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_TBHCOMP_TBHCOMP_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_RTISETINTENA--------------------*/
+/* field: SETOVL1INT - Set free running counter 1 overflow interrupt. */
+#define TMS570_RTI_SETINTENA_SETOVL1INT BSP_FLD32(18)
+
+/* field: SETOVL0INT - Set free running counter 0 overflow interrupt. */
+#define TMS570_RTI_SETINTENA_SETOVL0INT BSP_FLD32(17)
+
+/* field: SETTBINT - Set timebase interrupt. */
+#define TMS570_RTI_SETINTENA_SETTBINT BSP_FLD32(16)
+
+/* field: SETDMA3 - Set compare DMA request 3. */
+#define TMS570_RTI_SETINTENA_SETDMA3 BSP_FLD32(11)
+
+/* field: SETDMA2 - Set compare DMA request 2. */
+#define TMS570_RTI_SETINTENA_SETDMA2 BSP_FLD32(10)
+
+/* field: SETDMA1 - Set compare DMA request 1. */
+#define TMS570_RTI_SETINTENA_SETDMA1 BSP_FLD32(9)
+
+/* field: SETDMA0 - Set compare DMA request 0. */
+#define TMS570_RTI_SETINTENA_SETDMA0 BSP_FLD32(8)
+
+/* field: SETINT3 - Set compare interrupt 3. */
+#define TMS570_RTI_SETINTENA_SETINT3 BSP_FLD32(3)
+
+/* field: SETINT2 - Set compare interrupt 2. */
+#define TMS570_RTI_SETINTENA_SETINT2 BSP_FLD32(2)
+
+/* field: SETINT1 - Set compare interrupt 1. */
+#define TMS570_RTI_SETINTENA_SETINT1 BSP_FLD32(1)
+
+/* field: SETINT0 - Set compare interrupt 0. */
+#define TMS570_RTI_SETINTENA_SETINT0 BSP_FLD32(0)
+
+
+/*-------------------TMS570_RTICLEARINTENA-------------------*/
+/* field: CLEAROVL1INT - Clear free running counter 1 overflow interrupt. */
+#define TMS570_RTI_CLEARINTENA_CLEAROVL1INT BSP_FLD32(18)
+
+/* field: CLEAROVL0INT - Clear free running counter 0 overflow interrupt. */
+#define TMS570_RTI_CLEARINTENA_CLEAROVL0INT BSP_FLD32(17)
+
+/* field: CLEARTBINT - Clear timebase interrupt. */
+#define TMS570_RTI_CLEARINTENA_CLEARTBINT BSP_FLD32(16)
+
+/* field: CLEARDMA3 - Clear compare DMA request 3. */
+#define TMS570_RTI_CLEARINTENA_CLEARDMA3 BSP_FLD32(11)
+
+/* field: CLEARDMA2 - Clear compare DMA request 2. */
+#define TMS570_RTI_CLEARINTENA_CLEARDMA2 BSP_FLD32(10)
+
+/* field: CLEARDMA1 - Clear compare DMA request 1. */
+#define TMS570_RTI_CLEARINTENA_CLEARDMA1 BSP_FLD32(9)
+
+/* field: CLEARDMA0 - Clear compare DMA request 0. */
+#define TMS570_RTI_CLEARINTENA_CLEARDMA0 BSP_FLD32(8)
+
+/* field: CLEARINT3 - Clear compare interrupt 3. */
+#define TMS570_RTI_CLEARINTENA_CLEARINT3 BSP_FLD32(3)
+
+/* field: CLEARINT2 - Clear compare interrupt 2. */
+#define TMS570_RTI_CLEARINTENA_CLEARINT2 BSP_FLD32(2)
+
+/* field: CLEARINT1 - Clear compare interrupt 1. */
+#define TMS570_RTI_CLEARINTENA_CLEARINT1 BSP_FLD32(1)
+
+/* field: CLEARINT0 - Clear compare interrupt 0. */
+#define TMS570_RTI_CLEARINTENA_CLEARINT0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTIINTFLAG---------------------*/
+/* field: OVL1INT - Free running counter 1 overflow interrupt flag. This bit determines if an interrupt is pending. */
+#define TMS570_RTI_INTFLAG_OVL1INT BSP_FLD32(18)
+
+/* field: OVL0INT - Free running counter 0 overflow interrupt flag. This bit determines if an interrupt is pending. */
+#define TMS570_RTI_INTFLAG_OVL0INT BSP_FLD32(17)
+
+/* field: TBINT - Timebase interrupt flag. */
+#define TMS570_RTI_INTFLAG_TBINT BSP_FLD32(16)
+
+/* field: INT3 - Interrupt flag 3. These bits determine if an interrupt due to a Compare 3 match is pending. */
+#define TMS570_RTI_INTFLAG_INT3 BSP_FLD32(3)
+
+/* field: INT2 - Interrupt flag 2. These bits determine if an interrupt due to a Compare 2 match is pending. */
+#define TMS570_RTI_INTFLAG_INT2 BSP_FLD32(2)
+
+/* field: INT1 - Interrupt flag 1. These bits determine if an interrupt due to a Compare 1 match is pending. */
+#define TMS570_RTI_INTFLAG_INT1 BSP_FLD32(1)
+
+/* field: INT0 - Interrupt flag 0. These bits determine if an interrupt due to a Compare 0 match is pending. */
+#define TMS570_RTI_INTFLAG_INT0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTIDWDCTRL---------------------*/
+/* field: DWDCTRL - DWDCTRL Digital Watchdog Control. */
+#define TMS570_RTI_DWDCTRL_DWDCTRL(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_DWDCTRL_DWDCTRL_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_DWDCTRL_DWDCTRL_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_RTIDWDPRLD---------------------*/
+/* field: DWDPRLD - Digital Watchdog Preload Value. */
+#define TMS570_RTI_DWDPRLD_DWDPRLD(val) BSP_FLD32(val,0, 15)
+#define TMS570_RTI_DWDPRLD_DWDPRLD_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_RTI_DWDPRLD_DWDPRLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_RTIWDSTATUS---------------------*/
+/* field: DWWD_ST - Windowed Watchdog Status */
+#define TMS570_RTI_WDSTATUS_DWWD_ST BSP_FLD32(5)
+
+/* field: END_TIME_VIOL - Windowed Watchdog End Time Violation Status. */
+#define TMS570_RTI_WDSTATUS_END_TIME_VIOL BSP_FLD32(4)
+
+/* field: START_TIME_VIOL - Windowed Watchdog Start Time Violation Status. */
+#define TMS570_RTI_WDSTATUS_START_TIME_VIOL BSP_FLD32(3)
+
+/* field: KEY_ST - Watchdog key status. */
+#define TMS570_RTI_WDSTATUS_KEY_ST BSP_FLD32(2)
+
+/* field: DWD_ST - DWD status. */
+#define TMS570_RTI_WDSTATUS_DWD_ST BSP_FLD32(1)
+
+
+/*----------------------TMS570_RTIWDKEY----------------------*/
+/* field: WDKEY - Watchdog key. These bits provide the key sequence location. */
+#define TMS570_RTI_WDKEY_WDKEY(val) BSP_FLD32(val,0, 15)
+#define TMS570_RTI_WDKEY_WDKEY_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_RTI_WDKEY_WDKEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_RTIDWDCNTR---------------------*/
+/* field: DWDCNTR - DWD down counter. */
+#define TMS570_RTI_DWDCNTR_DWDCNTR(val) BSP_FLD32(val,0, 24)
+#define TMS570_RTI_DWDCNTR_DWDCNTR_GET(reg) BSP_FLD32GET(reg,0, 24)
+#define TMS570_RTI_DWDCNTR_DWDCNTR_SET(reg,val) BSP_FLD32SET(reg, val,0, 24)
+
+
+/*--------------------TMS570_RTIWWDRXNCTRL--------------------*/
+/* field: WWDRXN - The DWWD reaction */
+#define TMS570_RTI_WWDRXNCTRL_WWDRXN(val) BSP_FLD32(val,0, 3)
+#define TMS570_RTI_WWDRXNCTRL_WWDRXN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_RTI_WWDRXNCTRL_WWDRXN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_RTIWWDSIZECTRL-------------------*/
+/* field: WWDSIZE - The DWWD window size */
+#define TMS570_RTI_WWDSIZECTRL_WWDSIZE(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_WWDSIZECTRL_WWDSIZE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-------------------TMS570_RTIINTCLRENABLE-------------------*/
+/* field: INTCLRENABLE3 - Enables the auto-clear functionality on the compare 3 interrupt. */
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE3_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: INTCLRENABLE2 - Enables the auto-clear functionality on the compare 2 interrupt. */
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2(val) BSP_FLD32(val,16, 19)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE2_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: INTCLRENABLE1 - Enables the auto-clear functionality on the compare 1 interrupt. */
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1(val) BSP_FLD32(val,8, 11)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE1_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: INTCLRENABLE0 - Enables the auto-clear functionality on the compare 0 interrupt. */
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0(val) BSP_FLD32(val,0, 3)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_RTI_INTCLRENABLE_INTCLRENABLE0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_RTICOMP0CLR---------------------*/
+/* field: CMP0CLR - Compare 0 clear. */
+#define TMS570_RTI_COMP0CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_COMP0CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_COMP0CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_RTICOMP1CLR---------------------*/
+/* field: CMP0CLR - Compare 1 clear. */
+#define TMS570_RTI_COMP1CLR_CMP0CLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_COMP1CLR_CMP0CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_COMP1CLR_CMP0CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_RTICOMP2CLR---------------------*/
+/* field: CMP2CLR - Compare 2 clear. */
+#define TMS570_RTI_COMP2CLR_CMP2CLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_COMP2CLR_CMP2CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_COMP2CLR_CMP2CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_RTICOMP3CLR---------------------*/
+/* field: CMP3CLR - Compare 3 clear. */
+#define TMS570_RTI_COMP3CLR_CMP3CLR(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTI_COMP3CLR_CMP3CLR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTI_COMP3CLR_CMP3CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_RTI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
new file mode 100644
index 0000000..1faee61
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_rtp.h
@@ -0,0 +1,230 @@
+/* The header file is generated by make_header.py from RTP.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_RTP
+#define LIBBSP_ARM_tms570_RTP
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GLBCTRL; /*RTP Global Control Register*/
+ uint32_t TRENA; /*RTP Trace Enable Register*/
+ uint32_t GSR; /*RTP Global Status Register*/
+ uint32_t RAM1REG1; /*RTP RAM 1 Trace Region 1 Register*/
+ uint32_t RAM1REG2; /*RTP RAM 1 Trace Region 2 Register*/
+ uint32_t RAM2REG1; /*RTP RAM 2 Trace Region 1 Register*/
+ uint32_t RAM2REG2; /*RTP RAM 2 Trace Region 2 Register*/
+ uint8_t reserved1 [8];
+ uint32_t PERREG1; /*RTP Peripheral Trace Region 1 Register*/
+ uint32_t PERREG2; /*RTP Peripheral Trace Region 2 Register*/
+ uint32_t DDMW; /*RTP Direct Data Mode Write Register*/
+ uint8_t reserved2 [4];
+ uint32_t PC0; /*RTP Pin Control 0 Register*/
+ uint32_t PC1; /*RTP Pin Control 1 Register*/
+ uint32_t PC2; /*RTP Pin Control 2 Register*/
+ uint32_t PC3; /*RTP Pin Control 3 Register*/
+ uint32_t PC4; /*RTP Pin Control 4 Register*/
+ uint32_t PC5; /*RTP Pin Control 5 Register*/
+ uint32_t PC6; /*RTP Pin Control 6 Register*/
+ uint32_t PC7; /*RTP Pin Control 7 Register*/
+ uint32_t PC8; /*RTP Pin Control 8 Register*/
+} tms570_rtp_t;
+
+
+/*---------------------TMS570_RTPGLBCTRL---------------------*/
+/* field: TEST - By setting the bit, the FIFO RAM will be mapped into the SYSTEM Peripheral frame starting at */
+#define TMS570_RTP_GLBCTRL_TEST BSP_FLD32(24)
+
+/* field: PRESCALER - The prescaler divides HCLK down to the desired RTPCLK frequency. */
+#define TMS570_RTP_GLBCTRL_PRESCALER(val) BSP_FLD32(val,16, 18)
+#define TMS570_RTP_GLBCTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_RTP_GLBCTRL_PRESCALER_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: DDM_WIDTH - Direct data mode word size width. */
+#define TMS570_RTP_GLBCTRL_DDM_WIDTH(val) BSP_FLD32(val,12, 13)
+#define TMS570_RTP_GLBCTRL_DDM_WIDTH_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_RTP_GLBCTRL_DDM_WIDTH_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: DDM_RW - */
+#define TMS570_RTP_GLBCTRL_DDM_RW BSP_FLD32(11)
+
+/* field: TM_DDM - Trace Mode or Direct Data Mode */
+#define TMS570_RTP_GLBCTRL_TM_DDM BSP_FLD32(10)
+
+/* field: PW - Port width. This bit field configures the RTP to the desired port width. */
+#define TMS570_RTP_GLBCTRL_PW(val) BSP_FLD32(val,8, 9)
+#define TMS570_RTP_GLBCTRL_PW_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_RTP_GLBCTRL_PW_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: RESET - This bit resets the state machine and the registers to their reset value. */
+#define TMS570_RTP_GLBCTRL_RESET BSP_FLD32(7)
+
+/* field: CONTCLK - Continuous RTPCLK enable. */
+#define TMS570_RTP_GLBCTRL_CONTCLK BSP_FLD32(6)
+
+/* field: HOVF - Halt on overflow. */
+#define TMS570_RTP_GLBCTRL_HOVF BSP_FLD32(5)
+
+/* field: INV_RGN - Trace inside or outside of defined trace regions. */
+#define TMS570_RTP_GLBCTRL_INV_RGN BSP_FLD32(4)
+
+/* field: ON_OFF - ON/Off switch. */
+#define TMS570_RTP_GLBCTRL_ON_OFF(val) BSP_FLD32(val,0, 3)
+#define TMS570_RTP_GLBCTRL_ON_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_RTP_GLBCTRL_ON_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_RTPTRENA----------------------*/
+/* field: ENA4 - Enable tracing for peripherals. */
+#define TMS570_RTP_TRENA_ENA4 BSP_FLD32(24)
+
+/* field: ENA2 - Enable tracing for RAM block 2. */
+#define TMS570_RTP_TRENA_ENA2 BSP_FLD32(8)
+
+/* field: ENA1 - */
+#define TMS570_RTP_TRENA_ENA1 BSP_FLD32(0)
+
+
+/*-----------------------TMS570_RTPGSR-----------------------*/
+/* field: EMPTYSER - Serializer empty. This bit determines if there is data left in the serializer. */
+#define TMS570_RTP_GSR_EMPTYSER BSP_FLD32(12)
+
+/* field: EMPTYPER - Peripheral FIFO empty. This bit determines if there are entries left in the FIFO. */
+#define TMS570_RTP_GSR_EMPTYPER BSP_FLD32(11)
+
+/* field: EMPTY2 - RAM block 2 FIFO empty. This bit determines if there are entries left in the FIFO. */
+#define TMS570_RTP_GSR_EMPTY2 BSP_FLD32(9)
+
+/* field: EMPTY1 - RAM block 1 FIFO empty. This bit determines if there are entries left in the FIFO. */
+#define TMS570_RTP_GSR_EMPTY1 BSP_FLD32(8)
+
+/* field: OVFPER - Overflow peripheral FIFO. */
+#define TMS570_RTP_GSR_OVFPER BSP_FLD32(3)
+
+/* field: OVF2 - Overflow RAM block 2 FIFO. */
+#define TMS570_RTP_GSR_OVF2 BSP_FLD32(1)
+
+/* field: OVF1 - Overflow RAM block 1 FIFO. */
+#define TMS570_RTP_GSR_OVF1 BSP_FLD32(0)
+
+
+/*---------------------TMS570_RTPRAM1REG1---------------------*/
+/* field: CPU_DMA - CPU and/or other master access. */
+#define TMS570_RTP_RAM1REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM1REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM1REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
+/* field: RW - Read/Write. */
+#define TMS570_RTP_RAM1REG1_RW BSP_FLD32(28)
+
+/* field: BLOCKSIZE - These bits define the length of the trace region. */
+#define TMS570_RTP_RAM1REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM1REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM1REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
+#define TMS570_RTP_RAM1REG1_STARTADDR(val) BSP_FLD32(val,0, 17)
+#define TMS570_RTP_RAM1REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 17)
+#define TMS570_RTP_RAM1REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 17)
+
+
+/*---------------------TMS570_RTPRAM2REG1---------------------*/
+/* field: CPU_DMA - CPU and/or other master access. */
+#define TMS570_RTP_RAM2REG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_RAM2REG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_RAM2REG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
+/* field: RW - Read/Write. */
+#define TMS570_RTP_RAM2REG1_RW BSP_FLD32(28)
+
+/* field: BLOCKSIZE - These bits define the length of the trace region. */
+#define TMS570_RTP_RAM2REG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_RAM2REG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_RAM2REG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
+#define TMS570_RTP_RAM2REG1_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_RAM2REG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_RAM2REG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*---------------------TMS570_RTPPERREG1---------------------*/
+/* field: CPU_DMA - CPU and/or other master access. */
+#define TMS570_RTP_PERREG1_CPU_DMA(val) BSP_FLD32(val,29, 30)
+#define TMS570_RTP_PERREG1_CPU_DMA_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_RTP_PERREG1_CPU_DMA_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
+/* field: RW - Read/Write. */
+#define TMS570_RTP_PERREG1_RW BSP_FLD32(28)
+
+/* field: BLOCKSIZE - These bits define the length of the trace region. */
+#define TMS570_RTP_PERREG1_BLOCKSIZE(val) BSP_FLD32(val,24, 27)
+#define TMS570_RTP_PERREG1_BLOCKSIZE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_RTP_PERREG1_BLOCKSIZE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: STARTADDR - These bits define the starting address of the address region that should be traced. */
+#define TMS570_RTP_PERREG1_STARTADDR(val) BSP_FLD32(val,0, 23)
+#define TMS570_RTP_PERREG1_STARTADDR_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_RTP_PERREG1_STARTADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*-----------------------TMS570_RTPDDMW-----------------------*/
+/* field: DATA - This register must be written to in a Direct Data Mode write operation to store the data into */
+#define TMS570_RTP_DDMW_DATA(val) BSP_FLD32(val,0, 31)
+#define TMS570_RTP_DDMW_DATA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_RTP_DDMW_DATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*-----------------------TMS570_RTPPC0-----------------------*/
+/* field: ENAFUNC - Functional mode of RTPENA pin. */
+#define TMS570_RTP_PC0_ENAFUNC BSP_FLD32(18)
+
+/* field: CLKFUNC - Functional mode of RTPCLK pin. */
+#define TMS570_RTP_PC0_CLKFUNC BSP_FLD32(17)
+
+/* field: SYNCFUNC - Functional mode of RTPSYNC pin. */
+#define TMS570_RTP_PC0_SYNCFUNC BSP_FLD32(16)
+
+/* field: DATAFUNC - Functional mode of RTPDATA[15:0] pins. */
+#define TMS570_RTP_PC0_DATAFUNC(val) BSP_FLD32(val,0, 15)
+#define TMS570_RTP_PC0_DATAFUNC_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_RTP_PC0_DATAFUNC_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+
+#endif /* LIBBSP_ARM_tms570_RTP */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
new file mode 100644
index 0000000..e4e4eb3
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sci.h
@@ -0,0 +1,450 @@
+/* The header file is generated by make_header.py from SCI.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_SCI
+#define LIBBSP_ARM_tms570_SCI
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GCR0; /*SCI Global Control Register 0*/
+ uint32_t GCR1; /*SCI Global Control Register 1*/
+ uint32_t GCR2; /*SCI Global Control Register 2*/
+ uint32_t SETINT; /*SCI Set Interrupt Register*/
+ uint32_t CLEARINT; /*SCI Clear Interrupt Register*/
+ uint32_t SETINTLVL; /*SCI Set Interrupt Level Register*/
+ uint32_t CLEARINTLVL; /*SCI Clear Interrupt Level Register*/
+ uint32_t FLR; /*SCI Flags Register*/
+ uint32_t INTVECT0; /*SCI Interrupt Vector Offset 0*/
+ uint32_t INTVECT1; /*SCI Interrupt Vector Offset 1*/
+ uint32_t FORMAT; /*SCI Format Control Register*/
+ uint32_t BRS; /*Baud Rate Selection Register*/
+ uint32_t ED; /*Receiver Emulation Data Buffer*/
+ uint32_t RD; /*Receiver Data Buffer*/
+ uint32_t TD; /*Transmit Data Buffer*/
+ uint32_t PIO0; /*SCI Pin I/O Control Register 0*/
+ uint32_t PIO1; /*SCI Pin I/O Control Register 1*/
+ uint32_t PIO2; /*SCI Pin I/O Control Register 2*/
+ uint32_t PIO3; /*SCI Pin I/O Control Register 3*/
+ uint32_t PIO4; /*SCI Pin I/O Control Register 4*/
+ uint32_t PIO5; /*SCI Pin I/O Control Register 5*/
+ uint32_t PIO6; /*SCI Pin I/O Control Register 6*/
+ uint32_t PIO7; /*SCI Pin I/O Control Register 7*/
+ uint32_t PIO8; /*SCI Pin I/O Control Register 8*/
+ uint8_t reserved1 [48];
+ uint32_t IODFTCTRL; /*Input/Output Error Enable Register*/
+} tms570_sci_t;
+
+
+/*-----------------------TMS570_SCIGCR0-----------------------*/
+/* field: Reserved - Read returns 0. Writes have no effect. */
+#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
+#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
+#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
+
+/* field: RESET - This bit resets the SCI module. */
+#define TMS570_SCI_GCR0_RESET BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SCIGCR1-----------------------*/
+/* field: TXENA - Transmit enable. */
+#define TMS570_SCI_GCR1_TXENA BSP_FLD32(25)
+
+/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
+#define TMS570_SCI_GCR1_RXENA BSP_FLD32(24)
+
+/* field: CONT - Continue on suspend. */
+#define TMS570_SCI_GCR1_CONT BSP_FLD32(17)
+
+/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
+#define TMS570_SCI_GCR1_LOOP_BACK BSP_FLD32(16)
+
+/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
+#define TMS570_SCI_GCR1_POWERDOWN BSP_FLD32(9)
+
+/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
+#define TMS570_SCI_GCR1_SLEEP BSP_FLD32(8)
+
+/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
+#define TMS570_SCI_GCR1_SWnRST BSP_FLD32(7)
+
+/* field: CLOCK - CLOCK */
+#define TMS570_SCI_GCR1_CLOCK BSP_FLD32(5)
+
+/* field: STOP - SCI number of stop bits per frame. */
+#define TMS570_SCI_GCR1_STOP BSP_FLD32(4)
+
+/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
+#define TMS570_SCI_GCR1_PARITY BSP_FLD32(3)
+
+/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
+#define TMS570_SCI_GCR1_PARITY_ENA BSP_FLD32(2)
+
+/* field: TIMING_MODE - SCI timing mode bit. */
+#define TMS570_SCI_GCR1_TIMING_MODE BSP_FLD32(1)
+
+/* field: COMM_MODE - SCI communication mode bit. */
+#define TMS570_SCI_GCR1_COMM_MODE BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SCIGCR2-----------------------*/
+/* field: CC - Compare checksum. LIN mode only. */
+#define TMS570_SCI_GCR2_CC BSP_FLD32(17)
+
+/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
+#define TMS570_SCI_GCR2_SC BSP_FLD32(16)
+
+/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
+#define TMS570_SCI_GCR2_GEN_WU BSP_FLD32(8)
+
+/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
+#define TMS570_SCI_GCR2_POWERDOWN BSP_FLD32(0)
+
+
+/*----------------------TMS570_SCISETINT----------------------*/
+/* field: SET_FE_INT - */
+#define TMS570_SCI_SETINT_SET_FE_INT BSP_FLD32(26)
+
+/* field: SET_OE_INT - SET OE INT */
+#define TMS570_SCI_SETINT_SET_OE_INT BSP_FLD32(25)
+
+/* field: SET_PE_INT - Set parity interrupt. */
+#define TMS570_SCI_SETINT_SET_PE_INT BSP_FLD32(24)
+
+/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
+#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_FLD32(18)
+
+/* field: SET_RX_DMA - SET RX DMA */
+#define TMS570_SCI_SETINT_SET_RX_DMA BSP_FLD32(17)
+
+/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
+#define TMS570_SCI_SETINT_SET_TX_DMA BSP_FLD32(16)
+
+/* field: SET_RX_INT - SET RX INT */
+#define TMS570_SCI_SETINT_SET_RX_INT BSP_FLD32(9)
+
+/* field: SET_TX_INT - Set transmitter interrupt. */
+#define TMS570_SCI_SETINT_SET_TX_INT BSP_FLD32(8)
+
+/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
+#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_FLD32(1)
+
+/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
+#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_FLD32(0)
+
+
+/*---------------------TMS570_SCICLEARINT---------------------*/
+/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_FLD32(26)
+
+/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_FLD32(25)
+
+/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_FLD32(24)
+
+/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_FLD32(18)
+
+/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
+#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_FLD32(17)
+
+/* field: CLR_TX_DMA - CLR TX DMA */
+#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_FLD32(16)
+
+/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_FLD32(9)
+
+/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_FLD32(8)
+
+/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_FLD32(1)
+
+/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
+#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_FLD32(0)
+
+
+/*--------------------TMS570_SCISETINTLVL--------------------*/
+/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_FLD32(26)
+
+/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_FLD32(25)
+
+/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_FLD32(24)
+
+/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
+#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_FLD32(18)
+
+/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_FLD32(9)
+
+/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_FLD32(8)
+
+/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
+#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_FLD32(1)
+
+/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
+#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_FLD32(0)
+
+
+/*-------------------TMS570_SCICLEARINTLVL-------------------*/
+/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
+#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_FLD32(26)
+
+/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+
+/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
+#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_FLD32(25)
+
+/* field: CLR_PE_INT_LVL - */
+#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_FLD32(24)
+
+/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_FLD32(18)
+
+/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
+#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_FLD32(9)
+
+/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
+#define TMS570_SCI_CLEARINTLVL_8 BSP_FLD32(8)
+
+/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
+#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_FLD32(1)
+
+/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
+#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SCIFLR-----------------------*/
+/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
+#define TMS570_SCI_FLR_FE BSP_FLD32(26)
+
+/* field: OE - Overrun error flag. */
+#define TMS570_SCI_FLR_OE BSP_FLD32(25)
+
+/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
+#define TMS570_SCI_FLR_PE BSP_FLD32(24)
+
+/* field: RXWAKE - Receiver wakeup detect flag. */
+#define TMS570_SCI_FLR_RXWAKE BSP_FLD32(12)
+
+/* field: TX_EMPTY - Transmitter empty flag. */
+#define TMS570_SCI_FLR_TX_EMPTY BSP_FLD32(11)
+
+/* field: TXWAKE - Transmitter wakeup method select. */
+#define TMS570_SCI_FLR_TXWAKE BSP_FLD32(10)
+
+/* field: RXRDY - Receiver ready flag. */
+#define TMS570_SCI_FLR_RXRDY BSP_FLD32(9)
+
+/* field: TXRDY - Transmitter buffer register ready flag. */
+#define TMS570_SCI_FLR_TXRDY BSP_FLD32(8)
+
+/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
+#define TMS570_SCI_FLR_BUSY BSP_FLD32(3)
+
+/* field: IDLE - SCI receiver in idle state. */
+#define TMS570_SCI_FLR_IDLE BSP_FLD32(2)
+
+/* field: WAKEUP - Wakeup flag. */
+#define TMS570_SCI_FLR_WAKEUP BSP_FLD32(1)
+
+/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
+#define TMS570_SCI_FLR_BRKDT BSP_FLD32(0)
+
+
+/*---------------------TMS570_SCIINTVECT0---------------------*/
+/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
+#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
+#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SCIINTVECT1---------------------*/
+/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
+#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
+#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_SCIFORMAT----------------------*/
+/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
+#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
+#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*-----------------------TMS570_SCIBRS-----------------------*/
+/* field: BAUD - SCI 24-bit baud selection. */
+#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
+#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
+#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
+
+
+/*------------------------TMS570_SCIED------------------------*/
+/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
+#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
+#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------------TMS570_SCIRD------------------------*/
+/* field: RD - Receiver data. */
+#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
+#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*------------------------TMS570_SCITD------------------------*/
+/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
+#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
+#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SCIPIO0-----------------------*/
+/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
+#define TMS570_SCI_PIO0_TX_FUNC BSP_FLD32(2)
+
+/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
+#define TMS570_SCI_PIO0_RX_FUNC BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO1-----------------------*/
+/* field: TX_DIR - Transmit pin direction. */
+#define TMS570_SCI_PIO1_TX_DIR BSP_FLD32(2)
+
+/* field: RX_DIR - Receive pin direction. */
+#define TMS570_SCI_PIO1_RX_DIR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO2-----------------------*/
+/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
+#define TMS570_SCI_PIO2_TX_IN BSP_FLD32(2)
+
+/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
+#define TMS570_SCI_PIO2_RX_IN BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO3-----------------------*/
+/* field: TX_OUT - Transmit pin out. */
+#define TMS570_SCI_PIO3_TX_OUT BSP_FLD32(2)
+
+/* field: RX_OUT - Receive pin out. */
+#define TMS570_SCI_PIO3_RX_OUT BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO4-----------------------*/
+/* field: TX_SET - Transmit pin set. */
+#define TMS570_SCI_PIO4_TX_SET BSP_FLD32(2)
+
+/* field: RX_SET - Receive pin set. */
+#define TMS570_SCI_PIO4_RX_SET BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO5-----------------------*/
+/* field: TX_CLR - Transmit pin clear. */
+#define TMS570_SCI_PIO5_TX_CLR BSP_FLD32(2)
+
+/* field: RX_CLR - Receive pin clear. */
+#define TMS570_SCI_PIO5_RX_CLR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO6-----------------------*/
+/* field: TX_PDR - Transmit pin open drain enable. */
+#define TMS570_SCI_PIO6_TX_PDR BSP_FLD32(2)
+
+/* field: RX_PDR - Receive pin open drain enable. */
+#define TMS570_SCI_PIO6_RX_PDR BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO7-----------------------*/
+/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
+#define TMS570_SCI_PIO7_TX_PD BSP_FLD32(2)
+
+/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
+#define TMS570_SCI_PIO7_RX_PD BSP_FLD32(1)
+
+
+/*-----------------------TMS570_SCIPIO8-----------------------*/
+/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
+#define TMS570_SCI_PIO8_TX_PSL BSP_FLD32(2)
+
+/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
+#define TMS570_SCI_PIO8_RX_PSL BSP_FLD32(1)
+
+
+/*--------------------TMS570_SCIIODFTCTRL--------------------*/
+/* field: FEN - Frame error enable. This bit is used to create a frame error. */
+#define TMS570_SCI_IODFTCTRL_FEN BSP_FLD32(26)
+
+/* field: PEN - Parity error enable. This bit is used to create a parity error. */
+#define TMS570_SCI_IODFTCTRL_PEN BSP_FLD32(25)
+
+/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
+#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_FLD32(24)
+
+/* field: PIN_SAMPLE_MASK - Pin sample mask. */
+#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
+#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20)
+#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20)
+
+/* field: TX_SHIFT - Transmit shift. */
+#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18)
+#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18)
+#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
+
+/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */
+#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11)
+#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
+#define TMS570_SCI_IODFTCTRL_LPBENA BSP_FLD32(1)
+
+/* field: RXPENA - Module analog loopback through receive pin enable. */
+#define TMS570_SCI_IODFTCTRL_RXPENA BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_SCI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
new file mode 100644
index 0000000..a92c0a8
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_spi.h
@@ -0,0 +1,918 @@
+/* The header file is generated by make_header.py from SPI.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_SPI
+#define LIBBSP_ARM_tms570_SPI
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t GCR0; /*SPI Global Control Register 0*/
+ uint32_t GCR1; /*SPI Global Control Register 1*/
+ uint32_t INT0; /*SPI Interrupt Register*/
+ uint32_t LVL; /*SPI Interrupt Level Register*/
+ uint32_t FLG; /*SPI Flag Register*/
+ uint32_t PC0; /*SPI Pin Control Register 0*/
+ uint32_t PC1; /*SPI Pin Control Register 1*/
+ uint32_t PC2; /*SPI Pin Control Register 2*/
+ uint32_t PC3; /*SPI Pin Control Register 3*/
+ uint32_t PC4; /*SPI Pin Control Register 4*/
+ uint32_t PC5; /*SPI Pin Control Register 5*/
+ uint32_t PC6; /*SPI Pin Control Register 6*/
+ uint32_t PC7; /*SPI Pin Control Register 7*/
+ uint32_t PC8; /*SPI Pin Control Register 8*/
+ uint32_t DAT0; /*SPI Transmit Data Register 0*/
+ uint32_t DAT1; /*SPI Transmit Data Register 1*/
+ uint32_t BUF; /*SPI Receive Buffer Register*/
+ uint32_t EMU; /*SPI Emulation Register*/
+ uint32_t DELAY; /*SPI Delay Register*/
+ uint32_t DEF; /*SPI Default Chip Select Register*/
+ uint32_t FMT0; /*SPI Data Format Register 0*/
+ uint32_t FMT1; /*SPI Data Format Register 1*/
+ uint32_t FMT2; /*SPI Data Format Register 2*/
+ uint32_t FMT3; /*SPI Data Format Register 3*/
+ uint32_t INTVECT0; /*Interrupt Vector 0*/
+ uint32_t INTVECT1; /*Interrupt Vector 1*/
+ uint8_t reserved1 [4];
+ uint32_t PMCTRL; /*Parallel/Modulo Mode Control Register*/
+ uint32_t MIBSPIE; /*Multi-buffer Mode Enable Register*/
+ uint32_t TGITENST; /*TG Interrupt Enable Set Register*/
+ uint32_t TGITENCR; /*TG Interrupt Enable Clear Register*/
+ uint32_t TGITLVST; /*Transfer Group Interrupt Level Set Register*/
+ uint32_t TGITLVCR; /*Transfer Group Interrupt Level Clear Register*/
+ uint32_t TGINTFLG; /*Transfer Group Interrupt Flag Register*/
+ uint8_t reserved2 [8];
+ uint32_t TICKCNT; /*Tick Count Register*/
+ uint32_t LTGPEND; /*Last TG End Pointer*/
+ uint32_t TGCTRL[16]; /*TG Control Registers*/
+ uint32_t DMACTRL[8]; /*DMA Channel Control Register*/
+ uint32_t DMACOUNT[8]; /*DMA COUNT Register*/
+ uint32_t DMACNTLEN; /*DMA Large Count*/
+ uint8_t reserved3 [4];
+ uint32_t UERRCTRL; /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/
+ uint32_t UERRSTAT; /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/
+ uint32_t UERRADDRRX; /*RXRAM Uncorrectable Parity Error Address Register*/
+ uint32_t UERRADDRTX; /*TXRAM Uncorrectable Parity Error Address Register*/
+ uint32_t RXOVRN_BUF_ADDR; /*RXRAM Overrun Buffer Address Register*/
+ uint32_t IOLPBKTSTCR; /*I/O Loopback Test Control Register*/
+ uint32_t EXT_PRESCALE1; /*SPI Extended Prescale Register 1*/
+ uint32_t EXT_PRESCALE2; /*SPI Extended Prescale Register 2*/
+} tms570_spi_t;
+
+
+/*-----------------------TMS570_SPIGCR0-----------------------*/
+/* field: nRESET - This is the local reset control for the module. */
+#define TMS570_SPI_GCR0_nRESET BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SPIGCR1-----------------------*/
+/* field: SPIEN - SPI enable. This bit enables SPI transfers. */
+#define TMS570_SPI_GCR1_SPIEN BSP_FLD32(24)
+
+/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
+#define TMS570_SPI_GCR1_LOOPBACK BSP_FLD32(16)
+
+/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
+#define TMS570_SPI_GCR1_POWERDOWN BSP_FLD32(8)
+
+/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
+#define TMS570_SPI_GCR1_CLKMOD BSP_FLD32(1)
+
+/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
+#define TMS570_SPI_GCR1_MASTER BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SPIINT0-----------------------*/
+/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
+#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_FLD32(24)
+
+/* field: DMAREQEN - DMA request enable. */
+#define TMS570_SPI_INT0_DMAREQEN BSP_FLD32(16)
+
+
+/*-----------------------TMS570_SPILVL-----------------------*/
+/* field: TXINTLVL - Transmit interrupt level. */
+#define TMS570_SPI_LVL_TXINTLVL BSP_FLD32(9)
+
+/* field: RXINTLVL - Receive interrupt level. */
+#define TMS570_SPI_LVL_RXINTLVL BSP_FLD32(8)
+
+/* field: RXOVRNINTLVL - Receive overrun interrupt level. */
+#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_FLD32(6)
+
+/* field: BITERRLVL - Bit error interrupt level. */
+#define TMS570_SPI_LVL_BITERRLVL BSP_FLD32(4)
+
+/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
+#define TMS570_SPI_LVL_DESYNCLVL BSP_FLD32(3)
+
+/* field: PARERRLVL - Parity error interrupt level. */
+#define TMS570_SPI_LVL_PARERRLVL BSP_FLD32(2)
+
+/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
+#define TMS570_SPI_LVL_TIMEOUTLVL BSP_FLD32(1)
+
+/* field: DLENERRLVL - Data length error interrupt level (line) select. */
+#define TMS570_SPI_LVL_DLENERRLVL BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SPIFLG-----------------------*/
+/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
+#define TMS570_SPI_FLG_BUFINITACTIVE BSP_FLD32(24)
+
+/* field: TXINTFLG - Transmitter-empty interrupt flag. */
+#define TMS570_SPI_FLG_TXINTFLG BSP_FLD32(9)
+
+/* field: RXINTFLG - Receiver-full interrupt flag. */
+#define TMS570_SPI_FLG_RXINTFLG BSP_FLD32(8)
+
+/* field: RXOVRNINTFLG - Receiver overrun flag. */
+#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_FLD32(6)
+
+/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
+#define TMS570_SPI_FLG_BITERRFLG BSP_FLD32(4)
+
+/* field: DESYNCFLG - Desynchronization of slave device. */
+#define TMS570_SPI_FLG_DESYNCFLG BSP_FLD32(3)
+
+/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
+#define TMS570_SPI_FLG_PARITYERRFLG BSP_FLD32(2)
+
+/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
+#define TMS570_SPI_FLG_TIMEOUTFLG BSP_FLD32(1)
+
+/* field: DLENERRFLG - Data-length error flag. */
+#define TMS570_SPI_FLG_DLENERRFLG BSP_FLD32(0)
+
+
+/*-----------------------TMS570_SPIPC0-----------------------*/
+/* field: SOMIFUN - Slave out, master in function. */
+#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMOFUN - Slave in, master out function. */
+#define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIFUN0 - SOMIFUN0 */
+#define TMS570_SPI_PC0_SOMIFUN0 BSP_FLD32(11)
+
+/* field: SIMOFUN0 - Slave in, master out function. */
+#define TMS570_SPI_PC0_SIMOFUN0 BSP_FLD32(10)
+
+/* field: CLKFUN - CLKFUN */
+#define TMS570_SPI_PC0_CLKFUN BSP_FLD32(9)
+
+/* field: ENAFUN - SPIENA function. */
+#define TMS570_SPI_PC0_ENAFUN BSP_FLD32(8)
+
+/* field: SCSFUN - SPISCSx function. */
+#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC1-----------------------*/
+/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
+#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */
+#define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIDIR0 - PISOMI0 direction. */
+#define TMS570_SPI_PC1_SOMIDIR0 BSP_FLD32(11)
+
+/* field: SIMODIR0 - SPISIMO0 direction. */
+#define TMS570_SPI_PC1_SIMODIR0 BSP_FLD32(10)
+
+/* field: CLKDIR - SPICLK direction. */
+#define TMS570_SPI_PC1_CLKDIR BSP_FLD32(9)
+
+/* field: ENADIR - SPIENA direction. */
+#define TMS570_SPI_PC1_ENADIR BSP_FLD32(8)
+
+/* field: SCSDIR - SPISCSx direction. */
+#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC2-----------------------*/
+/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
+#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */
+#define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
+#define TMS570_SPI_PC2_SOMIDIN0 BSP_FLD32(11)
+
+/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
+#define TMS570_SPI_PC2_SIMODIN0 BSP_FLD32(10)
+
+/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
+#define TMS570_SPI_PC2_CLKDIN BSP_FLD32(9)
+
+/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
+#define TMS570_SPI_PC2_ENADIN BSP_FLD32(8)
+
+/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
+#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC3-----------------------*/
+/* field: SOMIDOUT - SPISOMIx data out write. */
+#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMODOUT - SPISIMOx data out write. */
+#define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIDOUT0 - SPISOMI0 data out write. */
+#define TMS570_SPI_PC3_SOMIDOUT0 BSP_FLD32(11)
+
+/* field: SIMODOUT0 - SPISIMO0 data out write. */
+#define TMS570_SPI_PC3_SIMODOUT0 BSP_FLD32(10)
+
+/* field: CLKDOUT - SPICLK data out write. */
+#define TMS570_SPI_PC3_CLKDOUT BSP_FLD32(9)
+
+/* field: ENADOUT - SPIENA data out write. */
+#define TMS570_SPI_PC3_ENADOUT BSP_FLD32(8)
+
+/* field: SCSDOUT - SPISCSx data out write. */
+#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC4-----------------------*/
+/* field: SOMISET - SPISOMIx data out set. */
+#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMOSET - SPISIMOx data out set. */
+#define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMISET0 - SPISOMI0 data out set. */
+#define TMS570_SPI_PC4_SOMISET0 BSP_FLD32(11)
+
+/* field: SIMOSET0 - purpose */
+#define TMS570_SPI_PC4_SIMOSET0 BSP_FLD32(10)
+
+/* field: CLKSET - SPICLK data out set. */
+#define TMS570_SPI_PC4_CLKSET BSP_FLD32(9)
+
+/* field: ENASET - SPIENA data out set. */
+#define TMS570_SPI_PC4_ENASET BSP_FLD32(8)
+
+/* field: SCSSET - SPISCSx data out set. */
+#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC5-----------------------*/
+/* field: SOMICLR - SPISOMIx data out clear. */
+#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMOCLR - SPISIMOx data out clear. */
+#define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMICLR0 - SPISOMI0 data out cleart. */
+#define TMS570_SPI_PC5_SOMICLR0 BSP_FLD32(11)
+
+/* field: SIMOCLR0 - SPISIMO0 data out clear. */
+#define TMS570_SPI_PC5_SIMOCLR0 BSP_FLD32(10)
+
+/* field: CLKCLR - SPICLK data out clear. */
+#define TMS570_SPI_PC5_CLKCLR BSP_FLD32(9)
+
+/* field: ENACLR - SPIENA data out clear. */
+#define TMS570_SPI_PC5_ENACLR BSP_FLD32(8)
+
+/* field: SCSCLR - SPISCSx data out clear. */
+#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC6-----------------------*/
+/* field: SOMIPDR - SPISOMIx open drain enable. */
+#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMOPDR - SPISIMOx open drain enable. */
+#define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIPDR0 - SOMI0 open-drain enable. */
+#define TMS570_SPI_PC6_SOMIPDR0 BSP_FLD32(11)
+
+/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
+#define TMS570_SPI_PC6_SIMOPDR0 BSP_FLD32(10)
+
+/* field: CLKPDR - CLK open drain enable. */
+#define TMS570_SPI_PC6_CLKPDR BSP_FLD32(9)
+
+/* field: ENAPDR - SPIENA pin open drain enable. */
+#define TMS570_SPI_PC6_ENAPDR BSP_FLD32(8)
+
+/* field: SCSPDR - SPISCSx open drain enable. */
+#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC7-----------------------*/
+/* field: SOMIDIS - SOMIx pull control enable/disable. */
+#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMODIS - SIMOx pull control enable/disable. */
+#define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
+#define TMS570_SPI_PC7_SOMIPDIS0 BSP_FLD32(11)
+
+/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
+#define TMS570_SPI_PC7_SIMOPDIS0 BSP_FLD32(10)
+
+/* field: CLKPDIS - CLK pull control enable/disable. */
+#define TMS570_SPI_PC7_CLKPDIS BSP_FLD32(9)
+
+/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
+#define TMS570_SPI_PC7_ENAPDIS BSP_FLD32(8)
+
+/* field: SCSPDIS - SCSx pull control enable/disable. */
+#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIPC8-----------------------*/
+/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
+#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */
+#define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
+#define TMS570_SPI_PC8_SOMIPSEL0 BSP_FLD32(11)
+
+/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
+#define TMS570_SPI_PC8_SIMOPSEL0 BSP_FLD32(10)
+
+/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
+#define TMS570_SPI_PC8_CLKPSEL BSP_FLD32(9)
+
+/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
+#define TMS570_SPI_PC8_ENAPSEL BSP_FLD32(8)
+
+/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
+#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIDAT0-----------------------*/
+/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
+#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_SPIDAT1-----------------------*/
+/* field: CSHOLD - Chip select hold mode. */
+#define TMS570_SPI_DAT1_CSHOLD BSP_FLD32(28)
+
+/* field: WDEL - Enable the delay counter at the end of the current transaction. */
+#define TMS570_SPI_DAT1_WDEL BSP_FLD32(26)
+
+/* field: DFSEL - Data word format select */
+#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
+#define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25)
+#define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
+
+/* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */
+#define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */
+#define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_SPIBUF-----------------------*/
+/* field: RXEMPTY - Receive data buffer empty. */
+#define TMS570_SPI_BUF_RXEMPTY BSP_FLD32(31)
+
+/* field: RXOVR - Receive data buffer overrun. */
+#define TMS570_SPI_BUF_RXOVR BSP_FLD32(30)
+
+/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
+#define TMS570_SPI_BUF_TXFULL BSP_FLD32(29)
+
+/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
+#define TMS570_SPI_BUF_BITERR BSP_FLD32(28)
+
+/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
+#define TMS570_SPI_BUF_DESYNC BSP_FLD32(27)
+
+/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
+#define TMS570_SPI_BUF_PARITYERR BSP_FLD32(26)
+
+/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
+#define TMS570_SPI_BUF_TIMEOUT BSP_FLD32(25)
+
+/* field: DLENERR - Data length error flag. */
+#define TMS570_SPI_BUF_DLENERR BSP_FLD32(24)
+
+/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
+#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: RXDATA - SPI receive data. */
+#define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-----------------------TMS570_SPIEMU-----------------------*/
+/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
+#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*----------------------TMS570_SPIDELAY----------------------*/
+/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
+#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: T2CDELAY - T2CDELAY */
+#define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23)
+#define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23)
+#define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
+
+/* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */
+#define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15)
+#define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */
+#define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIDEF-----------------------*/
+/* field: CDEF - Chip select default pattern. Master-mode only. */
+#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
+#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*-----------------------TMS570_SPIFMT0-----------------------*/
+/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
+#define TMS570_SPI_FMT0_WDELAY(val) BSP_FLD32(val,24, 31)
+#define TMS570_SPI_FMT0_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
+#define TMS570_SPI_FMT0_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
+
+/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
+#define TMS570_SPI_FMT0_PARPOL BSP_FLD32(23)
+
+/* field: PARITYENA - Parity enable for data format x. */
+#define TMS570_SPI_FMT0_PARITYENA BSP_FLD32(22)
+
+/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
+#define TMS570_SPI_FMT0_WAITENA BSP_FLD32(21)
+
+/* field: SHIFTDIR - Shift direction for data format x. */
+#define TMS570_SPI_FMT0_SHIFTDIR BSP_FLD32(20)
+
+/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
+#define TMS570_SPI_FMT0_HDUPLEX_ENAx BSP_FLD32(19)
+
+/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
+#define TMS570_SPI_FMT0_DIS_CS_TIMERS BSP_FLD32(18)
+
+/* field: POLARITY - POLARITY */
+#define TMS570_SPI_FMT0_POLARITY BSP_FLD32(17)
+
+/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
+#define TMS570_SPI_FMT0_PHASE BSP_FLD32(16)
+
+/* field: PRESCALE - SPI data format x prescaler. */
+#define TMS570_SPI_FMT0_PRESCALE(val) BSP_FLD32(val,8, 15)
+#define TMS570_SPI_FMT0_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SPI_FMT0_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
+#define TMS570_SPI_FMT0_CHARLEN(val) BSP_FLD32(val,0, 4)
+#define TMS570_SPI_FMT0_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_SPI_FMT0_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*---------------------TMS570_SPIINTVECT0---------------------*/
+/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
+#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
+#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
+#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
+
+/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
+#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_SPIINTVECT1---------------------*/
+/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
+#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
+#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
+#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
+
+/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
+#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_FLD32(0)
+
+
+/*----------------------TMS570_SPIPMCTRL----------------------*/
+/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_FLD32(29)
+
+/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
+#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
+#define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28)
+#define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28)
+
+/* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
+#define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25)
+#define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25)
+#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
+
+/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_FLD32(21)
+
+/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
+#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
+#define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20)
+#define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20)
+
+/* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
+#define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17)
+#define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17)
+#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
+
+/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_FLD32(13)
+
+/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
+#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
+#define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12)
+#define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12)
+
+/* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
+#define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9)
+#define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
+#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_FLD32(5)
+
+/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
+#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
+#define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4)
+#define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4)
+
+/* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
+#define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1)
+#define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_SPIMIBSPIE---------------------*/
+/* field: RXRAM_ACCESS - Receive-RAM access control. */
+#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_FLD32(16)
+
+/* field: MSPIENA - Multi-buffer mode enable. */
+#define TMS570_SPI_MIBSPIE_MSPIENA BSP_FLD32(0)
+
+
+/*---------------------TMS570_SPITGITENST---------------------*/
+/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
+#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */
+#define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPITGITENCR---------------------*/
+/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
+#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: CLR_INTENSUS - CLR INTENSUS */
+#define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPITGITLVST---------------------*/
+/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
+#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */
+#define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPITGITLVCR---------------------*/
+/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPITGINTFLG---------------------*/
+/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
+#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */
+#define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPITICKCNT---------------------*/
+/* field: TICKENA - Tick counter enable. */
+#define TMS570_SPI_TICKCNT_TICKENA BSP_FLD32(31)
+
+/* field: RELOAD - Pre-load the tick counter. */
+#define TMS570_SPI_TICKCNT_RELOAD BSP_FLD32(30)
+
+/* field: CLKCTRL - Tick counter clock source control. */
+#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
+#define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29)
+#define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
+
+/* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */
+#define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SPILTGPEND---------------------*/
+/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
+#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
+#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: LPEND - Last TG end pointer. */
+#define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14)
+#define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14)
+#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
+
+
+/*----------------------TMS570_SPITGCTRL----------------------*/
+/* field: TGENA - TGx enable. */
+#define TMS570_SPI_TGCTRL_TGENA BSP_FLD32(31)
+
+/* field: ONESHOTx - Single transfer for TGx. */
+#define TMS570_SPI_TGCTRL_ONESHOTx BSP_FLD32(30)
+
+/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
+#define TMS570_SPI_TGCTRL_PRSTx BSP_FLD32(29)
+
+/* field: TGTDx - TG triggered. */
+#define TMS570_SPI_TGCTRL_TGTDx BSP_FLD32(28)
+
+
+/*---------------------TMS570_SPIDMACTRL---------------------*/
+/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
+#define TMS570_SPI_DMACTRL_ONESHOT BSP_FLD32(31)
+
+/* field: BUFIDx - Buffer utilized for DMA transfer. */
+#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
+#define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30)
+#define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
+
+/* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
+#define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23)
+#define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23)
+#define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
+
+/* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
+#define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19)
+#define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: RXDMAENAx - Receive data DMA channel enable. */
+#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_FLD32(15)
+
+/* field: TXDAMENAx - Transmit data DMA channel enable. */
+#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_FLD32(14)
+
+/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
+#define TMS570_SPI_DMACTRL_NOBRKx BSP_FLD32(13)
+
+/* field: ICOUNTx - Initial count of DMA transfers. */
+#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
+#define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+
+/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
+#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_FLD32(6)
+
+/* field: COUNTx - Actual number of remaining DMA transfers. */
+#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
+#define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5)
+#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
+
+
+/*---------------------TMS570_SPIDMACOUNT---------------------*/
+/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
+#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
+#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: COUNTx - The actual number of remaining DMA transfers. */
+#define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15)
+#define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_SPIDMACNTLEN--------------------*/
+/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
+#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_FLD32(0)
+
+
+/*---------------------TMS570_SPIUERRCTRL---------------------*/
+/* field: PTESTEN - Parity memory test enable. */
+#define TMS570_SPI_UERRCTRL_PTESTEN BSP_FLD32(8)
+
+/* field: EDEN - Error detection enable. These bits enable parity error detection. */
+#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
+#define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SPIUERRSTAT---------------------*/
+/* field: EDFLG1 - RXRAM. */
+#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_FLD32(1)
+
+/* field: EDFLG0 - Uncorrectable parity error detection flag. */
+#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_FLD32(0)
+
+
+/*--------------------TMS570_SPIUERRADDRRX--------------------*/
+/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
+#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
+#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*--------------------TMS570_SPIUERRADDRTX--------------------*/
+/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
+#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
+#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*-----------------TMS570_SPIRXOVRN_BUF_ADDR-----------------*/
+/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
+#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
+#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
+#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
+
+
+/*-------------------TMS570_SPIIOLPBKTSTCR-------------------*/
+/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
+#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_FLD32(24)
+
+/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_FLD32(20)
+
+/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_FLD32(19)
+
+/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_FLD32(18)
+
+/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_FLD32(17)
+
+/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_FLD32(16)
+
+/* field: IOLPBKSTENA - Module I/O loopback test enable key. */
+#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
+#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */
+#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5)
+#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5)
+#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
+
+/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
+#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_FLD32(2)
+
+/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
+#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_FLD32(1)
+
+/* field: RXP_ENA - Enable analog loopback through the receive pin. */
+#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_FLD32(0)
+
+
+/*------------------TMS570_SPIEXT_PRESCALE1------------------*/
+/* field: EPRESCALE_FMT1 - EPRESCALE_FMT1. Extended Prescale value for SPIFMT1. */
+#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1(val) BSP_FLD32(val,16, 26)
+#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_GET(reg) BSP_FLD32GET(reg,16, 26)
+#define TMS570_SPI_EXT_PRESCALE1_EPRESCALE_FMT1_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
+
+
+
+#endif /* LIBBSP_ARM_tms570_SPI */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
new file mode 100644
index 0000000..a841ca5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_stc.h
@@ -0,0 +1,188 @@
+/* The header file is generated by make_header.py from STC.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_STC
+#define LIBBSP_ARM_tms570_STC
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t STCGCR0; /*STC Global Control Register 0*/
+ uint32_t STCGCR1; /*STCGlobal Control Register 1*/
+ uint32_t STCTPR; /*Self-Test Run Timeout Counter Preload Register*/
+ uint32_t STC_CADDR; /*STC Current ROM Address Register*/
+ uint32_t STCCICR; /*STC Current Interval Count Register*/
+ uint32_t STCGSTAT; /*Self-Test Global Status Register*/
+ uint32_t STCFSTAT; /*Self-Test Fail Status Register*/
+ uint32_t CPU1_CURMISR3; /*CPU1 Current MISR Register 3*/
+ uint32_t CPU1_CURMISR2; /*CPU1 Current MISR Register 2*/
+ uint32_t CPU1_CURMISR1; /*CPU1 Current MISR Register 1*/
+ uint32_t CPU1_CURMISR0; /*CPU1 Current MISR Register 0*/
+ uint32_t CPU2_CURMISR3; /*CPU2 Current MISR Register 3*/
+ uint32_t CPU2_CURMISR2; /*CPU2 Current MISR Register 2*/
+ uint32_t CPU2_CURMISR1; /*CPU2 Current MISR Register 1*/
+ uint32_t CPU2_CURMISR0; /*CPU2 Current MISR Register 0*/
+ uint32_t STCSCSCR; /*Signature Compare Self-Check Register*/
+} tms570_stc_t;
+
+
+/*---------------------TMS570_STCSTCGCR0---------------------*/
+/* field: INTCOUNT - Number of intervals of self-test run */
+#define TMS570_STC_STCGCR0_INTCOUNT(val) BSP_FLD32(val,16, 31)
+#define TMS570_STC_STCGCR0_INTCOUNT_GET(reg) BSP_FLD32GET(reg,16, 31)
+#define TMS570_STC_STCGCR0_INTCOUNT_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
+
+/* field: RS_CNT - Restart or Continue */
+#define TMS570_STC_STCGCR0_RS_CNT BSP_FLD32(0)
+
+
+/*---------------------TMS570_STCSTCGCR1---------------------*/
+/* field: STC_ENA - Self-test run enable key */
+#define TMS570_STC_STCGCR1_STC_ENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_STC_STCGCR1_STC_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_STC_STCGCR1_STC_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_STCSTCTPR----------------------*/
+/* field: RTOD - Self-test timeout count preload */
+#define TMS570_STC_STCTPR_RTOD(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_STCTPR_RTOD_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_STCTPR_RTOD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_STCSTC_CADDR--------------------*/
+/* field: ADDR - Current ROM Address */
+#define TMS570_STC_STC_CADDR_ADDR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_STC_CADDR_ADDR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_STC_CADDR_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_STCSTCCICR---------------------*/
+/* field: N - Interval Number */
+#define TMS570_STC_STCCICR_N(val) BSP_FLD32(val,0, 15)
+#define TMS570_STC_STCCICR_N_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_STC_STCCICR_N_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_STCSTCGSTAT---------------------*/
+/* field: TEST_FAIL - Test Fail */
+#define TMS570_STC_STCGSTAT_TEST_FAIL BSP_FLD32(1)
+
+/* field: TEST_DONE - Test Done */
+#define TMS570_STC_STCGSTAT_TEST_DONE BSP_FLD32(0)
+
+
+/*---------------------TMS570_STCSTCFSTAT---------------------*/
+/* field: TO_ERR - Timeout Error */
+#define TMS570_STC_STCFSTAT_TO_ERR BSP_FLD32(2)
+
+/* field: CPU2_FAIL - CPU2 failure info */
+#define TMS570_STC_STCFSTAT_CPU2_FAIL BSP_FLD32(1)
+
+/* field: CPU1_FAIL - CPU1 failure info */
+#define TMS570_STC_STCFSTAT_CPU1_FAIL BSP_FLD32(0)
+
+
+/*------------------TMS570_STCCPU1_CURMISR3------------------*/
+/* field: MISR - MISR data from CPU1 */
+#define TMS570_STC_CPU1_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU1_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU1_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU1_CURMISR2------------------*/
+/* field: MISR - MISR data from CPU1 */
+#define TMS570_STC_CPU1_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU1_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU1_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU1_CURMISR1------------------*/
+/* field: MISR - MISR data from CPU1 */
+#define TMS570_STC_CPU1_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU1_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU1_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU1_CURMISR0------------------*/
+/* field: MISR - MISR data from CPU1 */
+#define TMS570_STC_CPU1_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU1_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU1_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU2_CURMISR3------------------*/
+/* field: MISR - MISR data from CPU2 */
+#define TMS570_STC_CPU2_CURMISR3_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU2_CURMISR3_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU2_CURMISR3_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU2_CURMISR2------------------*/
+/* field: MISR - MISR data from CPU2 */
+#define TMS570_STC_CPU2_CURMISR2_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU2_CURMISR2_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU2_CURMISR2_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU2_CURMISR1------------------*/
+/* field: MISR - MISR data from CPU2 */
+#define TMS570_STC_CPU2_CURMISR1_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU2_CURMISR1_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU2_CURMISR1_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*------------------TMS570_STCCPU2_CURMISR0------------------*/
+/* field: MISR - MISR data from CPU2 */
+#define TMS570_STC_CPU2_CURMISR0_MISR(val) BSP_FLD32(val,0, 31)
+#define TMS570_STC_CPU2_CURMISR0_MISR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_STC_CPU2_CURMISR0_MISR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_STCSTCSCSCR---------------------*/
+/* field: FAULT_INS - Enable / Disable fault insertion. */
+#define TMS570_STC_STCSCSCR_FAULT_INS BSP_FLD32(4)
+
+/* field: SELF_CHECK_KEY - Signature compare logic self-check enable key */
+#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_STC_STCSCSCR_SELF_CHECK_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+
+#endif /* LIBBSP_ARM_tms570_STC */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
new file mode 100644
index 0000000..71679ee
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys.h
@@ -0,0 +1,704 @@
+/* The header file is generated by make_header.py from SYS.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_SYS1
+#define LIBBSP_ARM_tms570_SYS1
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t SYSPC1; /*SYS Pin Control Register 1*/
+ uint32_t SYSPC2; /*SYS Pin Control Register 2*/
+ uint32_t SYSPC3; /*SYS Pin Control Register 3*/
+ uint32_t SYSPC4; /*SYS Pin Control Register 4*/
+ uint32_t SYSPC5; /*SYS Pin Control Register 5*/
+ uint32_t SYSPC6; /*SYS Pin Control Register 6*/
+ uint32_t SYSPC7; /*SYS Pin Control Register 7*/
+ uint32_t SYSPC8; /*SYS Pin Control Register 8*/
+ uint32_t SYSPC9; /*SYS Pin Control Register 9*/
+ uint8_t reserved1 [12];
+ uint32_t CSDIS; /*Clock Source Disable Register*/
+ uint32_t CSDISSET; /*Clock Source Disable Set Register*/
+ uint32_t CSDISCLR; /*Clock Source Disable Clear Register*/
+ uint32_t CDDIS; /*Clock Domain Disable Register*/
+ uint32_t CDDISSET; /*Clock Domain Disable Set Register*/
+ uint32_t CDDISCLR; /*Clock Domain Disable Clear Register*/
+ uint32_t GHVSRC; /*GCLK, HCLK, VCLK, and VCLK2 Source Register*/
+ uint32_t VCLKASRC; /*Peripheral Asynchronous Clock Source Register*/
+ uint32_t RCLKSRC; /*RTI Clock Source Register*/
+ uint32_t CSVSTAT; /*Clock Source Valid Status Register*/
+ uint32_t MSTGCR; /*Memory Self-Test Global Control Register*/
+ uint32_t MINITGCR; /*Memory Hardware Initialization Global Control Register*/
+ uint32_t MSIENA; /*Memory Self-Test/Initialization Enable Register*/
+ uint8_t reserved2 [4];
+ uint32_t MSTCGSTAT; /*MSTC Global Status Register*/
+ uint32_t MINISTAT; /*Memory Hardware Initialization Status Register*/
+ uint32_t PLLCTL1; /*PLL Control Register 1*/
+ uint32_t PLLCTL2; /*PLL Control Register 2*/
+ uint32_t SYSPC10; /*SYS Pin Control Register 10*/
+ uint32_t DIEIDL; /*Die Identification Register, Lower Word*/
+ uint32_t DIEIDH; /*Die Identification Register, Upper Word*/
+ uint8_t reserved3 [4];
+ uint32_t LPOMONCTL; /*LPO/Clock Monitor Control Register*/
+ uint32_t CLKTEST; /*Clock Test Register*/
+ uint32_t DFTCTRLREG1; /*DFT Control Register*/
+ uint32_t DFTCTRLREG2; /*DFT Control Register 2*/
+ uint8_t reserved4 [8];
+ uint32_t GPREG1; /*General Purpose Register*/
+ uint8_t reserved5 [4];
+ uint32_t IMPFASTS; /*Imprecise Fault Status Register*/
+ uint32_t IMPFTADD; /*Imprecise Fault Write Address Register*/
+ uint32_t SSIR1; /*System Software Interrupt Request 1 Register*/
+ uint32_t SSIR2; /*System Software Interrupt Request 2 Register*/
+ uint32_t SSIR3; /*System Software Interrupt Request 3 Register*/
+ uint32_t SSIR4; /*System Software Interrupt Request 4 Register*/
+ uint32_t RAMGCR; /*RAM Control Register*/
+ uint32_t BMMCR1; /*Bus Matrix Module Control Register 1*/
+ uint8_t reserved6 [4];
+ uint32_t CPURSTCR; /*CPU Reset Control Register*/
+ uint32_t CLKCNTL; /*Clock Control Register*/
+ uint32_t ECPCNTL; /*ECP Control Register*/
+ uint8_t reserved7 [4];
+ uint32_t DEVCR1; /*DEV Parity Control Register 1*/
+ uint32_t SYSECR; /*System Exception Control Register*/
+ uint32_t SYSESR; /*System Exception Status Register*/
+ uint32_t SYSTASR; /*System Test Abort Status Register*/
+ uint32_t GLBSTAT; /*Global Status Register*/
+ uint32_t DEVID; /*Device Identification Register*/
+ uint32_t SSIVEC; /*Software Interrupt Vector Register*/
+ uint32_t SSIF; /*System Software Interrupt Flag Register*/
+} tms570_sys1_t;
+
+
+/*---------------------TMS570_SYS1SYSPC1---------------------*/
+/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
+#define TMS570_SYS1_SYSPC1_ECPCLKFUN BSP_FLD32(0)
+
+
+/*----------------------TMS570_SYS1CSDIS----------------------*/
+/* field: CLKSROFF - Clock source[7-3] off. */
+#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLKSROFF - Clock source[1-0] off. */
+#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*--------------------TMS570_SYS1CSDISSET--------------------*/
+/* field: SETCLKSR_OFF - Set clock source[7-3] to the disabled state. */
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: SETCLKSR_OFF - Set clock source[1-0] to the disabled state. */
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*--------------------TMS570_SYS1CSDISCLR--------------------*/
+/* field: CLRCLKSR_OFF - Enables clock source[7-3]. */
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,3, 7)
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLRCLKSR_OFF - Enables clock source[1-0]. */
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 1)
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*----------------------TMS570_SYS1CDDIS----------------------*/
+/* field: VCLKAOFF - VCLKA[4-3] domain off. */
+#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,10, 11)
+#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: VCLK3OFF - VCLK3 domain off. */
+#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_FLD32(8)
+
+/* field: RTICLK1OFF - RTICLK1 domain off. */
+#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_FLD32(6)
+
+/* field: VCLKAOFF - VCLKA[2-1] domain off. */
+#define TMS570_SYS1_CDDIS_VCLKAOFF(val) BSP_FLD32(val,4, 5)
+#define TMS570_SYS1_CDDIS_VCLKAOFF_GET(reg) BSP_FLD32GET(reg,4, 5)
+#define TMS570_SYS1_CDDIS_VCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,4, 5)
+
+/* field: VCLK2OFF - VCLK2 domain off. */
+#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_FLD32(3)
+
+/* field: VCLKPOFF - VCLK_periph domain off. */
+#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_FLD32(2)
+
+/* field: HCLKOFF - HCLK and VCLK_sys domains off. */
+#define TMS570_SYS1_CDDIS_HCLKOFF BSP_FLD32(1)
+
+/* field: GCLKOFF - GCLK domain off. */
+#define TMS570_SYS1_CDDIS_GCLKOFF BSP_FLD32(0)
+
+
+/*--------------------TMS570_SYS1CDDISSET--------------------*/
+/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
+#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
+#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: SETVCLK3OFF - Set VCLK3 domain. */
+#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_FLD32(8)
+
+/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
+#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_FLD32(6)
+
+/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
+#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_FLD32(5)
+
+/* field: SETVCLKA1OFF - Set VCLKA1 domain. */
+#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_FLD32(4)
+
+/* field: SETVCLK2OFF - Set VCLK2 domain. */
+#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_FLD32(3)
+
+/* field: SETVCLKPOFF - Set VCLK_periph domain. */
+#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_FLD32(2)
+
+/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
+#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_FLD32(1)
+
+/* field: SETGCLKOFF - Set GCLK domain. */
+#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_FLD32(0)
+
+
+/*--------------------TMS570_SYS1CDDISCLR--------------------*/
+/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
+#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
+#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
+
+/* field: Reserved - Reserved */
+#define TMS570_SYS1_CDDISCLR_Reserved BSP_FLD32(9)
+
+/* field: CLRVCLK3OFF - Clear VCLK3 domain. */
+#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_FLD32(8)
+
+/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
+#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_FLD32(6)
+
+/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
+#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_FLD32(5)
+
+/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
+#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_FLD32(4)
+
+/* field: CLRVCLK2OFF - Clear VCLK2 domain. */
+#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_FLD32(3)
+
+/* field: CLRVCLKPOFF - CLRVCLKPOFF */
+#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_FLD32(2)
+
+/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
+#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_FLD32(1)
+
+/* field: CLRGCLKOFF - Clear GCLK domain. */
+#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_FLD32(0)
+
+
+/*---------------------TMS570_SYS1GHVSRC---------------------*/
+/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
+#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
+#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */
+#define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */
+#define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_SYS1VCLKASRC--------------------*/
+/* field: VCLKA2S - Peripheral asynchronous clock2 source. */
+#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
+#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: VCLKA1S - Peripheral asynchronous clock1 source. */
+#define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS1RCLKSRC---------------------*/
+/* field: RTI1DIV - RTI clock1 Divider. */
+#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
+#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: RTI1SRC - RTI clock1 source. */
+#define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS1CSVSTAT---------------------*/
+/* field: CLKSRV - Clock source[7-0] valid. */
+#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
+#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: CLKSRV - Clock source[1–0] valid. */
+#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,0, 1)
+#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_SYS1MSTGCR---------------------*/
+/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
+#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
+#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: MSTGENA - Memory self-test controller global enable key */
+#define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_SYS1MINITGCR--------------------*/
+/* field: MINITGENA - Memory hardware initialization global enable key. */
+#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS1MSIENA---------------------*/
+/* field: MSIENA - PBIST controller and memory initialization enable register. */
+#define TMS570_SYS1_MSIENA_MSIENA(val) BSP_FLD32(val,0, 31)
+#define TMS570_SYS1_MSIENA_MSIENA_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_SYS1_MSIENA_MSIENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_SYS1MSTCGSTAT--------------------*/
+/* field: MINIDONE - Memory hardware initialization complete status. */
+#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_FLD32(8)
+
+/* field: MSTDONE - Memory self-test run complete status. */
+#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_FLD32(0)
+
+
+/*--------------------TMS570_SYS1MINISTAT--------------------*/
+/* field: MIDONE - Memory hardware initialization status bit. */
+#define TMS570_SYS1_MINISTAT_MIDONE(val) BSP_FLD32(val,0, 31)
+#define TMS570_SYS1_MINISTAT_MIDONE_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_SYS1_MINISTAT_MIDONE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_SYS1PLLCTL1---------------------*/
+/* field: ROS - Reset on PLL Slip */
+#define TMS570_SYS1_PLLCTL1_ROS BSP_FLD32(31)
+
+/* field: MASK_SLIP - Mask detection of PLL slip */
+#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
+#define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
+#define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
+
+/* field: PLLDIV - PLL Output Clock Divider */
+#define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
+#define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: ROF - Reset on Oscillator Fail */
+#define TMS570_SYS1_PLLCTL1_ROF BSP_FLD32(23)
+
+/* field: REFCLKDIV - Reference Clock Divider */
+#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
+#define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: PLLMUL - PLL Multiplication Factor */
+#define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
+#define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SYS1PLLCTL2---------------------*/
+/* field: FMENA - Frequency Modulation Enable. */
+#define TMS570_SYS1_PLLCTL2_FMENA BSP_FLD32(31)
+
+/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
+#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
+#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
+#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
+
+/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
+#define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
+#define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
+#define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
+
+/* field: ODPLL - Internal PLL Output Divider. */
+#define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
+#define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
+#define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
+
+/* field: SPR_AMOUNT - Spreading Amount. */
+#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
+#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
+#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
+
+
+/*---------------------TMS570_SYS1SYSPC10---------------------*/
+/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
+#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_FLD32(0)
+
+
+/*---------------------TMS570_SYS1DIEIDL---------------------*/
+/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
+#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
+#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
+#define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31)
+
+/* field: WAFER - These read only bits contain the wafer number of the device. */
+#define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21)
+#define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */
+#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15)
+#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */
+#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7)
+#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_SYS1DIEIDH---------------------*/
+/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
+#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
+#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
+#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
+
+
+/*--------------------TMS570_SYS1LPOMONCTL--------------------*/
+/* field: BIAS_ENABLE - Bias enable. */
+#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_FLD32(24)
+
+/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
+#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_FLD32(16)
+
+/* field: HFTRIM - High frequency oscillator trim value. */
+#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
+#define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
+#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
+
+
+/*---------------------TMS570_SYS1CLKTEST---------------------*/
+/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
+#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_FLD32(26)
+
+/* field: RANGEDETCTRL - Range detection control. */
+#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_FLD32(25)
+
+/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
+#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_FLD32(24)
+
+/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
+#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */
+#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11)
+#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11)
+#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
+
+/* field: SEL_ECP_PIN - ECLK pin clock source select */
+#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_SYS1DFTCTRLREG1-------------------*/
+/* field: DFTWRITE - DFT logic access. */
+#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
+#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
+#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
+
+/* field: DFTREAD - DFT logic access. */
+#define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9)
+#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9)
+#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
+
+/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
+#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_SYS1DFTCTRLREG2-------------------*/
+/* field: IMPDF - DFT Implementation defined bits. */
+#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
+#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
+#define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
+
+/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
+#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS1GPREG1---------------------*/
+/* field: EMIF_FUNC - Enable EMIF functions to be output. */
+#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_FLD32(31)
+
+/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
+#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
+#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
+#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
+
+/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
+#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
+#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
+#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_SYS1IMPFASTS--------------------*/
+/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
+#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_FLD32(0)
+
+
+/*--------------------TMS570_SYS1IMPFTADD--------------------*/
+/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
+#define TMS570_SYS1_IMPFTADD_IMPFTADD(val) BSP_FLD32(val,0, 31)
+#define TMS570_SYS1_IMPFTADD_IMPFTADD_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_SYS1_IMPFTADD_IMPFTADD_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_SYS1SSIR1----------------------*/
+/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
+#define TMS570_SYS1_SSIR1_SSKEY1(val) BSP_FLD32(val,8, 15)
+#define TMS570_SYS1_SSIR1_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SYS1_SSIR1_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
+#define TMS570_SYS1_SSIR1_SSDATA1(val) BSP_FLD32(val,0, 7)
+#define TMS570_SYS1_SSIR1_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SYS1_SSIR1_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_SYS1RAMGCR---------------------*/
+/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
+#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
+#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_FLD32(2)
+
+/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
+#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_FLD32(0)
+
+
+/*---------------------TMS570_SYS1BMMCR1---------------------*/
+/* field: MEMSW - Memory swap key. */
+#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_SYS1CPURSTCR--------------------*/
+/* field: CPU_RESET - CPU Reset. */
+#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_FLD32(0)
+
+
+/*---------------------TMS570_SYS1CLKCNTL---------------------*/
+/* field: VCLK2R - VBUS clock2 ratio. */
+#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
+#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: VCLKR - VBUS clock ratio. */
+#define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: PENA - Peripheral enable bit. */
+#define TMS570_SYS1_CLKCNTL_PENA BSP_FLD32(8)
+
+
+/*---------------------TMS570_SYS1ECPCNTL---------------------*/
+/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
+#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_FLD32(24)
+
+/* field: ECPCOS - ECP continue on suspend. */
+#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_FLD32(23)
+
+/* field: ECPINSEL - Select ECP input clock source. */
+#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
+#define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
+#define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
+
+/* field: ECPDIV - ECP divider value. */
+#define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
+#define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*---------------------TMS570_SYS1DEVCR1---------------------*/
+/* field: DEVPARSEL - Device parity select bit key. */
+#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS1SYSECR---------------------*/
+/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
+#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
+#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
+#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
+
+
+/*---------------------TMS570_SYS1SYSESR---------------------*/
+/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
+#define TMS570_SYS1_SYSESR_PORST BSP_FLD32(15)
+
+/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
+#define TMS570_SYS1_SYSESR_OSCRST BSP_FLD32(14)
+
+/* field: WDRST - Watchdog reset flag. */
+#define TMS570_SYS1_SYSESR_WDRST BSP_FLD32(13)
+
+/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
+#define TMS570_SYS1_SYSESR_CPURST BSP_FLD32(5)
+
+/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
+#define TMS570_SYS1_SYSESR_SWRST BSP_FLD32(4)
+
+/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
+#define TMS570_SYS1_SYSESR_EXTRST BSP_FLD32(3)
+
+/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
+#define TMS570_SYS1_SYSESR_MPMODE BSP_FLD32(0)
+
+
+/*---------------------TMS570_SYS1SYSTASR---------------------*/
+/* field: EFUSE_Abort - Test Abort status flag. */
+#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
+#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
+#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
+
+
+/*---------------------TMS570_SYS1GLBSTAT---------------------*/
+/* field: FBSLIP - PLL over cycle slip detection. */
+#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_FLD32(9)
+
+/* field: RFSLIP - PLL under cycle slip detection. */
+#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_FLD32(8)
+
+/* field: OSCFAIL - Oscillator fail flag bit. */
+#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_FLD32(0)
+
+
+/*----------------------TMS570_SYS1DEVID----------------------*/
+/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
+#define TMS570_SYS1_DEVID_CP15 BSP_FLD32(31)
+
+/* field: TECH - These bits define the process technology by which the device was manufactured. */
+#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
+#define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16)
+#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
+
+/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
+#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_FLD32(12)
+
+/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
+#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_FLD32(11)
+
+/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
+#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
+#define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10)
+#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
+
+/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
+#define TMS570_SYS1_DEVID_RAM_ECC BSP_FLD32(8)
+
+/* field: VERSION - Version. These bits provide the revision of the device. */
+#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
+#define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7)
+#define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
+
+/* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */
+#define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2)
+#define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2)
+#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
+
+
+/*---------------------TMS570_SYS1SSIVEC---------------------*/
+/* field: SSIDATA - System software interrupt data key. */
+#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
+#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
+#define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
+
+/* field: SSIVECT - These bits contain the source for the system software interrupt. */
+#define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7)
+#define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_SYS1SSIF----------------------*/
+/* field: SSI_FLAG - System software interrupt flag[4-1]. */
+#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+
+#endif /* LIBBSP_ARM_tms570_SYS1 */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
new file mode 100644
index 0000000..f936661
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_sys2.h
@@ -0,0 +1,173 @@
+/* The header file is generated by make_header.py from SYS2.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_SYS2
+#define LIBBSP_ARM_tms570_SYS2
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PLLCTL3; /*PLL Control Register 3*/
+ uint8_t reserved1 [4];
+ uint32_t STCCLKDIV; /*CPU Logic BIST Clock Divider*/
+ uint8_t reserved2 [24];
+ uint32_t ECPCNTL; /*ECP Control Register*/
+ uint8_t reserved3 [20];
+ uint32_t CLK2CNTRL; /*Clock 2 Control Register*/
+ uint32_t VCLKACON1; /*Peripheral Asynchronous Clock Configuration 1 Register*/
+ uint8_t reserved4 [44];
+ uint32_t CLKSLIP; /*Clock Slip Register*/
+ uint8_t reserved5 [120];
+ uint32_t EFC_CTLREG; /*EFUSE Controller Control Register*/
+ uint32_t DIEDL_REG0; /*Die Identification Register*/
+ uint32_t DIEDH_REG1; /*Die Identification Register*/
+ uint32_t DIEDL_REG2; /*Die Identification Register*/
+ uint32_t DIEDH_REG3; /*Die Identification Register*/
+} tms570_sys2_t;
+
+
+/*---------------------TMS570_SYS2PLLCTL3---------------------*/
+/* field: ODPLL2 - Internal PLL Output Divider */
+#define TMS570_SYS2_PLLCTL3_ODPLL2(val) BSP_FLD32(val,29, 31)
+#define TMS570_SYS2_PLLCTL3_ODPLL2_GET(reg) BSP_FLD32GET(reg,29, 31)
+#define TMS570_SYS2_PLLCTL3_ODPLL2_SET(reg,val) BSP_FLD32SET(reg, val,29, 31)
+
+/* field: PLLDIV2 - PLL2 Output Clock Divider */
+#define TMS570_SYS2_PLLCTL3_PLLDIV2(val) BSP_FLD32(val,24, 28)
+#define TMS570_SYS2_PLLCTL3_PLLDIV2_GET(reg) BSP_FLD32GET(reg,24, 28)
+#define TMS570_SYS2_PLLCTL3_PLLDIV2_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
+
+/* field: REFCLKDIV2 - REFCLKDIV2 */
+#define TMS570_SYS2_PLLCTL3_REFCLKDIV2(val) BSP_FLD32(val,16, 21)
+#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_GET(reg) BSP_FLD32GET(reg,16, 21)
+#define TMS570_SYS2_PLLCTL3_REFCLKDIV2_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
+
+/* field: PLLMUL2 - PLL2 Multiplication Factor */
+#define TMS570_SYS2_PLLCTL3_PLLMUL2(val) BSP_FLD32(val,0, 15)
+#define TMS570_SYS2_PLLCTL3_PLLMUL2_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SYS2_PLLCTL3_PLLMUL2_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_SYS2STCCLKDIV--------------------*/
+/* field: CLKDIV - Clock divider/prescaler for CPU clock during logic BIST */
+#define TMS570_SYS2_STCCLKDIV_CLKDIV(val) BSP_FLD32(val,24, 26)
+#define TMS570_SYS2_STCCLKDIV_CLKDIV_GET(reg) BSP_FLD32GET(reg,24, 26)
+#define TMS570_SYS2_STCCLKDIV_CLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
+
+
+/*---------------------TMS570_SYS2ECPCNTL---------------------*/
+/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
+#define TMS570_SYS2_ECPCNTL_ECPSSEL BSP_FLD32(24)
+
+/* field: ECPCOS - ECP continue on suspend. */
+#define TMS570_SYS2_ECPCNTL_ECPCOS BSP_FLD32(23)
+
+/* field: ECPINSEL - Select ECP input clock source. */
+#define TMS570_SYS2_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
+#define TMS570_SYS2_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
+#define TMS570_SYS2_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
+
+/* field: ECPDIV - ECP divider value. */
+#define TMS570_SYS2_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
+#define TMS570_SYS2_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_SYS2_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_SYS2CLK2CNTRL--------------------*/
+/* field: VCLK3R - VBUS clock3 ratio. */
+#define TMS570_SYS2_CLK2CNTRL_VCLK3R(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS2_CLK2CNTRL_VCLK3R_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS2_CLK2CNTRL_VCLK3R_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*--------------------TMS570_SYS2VCLKACON1--------------------*/
+/* field: VCLKA4R - Clock divider for the VCLKA4 source. Output will be present on VCLKA4_DIVR. */
+#define TMS570_SYS2_VCLKACON1_VCLKA4R(val) BSP_FLD32(val,24, 26)
+#define TMS570_SYS2_VCLKACON1_VCLKA4R_GET(reg) BSP_FLD32GET(reg,24, 26)
+#define TMS570_SYS2_VCLKACON1_VCLKA4R_SET(reg,val) BSP_FLD32SET(reg, val,24, 26)
+
+/* field: VCLKA4_DIV_CDDIS - Disable the VCLKA4 divider output. */
+#define TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS BSP_FLD32(20)
+
+/* field: VCLKA4S - Peripheral asynchronous clock4 source. */
+#define TMS570_SYS2_VCLKACON1_VCLKA4S(val) BSP_FLD32(val,16, 19)
+#define TMS570_SYS2_VCLKACON1_VCLKA4S_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_SYS2_VCLKACON1_VCLKA4S_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: VCLKA3R - Clock divider for the VCLKA3 source. Output will be present on VCLKA3_DIVR. */
+#define TMS570_SYS2_VCLKACON1_VCLKA3R(val) BSP_FLD32(val,8, 10)
+#define TMS570_SYS2_VCLKACON1_VCLKA3R_GET(reg) BSP_FLD32GET(reg,8, 10)
+#define TMS570_SYS2_VCLKACON1_VCLKA3R_SET(reg,val) BSP_FLD32SET(reg, val,8, 10)
+
+/* field: VCLKA3_DIV_CDDIS - Disable the VCLKA3 divider output. */
+#define TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS BSP_FLD32(4)
+
+/* field: VCLKA3S - Peripheral asynchronous clock3 source. */
+#define TMS570_SYS2_VCLKACON1_VCLKA3S(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS2_VCLKACON1_VCLKA3S_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS2_VCLKACON1_VCLKA3S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*---------------------TMS570_SYS2CLKSLIP---------------------*/
+/* field: PLL1_SLIP_FILTER_COUNT - Configure the count for the filtered PLL slip. Count is on 10M clock. */
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT(val) BSP_FLD32(val,8, 13)
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_GET(reg) BSP_FLD32GET(reg,8, 13)
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_COUNT_SET(reg,val) BSP_FLD32SET(reg, val,8, 13)
+
+/* field: PLL1_SLIP_FILTER_KEY - Enable the PLL filtering. */
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS2_CLKSLIP_PLL1_SLIP_FILTER_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_SYS2EFC_CTLREG-------------------*/
+/* field: EFC_INSTR_WEN - Enable user write of 4 EFUSE controller instructions. */
+#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN(val) BSP_FLD32(val,0, 3)
+#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_SYS2_EFC_CTLREG_EFC_INSTR_WEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-------------------TMS570_SYS2DIEDL_REG0-------------------*/
+/* field: DIE - This read-only register contains the lower/upper word (31:0) of the die ID information. */
+#define TMS570_SYS2_DIEDL_REG0_DIE(val) BSP_FLD32(val,0, 31)
+#define TMS570_SYS2_DIEDL_REG0_DIE_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_SYS2_DIEDL_REG0_DIE_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+
+#endif /* LIBBSP_ARM_tms570_SYS2 */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
new file mode 100644
index 0000000..e71dd52
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcr.h
@@ -0,0 +1,84 @@
+/* The header file is generated by make_header.py from TCR.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_TCR
+#define LIBBSP_ARM_tms570_TCR
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t TCR[128]; /*Transfer Configuration RAM*/
+ uint32_t TCR_Parity[128]; /*TCR Parity Test Mode*/
+} tms570_tcr_t;
+
+
+/*-----------------------TMS570_TCRTCR-----------------------*/
+/* field: STXR - Set Transmit Request. */
+#define TMS570_TCR_TCR_STXR BSP_FLD32(18)
+
+/* field: THTSM - Transfer Header to System Memory. */
+#define TMS570_TCR_TCR_THTSM BSP_FLD32(17)
+
+/* field: TPTSM - Transfer Payload to System Memory. */
+#define TMS570_TCR_TCR_TPTSM BSP_FLD32(16)
+
+/* field: THTCC - Transfer Header to Communication Controller. */
+#define TMS570_TCR_TCR_THTCC BSP_FLD32(15)
+
+/* field: TPTCC - Transfer Payload to Communication Controller. */
+#define TMS570_TCR_TCR_TPTCC BSP_FLD32(14)
+
+/* field: TSO - Transfer Start Offset. */
+#define TMS570_TCR_TCR_TSO(val) BSP_FLD32(val,0, 13)
+#define TMS570_TCR_TCR_TSO_GET(reg) BSP_FLD32GET(reg,0, 13)
+#define TMS570_TCR_TCR_TSO_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
+
+
+/*--------------------TMS570_TCRTCR_Parity--------------------*/
+/* field: PAB2 - Parity Bit for TCRx Byte 2. Parity information for byte 2 of TCRx(18-16). */
+#define TMS570_TCR_TCR_Parity_PAB2 BSP_FLD32(16)
+
+/* field: PAB1 - Parity Bit for TCRx Byte 1. Parity information for byte 1 of TCRx(15:8). */
+#define TMS570_TCR_TCR_Parity_PAB1 BSP_FLD32(8)
+
+/* field: PAB0 - Parity Bit for Byte 0. */
+#define TMS570_TCR_TCR_Parity_PAB0 BSP_FLD32(0)
+
+
+
+#endif /* LIBBSP_ARM_tms570_TCR */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
new file mode 100644
index 0000000..9092bfe
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_tcram.h
@@ -0,0 +1,170 @@
+/* The header file is generated by make_header.py from TCRAM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_TCRAM
+#define LIBBSP_ARM_tms570_TCRAM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t RAMCTRL; /*TCRAM Module Control Register*/
+ uint32_t RAMTHRESHOLD; /*TCRAM Module Single-Bit Error Correction Threshold Register*/
+ uint32_t RAMOCCUR; /*TCRAM Module Single-Bit Error Occurrences Control Register*/
+ uint32_t RAMINTCTRL; /*TCRAM Module Interrupt Control Register*/
+ uint32_t RAMERRSTATUS; /*TCRAM Module Error Status Register*/
+ uint32_t RAMSERRADDR; /*TCRAM Module Single-Bit Error Address Register*/
+ uint8_t reserved1 [4];
+ uint32_t RAMUERRADDR; /*TCRAM Module Uncorrectable Error Address Register*/
+ uint8_t reserved2 [16];
+ uint32_t RAMTEST; /*TCRAM Module Test Mode Control Register*/
+ uint8_t reserved3 [4];
+ uint32_t RAMADDRDECVECT; /*TCRAM Module Test Mode Vector Register*/
+ uint32_t RAMPERADDR; /*TCRAM Module Parity Error Address Register*/
+} tms570_tcram_t;
+
+
+/*--------------------TMS570_TCRAMRAMCTRL--------------------*/
+/* field: EMU_TRACE_DIS - Emulation Mode Trace Disable. */
+#define TMS570_TCRAM_RAMCTRL_EMU_TRACE_DIS BSP_FLD32(30)
+
+/* field: ADDR_PARITY_OVERRIDE - Address Parity Override. */
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE(val) BSP_FLD32(val,24, 27)
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_GET(reg) BSP_FLD32GET(reg,24, 27)
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_OVERRIDE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
+
+/* field: ADDR_PARITY_DISABLE - Address Parity Detect Disable. */
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE(val) BSP_FLD32(val,16, 19)
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_GET(reg) BSP_FLD32GET(reg,16, 19)
+#define TMS570_TCRAM_RAMCTRL_ADDR_PARITY_DISABLE_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
+
+/* field: ECC_WR_EN - ECC Memory Write Enable. */
+#define TMS570_TCRAM_RAMCTRL_ECC_WR_EN BSP_FLD32(8)
+
+/* field: ECC_DETECT_EN - ECC Detect Enable. */
+#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN(val) BSP_FLD32(val,0, 3)
+#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_TCRAM_RAMCTRL_ECC_DETECT_EN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*------------------TMS570_TCRAMRAMTHRESHOLD------------------*/
+/* field: THRESHOLD - Single-bit Error Threshold Count. */
+#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD(val) BSP_FLD32(val,0, 15)
+#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_TCRAM_RAMTHRESHOLD_THRESHOLD_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*--------------------TMS570_TCRAMRAMOCCUR--------------------*/
+/* field: SINGLE_ERROR - Single-bit Error Correction Occurrences. */
+#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR(val) BSP_FLD32(val,0, 15)
+#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_TCRAM_RAMOCCUR_SINGLE_ERROR_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_TCRAMRAMINTCTRL-------------------*/
+/* field: SERR_EN - Single-bit Error Correction Interrupt Enable. */
+#define TMS570_TCRAM_RAMINTCTRL_SERR_EN BSP_FLD32(0)
+
+
+/*------------------TMS570_TCRAMRAMERRSTATUS------------------*/
+/* field: WADDR_PAR_FAIL - This bit indicates a Write Address Parity Failure. */
+#define TMS570_TCRAM_RAMERRSTATUS_WADDR_PAR_FAIL BSP_FLD32(9)
+
+/* field: RADDR_PAR_FAIL - This bit indicates a Read Address Parity Failure. */
+#define TMS570_TCRAM_RAMERRSTATUS_RADDR_PAR_FAIL BSP_FLD32(8)
+
+/* field: DERR - This bit indicates a multi-bit error detected by the Cortex-R4F SECDED logic. */
+#define TMS570_TCRAM_RAMERRSTATUS_DERR BSP_FLD32(5)
+
+/* field: ADDR_COMP_LOGIC_FAIL - Address decode logic element failed. */
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_COMP_LOGIC_FAIL BSP_FLD32(4)
+
+/* field: ADDR_DEC_FAIL - Address decode failed. */
+#define TMS570_TCRAM_RAMERRSTATUS_ADDR_DEC_FAIL BSP_FLD32(2)
+
+/* field: SERR - Single Error Status. */
+#define TMS570_TCRAM_RAMERRSTATUS_SERR BSP_FLD32(0)
+
+
+/*------------------TMS570_TCRAMRAMSERRADDR------------------*/
+/* field: SINGLE_ERROR_ADDRESS - This register captures the bits 17-3 of the address for which the Cortex-R4F CPU */
+#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS(val) BSP_FLD32(val,3, 17)
+#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,3, 17)
+#define TMS570_TCRAM_RAMSERRADDR_SINGLE_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,3, 17)
+
+
+/*------------------TMS570_TCRAMRAMUERRADDR------------------*/
+/* field: UNCORRECTABLE - address parity error. */
+#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE(val) BSP_FLD32(val,3, 22)
+#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_GET(reg) BSP_FLD32GET(reg,3, 22)
+#define TMS570_TCRAM_RAMUERRADDR_UNCORRECTABLE_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
+
+
+/*--------------------TMS570_TCRAMRAMTEST--------------------*/
+/* field: TRIGGER - Test Trigger. */
+#define TMS570_TCRAM_RAMTEST_TRIGGER BSP_FLD32(8)
+
+/* field: TEST_MODE - Test Mode. This field selects either equality of inequality testing schemes. */
+#define TMS570_TCRAM_RAMTEST_TEST_MODE(val) BSP_FLD32(val,6, 7)
+#define TMS570_TCRAM_RAMTEST_TEST_MODE_GET(reg) BSP_FLD32GET(reg,6, 7)
+#define TMS570_TCRAM_RAMTEST_TEST_MODE_SET(reg,val) BSP_FLD32SET(reg, val,6, 7)
+
+/* field: TEST_ENABLE - Test Enable. */
+#define TMS570_TCRAM_RAMTEST_TEST_ENABLE(val) BSP_FLD32(val,0, 3)
+#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_TCRAM_RAMTEST_TEST_ENABLE_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*-----------------TMS570_TCRAMRAMADDRDECVECT-----------------*/
+/* field: ECC_SELECT - ECC Select. */
+#define TMS570_TCRAM_RAMADDRDECVECT_ECC_SELECT BSP_FLD32(26)
+
+/* field: RAM_CHIP_SELECT - RAM Chip Select. */
+#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT(val) BSP_FLD32(val,0, 15)
+#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_GET(reg) BSP_FLD32GET(reg,0, 15)
+#define TMS570_TCRAM_RAMADDRDECVECT_RAM_CHIP_SELECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
+
+
+/*-------------------TMS570_TCRAMRAMPERADDR-------------------*/
+/* field: ADDRESS_PARITY - Parity Error Address. */
+#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY(val) BSP_FLD32(val,3, 22)
+#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_GET(reg) BSP_FLD32GET(reg,3, 22)
+#define TMS570_TCRAM_RAMPERADDR_ADDRESS_PARITY_SET(reg,val) BSP_FLD32SET(reg, val,3, 22)
+
+
+
+#endif /* LIBBSP_ARM_tms570_TCRAM */
diff --git a/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
new file mode 100644
index 0000000..a52c376
--- /dev/null
+++ b/c/src/lib/libbsp/arm/tms570/include/ti_herc/reg_vim.h
@@ -0,0 +1,217 @@
+/* The header file is generated by make_header.py from VIM.json */
+/* Current script's version can be found at: */
+/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
+
+/*
+ * Copyright (c) 2014-2015, Premysl Houdek <kom541000 at gmail.com>
+ *
+ * Czech Technical University in Prague
+ * Zikova 1903/4
+ * 166 36 Praha 6
+ * Czech Republic
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation are those
+ * of the authors and should not be interpreted as representing official policies,
+ * either expressed or implied, of the FreeBSD Project.
+*/
+#ifndef LIBBSP_ARM_tms570_VIM
+#define LIBBSP_ARM_tms570_VIM
+
+#include <bsp/utility.h>
+
+typedef struct{
+ uint32_t PARFLG; /*Interrupt Vector Table Parity Flag Register*/
+ uint32_t PARCTL; /*Interrupt Vector Table Parity Control Register*/
+ uint32_t ADDERR; /*Address Parity Error Register*/
+ uint32_t FBPARERR; /*Fall-Back Address Parity Error Register*/
+ uint8_t reserved1 [4];
+ uint32_t IRQINDEX; /*IRQ Index Offset Vector Register*/
+ uint32_t FIQINDEX; /*FIQ Index Offset Vector Register*/
+ uint8_t reserved2 [8];
+ uint32_t FIRQPR[3]; /*FIQ/IRQ Program Control Register*/
+ uint8_t reserved3 [4];
+ uint32_t INTREQ[3]; /*Pending Interrupt Read Location Register*/
+ uint8_t reserved4 [4];
+ uint32_t REQENASET[3]; /*Interrupt Enable Set Register */
+ uint8_t reserved5 [4];
+ uint32_t REQENACLR[3]; /*Interrupt Enable Clear Register */
+ uint8_t reserved6 [4];
+ uint32_t WAKEENASET[3]; /*Wake-Up Enable Set Register*/
+ uint8_t reserved7 [4];
+ uint32_t WAKEENACLR[3]; /*Wake-Up Enable Clear Registers*/
+ uint8_t reserved8 [4];
+ uint32_t IRQVECREG; /*IRQ Interrupt Vector Register*/
+ uint32_t FIQVECREG; /*FIQ Interrupt Vector Register*/
+ uint32_t CAPEVT; /*Capture Event Register*/
+ uint8_t reserved9 [4];
+ uint32_t CHANCTRL[24]; /*VIM Interrupt Control Register*/
+} tms570_vim_t;
+
+
+/*----------------------TMS570_VIMPARFLG----------------------*/
+/* field: PARFLG - The PARFLG indicates that a parity error has been found and that theInterrupt Vector Table is */
+#define TMS570_VIM_PARFLG_PARFLG BSP_FLD32(0)
+
+
+/*----------------------TMS570_VIMPARCTL----------------------*/
+/* field: TEST - This bit maps the parity bits into the Interrupt Vector Table frame to make them accessible by the */
+#define TMS570_VIM_PARCTL_TEST BSP_FLD32(8)
+
+/* field: PARENA - VIM parity enable. */
+#define TMS570_VIM_PARCTL_PARENA(val) BSP_FLD32(val,0, 3)
+#define TMS570_VIM_PARCTL_PARENA_GET(reg) BSP_FLD32GET(reg,0, 3)
+#define TMS570_VIM_PARCTL_PARENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
+
+
+/*----------------------TMS570_VIMADDERR----------------------*/
+/* field: Interrupt_Vector_Table - Interrupt Vector Table offset. */
+#define TMS570_VIM_ADDERR_Interrupt_Vector_Table(val) BSP_FLD32(val,9, 31)
+#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_GET(reg) BSP_FLD32GET(reg,9, 31)
+#define TMS570_VIM_ADDERR_Interrupt_Vector_Table_SET(reg,val) BSP_FLD32SET(reg, val,9, 31)
+
+/* field: ADDERR - Address parity error register. */
+#define TMS570_VIM_ADDERR_ADDERR(val) BSP_FLD32(val,2, 8)
+#define TMS570_VIM_ADDERR_ADDERR_GET(reg) BSP_FLD32GET(reg,2, 8)
+#define TMS570_VIM_ADDERR_ADDERR_SET(reg,val) BSP_FLD32SET(reg, val,2, 8)
+
+/* field: Word_offset - Word offset. Reads are always 0; writes have no effect. */
+#define TMS570_VIM_ADDERR_Word_offset(val) BSP_FLD32(val,0, 1)
+#define TMS570_VIM_ADDERR_Word_offset_GET(reg) BSP_FLD32GET(reg,0, 1)
+#define TMS570_VIM_ADDERR_Word_offset_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
+
+
+/*---------------------TMS570_VIMFBPARERR---------------------*/
+/* field: FBPARERR - Fall back address parity error. */
+#define TMS570_VIM_FBPARERR_FBPARERR(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_FBPARERR_FBPARERR_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_FBPARERR_FBPARERR_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*---------------------TMS570_VIMIRQINDEX---------------------*/
+/* field: IRQINDEX - IRQ index vector. */
+#define TMS570_VIM_IRQINDEX_IRQINDEX(val) BSP_FLD32(val,0, 7)
+#define TMS570_VIM_IRQINDEX_IRQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_VIM_IRQINDEX_IRQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*---------------------TMS570_VIMFIQINDEX---------------------*/
+/* field: FIQINDEX - FIQ index offset vector. */
+#define TMS570_VIM_FIQINDEX_FIQINDEX(val) BSP_FLD32(val,0, 7)
+#define TMS570_VIM_FIQINDEX_FIQINDEX_GET(reg) BSP_FLD32GET(reg,0, 7)
+#define TMS570_VIM_FIQINDEX_FIQINDEX_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
+
+
+/*----------------------TMS570_VIMFIRQPR----------------------*/
+/* field: FIRQPRx - FIQ/IRQ program control bits. 96 bit register. 0-1 bits reserved. */
+#define TMS570_VIM_FIRQPR_FIRQPRx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_FIRQPR_FIRQPRx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_FIRQPR_FIRQPRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_VIMINTREQ----------------------*/
+/* field: INTREQx - Pending interrupt bits. 96 bit register. */
+#define TMS570_VIM_INTREQ_INTREQx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_INTREQ_INTREQx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_INTREQ_INTREQx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMREQENASET--------------------*/
+/* field: REQENASETx - Request enable set bits. 96 bit register. 0-1 bits reserved. */
+#define TMS570_VIM_REQENASET_REQENASETx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_REQENASET_REQENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_REQENASET_REQENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMREQENACLR--------------------*/
+/* field: REQENACLRx - Request enable clear bits. 96 bit register. 0-1 bits reserved. */
+#define TMS570_VIM_REQENACLR_REQENACLRx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_REQENACLR_REQENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_REQENACLR_REQENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMWAKEENASET--------------------*/
+/* field: WAKEENASETx - Wake-up enable set bits. This vector determines whether the wake-up interrupt line is enabled. */
+#define TMS570_VIM_WAKEENASET_WAKEENASETx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_WAKEENASET_WAKEENASETx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_WAKEENASET_WAKEENASETx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMWAKEENACLR--------------------*/
+/* field: WAKEENACLRx - Wake-up enable clear bits. This vector determines whether the wake-up interrupt line is enabled. */
+#define TMS570_VIM_WAKEENACLR_WAKEENACLRx(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_WAKEENACLR_WAKEENACLRx_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMIRQVECREG--------------------*/
+/* field: IRQVECREG - IRQ interrupt vector register. */
+#define TMS570_VIM_IRQVECREG_IRQVECREG(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_IRQVECREG_IRQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_IRQVECREG_IRQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*--------------------TMS570_VIMFIQVECREG--------------------*/
+/* field: FIQVECREG - FIQ interrupt vector register. */
+#define TMS570_VIM_FIQVECREG_FIQVECREG(val) BSP_FLD32(val,0, 31)
+#define TMS570_VIM_FIQVECREG_FIQVECREG_GET(reg) BSP_FLD32GET(reg,0, 31)
+#define TMS570_VIM_FIQVECREG_FIQVECREG_SET(reg,val) BSP_FLD32SET(reg, val,0, 31)
+
+
+/*----------------------TMS570_VIMCAPEVT----------------------*/
+/* field: CAPEVTSRC1 - Capture event source 1 mapping control. */
+#define TMS570_VIM_CAPEVT_CAPEVTSRC1(val) BSP_FLD32(val,16, 22)
+#define TMS570_VIM_CAPEVT_CAPEVTSRC1_GET(reg) BSP_FLD32GET(reg,16, 22)
+#define TMS570_VIM_CAPEVT_CAPEVTSRC1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
+
+/* field: CAPEVTSRC0 - the capture event source 0 of the RTI: */
+#define TMS570_VIM_CAPEVT_CAPEVTSRC0(val) BSP_FLD32(val,0, 6)
+#define TMS570_VIM_CAPEVT_CAPEVTSRC0_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_VIM_CAPEVT_CAPEVTSRC0_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+/*---------------------TMS570_VIMCHANCTRL---------------------*/
+/* field: CHANMAPx0 - CHANMAPx 0(6-0). Interrupt CHANx 0 mapping control. */
+#define TMS570_VIM_CHANCTRL_CHANMAPx0(val) BSP_FLD32(val,24, 30)
+#define TMS570_VIM_CHANCTRL_CHANMAPx0_GET(reg) BSP_FLD32GET(reg,24, 30)
+#define TMS570_VIM_CHANCTRL_CHANMAPx0_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
+
+/* field: CHANMAPx1 - CHANMAPx 1(6-0). Interrupt CHANx 1 mapping control. */
+#define TMS570_VIM_CHANCTRL_CHANMAPx1(val) BSP_FLD32(val,16, 22)
+#define TMS570_VIM_CHANCTRL_CHANMAPx1_GET(reg) BSP_FLD32GET(reg,16, 22)
+#define TMS570_VIM_CHANCTRL_CHANMAPx1_SET(reg,val) BSP_FLD32SET(reg, val,16, 22)
+
+/* field: CHANMAPx2 - CHANMAPx 2(6-0). Interrupt CHANx 2 mapping control. */
+#define TMS570_VIM_CHANCTRL_CHANMAPx2(val) BSP_FLD32(val,8, 14)
+#define TMS570_VIM_CHANCTRL_CHANMAPx2_GET(reg) BSP_FLD32GET(reg,8, 14)
+#define TMS570_VIM_CHANCTRL_CHANMAPx2_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
+
+/* field: CHANMAPx3 - CHANMAPx 3(6-0). Interrupt CHANx 3 mapping control. */
+#define TMS570_VIM_CHANCTRL_CHANMAPx3(val) BSP_FLD32(val,0, 6)
+#define TMS570_VIM_CHANCTRL_CHANMAPx3_GET(reg) BSP_FLD32GET(reg,0, 6)
+#define TMS570_VIM_CHANCTRL_CHANMAPx3_SET(reg,val) BSP_FLD32SET(reg, val,0, 6)
+
+
+
+#endif /* LIBBSP_ARM_tms570_VIM */
--
1.9.1
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