[PATCH] GSoC: Cache configurations Raspberry Pi 2 support

Tue Jun 23 10:57:10 UTC 2015

On Tue, Jun 23, 2015 at 1:44 PM, Sebastian Huber <
sebastian.huber at embedded-brains.de> wrote:

> Please avoid unnecessary white-space changes and white-space at the end of
> line.
>
> Something went wrong with the whitespace. I couldn't see that change in my
code. I'll rectify it.

>
> On 22/06/15 22:59, Rohini Kulkarni wrote:
>
>> ---
>>  .../arm/raspberrypi/startup/mm_config_table.c      |   18 +++++++--------
>>  c/src/lib/libbsp/arm/shared/mminit.c               |   23
>> ++++++++++++++++++++
>>  2 files changed, 32 insertions(+), 9 deletions(-)
>>
>> diff --git a/c/src/lib/libbsp/arm/raspberrypi/startup/mm_config_table.c
>> b/c/src/lib/libbsp/arm/raspberrypi/startup/mm_config_table.c
>> index 8a6d37a..dd1941e 100644
>> --- a/c/src/lib/libbsp/arm/raspberrypi/startup/mm_config_table.c
>> +++ b/c/src/lib/libbsp/arm/raspberrypi/startup/mm_config_table.c
>> @@ -31,39 +31,39 @@ const arm_cp15_start_section_config
>> arm_cp15_start_mmu_config_table[] = {
>>    }, {
>>      .begin = (uint32_t) bsp_section_fast_data_begin,
>>      .end = (uint32_t) bsp_section_fast_data_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_start_begin,
>>      .end = (uint32_t) bsp_section_start_end,
>> -    .flags = ARMV7_MMU_CODE_CACHED
>> +    .flags = ARMV7_MMU_CODE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_vector_begin,
>>      .end = (uint32_t) bsp_section_vector_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_text_begin,
>>      .end = (uint32_t) bsp_section_text_end,
>> -    .flags = ARMV7_MMU_READ_WRITE
>> +    .flags = ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B
>>
>
> Why is this not ARMV7_MMU_CODE_CACHED?  Why can't this BSP use
> ARMV7_CP15_START_DEFAULT_SECTIONS?
>
> One question that came up when I figured out last night that this was the
only required change. This was the only uncached normal memory section in
the table. So there were many changes I tried before I made this cacheable.
Why was it not made cacheable (MMU_CODE_CACHED is read only. But then yes,
why is this made read write, differently from
ARMV7_CP15_START_DEFAULT_SECTIONS)

The TEX bits 2 and 1 have been assigned the value for cacheable memory but
are used in the defines for CACHED sections.

>
>     }, {
>>      .begin = (uint32_t) bsp_section_rodata_begin,
>>      .end = (uint32_t) bsp_section_rodata_end,
>> -    .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_data_begin,
>>      .end = (uint32_t) bsp_section_data_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_bss_begin,
>>      .end = (uint32_t) bsp_section_bss_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_work_begin,
>>      .end = (uint32_t) bsp_section_work_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = (uint32_t) bsp_section_stack_begin,
>>      .end = (uint32_t) bsp_section_stack_end,
>> -    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>> +    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
>>    }, {
>>      .begin = RPI_PERIPHERAL_BASE,
>>      .end =   RPI_PERIPHERAL_BASE + RPI_PERIPHERAL_SIZE,
>> diff --git a/c/src/lib/libbsp/arm/shared/mminit.c
>> b/c/src/lib/libbsp/arm/shared/mminit.c
>> index acfbfc0..96ca1ec 100644
>> --- a/c/src/lib/libbsp/arm/shared/mminit.c
>> +++ b/c/src/lib/libbsp/arm/shared/mminit.c
>> @@ -13,6 +13,28 @@
>>  #include <bsp/linker-symbols.h>
>>  #include <bsp/mm.h>
>>
>> +#if (BSP_IS_RPI2 == 1)
>>
>
> Such a construct in a shared folder makes no sense.
>

Thats right. Will change the integration for the two memory initializations

>
>  +BSP_START_TEXT_SECTION void bsp_memory_management_initialize(void)
>> +{
>> +  /* Enable SMP in auxiliary control */
>> +  uint32_t actlr = arm_cp15_get_auxiliary_control();
>> +  actlr |= ARM_CORTEX_A9_ACTL_SMP;
>> +  arm_cp15_set_auxiliary_control(actlr);
>> +
>> +  uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
>> +    ARM_CP15_CTRL_A,
>> +    ARM_CP15_CTRL_AFE| ARM_CP15_CTRL_Z
>> +  );
>> +
>> + arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
>> +    ctrl,
>> +    (uint32_t *) bsp_translation_table_base,
>> +    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
>> +    &arm_cp15_start_mmu_config_table[0],
>> +    arm_cp15_start_mmu_config_table_size
>> +  );
>> +}
>> +#else
>>  BSP_START_TEXT_SECTION void bsp_memory_management_initialize(void)
>>  {
>>    uint32_t ctrl = arm_cp15_get_control();
>> @@ -27,3 +49,4 @@ BSP_START_TEXT_SECTION void
>> bsp_memory_management_initialize(void)
>>      arm_cp15_start_mmu_config_table_size
>>    );
>>  }
>> +#endif
>> \ No newline at end of file
>> --
>> 1.7.9.5
>>
>> --
>> Rohini Kulkarni
>>
>>
>> _______________________________________________
>> devel mailing list
>> devel at rtems.org
>> http://lists.rtems.org/mailman/listinfo/devel
>>
>
> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
> PGP     : Public key available on request.
>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>
>

-- 
Rohini Kulkarni
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