[PATCH] arm/cortex-a: Fix cache flush/invalidate after u-boot.

Chris Johns chrisj at rtems.org
Mon Aug 15 05:30:56 UTC 2016


This is a copy of the patch from Pavel to fix some strange behaviour with
data cache, instruction cache and MMU being enabled by u-boot on the
RaspberryPi.

Closes #2774.
---
 .../libbsp/arm/shared/include/arm-a9mpcore-start.h | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
index 7d6185b..08a4d7b 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h
@@ -129,8 +129,37 @@ BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
   volatile a9mpcore_scu *scu =
     (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
   uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
+  uint32_t sctlr_val;
 
+  sctlr_val = arm_cp15_get_control();
+
+  /*
+   * Current U-boot loader seems to start kernel image
+   * with I and D caches on and MMU enabled.
+   * If RTEMS application image finds that cache is on
+   * during startup then disable caches.
+   */
+  if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+    if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
+      /*
+       * If the data cache is on then ensure that it is clean
+       * before switching off to be extra carefull.
+       */
+      rtems_cache_flush_entire_data();
+      rtems_cache_invalidate_entire_data();
+    }
+    arm_cp15_flush_prefetch_buffer();
+    sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A);
+    arm_cp15_set_control(sctlr_val);
+  }
+  rtems_cache_invalidate_entire_data();
+  rtems_cache_invalidate_entire_instruction();
   arm_cp15_branch_predictor_invalidate_all();
+  arm_cp15_tlb_invalidate();
+  arm_cp15_flush_prefetch_buffer();
+
+  /* Clear Translation Table Base Control Register */
+  arm_cp15_set_translation_table_base_control_register(0);
 
   if (cpu_id == 0) {
     arm_a9mpcore_start_scu_enable(scu);
-- 
2.4.6



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