[PATCH 2/2] RTEMS changes for lpc32xx VFP support

Kirspel, Kevin Kevin-Kirspel at idexx.com
Mon Aug 22 15:24:59 UTC 2016


diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
old mode 100644
new mode 100755
index f184741..441976d
--- a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
+++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc
@@ -6,7 +6,8 @@ include $(RTEMS_ROOT)/make/custom/default.cfg

RTEMS_CPU = arm

-CPU_CFLAGS = -mcpu=arm926ej-s -mthumb
+#CPU_CFLAGS = -mcpu=arm926ej-s -mthumb
+CPU_CFLAGS = -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=hard

CFLAGS_OPTIMIZE_V ?= -O2 -g
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
diff --git a/c/src/lib/libbsp/arm/shared/start/start.S b/c/src/lib/libbsp/arm/shared/start/start.S
old mode 100644
new mode 100755
index 30501be..f95a9d3
--- a/c/src/lib/libbsp/arm/shared/start/start.S
+++ b/c/src/lib/libbsp/arm/shared/start/start.S
@@ -19,9 +19,9 @@
  */

#include <rtems/asm.h>
-#include <rtems/system.h>
+#include <rtems/system.h>
#include <rtems/score/cpu.h>
-
+
#include <bspopts.h>
#include <bsp/irq.h>
#include <bsp/linker-symbols.h>
@@ -265,6 +265,7 @@ bsp_start_skip_hyp_svc_switch:
               /* Stay in SVC mode */

#ifdef ARM_MULTILIB_VFP
+#ifdef ARM_MULTILIB_HAS_CPACR
               /* Read CPACR */
               mrc p15, 0, r0, c1, c0, 2

@@ -280,11 +281,18 @@ bsp_start_skip_hyp_svc_switch:
               /* Write CPACR */
               mcr p15, 0, r0, c1, c0, 2
               isb
+#endif

               /* Enable FPU */
               mov r0, #(1 << 30)
               vmsr FPEXC, r0

+#ifdef __FAST_MATH__
+  /* Enable Fast FPU options */
+  mov r0, #(3 << 24)
+  vmsr FPSCR, r0
+#endif
+
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
               bl bsp_start_init_registers_vfp
#endif
@@ -399,6 +407,7 @@ _start:
#endif

#ifdef ARM_MULTILIB_VFP
+#ifdef ARM_MULTILIB_HAS_CPACR
               /*
                * Enable CP10 and CP11 coprocessors for privileged and user mode in
                * CPACR (bits 20-23).  Ensure that write to register completes.
@@ -409,6 +418,7 @@ _start:
               str           r1, [r0]
               dsb
               isb
+#endif

#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
               bl bsp_start_init_registers_vfp
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
old mode 100644
new mode 100755
index 666ee54..7e511ac
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -57,6 +57,13 @@ extern "C" {
#if defined(__ARM_ARCH_7A__)
   #define ARM_MULTILIB_CACHE_LINE_MAX_64
#endif
+
+#if defined(__ARM_ARCH_7A__) \
+  || defined(__ARM_ARCH_7M__) \
+  || defined(__ARM_ARCH_7EM__)
+  #define ARM_MULTILIB_HAS_CPACR
+#endif
+

#if !defined(__SOFTFP__)
   #if defined(__ARM_NEON__)
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