[PATCH 6/7] OR1k cache invalidate additions

[Jakob Viketoft]

diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2..49f5ca9 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -4,9 +4,14 @@
  * COPYRIGHT (c) 1989-2006
  * On-Line Applications Research Corporation (OAR).
  *
+ * Copyright (c) 2014 ÅAC Microtec AB <www.aacmicrotec.com>
+ * Contributor(s):
+ *  Karol Gugala <kgugala at antmicro.com>
+ *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
  * http://www.rtems.org/license/LICENSE.
+ *
  */
 
 #include <rtems/score/cpu.h>
@@ -14,13 +19,15 @@
 #include <rtems/score/or1k-utility.h>
 #include <rtems/score/percpu.h>
 #include <libcpu/cache.h>
+#include <cache_.h>
 
 static inline void _CPU_OR1K_Cache_enable_data(void)
 {
   uint32_t sr;
-   ISR_Level level;
+  ISR_Level level;
 
   _ISR_Disable (level);
+
   sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
   _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
 
@@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
 static inline void _CPU_OR1K_Cache_disable_data(void)
 {
   uint32_t sr;
-   ISR_Level level;
+  ISR_Level level;
 
   _ISR_Disable (level);
 
@@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
 static inline void _CPU_OR1K_Cache_enable_instruction(void)
 {
   uint32_t sr;
-   ISR_Level level;
+  ISR_Level level;
 
   _ISR_Disable (level);
 
@@ -79,7 +86,8 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 
 static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
@@ -89,7 +97,8 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
 
 static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
@@ -99,7 +108,8 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
 
 static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
@@ -109,7 +119,8 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
 
 static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
@@ -120,7 +131,8 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
 static inline void _CPU_OR1K_Cache_instruction_block_prefetch
 (const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
@@ -131,7 +143,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch
 static inline void _CPU_OR1K_Cache_instruction_block_invalidate
 (const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
@@ -142,7 +155,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate
 static inline void _CPU_OR1K_Cache_instruction_block_lock
 (const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
@@ -152,9 +166,11 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 
 /* Implement RTEMS cache manager functions */
 
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+void _CPU_cache_flush_1_data_line
+(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _CPU_OR1K_Cache_data_block_flush(d_addr);
@@ -164,9 +180,11 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
   _ISR_Enable(level);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+void _CPU_cache_invalidate_1_data_line
+(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _CPU_OR1K_Cache_data_block_invalidate(d_addr);
@@ -184,9 +202,11 @@ void _CPU_cache_unfreeze_data(void)
   /* Do nothing */
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+void _CPU_cache_invalidate_1_instruction_line
+(const void *d_addr)
 {
-   ISR_Level level;
+  ISR_Level level;
+
   _ISR_Disable (level);
 
   _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
@@ -206,17 +226,45 @@ void _CPU_cache_unfreeze_instruction(void)
 
 void _CPU_cache_flush_entire_data(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (addr = _CPU_cache_get_data_cache_size(0);
+       addr > 0;
+       addr -= CPU_DATA_CACHE_ALIGNMENT) {
+    _CPU_OR1K_Cache_data_block_flush((void*) addr);
+  }
 }
 
 void _CPU_cache_invalidate_entire_data(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (addr = _CPU_cache_get_data_cache_size(0);
+       addr > 0;
+       addr -= CPU_DATA_CACHE_ALIGNMENT) {
+    _CPU_cache_invalidate_1_data_line((void*) addr);
+  }
 }
 
 void _CPU_cache_invalidate_entire_instruction(void)
 {
-
+  int addr;
+
+  /* We have only 0 level cache so we do not need to invalidate others */
+  for (addr = _CPU_cache_get_instruction_cache_size(0);
+       addr > 0;
+       addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT) {
+    _CPU_cache_invalidate_1_instruction_line((void*) addr);
+  }
+
+  /* Flush instructions out of instruction buffer */
+  asm volatile("l.nop");
+  asm volatile("l.nop");
+  asm volatile("l.nop");
+  asm volatile("l.nop");
+  asm volatile("l.nop");
 }
 
 void _CPU_cache_enable_data(void)


Jakob Viketoft
Senior Engineer in RTL and embedded software

ÅAC Microtec AB
Dag Hammarskjölds väg 48
SE-751 83 Uppsala, Sweden

T: +46 702 80 95 97
http://www.aacmicrotec.com