[PATCH 7/8] OR1k cache flush/invalidate additions
Jakob Viketoft
jakob.viketoft at aacmicrotec.com
Wed Feb 24 22:15:02 UTC 2016
_______________________________________
From: devel [devel-bounces at rtems.org] on behalf of Hesham Almatary [heshamelmatary at gmail.com]
Sent: Wednesday, February 24, 2016 18:08
To: jakob.viketoft at gmail.com
Cc: rtems-devel at rtems.org
Subject: Re: [PATCH 7/8] OR1k cache flush/invalidate additions
>This definition conflicts with the prototype at
>ibcpu/include/cache.h. It produces a compilation error
Which only goes to show that I really shouldn't be doing stuff like this late Saturday evening. :)
Anyway, I inline and attach (since there was some stuff with encoding etc which played foul tricks on the previous version) a new version of the patch which _should_ work.
/Jakob
>From 2c27d1b315c75c787ccbfa353a5757d52ea309ff Mon Sep 17 00:00:00 2001
From: Jakob Viketoft <jakob.viketoft at aacmicrotec.com>
Date: Sat, 20 Feb 2016 23:23:27 +0100
Subject: [PATCH 7/8] OR1k cache flush/invalidate additions
Close #2602
---
c/src/lib/libcpu/or1k/shared/cache/cache.c | 113 ++++++++++++++++++++++-------
1 file changed, 86 insertions(+), 27 deletions(-)
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2..ff28a61 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -4,9 +4,14 @@
* COPYRIGHT (c) 1989-2006
* On-Line Applications Research Corporation (OAR).
*
+ * Copyright (c) 2014 ÅAC Microtec AB <www.aacmicrotec.com>
+ * Contributor(s):
+ * Karol Gugala <kgugala at antmicro.com>
+ *
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
+ *
*/
#include <rtems/score/cpu.h>
@@ -14,13 +19,15 @@
#include <rtems/score/or1k-utility.h>
#include <rtems/score/percpu.h>
#include <libcpu/cache.h>
+#include <cache_.h>
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
+
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
@@ -30,7 +37,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
static inline void _CPU_OR1K_Cache_disable_data(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -43,7 +50,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
static inline void _CPU_OR1K_Cache_enable_instruction(void)
{
uint32_t sr;
- ISR_Level level;
+ ISR_Level level;
_ISR_Disable (level);
@@ -66,7 +73,8 @@ static inline void _CPU_OR1K_Cache_disable_instruction(void)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_prefetch
+(const void *d_addr)
{
ISR_Level level;
@@ -77,9 +85,11 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_flush
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
@@ -87,9 +97,11 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_invalidate
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
@@ -97,9 +109,11 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_writeback
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
@@ -107,9 +121,11 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
_ISR_Enable(level);
}
-static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
+static inline void _CPU_OR1K_Cache_data_block_lock
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
@@ -120,7 +136,8 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
@@ -131,7 +148,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
@@ -142,7 +160,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
@@ -152,24 +171,28 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
/* Implement RTEMS cache manager functions */
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+void _CPU_cache_flush_1_data_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _CPU_OR1K_Cache_data_block_flush(d_addr);
+ _CPU_OR1K_Cache_data_block_flush((uintptr_t) d_addr);
//asm volatile("l.csync");
_ISR_Enable(level);
}
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+void _CPU_cache_invalidate_1_data_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _CPU_OR1K_Cache_data_block_invalidate(d_addr);
+ _CPU_OR1K_Cache_data_block_invalidate((uintptr_t) d_addr);
_ISR_Enable(level);
}
@@ -184,12 +207,14 @@ void _CPU_cache_unfreeze_data(void)
/* Do nothing */
}
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+void _CPU_cache_invalidate_1_instruction_line
+(const void *d_addr)
{
- ISR_Level level;
+ ISR_Level level;
+
_ISR_Disable (level);
- _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
+ _CPU_OR1K_Cache_instruction_block_invalidate((uintptr_t) d_addr);
_ISR_Enable(level);
}
@@ -206,17 +231,51 @@ void _CPU_cache_unfreeze_instruction(void)
void _CPU_cache_flush_entire_data(void)
{
-
+ int addr;
+
+ /* We have only 0 level cache so we do not need to invalidate others */
+ for (
+ addr = _CPU_cache_get_data_cache_size(0);
+ addr > 0;
+ addr -= CPU_DATA_CACHE_ALIGNMENT
+ ) {
+ _CPU_OR1K_Cache_data_block_flush((void*) addr);
+ }
}
void _CPU_cache_invalidate_entire_data(void)
{
-
+ int addr;
+
+ /* We have only 0 level cache so we do not need to invalidate others */
+ for (
+ addr = _CPU_cache_get_data_cache_size(0);
+ addr > 0;
+ addr -= CPU_DATA_CACHE_ALIGNMENT
+ ) {
+ _CPU_cache_invalidate_1_data_line((void*) addr);
+ }
}
void _CPU_cache_invalidate_entire_instruction(void)
{
-
+ int addr;
+
+ /* We have only 0 level cache so we do not need to invalidate others */
+ for (
+ addr = _CPU_cache_get_instruction_cache_size(0);
+ addr > 0;
+ addr -= CPU_INSTRUCTION_CACHE_ALIGNMENT
+ ) {
+ _CPU_cache_invalidate_1_instruction_line((void*) addr);
+ }
+
+ /* Flush instructions out of instruction buffer */
+ asm volatile("l.nop");
+ asm volatile("l.nop");
+ asm volatile("l.nop");
+ asm volatile("l.nop");
+ asm volatile("l.nop");
}
void _CPU_cache_enable_data(void)
--
2.1.4
Jakob Viketoft
Senior Engineer in RTL and embedded software
ÅAC Microtec AB
Dag Hammarskjölds väg 48
SE-751 83 Uppsala, Sweden
T: +46 702 80 95 97
http://www.aacmicrotec.com
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