[PATCH 6/6] Remove AVR Architectural Port

Joel Sherrill joel at rtems.org
Sun Jan 3 21:28:08 UTC 2016


From: Joel Sherrill <joel.sherrill at oarcorp.com>

Updates #2443.
---
 c/src/aclocal/check-networking.m4                |    2 +-
 c/src/aclocal/rtems-cpu-subdirs.m4               |    1 -
 c/src/lib/libbsp/avr/Makefile.am                 |    9 -
 c/src/lib/libbsp/avr/acinclude.m4                |    8 -
 c/src/lib/libbsp/avr/avrtest/configure.ac        |   20 -
 c/src/lib/libbsp/avr/configure.ac                |   19 -
 cpukit/aclocal/check-networking.m4               |    2 +-
 cpukit/configure.ac                              |    1 -
 cpukit/librpc/src/xdr/xdr_float.c                |    1 -
 cpukit/score/cpu/Makefile.am                     |    1 -
 cpukit/score/cpu/avr/Makefile.am                 |  170 -
 cpukit/score/cpu/avr/README                      |    5 -
 cpukit/score/cpu/avr/avr-exception-frame-print.c |   24 -
 cpukit/score/cpu/avr/avr/boot.h                  |  687 --
 cpukit/score/cpu/avr/avr/common.h                |  335 -
 cpukit/score/cpu/avr/avr/crc16.h                 |   54 -
 cpukit/score/cpu/avr/avr/delay.h                 |   55 -
 cpukit/score/cpu/avr/avr/eeprom.h                |  620 --
 cpukit/score/cpu/avr/avr/fuse.h                  |  268 -
 cpukit/score/cpu/avr/avr/interrupt.h             |  343 -
 cpukit/score/cpu/avr/avr/io.h                    |  429 --
 cpukit/score/cpu/avr/avr/io1200.h                |  282 -
 cpukit/score/cpu/avr/avr/io2313.h                |  370 --
 cpukit/score/cpu/avr/avr/io2323.h                |  203 -
 cpukit/score/cpu/avr/avr/io2333.h                |  456 --
 cpukit/score/cpu/avr/avr/io2343.h                |  221 -
 cpukit/score/cpu/avr/avr/io43u32x.h              |  448 --
 cpukit/score/cpu/avr/avr/io43u35x.h              |  440 --
 cpukit/score/cpu/avr/avr/io4414.h                |  501 --
 cpukit/score/cpu/avr/avr/io4433.h                |  484 --
 cpukit/score/cpu/avr/avr/io4434.h                |  578 --
 cpukit/score/cpu/avr/avr/io76c711.h              |  511 --
 cpukit/score/cpu/avr/avr/io8515.h                |  485 --
 cpukit/score/cpu/avr/avr/io8534.h                |  233 -
 cpukit/score/cpu/avr/avr/io8535.h                |  580 --
 cpukit/score/cpu/avr/avr/io86r401.h              |  321 -
 cpukit/score/cpu/avr/avr/io90pwm1.h              | 1137 ----
 cpukit/score/cpu/avr/avr/io90pwm216.h            | 1197 ----
 cpukit/score/cpu/avr/avr/io90pwm2b.h             | 1404 ----
 cpukit/score/cpu/avr/avr/io90pwm316.h            | 1223 ----
 cpukit/score/cpu/avr/avr/io90pwm3b.h             | 1408 ----
 cpukit/score/cpu/avr/avr/io90pwm81.h             | 1040 ---
 cpukit/score/cpu/avr/avr/io90pwmx.h              | 1387 ----
 cpukit/score/cpu/avr/avr/io90scr100.h            | 1708 -----
 cpukit/score/cpu/avr/avr/ioa6289.h               |  855 ---
 cpukit/score/cpu/avr/avr/ioat94k.h               |  569 --
 cpukit/score/cpu/avr/avr/iocan128.h              |   93 -
 cpukit/score/cpu/avr/avr/iocan32.h               |  109 -
 cpukit/score/cpu/avr/avr/iocan64.h               |   93 -
 cpukit/score/cpu/avr/avr/iocanxx.h               | 1990 ------
 cpukit/score/cpu/avr/avr/iom103.h                |  687 --
 cpukit/score/cpu/avr/avr/iom128.h                | 1215 ----
 cpukit/score/cpu/avr/avr/iom1280.h               |  108 -
 cpukit/score/cpu/avr/avr/iom1281.h               |  106 -
 cpukit/score/cpu/avr/avr/iom1284p.h              | 1141 ----
 cpukit/score/cpu/avr/avr/iom128rfa1.h            | 5372 ---------------
 cpukit/score/cpu/avr/avr/iom16.h                 |  625 --
 cpukit/score/cpu/avr/avr/iom161.h                |  685 --
 cpukit/score/cpu/avr/avr/iom162.h                |  964 ---
 cpukit/score/cpu/avr/avr/iom163.h                |  651 --
 cpukit/score/cpu/avr/avr/iom164.h                |  108 -
 cpukit/score/cpu/avr/avr/iom165.h                |  836 ---
 cpukit/score/cpu/avr/avr/iom165p.h               |  821 ---
 cpukit/score/cpu/avr/avr/iom168.h                |  104 -
 cpukit/score/cpu/avr/avr/iom168p.h               |  885 ---
 cpukit/score/cpu/avr/avr/iom169.h                | 1123 ----
 cpukit/score/cpu/avr/avr/iom169p.h               | 1046 ---
 cpukit/score/cpu/avr/avr/iom169pa.h              | 1483 -----
 cpukit/score/cpu/avr/avr/iom16a.h                |  937 ---
 cpukit/score/cpu/avr/avr/iom16hva.h              |   89 -
 cpukit/score/cpu/avr/avr/iom16hva2.h             |  881 ---
 cpukit/score/cpu/avr/avr/iom16hvb.h              | 1049 ---
 cpukit/score/cpu/avr/avr/iom16m1.h               | 1557 -----
 cpukit/score/cpu/avr/avr/iom16u2.h               |  990 ---
 cpukit/score/cpu/avr/avr/iom16u4.h               | 1366 ----
 cpukit/score/cpu/avr/avr/iom2560.h               |  109 -
 cpukit/score/cpu/avr/avr/iom2561.h               |   93 -
 cpukit/score/cpu/avr/avr/iom32.h                 |  707 --
 cpukit/score/cpu/avr/avr/iom323.h                |  699 --
 cpukit/score/cpu/avr/avr/iom324.h                |  105 -
 cpukit/score/cpu/avr/avr/iom324pa.h              | 1354 ----
 cpukit/score/cpu/avr/avr/iom325.h                |  837 ---
 cpukit/score/cpu/avr/avr/iom3250.h               |  936 ---
 cpukit/score/cpu/avr/avr/iom328p.h               |  891 ---
 cpukit/score/cpu/avr/avr/iom329.h                | 1031 ---
 cpukit/score/cpu/avr/avr/iom3290.h               | 1169 ----
 cpukit/score/cpu/avr/avr/iom32c1.h               | 1308 ----
 cpukit/score/cpu/avr/avr/iom32hvb.h              |  884 ---
 cpukit/score/cpu/avr/avr/iom32m1.h               | 1582 -----
 cpukit/score/cpu/avr/avr/iom32u2.h               | 1009 ---
 cpukit/score/cpu/avr/avr/iom32u4.h               | 1518 -----
 cpukit/score/cpu/avr/avr/iom32u6.h               | 1421 ----
 cpukit/score/cpu/avr/avr/iom406.h                |  780 ---
 cpukit/score/cpu/avr/avr/iom48.h                 |  100 -
 cpukit/score/cpu/avr/avr/iom48p.h                |  879 ---
 cpukit/score/cpu/avr/avr/iom64.h                 | 1226 ----
 cpukit/score/cpu/avr/avr/iom640.h                |  106 -
 cpukit/score/cpu/avr/avr/iom644.h                |  108 -
 cpukit/score/cpu/avr/avr/iom644p.h               |  109 -
 cpukit/score/cpu/avr/avr/iom644pa.h              | 1380 ----
 cpukit/score/cpu/avr/avr/iom645.h                |  827 ---
 cpukit/score/cpu/avr/avr/iom6450.h               |  923 ---
 cpukit/score/cpu/avr/avr/iom649.h                | 1005 ---
 cpukit/score/cpu/avr/avr/iom6490.h               | 1158 ----
 cpukit/score/cpu/avr/avr/iom649p.h               | 1476 -----
 cpukit/score/cpu/avr/avr/iom64c1.h               | 1313 ----
 cpukit/score/cpu/avr/avr/iom64hve.h              | 1030 ---
 cpukit/score/cpu/avr/avr/iom64m1.h               | 1581 -----
 cpukit/score/cpu/avr/avr/iom8.h                  |  630 --
 cpukit/score/cpu/avr/avr/iom8515.h               |  647 --
 cpukit/score/cpu/avr/avr/iom8535.h               |  737 ---
 cpukit/score/cpu/avr/avr/iom88.h                 |  105 -
 cpukit/score/cpu/avr/avr/iom88p.h                |  884 ---
 cpukit/score/cpu/avr/avr/iom88pa.h               | 1166 ----
 cpukit/score/cpu/avr/avr/iom8hva.h               |   84 -
 cpukit/score/cpu/avr/avr/iom8u2.h                |  983 ---
 cpukit/score/cpu/avr/avr/iomx8.h                 |  747 ---
 cpukit/score/cpu/avr/avr/iomxx0_1.h              | 1564 -----
 cpukit/score/cpu/avr/avr/iomxx4.h                |  882 ---
 cpukit/score/cpu/avr/avr/iomxxhva.h              |  534 --
 cpukit/score/cpu/avr/avr/iotn11.h                |  246 -
 cpukit/score/cpu/avr/avr/iotn12.h                |  276 -
 cpukit/score/cpu/avr/avr/iotn13.h                |  376 --
 cpukit/score/cpu/avr/avr/iotn13a.h               |  409 --
 cpukit/score/cpu/avr/avr/iotn15.h                |  345 -
 cpukit/score/cpu/avr/avr/iotn167.h               |  846 ---
 cpukit/score/cpu/avr/avr/iotn22.h                |  204 -
 cpukit/score/cpu/avr/avr/iotn2313.h              |  649 --
 cpukit/score/cpu/avr/avr/iotn2313a.h             |  779 ---
 cpukit/score/cpu/avr/avr/iotn24.h                |  101 -
 cpukit/score/cpu/avr/avr/iotn24a.h               |  841 ---
 cpukit/score/cpu/avr/avr/iotn25.h                |   88 -
 cpukit/score/cpu/avr/avr/iotn26.h                |  401 --
 cpukit/score/cpu/avr/avr/iotn261.h               |  102 -
 cpukit/score/cpu/avr/avr/iotn261a.h              |  986 ---
 cpukit/score/cpu/avr/avr/iotn28.h                |  291 -
 cpukit/score/cpu/avr/avr/iotn4313.h              |  779 ---
 cpukit/score/cpu/avr/avr/iotn43u.h               |  586 --
 cpukit/score/cpu/avr/avr/iotn44.h                |  101 -
 cpukit/score/cpu/avr/avr/iotn44a.h               |  830 ---
 cpukit/score/cpu/avr/avr/iotn45.h                |  101 -
 cpukit/score/cpu/avr/avr/iotn461.h               |  103 -
 cpukit/score/cpu/avr/avr/iotn461a.h              |  986 ---
 cpukit/score/cpu/avr/avr/iotn48.h                |  767 ---
 cpukit/score/cpu/avr/avr/iotn84.h                |   88 -
 cpukit/score/cpu/avr/avr/iotn85.h                |  101 -
 cpukit/score/cpu/avr/avr/iotn861.h               |  105 -
 cpukit/score/cpu/avr/avr/iotn861a.h              |  986 ---
 cpukit/score/cpu/avr/avr/iotn87.h                |  856 ---
 cpukit/score/cpu/avr/avr/iotn88.h                |  772 ---
 cpukit/score/cpu/avr/avr/iotnx4.h                |  464 --
 cpukit/score/cpu/avr/avr/iotnx5.h                |  428 --
 cpukit/score/cpu/avr/avr/iotnx61.h               |  528 --
 cpukit/score/cpu/avr/avr/iousb1286.h             |  105 -
 cpukit/score/cpu/avr/avr/iousb1287.h             |  106 -
 cpukit/score/cpu/avr/avr/iousb162.h              |  109 -
 cpukit/score/cpu/avr/avr/iousb646.h              |  106 -
 cpukit/score/cpu/avr/avr/iousb647.h              |  108 -
 cpukit/score/cpu/avr/avr/iousb82.h               |  102 -
 cpukit/score/cpu/avr/avr/iousbxx2.h              |  779 ---
 cpukit/score/cpu/avr/avr/iousbxx6_7.h            | 1296 ----
 cpukit/score/cpu/avr/avr/iox128a1.h              | 7583 ----------------------
 cpukit/score/cpu/avr/avr/iox128a3.h              | 6900 --------------------
 cpukit/score/cpu/avr/avr/iox128d3.h              | 5645 ----------------
 cpukit/score/cpu/avr/avr/iox16a4.h               | 6655 -------------------
 cpukit/score/cpu/avr/avr/iox16d4.h               | 5552 ----------------
 cpukit/score/cpu/avr/avr/iox192a3.h              | 6900 --------------------
 cpukit/score/cpu/avr/avr/iox192d3.h              | 5655 ----------------
 cpukit/score/cpu/avr/avr/iox256a3.h              | 6889 --------------------
 cpukit/score/cpu/avr/avr/iox256a3b.h             | 6902 --------------------
 cpukit/score/cpu/avr/avr/iox256d3.h              | 5468 ----------------
 cpukit/score/cpu/avr/avr/iox32a4.h               | 6655 -------------------
 cpukit/score/cpu/avr/avr/iox32d4.h               | 5560 ----------------
 cpukit/score/cpu/avr/avr/iox64a1.h               | 7150 --------------------
 cpukit/score/cpu/avr/avr/iox64a3.h               | 6899 --------------------
 cpukit/score/cpu/avr/avr/iox64d3.h               | 5669 ----------------
 cpukit/score/cpu/avr/avr/lock.h                  |  243 -
 cpukit/score/cpu/avr/avr/parity.h                |   55 -
 cpukit/score/cpu/avr/avr/pgmspace.h              |  887 ---
 cpukit/score/cpu/avr/avr/portpins.h              |  554 --
 cpukit/score/cpu/avr/avr/power.h                 | 1201 ----
 cpukit/score/cpu/avr/avr/sfr_defs.h              |  272 -
 cpukit/score/cpu/avr/avr/signal.h                |   54 -
 cpukit/score/cpu/avr/avr/signature.h             |   90 -
 cpukit/score/cpu/avr/avr/sleep.h                 |  609 --
 cpukit/score/cpu/avr/avr/version.h               |  100 -
 cpukit/score/cpu/avr/avr/wdt.h                   |  420 --
 cpukit/score/cpu/avr/cpu.c                       |  131 -
 cpukit/score/cpu/avr/cpu_asm.S                   |  458 --
 cpukit/score/cpu/avr/preinstall.am               |  646 --
 cpukit/score/cpu/avr/rtems/asm.h                 |  464 --
 cpukit/score/cpu/avr/rtems/score/avr.h           |  111 -
 cpukit/score/cpu/avr/rtems/score/cpu.h           | 1176 ----
 cpukit/score/cpu/avr/rtems/score/cpu_asm.h       |   72 -
 cpukit/score/cpu/avr/rtems/score/cpuatomic.h     |   14 -
 cpukit/score/cpu/avr/rtems/score/types.h         |   47 -
 doc/cpu_supplement/Makefile.am                   |    6 -
 doc/cpu_supplement/avr.t                         |  133 -
 doc/cpu_supplement/cpu_supplement.texi           |    2 -
 doc/user/preface.texi                            |    1 -
 testsuites/support/include/buffer_test_io.h      |    4 +-
 201 files changed, 3 insertions(+), 208887 deletions(-)
 delete mode 100644 c/src/lib/libbsp/avr/Makefile.am
 delete mode 100644 c/src/lib/libbsp/avr/acinclude.m4
 delete mode 100644 c/src/lib/libbsp/avr/avrtest/configure.ac
 delete mode 100644 c/src/lib/libbsp/avr/configure.ac
 delete mode 100644 cpukit/score/cpu/avr/Makefile.am
 delete mode 100644 cpukit/score/cpu/avr/README
 delete mode 100644 cpukit/score/cpu/avr/avr-exception-frame-print.c
 delete mode 100644 cpukit/score/cpu/avr/avr/boot.h
 delete mode 100644 cpukit/score/cpu/avr/avr/common.h
 delete mode 100644 cpukit/score/cpu/avr/avr/crc16.h
 delete mode 100644 cpukit/score/cpu/avr/avr/delay.h
 delete mode 100644 cpukit/score/cpu/avr/avr/eeprom.h
 delete mode 100644 cpukit/score/cpu/avr/avr/fuse.h
 delete mode 100644 cpukit/score/cpu/avr/avr/interrupt.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io1200.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io2313.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io2323.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io2333.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io2343.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io43u32x.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io43u35x.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io4414.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io4433.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io4434.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io76c711.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io8515.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io8534.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io8535.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io86r401.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm216.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm2b.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm316.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm3b.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwm81.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90pwmx.h
 delete mode 100644 cpukit/score/cpu/avr/avr/io90scr100.h
 delete mode 100644 cpukit/score/cpu/avr/avr/ioa6289.h
 delete mode 100644 cpukit/score/cpu/avr/avr/ioat94k.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iocan128.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iocan32.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iocan64.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iocanxx.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom103.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom128.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom1280.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom1281.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom1284p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom128rfa1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom161.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom162.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom163.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom164.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom165.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom165p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom168.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom168p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom169.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom169p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom169pa.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16hva.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16hva2.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16hvb.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16m1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16u2.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom16u4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom2560.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom2561.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom323.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom324.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom324pa.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom325.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom3250.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom328p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom329.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom3290.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32c1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32hvb.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32m1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32u2.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32u4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom32u6.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom406.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom48.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom48p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom64.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom640.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom644.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom644p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom644pa.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom645.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom6450.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom649.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom6490.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom649p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom64c1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom64hve.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom64m1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom8.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom8515.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom8535.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom88.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom88p.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom88pa.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom8hva.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iom8u2.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iomx8.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iomxx0_1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iomxx4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iomxxhva.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn11.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn12.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn13.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn13a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn15.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn167.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn22.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn2313.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn2313a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn24.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn24a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn25.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn26.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn261.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn261a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn28.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn4313.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn43u.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn44.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn44a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn45.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn461.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn461a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn48.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn84.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn85.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn861.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn861a.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn87.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotn88.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotnx4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotnx5.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iotnx61.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb1286.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb1287.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb162.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb646.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb647.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousb82.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousbxx2.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iousbxx6_7.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox128a1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox128a3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox128d3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox16a4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox16d4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox192a3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox192d3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox256a3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox256a3b.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox256d3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox32a4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox32d4.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox64a1.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox64a3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/iox64d3.h
 delete mode 100644 cpukit/score/cpu/avr/avr/lock.h
 delete mode 100644 cpukit/score/cpu/avr/avr/parity.h
 delete mode 100644 cpukit/score/cpu/avr/avr/pgmspace.h
 delete mode 100644 cpukit/score/cpu/avr/avr/portpins.h
 delete mode 100644 cpukit/score/cpu/avr/avr/power.h
 delete mode 100644 cpukit/score/cpu/avr/avr/sfr_defs.h
 delete mode 100644 cpukit/score/cpu/avr/avr/signal.h
 delete mode 100644 cpukit/score/cpu/avr/avr/signature.h
 delete mode 100644 cpukit/score/cpu/avr/avr/sleep.h
 delete mode 100644 cpukit/score/cpu/avr/avr/version.h
 delete mode 100644 cpukit/score/cpu/avr/avr/wdt.h
 delete mode 100644 cpukit/score/cpu/avr/cpu.c
 delete mode 100644 cpukit/score/cpu/avr/cpu_asm.S
 delete mode 100644 cpukit/score/cpu/avr/preinstall.am
 delete mode 100644 cpukit/score/cpu/avr/rtems/asm.h
 delete mode 100644 cpukit/score/cpu/avr/rtems/score/avr.h
 delete mode 100644 cpukit/score/cpu/avr/rtems/score/cpu.h
 delete mode 100644 cpukit/score/cpu/avr/rtems/score/cpu_asm.h
 delete mode 100644 cpukit/score/cpu/avr/rtems/score/cpuatomic.h
 delete mode 100644 cpukit/score/cpu/avr/rtems/score/types.h
 delete mode 100644 doc/cpu_supplement/avr.t

diff --git a/c/src/aclocal/check-networking.m4 b/c/src/aclocal/check-networking.m4
index 69265ac..250d669 100644
--- a/c/src/aclocal/check-networking.m4
+++ b/c/src/aclocal/check-networking.m4
@@ -8,7 +8,7 @@ AC_CACHE_CHECK([whether BSP supports networking],
   [dnl
     case "$RTEMS_CPU" in
     # do not have address space to hold BSD TCP/IP stack
-    avr*|m32c*)
+    m32c*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
     *)
diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4
index 5f10bda..44d38c9 100644
--- a/c/src/aclocal/rtems-cpu-subdirs.m4
+++ b/c/src/aclocal/rtems-cpu-subdirs.m4
@@ -13,7 +13,6 @@ case $RTEMS_CPU in
 _RTEMS_CPU_SUBDIR([arm],[$1]);;
 _RTEMS_CPU_SUBDIR([bfin],[$1]);;
 _RTEMS_CPU_SUBDIR([epiphany],[$1]);;
-_RTEMS_CPU_SUBDIR([avr],[$1]);;
 _RTEMS_CPU_SUBDIR([i386],[$1]);;
 _RTEMS_CPU_SUBDIR([lm32],[$1]);;
 _RTEMS_CPU_SUBDIR([m32c],[$1]);;
diff --git a/c/src/lib/libbsp/avr/Makefile.am b/c/src/lib/libbsp/avr/Makefile.am
deleted file mode 100644
index f504c03..0000000
--- a/c/src/lib/libbsp/avr/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-ACLOCAL_AMFLAGS = -I ../../../aclocal
-
-## Descend into the @RTEMS_BSP_FAMILY@ directory
-SUBDIRS = @RTEMS_BSP_FAMILY@
-
-EXTRA_DIST =
-
-include $(top_srcdir)/../../../automake/subdirs.am
-include $(top_srcdir)/../../../automake/local.am
diff --git a/c/src/lib/libbsp/avr/acinclude.m4 b/c/src/lib/libbsp/avr/acinclude.m4
deleted file mode 100644
index 296a6f7..0000000
--- a/c/src/lib/libbsp/avr/acinclude.m4
+++ /dev/null
@@ -1,8 +0,0 @@
-# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
-AC_DEFUN([RTEMS_CHECK_BSPDIR],
-[
-  case "$1" in
-  *)
-    AC_MSG_ERROR([Invalid BSP]);;
-  esac
-])
diff --git a/c/src/lib/libbsp/avr/avrtest/configure.ac b/c/src/lib/libbsp/avr/avrtest/configure.ac
deleted file mode 100644
index f9c0b5c..0000000
--- a/c/src/lib/libbsp/avr/avrtest/configure.ac
+++ /dev/null
@@ -1,20 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-avr-avrtest],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-AC_CONFIG_SRCDIR([bsp_specs])
-RTEMS_TOP(../../../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2])
-RTEMS_BSP_CONFIGURE
-
-RTEMS_PROG_CC_FOR_TARGET
-RTEMS_CANONICALIZE_TOOLS
-RTEMS_PROG_CCAS
-
-RTEMS_BSP_CLEANUP_OPTIONS(0, 0)
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/c/src/lib/libbsp/avr/configure.ac b/c/src/lib/libbsp/avr/configure.ac
deleted file mode 100644
index 32ecf2e..0000000
--- a/c/src/lib/libbsp/avr/configure.ac
+++ /dev/null
@@ -1,19 +0,0 @@
-## Process this file with autoconf to produce a configure script.
-
-AC_PREREQ([2.69])
-AC_INIT([rtems-c-src-lib-libbsp-avr],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
-RTEMS_TOP(../../../../..)
-
-RTEMS_CANONICAL_TARGET_CPU
-AM_INIT_AUTOMAKE([no-define foreign 1.12.2])
-AM_MAINTAINER_MODE
-
-RTEMS_ENV_RTEMSBSP
-
-RTEMS_PROJECT_ROOT
-
-RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])
-
-# Explicitly list all Makefiles here
-AC_CONFIG_FILES([Makefile])
-AC_OUTPUT
diff --git a/cpukit/aclocal/check-networking.m4 b/cpukit/aclocal/check-networking.m4
index 50982f3..e15cf05 100644
--- a/cpukit/aclocal/check-networking.m4
+++ b/cpukit/aclocal/check-networking.m4
@@ -9,7 +9,7 @@ AC_CACHE_CHECK([whether CPU supports networking],
   [dnl
     case "$host" in
     # do not have address space to hold BSD TCP/IP stack
-    avr*|m32c*)
+    m32c*)
       rtems_cv_HAS_NETWORKING="no"
       ;;
     *-*-rtems*)
diff --git a/cpukit/configure.ac b/cpukit/configure.ac
index c5bbee8..3ec966f 100644
--- a/cpukit/configure.ac
+++ b/cpukit/configure.ac
@@ -452,7 +452,6 @@ score/Makefile
 score/cpu/Makefile
 score/cpu/arm/Makefile
 score/cpu/bfin/Makefile
-score/cpu/avr/Makefile
 score/cpu/epiphany/Makefile
 score/cpu/i386/Makefile
 score/cpu/lm32/Makefile
diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c
index 74d0bbc..4c58720 100644
--- a/cpukit/librpc/src/xdr/xdr_float.c
+++ b/cpukit/librpc/src/xdr/xdr_float.c
@@ -73,7 +73,6 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
     defined(__sparc__) || \
     defined(__ppc__) || defined(__PPC__) || \
     defined(__sh__) || \
-    defined(__AVR__) || \
     defined(__BFIN__) || \
     defined(__m32c__) || \
     defined(__v850)
diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
index a973a82..1f57984 100644
--- a/cpukit/score/cpu/Makefile.am
+++ b/cpukit/score/cpu/Makefile.am
@@ -2,7 +2,6 @@ SUBDIRS = @RTEMS_CPU@
 
 DIST_SUBDIRS =
 DIST_SUBDIRS += arm
-DIST_SUBDIRS += avr
 DIST_SUBDIRS += bfin
 DIST_SUBDIRS += epiphany
 DIST_SUBDIRS += i386
diff --git a/cpukit/score/cpu/avr/Makefile.am b/cpukit/score/cpu/avr/Makefile.am
deleted file mode 100644
index 10ab19b..0000000
--- a/cpukit/score/cpu/avr/Makefile.am
+++ /dev/null
@@ -1,170 +0,0 @@
-include $(top_srcdir)/automake/compile.am
-
-include_rtemsdir = $(includedir)/rtems
-include_rtems_HEADERS = rtems/asm.h
-
-include_rtems_scoredir = $(includedir)/rtems/score
-include_rtems_score_HEADERS = rtems/score/cpu.h
-include_rtems_score_HEADERS += rtems/score/avr.h
-include_rtems_score_HEADERS += rtems/score/cpu_asm.h
-include_rtems_score_HEADERS += rtems/score/types.h
-include_rtems_score_HEADERS += rtems/score/cpuatomic.h
-
-include_rtems_avrdir = $(includedir)/avr
-include_rtems_avr_HEADERS = avr/boot.h
-include_rtems_avr_HEADERS += avr/common.h
-include_rtems_avr_HEADERS += avr/crc16.h
-include_rtems_avr_HEADERS += avr/delay.h
-include_rtems_avr_HEADERS += avr/eeprom.h
-include_rtems_avr_HEADERS += avr/fuse.h
-include_rtems_avr_HEADERS += avr/interrupt.h
-include_rtems_avr_HEADERS += avr/io1200.h
-include_rtems_avr_HEADERS += avr/io2313.h
-include_rtems_avr_HEADERS += avr/io2323.h
-include_rtems_avr_HEADERS += avr/io2333.h
-include_rtems_avr_HEADERS += avr/io2343.h
-include_rtems_avr_HEADERS += avr/io43u32x.h
-include_rtems_avr_HEADERS += avr/io43u35x.h
-include_rtems_avr_HEADERS += avr/io4414.h
-include_rtems_avr_HEADERS += avr/io4433.h
-include_rtems_avr_HEADERS += avr/io4434.h
-include_rtems_avr_HEADERS += avr/io76c711.h
-include_rtems_avr_HEADERS += avr/io8515.h
-include_rtems_avr_HEADERS += avr/io8534.h
-include_rtems_avr_HEADERS += avr/io8535.h
-include_rtems_avr_HEADERS += avr/io86r401.h
-include_rtems_avr_HEADERS += avr/io90pwm1.h
-include_rtems_avr_HEADERS += avr/io90pwm216.h
-include_rtems_avr_HEADERS += avr/io90pwm2b.h
-include_rtems_avr_HEADERS += avr/io90pwm316.h
-include_rtems_avr_HEADERS += avr/io90pwm3b.h
-include_rtems_avr_HEADERS += avr/io90pwm81.h
-include_rtems_avr_HEADERS += avr/io90pwmx.h
-include_rtems_avr_HEADERS += avr/io90scr100.h
-include_rtems_avr_HEADERS += avr/ioa6289.h
-include_rtems_avr_HEADERS += avr/ioat94k.h
-include_rtems_avr_HEADERS += avr/iocan128.h
-include_rtems_avr_HEADERS += avr/iocan32.h
-include_rtems_avr_HEADERS += avr/iocan64.h
-include_rtems_avr_HEADERS += avr/iocanxx.h
-include_rtems_avr_HEADERS += avr/io.h
-include_rtems_avr_HEADERS += avr/iom103.h
-include_rtems_avr_HEADERS += avr/iom1280.h
-include_rtems_avr_HEADERS += avr/iom1281.h
-include_rtems_avr_HEADERS += avr/iom1284p.h
-include_rtems_avr_HEADERS += avr/iom128.h
-include_rtems_avr_HEADERS += avr/iom128rfa1.h
-include_rtems_avr_HEADERS += avr/iom161.h
-include_rtems_avr_HEADERS += avr/iom162.h
-include_rtems_avr_HEADERS += avr/iom163.h
-include_rtems_avr_HEADERS += avr/iom164.h
-include_rtems_avr_HEADERS += avr/iom165.h
-include_rtems_avr_HEADERS += avr/iom165p.h
-include_rtems_avr_HEADERS += avr/iom168.h
-include_rtems_avr_HEADERS += avr/iom168p.h
-include_rtems_avr_HEADERS += avr/iom169.h
-include_rtems_avr_HEADERS += avr/iom169p.h
-include_rtems_avr_HEADERS += avr/iom16.h
-include_rtems_avr_HEADERS += avr/iom16hva.h
-include_rtems_avr_HEADERS += avr/iom16m1.h
-include_rtems_avr_HEADERS += avr/iom16u4.h
-include_rtems_avr_HEADERS += avr/iom2560.h
-include_rtems_avr_HEADERS += avr/iom2561.h
-include_rtems_avr_HEADERS += avr/iom323.h
-include_rtems_avr_HEADERS += avr/iom324.h
-include_rtems_avr_HEADERS += avr/iom3250.h
-include_rtems_avr_HEADERS += avr/iom325.h
-include_rtems_avr_HEADERS += avr/iom328p.h
-include_rtems_avr_HEADERS += avr/iom3290.h
-include_rtems_avr_HEADERS += avr/iom329.h
-include_rtems_avr_HEADERS += avr/iom32c1.h
-include_rtems_avr_HEADERS += avr/iom32.h
-include_rtems_avr_HEADERS += avr/iom32hvb.h
-include_rtems_avr_HEADERS += avr/iom32m1.h
-include_rtems_avr_HEADERS += avr/iom32u4.h
-include_rtems_avr_HEADERS += avr/iom32u6.h
-include_rtems_avr_HEADERS += avr/iom406.h
-include_rtems_avr_HEADERS += avr/iom48.h
-include_rtems_avr_HEADERS += avr/iom48p.h
-include_rtems_avr_HEADERS += avr/iom640.h
-include_rtems_avr_HEADERS += avr/iom644.h
-include_rtems_avr_HEADERS += avr/iom6450.h
-include_rtems_avr_HEADERS += avr/iom645.h
-include_rtems_avr_HEADERS += avr/iom6490.h
-include_rtems_avr_HEADERS += avr/iom649.h
-include_rtems_avr_HEADERS += avr/iom64c1.h
-include_rtems_avr_HEADERS += avr/iom64.h
-include_rtems_avr_HEADERS += avr/iom64m1.h
-include_rtems_avr_HEADERS += avr/iom8515.h
-include_rtems_avr_HEADERS += avr/iom8535.h
-include_rtems_avr_HEADERS += avr/iom88.h
-include_rtems_avr_HEADERS += avr/iom88p.h
-include_rtems_avr_HEADERS += avr/iom8.h
-include_rtems_avr_HEADERS += avr/iom8hva.h
-include_rtems_avr_HEADERS += avr/iomx8.h
-include_rtems_avr_HEADERS += avr/iomxx0_1.h
-include_rtems_avr_HEADERS += avr/iomxx4.h
-include_rtems_avr_HEADERS += avr/iomxxhva.h
-include_rtems_avr_HEADERS += avr/iotn11.h
-include_rtems_avr_HEADERS += avr/iotn12.h
-include_rtems_avr_HEADERS += avr/iotn13a.h
-include_rtems_avr_HEADERS += avr/iotn13.h
-include_rtems_avr_HEADERS += avr/iotn15.h
-include_rtems_avr_HEADERS += avr/iotn167.h
-include_rtems_avr_HEADERS += avr/iotn22.h
-include_rtems_avr_HEADERS += avr/iotn2313.h
-include_rtems_avr_HEADERS += avr/iotn24.h
-include_rtems_avr_HEADERS += avr/iotn25.h
-include_rtems_avr_HEADERS += avr/iotn261.h
-include_rtems_avr_HEADERS += avr/iotn26.h
-include_rtems_avr_HEADERS += avr/iotn28.h
-include_rtems_avr_HEADERS += avr/iotn43u.h
-include_rtems_avr_HEADERS += avr/iotn44.h
-include_rtems_avr_HEADERS += avr/iotn45.h
-include_rtems_avr_HEADERS += avr/iotn461.h
-include_rtems_avr_HEADERS += avr/iotn48.h
-include_rtems_avr_HEADERS += avr/iotn84.h
-include_rtems_avr_HEADERS += avr/iotn85.h
-include_rtems_avr_HEADERS += avr/iotn861.h
-include_rtems_avr_HEADERS += avr/iotn87.h
-include_rtems_avr_HEADERS += avr/iotn88.h
-include_rtems_avr_HEADERS += avr/iotnx4.h
-include_rtems_avr_HEADERS += avr/iotnx5.h
-include_rtems_avr_HEADERS += avr/iotnx61.h
-include_rtems_avr_HEADERS += avr/iousb1286.h
-include_rtems_avr_HEADERS += avr/iousb1287.h
-include_rtems_avr_HEADERS += avr/iousb162.h
-include_rtems_avr_HEADERS += avr/iousb646.h
-include_rtems_avr_HEADERS += avr/iousb647.h
-include_rtems_avr_HEADERS += avr/iousb82.h
-include_rtems_avr_HEADERS += avr/iousbxx2.h
-include_rtems_avr_HEADERS += avr/iousbxx6_7.h
-include_rtems_avr_HEADERS += avr/iox128a1.h
-include_rtems_avr_HEADERS += avr/iox128a3.h
-include_rtems_avr_HEADERS += avr/iox16a4.h
-include_rtems_avr_HEADERS += avr/iox16d4.h
-include_rtems_avr_HEADERS += avr/iox256a3b.h
-include_rtems_avr_HEADERS += avr/iox256a3.h
-include_rtems_avr_HEADERS += avr/iox32a4.h
-include_rtems_avr_HEADERS += avr/iox32d4.h
-include_rtems_avr_HEADERS += avr/iox64a1.h
-include_rtems_avr_HEADERS += avr/iox64a3.h
-include_rtems_avr_HEADERS += avr/lock.h
-include_rtems_avr_HEADERS += avr/parity.h
-include_rtems_avr_HEADERS += avr/pgmspace.h
-include_rtems_avr_HEADERS += avr/portpins.h
-include_rtems_avr_HEADERS += avr/power.h
-include_rtems_avr_HEADERS += avr/sfr_defs.h
-include_rtems_avr_HEADERS += avr/signal.h
-include_rtems_avr_HEADERS += avr/sleep.h
-include_rtems_avr_HEADERS += avr/version.h
-include_rtems_avr_HEADERS += avr/wdt.h
-
-noinst_LIBRARIES = libscorecpu.a
-libscorecpu_a_SOURCES = cpu.c cpu_asm.S
-libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
-libscorecpu_a_SOURCES += avr-exception-frame-print.c
-libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
-
-include $(srcdir)/preinstall.am
-include $(top_srcdir)/automake/local.am
diff --git a/cpukit/score/cpu/avr/README b/cpukit/score/cpu/avr/README
deleted file mode 100644
index 20ac7cc..0000000
--- a/cpukit/score/cpu/avr/README
+++ /dev/null
@@ -1,5 +0,0 @@
-WARNING
-=======
-
-This is just a stub and not a complete and functional port.
-
diff --git a/cpukit/score/cpu/avr/avr-exception-frame-print.c b/cpukit/score/cpu/avr/avr-exception-frame-print.c
deleted file mode 100644
index 71e7e1c..0000000
--- a/cpukit/score/cpu/avr/avr-exception-frame-print.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems at embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifdef HAVE_CONFIG_H
-  #include "config.h"
-#endif
-
-#include <rtems/score/cpu.h>
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
-{
-  /* TODO */
-}
diff --git a/cpukit/score/cpu/avr/avr/boot.h b/cpukit/score/cpu/avr/avr/boot.h
deleted file mode 100644
index 863143b..0000000
--- a/cpukit/score/cpu/avr/avr/boot.h
+++ /dev/null
@@ -1,687 +0,0 @@
-/**
- * @file
- *
- * @brief Bootloader Support Utilities
- *
- *  The macros in this module provide a C language interface to the
- *  bootloader support functionality of certain AVR processors. These
- *  macros are designed to work with all sizes of flash memory.
- *
- *  Global interrupts are not automatically disabled for these macros. It
- *  is left up to the programmer to do this. See the code example below.
- *  Also see the processor datasheet for caveats on having global interrupts
- *  enabled during writing of the Flash.
- *
- *  \note Not all AVR processors provide bootloader support. See your
- *  processor datasheet to see if it provides bootloader support.
- *
- *  From email with Marek: On smaller devices (all except ATmega64/128),
- *  __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
- *  instructions - since the boot loader has a limited size, this could be an
- *  important optimization.
- *
- *  API Usage Example
- *  The following code shows typical usage of the boot API.
- *
- *
- *  #include <inttypes.h>
- *  #include <avr/interrupt.h>
- *  #include <avr/pgmspace.h>
- *
- *  void boot_program_page (uint32_t page, uint8_t *buf)
- *  {
- *      uint16_t i;
- *      uint8_t sreg;
- *
- *      // Disable interrupts.
- *
- *      sreg = SREG;
- *      cli();
- *
- *      eeprom_busy_wait ();
- *
- *      boot_page_erase (page);
- *      boot_spm_busy_wait ();      // Wait until the memory is erased.
- *
- *      for (i=0; i<SPM_PAGESIZE; i+=2)
- *      {
- *          // Set up little-endian word.
- *
- *          uint16_t w = *buf++;
- *          w += (*buf++) << 8;
- *
- *          boot_page_fill (page + i, w);
- *      }
- *
- *      boot_page_write (page);     // Store buffer in flash page.
- *      boot_spm_busy_wait();       // Wait until the memory is written.
- *
- *      // Reenable RWW-section again. We need this if we want to jump back
- *      // to the application after bootloading.
- *
- *      boot_rww_enable ();
- *
- *      // Re-enable interrupts (if they were ever enabled).
- *
- *      SREG = sreg;
- *  }
- */
-
-/*
- *   Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009  Eric B. Weddington
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_BOOT_H_
-#define _AVR_BOOT_H_    1
-
-/**
- *  @defgroup avr_boot Bootloader Support Utilities
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/eeprom.h>
-#include <avr/io.h>
-#include <inttypes.h>
-#include <limits.h>
-
-/* Check for SPM Control Register in processor. */
-#if defined (SPMCSR)
-#  define __SPM_REG    SPMCSR
-#elif defined (SPMCR)
-#  define __SPM_REG    SPMCR
-#else
-#  error AVR processor does not provide bootloader support!
-#endif
-
-
-/* Check for SPM Enable bit. */
-#if defined(SPMEN)
-#  define __SPM_ENABLE  SPMEN
-#elif defined(SELFPRGEN)
-#  define __SPM_ENABLE  SELFPRGEN
-#else
-#  error Cannot find SPM Enable bit definition!
-#endif
-
-/** \ingroup avr_boot
-    \def BOOTLOADER_SECTION
-
-    Used to declare a function or variable to be placed into a
-    new section called .bootloader. This section and its contents
-    can then be relocated to any address (such as the bootloader
-    NRWW area) at link-time. */
-
-#define BOOTLOADER_SECTION    __attribute__ ((section (".bootloader")))
-
-/* Create common bit definitions. */
-#ifdef ASB
-#define __COMMON_ASB    ASB
-#else
-#define __COMMON_ASB    RWWSB
-#endif
-
-#ifdef ASRE
-#define __COMMON_ASRE   ASRE
-#else
-#define __COMMON_ASRE   RWWSRE
-#endif
-
-/* Define the bit positions of the Boot Lock Bits. */
-
-#define BLB12           5
-#define BLB11           4
-#define BLB02           3
-#define BLB01           2
-
-/** \ingroup avr_boot
-    \def boot_spm_interrupt_enable()
-    Enable the SPM interrupt. */
-
-#define boot_spm_interrupt_enable()   (__SPM_REG |= (uint8_t)_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_spm_interrupt_disable()
-    Disable the SPM interrupt. */
-
-#define boot_spm_interrupt_disable()  (__SPM_REG &= (uint8_t)~_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_is_spm_interrupt()
-    Check if the SPM interrupt is enabled. */
-
-#define boot_is_spm_interrupt()       (__SPM_REG & (uint8_t)_BV(SPMIE))
-
-/** \ingroup avr_boot
-    \def boot_rww_busy()
-    Check if the RWW section is busy. */
-
-#define boot_rww_busy()          (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
-
-/** \ingroup avr_boot
-    \def boot_spm_busy()
-    Check if the SPM instruction is busy. */
-
-#define boot_spm_busy()               (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
-
-/** \ingroup avr_boot
-    \def boot_spm_busy_wait()
-    Wait while the SPM instruction is busy. */
-
-#define boot_spm_busy_wait()          do{}while(boot_spm_busy())
-
-#define __BOOT_PAGE_ERASE         (_BV(__SPM_ENABLE) | _BV(PGERS))
-#define __BOOT_PAGE_WRITE         (_BV(__SPM_ENABLE) | _BV(PGWRT))
-#define __BOOT_PAGE_FILL          _BV(__SPM_ENABLE)
-#define __BOOT_RWW_ENABLE         (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
-#if defined(BLBSET)
-#define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(BLBSET))
-#elif defined(RFLB)  /* Some devices have RFLB defined instead of BLBSET. */
-#define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(RFLB))
-#endif
-
-#define __boot_page_fill_normal(address, data)   \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %3\n\t"                       \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "z" ((uint16_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0"                                   \
-    );                                           \
-}))
-
-#define __boot_page_fill_alternate(address, data)\
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %3\n\t"                       \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "z" ((uint16_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0"                                   \
-    );                                           \
-}))
-
-#define __boot_page_fill_extended(address, data) \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw  r0, %4\n\t"                       \
-        "movw r30, %A3\n\t"                      \
-        "sts %1, %C3\n\t"                        \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        "clr  r1\n\t"                            \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
-          "r" ((uint32_t)(address)),             \
-          "r" ((uint16_t)(data))                 \
-        : "r0", "r30", "r31"                     \
-    );                                           \
-}))
-
-#define __boot_page_erase_normal(address)        \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_erase_alternate(address)     \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_erase_extended(address)      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw r30, %A3\n\t"                      \
-        "sts  %1, %C3\n\t"                       \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
-          "r" ((uint32_t)(address))              \
-        : "r30", "r31"                           \
-    );                                           \
-}))
-
-#define __boot_page_write_normal(address)        \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_write_alternate(address)     \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "z" ((uint16_t)(address))              \
-    );                                           \
-}))
-
-#define __boot_page_write_extended(address)      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "movw r30, %A3\n\t"                      \
-        "sts %1, %C3\n\t"                        \
-        "sts %0, %2\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "i" (_SFR_MEM_ADDR(RAMPZ)),            \
-          "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
-          "r" ((uint32_t)(address))              \
-        : "r30", "r31"                           \
-    );                                           \
-}))
-
-#define __boot_rww_enable()                      \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
-    );                                           \
-}))
-
-#define __boot_rww_enable_alternate()            \
-(__extension__({                                 \
-    __asm__ __volatile__                         \
-    (                                            \
-        "sts %0, %1\n\t"                         \
-        "spm\n\t"                                \
-        ".word 0xffff\n\t"                       \
-        "nop\n\t"                                \
-        :                                        \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
-          "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
-    );                                           \
-}))
-
-/* From the mega16/mega128 data sheets (maybe others):
-
-     Bits by SPM To set the Boot Loader Lock bits, write the desired data to
-     R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
-     after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
-     that may prevent the Application and Boot Loader section from any
-     software update by the MCU.
-
-     If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
-     will be programmed if an SPM instruction is executed within four cycles
-     after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
-     don't care during this operation, but for future compatibility it is
-     recommended to load the Z-pointer with $0001 (same as used for reading the
-     Lock bits). For future compatibility It is also recommended to set bits 7,
-     6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
-     Lock bits the entire Flash can be read during the operation. */
-
-#define __boot_lock_bits_set(lock_bits)                    \
-(__extension__({                                           \
-    uint8_t value = (uint8_t)(~(lock_bits));               \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "ldi r30, 1\n\t"                                   \
-        "ldi r31, 0\n\t"                                   \
-        "mov r0, %2\n\t"                                   \
-        "sts %0, %1\n\t"                                   \
-        "spm\n\t"                                          \
-        :                                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "r" (value)                                      \
-        : "r0", "r30", "r31"                               \
-    );                                                     \
-}))
-
-#define __boot_lock_bits_set_alternate(lock_bits)          \
-(__extension__({                                           \
-    uint8_t value = (uint8_t)(~(lock_bits));               \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "ldi r30, 1\n\t"                                   \
-        "ldi r31, 0\n\t"                                   \
-        "mov r0, %2\n\t"                                   \
-        "sts %0, %1\n\t"                                   \
-        "spm\n\t"                                          \
-        ".word 0xffff\n\t"                                 \
-        "nop\n\t"                                          \
-        :                                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "r" (value)                                      \
-        : "r0", "r30", "r31"                               \
-    );                                                     \
-}))
-
-/*
-   Reading lock and fuse bits:
-
-     Similarly to writing the lock bits above, set BLBSET and SPMEN (or
-     SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
-     LPM instruction.
-
-     Z address:       contents:
-     0x0000           low fuse bits
-     0x0001           lock bits
-     0x0002           extended fuse bits
-     0x0003           high fuse bits
-
-     Sounds confusing, doesn't it?
-
-     Unlike the macros in pgmspace.h, no need to care for non-enhanced
-     cores here as these old cores do not provide SPM support anyway.
- */
-
-/** \ingroup avr_boot
-    \def GET_LOW_FUSE_BITS
-    address to read the low fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_LOW_FUSE_BITS           (0x0000)
-/** \ingroup avr_boot
-    \def GET_LOCK_BITS
-    address to read the lock bits, using boot_lock_fuse_bits_get
- */
-#define GET_LOCK_BITS               (0x0001)
-/** \ingroup avr_boot
-    \def GET_EXTENDED_FUSE_BITS
-    address to read the extended fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_EXTENDED_FUSE_BITS      (0x0002)
-/** \ingroup avr_boot
-    \def GET_HIGH_FUSE_BITS
-    address to read the high fuse bits, using boot_lock_fuse_bits_get
- */
-#define GET_HIGH_FUSE_BITS          (0x0003)
-
-/** \ingroup avr_boot
-    \def boot_lock_fuse_bits_get(address)
-
-    Read the lock or fuse bits at \c address.
-
-    Parameter \c address can be any of GET_LOW_FUSE_BITS,
-    GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
-
-    \note The lock and fuse bits returned are the physical values,
-    i.e. a bit returned as 0 means the corresponding fuse or lock bit
-    is programmed.
- */
-#define boot_lock_fuse_bits_get(address)                   \
-(__extension__({                                           \
-    uint8_t __result;                                      \
-    __asm__ __volatile__                                   \
-    (                                                      \
-        "sts %1, %2\n\t"                                   \
-        "lpm %0, Z\n\t"                                    \
-        : "=r" (__result)                                  \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
-          "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
-          "z" ((uint16_t)(address))                        \
-    );                                                     \
-    __result;                                              \
-}))
-
-/** \ingroup avr_boot
-    \def boot_signature_byte_get(address)
-
-    Read the Signature Row byte at \c address.  For some MCU types,
-    this function can also retrieve the factory-stored oscillator
-    calibration bytes.
-
-    Parameter \c address can be 0-0x1f as documented by the datasheet.
-    \note The values are MCU type dependent.
-*/
-
-#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
-
-#define boot_signature_byte_get(addr) \
-(__extension__({                      \
-      uint8_t __result;                         \
-      __asm__ __volatile__                      \
-      (                                         \
-        "sts %1, %2\n\t"                        \
-        "lpm %0, Z" "\n\t"                      \
-        : "=r" (__result)                       \
-        : "i" (_SFR_MEM_ADDR(__SPM_REG)),       \
-          "r" ((uint8_t)(__BOOT_SIGROW_READ)),  \
-          "z" ((uint16_t)(addr))                \
-      );                                        \
-      __result;                                 \
-}))
-
-/** \ingroup avr_boot
-    \def boot_page_fill(address, data)
-
-    Fill the bootloader temporary page buffer for flash
-    address with data word.
-
-    \note The address is a byte address. The data is a word. The AVR
-    writes data to the buffer a word at a time, but addresses the buffer
-    per byte! So, increment your address by 2 between calls, and send 2
-    data bytes in a word format! The LSB of the data is written to the lower
-    address; the MSB of the data is written to the higher address.*/
-
-/** \ingroup avr_boot
-    \def boot_page_erase(address)
-
-    Erase the flash page that contains address.
-
-    \note address is a byte address in flash, not a word address. */
-
-/** \ingroup avr_boot
-    \def boot_page_write(address)
-
-    Write the bootloader temporary page buffer
-    to flash page that contains address.
-
-    \note address is a byte address in flash, not a word address. */
-
-/** \ingroup avr_boot
-    \def boot_rww_enable()
-
-    Enable the Read-While-Write memory section. */
-
-/** \ingroup avr_boot
-    \def boot_lock_bits_set(lock_bits)
-
-    Set the bootloader lock bits.
-
-    \param lock_bits A mask of which Boot Loader Lock Bits to set.
-
-    \note In this context, a 'set bit' will be written to a zero value.
-    Note also that only BLBxx bits can be programmed by this command.
-
-    For example, to disallow the SPM instruction from writing to the Boot
-    Loader memory section of flash, you would use this macro as such:
-
-    \code
-    boot_lock_bits_set (_BV (BLB11));
-    \endcode
-
-    \note Like any lock bits, the Boot Loader Lock Bits, once set,
-    cannot be cleared again except by a chip erase which will in turn
-    also erase the boot loader itself. */
-
-/* Normal versions of the macros use 16-bit addresses.
-   Extended versions of the macros use 32-bit addresses.
-   Alternate versions of the macros use 16-bit addresses and require special
-   instruction sequences after LPM.
-
-   FLASHEND is defined in the ioXXXX.h file.
-   USHRT_MAX is defined in <limits.h>. */
-
-#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
-    || defined(__AVR_ATmega323__)
-
-/* Alternate: ATmega161/163/323 and 16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
-#define boot_page_erase(address)      __boot_page_erase_alternate(address)
-#define boot_page_write(address)      __boot_page_write_alternate(address)
-#define boot_rww_enable()             __boot_rww_enable_alternate()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
-
-#elif (FLASHEND > USHRT_MAX)
-
-/* Extended: >16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
-#define boot_page_erase(address)      __boot_page_erase_extended(address)
-#define boot_page_write(address)      __boot_page_write_extended(address)
-#define boot_rww_enable()             __boot_rww_enable()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
-
-#else
-
-/* Normal: 16 bit address */
-#define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
-#define boot_page_erase(address)      __boot_page_erase_normal(address)
-#define boot_page_write(address)      __boot_page_write_normal(address)
-#define boot_rww_enable()             __boot_rww_enable()
-#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
-
-#endif
-
-/** \ingroup avr_boot
-
-    Same as boot_page_fill() except it waits for eeprom and spm operations to
-    complete before filling the page. */
-
-#define boot_page_fill_safe(address, data) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_fill(address, data);              \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_page_erase() except it waits for eeprom and spm operations to
-    complete before erasing the page. */
-
-#define boot_page_erase_safe(address) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_erase (address);                  \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_page_write() except it waits for eeprom and spm operations to
-    complete before writing the page. */
-
-#define boot_page_write_safe(address) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_page_write (address);                  \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_rww_enable() except waits for eeprom and spm operations to
-    complete before enabling the RWW mameory. */
-
-#define boot_rww_enable_safe() \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_rww_enable();                          \
-} while (0)
-
-/** \ingroup avr_boot
-
-    Same as boot_lock_bits_set() except waits for eeprom and spm operations to
-    complete before setting the lock bits. */
-
-#define boot_lock_bits_set_safe(lock_bits) \
-do { \
-    boot_spm_busy_wait();                       \
-    eeprom_busy_wait();                         \
-    boot_lock_bits_set (lock_bits);             \
-} while (0)
-
-/**@}*/
-#endif /* _AVR_BOOT_H_ */
diff --git a/cpukit/score/cpu/avr/avr/common.h b/cpukit/score/cpu/avr/avr/common.h
deleted file mode 100644
index 1acfe26..0000000
--- a/cpukit/score/cpu/avr/avr/common.h
+++ /dev/null
@@ -1,335 +0,0 @@
-/**
- * @file
- *
- * @brief Common Symbols and Define Undefined Registers
- *
- * This purpose of this header is to define registers that have not been
- * previously defined in the individual device IO header files, and to define
- * other symbols that are common across AVR device families.
- *
- * This file is designed to be included in <avr/io.h> after the individual
- * device IO header files, and after <avr/sfr_defs.h>
- */
-
-/*
- *  Copyright (c) 2007 Eric B. Weddington
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-#ifndef _AVR_COMMON_H
-#define _AVR_COMMON_H
-
-/**
- *  @defgroup Avr_common Common Data
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/sfr_defs.h>
-
-/*------------ Registers Not Previously Defined ------------*/
-
-/*
-These are registers that are not previously defined in the individual
-IO header files, OR they are defined here because they are used in parts of
-avr-libc even if a device is not selected but a general architecture has
-been selected.
-*/
-
-
-/*
-Stack pointer register.
-
-AVR architecture 1 has no RAM, thus no stack pointer.
-
-All other architectures do have a stack pointer.  Some devices have only
-less than 256 bytes of possible RAM locations (128 Bytes of SRAM
-and no option for external RAM), thus SPH is officially "reserved"
-for them.
-*/
-#if __AVR_ARCH__ >= 100
-#  ifndef SPL
-#    define SPL _SFR_MEM8(0x3D)
-#  endif
-#  ifndef SPH
-#    define SPH _SFR_MEM8(0x3E)
-#  endif
-#  ifndef SP
-#    define SP _SFR_MEM16(0x3D)
-#  endif
-#elif __AVR_ARCH__ != 1
-#  ifndef SPL
-#    define SPL _SFR_IO8(0x3D)
-#  endif
-#  if XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__)
-#    ifndef SP
-#      define SP  _SFR_IO8(0x3D)
-#    endif
-#  else
-#    ifndef SP
-#      define SP  _SFR_IO16(0x3D)
-#    endif
-#    ifndef SPH
-#      define SPH _SFR_IO8(0x3E)
-#    endif
-#  endif /* XRAMEND < 0x100 && !defined(__COMPILING_AVR_LIBC__) */
-#endif /* __AVR_ARCH__ != 1 */
-
-
-/* Status Register */
-#ifndef SREG
-#  if __AVR_ARCH__ >= 100
-#    define SREG _SFR_MEM8(0x3F)
-#  else
-#    define SREG _SFR_IO8(0x3F)
-#  endif
-#endif
-
-
-/* SREG bit definitions */
-#ifndef SREG_C
-#  define SREG_C  (0)
-#endif
-#ifndef SREG_Z
-#  define SREG_Z  (1)
-#endif
-#ifndef SREG_N
-#  define SREG_N  (2)
-#endif
-#ifndef SREG_V
-#  define SREG_V  (3)
-#endif
-#ifndef SREG_S
-#  define SREG_S  (4)
-#endif
-#ifndef SREG_H
-#  define SREG_H  (5)
-#endif
-#ifndef SREG_T
-#  define SREG_T  (6)
-#endif
-#ifndef SREG_I
-#  define SREG_I  (7)
-#endif
-
-
-#if defined(__COMPILING_AVR_LIBC__)
-
-/* AVR 6 Architecture */
-#  if __AVR_ARCH__ == 6
-#    ifndef EIND
-#      define EIND  _SFR_IO8(0X3C)
-#    endif
-/* XMEGA Architectures */
-#  elif __AVR_ARCH__ >= 100
-#    ifndef EIND
-#      define EIND  _SFR_MEM8(0x3C)
-#    endif
-#  endif
-
-/*
-Only few devices come without EEPROM.  In order to assemble the
-EEPROM library components without defining a specific device, we
-keep the EEPROM-related definitions here.
-*/
-
-/* EEPROM Control Register */
-#  ifndef EECR
-#    define EECR   _SFR_IO8(0x1C)
-#  endif
-
-/* EEPROM Data Register */
-#  ifndef EEDR
-#    define EEDR   _SFR_IO8(0x1D)
-#  endif
-
-/* EEPROM Address Register */
-#  ifndef EEAR
-#    define EEAR   _SFR_IO16(0x1E)
-#  endif
-#  ifndef EEARL
-#    define EEARL  _SFR_IO8(0x1E)
-#  endif
-#  ifndef EEARH
-#    define EEARH  _SFR_IO8(0x1F)
-#  endif
-
-/* EEPROM Control Register bits */
-#  ifndef EERE
-#    define EERE   (0)
-#  endif
-#  ifndef EEWE
-#    define EEWE   (1)
-#  endif
-#  ifndef EEMWE
-#    define EEMWE  (2)
-#  endif
-#  ifndef EERIE
-#    define EERIE  (3)
-#  endif
-
-#endif /* __COMPILING_AVR_LIBC__ */
-
-
-
-/*------------ Common Symbols ------------*/
-
-/*
-Generic definitions for registers that are common across multiple AVR devices
-and families.
-*/
-
-/* Pointer registers definitions */
-#if __AVR_ARCH__ != 1  /* avr1 does not have X and Y pointers */
-#  define XL  r26
-#  define XH  r27
-#  define YL  r28
-#  define YH  r29
-#endif /* #if __AVR_ARCH__ != 1 */
-#define ZL  r30
-#define ZH  r31
-
-
-/* Status Register */
-#if defined(SREG)
-#  define AVR_STATUS_REG   SREG
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STATUS_ADDR  _SFR_MEM_ADDR(SREG)
-#  else
-#    define AVR_STATUS_ADDR  _SFR_IO_ADDR(SREG)
-#  endif
-#endif
-
-/* Stack Pointer (combined) Register */
-#if defined(SP)
-#  define AVR_STACK_POINTER_REG   SP
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_ADDR  _SFR_MEM_ADDR(SP)
-#  else
-#    define AVR_STACK_POINTER_ADDR  _SFR_IO_ADDR(SP)
-#  endif
-#endif
-
-/* Stack Pointer High Register */
-#if defined(SPH)
-#  define _HAVE_AVR_STACK_POINTER_HI 1
-#  define AVR_STACK_POINTER_HI_REG   SPH
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_HI_ADDR  _SFR_MEM_ADDR(SPH)
-#  else
-#    define AVR_STACK_POINTER_HI_ADDR  _SFR_IO_ADDR(SPH)
-#  endif
-#endif
-
-/* Stack Pointer Low Register */
-#if defined(SPL)
-#  define AVR_STACK_POINTER_LO_REG   SPL
-#  if __AVR_ARCH__ >= 100
-#    define AVR_STACK_POINTER_LO_ADDR  _SFR_MEM_ADDR(SPL)
-#  else
-#    define AVR_STACK_POINTER_LO_ADDR  _SFR_IO_ADDR(SPL)
-#  endif
-#endif
-
-/* RAMPD Register */
-#if defined(RAMPD)
-#  define AVR_RAMPD_REG   RAMPD
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPD_ADDR  _SFR_MEM_ADDR(RAMPD)
-#  else
-#    define AVR_RAMPD_ADDR  _SFR_IO_ADDR(RAMPD)
-#  endif
-#endif
-
-/* RAMPX Register */
-#if defined(RAMPX)
-#  define AVR_RAMPX_REG   RAMPX
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPX_ADDR  _SFR_MEM_ADDR(RAMPX)
-#  else
-#    define AVR_RAMPX_ADDR  _SFR_IO_ADDR(RAMPX)
-#  endif
-#endif
-
-/* RAMPY Register */
-#if defined(RAMPY)
-#  define AVR_RAMPY_REG   RAMPY
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPY_ADDR  _SFR_MEM_ADDR(RAMPY)
-#  else
-#    define AVR_RAMPY_ADDR  _SFR_IO_ADDR(RAMPY)
-#  endif
-#endif
-
-/* RAMPZ Register */
-#if defined(RAMPZ)
-#  define AVR_RAMPZ_REG   RAMPZ
-#  if __AVR_ARCH__ >= 100
-#    define AVR_RAMPZ_ADDR  _SFR_MEM_ADDR(RAMPZ)
-#  else
-#    define AVR_RAMPZ_ADDR  _SFR_IO_ADDR(RAMPZ)
-#  endif
-#endif
-
-/* Extended Indirect Register */
-#if defined(EIND)
-#  define AVR_EXTENDED_INDIRECT_REG   EIND
-#  if __AVR_ARCH__ >= 100
-#    define AVR_EXTENDED_INDIRECT_ADDR  _SFR_MEM_ADDR(EIND)
-#  else
-#    define AVR_EXTENDED_INDIRECT_ADDR  _SFR_IO_ADDR(EIND)
-#  endif
-#endif
-
-/*------------ Workaround to old compilers (4.1.2 and earlier)  ------------*/
-
-#ifndef __AVR_HAVE_MOVW__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_MOVW__ 1
-# endif
-#endif
-
-#ifndef __AVR_HAVE_LPMX__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_LPMX__ 1
-# endif
-#endif
-
-#ifndef __AVR_HAVE_MUL__
-# if  defined(__AVR_ENHANCED__) && __AVR_ENHANCED__
-#  define __AVR_HAVE_MUL__ 1
-# endif
-#endif
-
-/**@}*/
-#endif /* _AVR_COMMON_H */
diff --git a/cpukit/score/cpu/avr/avr/crc16.h b/cpukit/score/cpu/avr/avr/crc16.h
deleted file mode 100644
index fe6dfd4..0000000
--- a/cpukit/score/cpu/avr/avr/crc16.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/**
- * @file
- *
- * @brief Moved to <util/crc16.h>
- */
-
-/*
- *  Copyright (c) 2005 Joerg Wunsch
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_CRC16_H_
-#define _AVR_CRC16_H_
-
-/**
- *  @defgroup Avr_crc16 crc16
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#warning "This file has been moved to <util/crc16.h>."
-#include <util/crc16.h>
-
-/**@}*/
-#endif /* _AVR_CRC16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/delay.h b/cpukit/score/cpu/avr/avr/delay.h
deleted file mode 100644
index ad9db10..0000000
--- a/cpukit/score/cpu/avr/avr/delay.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- * @file
- *
- * @brief Moved to <util/delay.h>
- */
-
-/*
- * Copyright (c) 2005 Joerg Wunsch
- * All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_DELAY_H_
-#define _AVR_DELAY_H_
-
-/**
- * @defgroup AvrDelay Delay
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#warning "This file has been moved to <util/delay.h>."
-#include <util/delay.h>
-
-/** @} */
-#endif /* _AVR_DELAY_H_ */
diff --git a/cpukit/score/cpu/avr/avr/eeprom.h b/cpukit/score/cpu/avr/avr/eeprom.h
deleted file mode 100644
index 448248d..0000000
--- a/cpukit/score/cpu/avr/avr/eeprom.h
+++ /dev/null
@@ -1,620 +0,0 @@
-/**
- * @file
- *
- * @brief Data EEPROM Contained in the AVR Microcontrollers
- *
- * This header file declares the interface to some simple library
- * routines suitable for handling the data EEPROM contained in the
- * AVR microcontrollers.  The implementation uses a simple polled
- * mode interface.  Applications that require interrupt-controlled
- * EEPROM access to ensure that no time will be wasted in spinloops
- * will have to deploy their own implementation.
- *
- *  \par Notes:
- *
- *  - In addition to the write functions there is a set of update ones.
- *  This functions read each byte first and skip the burning if the
- *  old value is the same with new.  The scaning direction is from
- *  high address to low, to obtain quick return in common cases.
- *
- *  - All of the read/write functions first make sure the EEPROM is
- *  ready to be accessed.  Since this may cause long delays if a
- *  write operation is still pending, time-critical applications
- *  should first poll the EEPROM e. g. using eeprom_is_ready() before
- *  attempting any actual I/O.  But this functions are not wait until
- *  SELFPRGEN in SPMCSR becomes zero.  Do this manually, if your
- *  softwate contains the Flash burning.
- *
- *  - As these functions modify IO registers, they are known to be
- *  non-reentrant.  If any of these functions are used from both,
- *  standard and interrupt context, the applications must ensure
- *  proper protection (e.g. by disabling interrupts before accessing
- *  them).
- *
- *  - All write functions force erase_and_write programming mode.
- *
- *  - For Xmega the EEPROM start address is 0, like other architectures.
- *  The reading functions add the 0x2000 value to use EEPROM mapping into
- *  data space.
- */
-
-/*
- * Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
- * Copyright (c) 2005, 2006 Bjoern Haase
- * Copyright (c) 2008 Atmel Corporation
- * Copyright (c) 2008 Wouter van Gulik
- * Copyright (c) 2009 Dmitry Xmelkov
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_EEPROM_H_
-#define _AVR_EEPROM_H_ 1
-
-#include <avr/io.h>
-
-#if !E2END && !defined(__DOXYGEN__) && !defined(__COMPILING_AVR_LIBC__)
-# warning "Device does not have EEPROM available."
-#else
-
-#ifndef	__DOXYGEN__
-
-#if defined (__AVR_AT94K__)
-# define _EEPROM_SUFFIX _at94k
-#elif defined (__AVR_AT43USB320__)
-# define _EEPROM_SUFFIX _43u320
-#elif defined (__AVR_AT43USB355__)
-# define _EEPROM_SUFFIX _43u355
-#elif defined (__AVR_AT76C711__)
-# define _EEPROM_SUFFIX _76c711
-#elif defined (__AVR_AT86RF401__)
-# define _EEPROM_SUFFIX _86r401
-#elif defined (__AVR_AT90PWM1__)
-# define _EEPROM_SUFFIX _90pwm1
-#elif defined (__AVR_AT90PWM2__)
-# define _EEPROM_SUFFIX _90pwm2
-#elif defined (__AVR_AT90PWM2B__)
-# define _EEPROM_SUFFIX _90pwm2b
-#elif defined (__AVR_AT90PWM3__)
-# define _EEPROM_SUFFIX _90pwm3
-#elif defined (__AVR_AT90PWM3B__)
-# define _EEPROM_SUFFIX _90pwm3b
-#elif defined (__AVR_AT90PWM216__)
-# define _EEPROM_SUFFIX _90pwm216
-#elif defined (__AVR_AT90PWM316__)
-# define _EEPROM_SUFFIX _90pwm316
-#elif defined (__AVR_AT90PWM81__)
-# define _EEPROM_SUFFIX _90pwm81
-#elif defined (__AVR_ATmega16M1__)
-# define _EEPROM_SUFFIX  _m16m1
-#elif defined (__AVR_ATmega8U2__)
-# define _EEPROM_SUFFIX  _m8u2
-#elif defined (__AVR_ATmega16U2__)
-# define _EEPROM_SUFFIX  _m16u2
-#elif defined (__AVR_ATmega16U4__)
-# define _EEPROM_SUFFIX  _m16u4
-#elif defined (__AVR_ATmega32C1__)
-# define _EEPROM_SUFFIX  _m32c1
-#elif defined (__AVR_ATmega32M1__)
-# define _EEPROM_SUFFIX  _m32m1
-#elif defined (__AVR_ATmega32U2__)
-# define _EEPROM_SUFFIX  _m32u2
-#elif defined (__AVR_ATmega32U4__)
-# define _EEPROM_SUFFIX  _m32u4
-#elif defined (__AVR_ATmega32U6__)
-# define _EEPROM_SUFFIX  _m32u6
-#elif defined (__AVR_ATmega64C1__)
-# define _EEPROM_SUFFIX  _m64c1
-#elif defined (__AVR_ATmega64M1__)
-# define _EEPROM_SUFFIX  _m64m1
-#elif defined (__AVR_ATmega128__)
-# define _EEPROM_SUFFIX  _m128
-#elif defined (__AVR_ATmega1280__)
-# define _EEPROM_SUFFIX  _m1280
-#elif defined (__AVR_ATmega1281__)
-# define _EEPROM_SUFFIX  _m1281
-#elif defined (__AVR_ATmega1284P__)
-# define _EEPROM_SUFFIX  _m1284p
-#elif defined (__AVR_ATmega128RFA1__)
-# define _EEPROM_SUFFIX  _m128rfa1
-#elif defined (__AVR_ATmega2560__)
-# define _EEPROM_SUFFIX  _m2560
-#elif defined (__AVR_ATmega2561__)
-# define _EEPROM_SUFFIX  _m2561
-#elif defined (__AVR_AT90CAN32__)
-# define _EEPROM_SUFFIX _can32
-#elif defined (__AVR_AT90CAN64__)
-# define _EEPROM_SUFFIX _can64
-#elif defined (__AVR_AT90CAN128__)
-# define _EEPROM_SUFFIX _can128
-#elif defined (__AVR_AT90USB82__)
-# define _EEPROM_SUFFIX _usb82
-#elif defined (__AVR_AT90USB162__)
-# define _EEPROM_SUFFIX _usb162
-#elif defined (__AVR_AT90USB646__)
-# define _EEPROM_SUFFIX _usb646
-#elif defined (__AVR_AT90USB647__)
-# define _EEPROM_SUFFIX _usb647
-#elif defined (__AVR_AT90USB1286__)
-# define _EEPROM_SUFFIX _usb1286
-#elif defined (__AVR_AT90USB1287__)
-# define _EEPROM_SUFFIX _usb1287
-#elif defined (__AVR_ATmega64__)
-# define _EEPROM_SUFFIX  _m64
-#elif defined (__AVR_ATmega640__)
-# define _EEPROM_SUFFIX  _m640
-#elif defined (__AVR_ATmega644__)
-# define _EEPROM_SUFFIX  _m644
-#elif defined (__AVR_ATmega644A__)
-# define _EEPROM_SUFFIX  _m644a
-#elif defined (__AVR_ATmega644P__)
-# define _EEPROM_SUFFIX  _m644p
-#elif defined (__AVR_ATmega644PA__)
-# define _EEPROM_SUFFIX  _m644pa
-#elif defined (__AVR_ATmega645__)
-# define _EEPROM_SUFFIX  _m645
-#elif defined (__AVR_ATmega645A__)
-# define _EEPROM_SUFFIX  _m645a
-#elif defined (__AVR_ATmega645P__)
-# define _EEPROM_SUFFIX  _m645p
-#elif defined (__AVR_ATmega6450__)
-# define _EEPROM_SUFFIX  _m6450
-#elif defined (__AVR_ATmega6450A__)
-# define _EEPROM_SUFFIX  _m6450a
-#elif defined (__AVR_ATmega6450P__)
-# define _EEPROM_SUFFIX  _m6450p
-#elif defined (__AVR_ATmega649__)
-# define _EEPROM_SUFFIX  _m649
-#elif defined (__AVR_ATmega649A__)
-# define _EEPROM_SUFFIX  _m649a
-#elif defined (__AVR_ATmega649P__)
-# define _EEPROM_SUFFIX  _m649p
-#elif defined (__AVR_ATmega6490__)
-# define _EEPROM_SUFFIX  _m6490
-#elif defined (__AVR_ATmega6490A__)
-# define _EEPROM_SUFFIX  _m6490a
-#elif defined (__AVR_ATmega6490P__)
-# define _EEPROM_SUFFIX  _m6490p
-#elif defined (__AVR_ATmega103__)
-# define _EEPROM_SUFFIX  _m103
-#elif defined (__AVR_ATmega32__)
-# define _EEPROM_SUFFIX  _m32
-#elif defined (__AVR_ATmega323__)
-# define _EEPROM_SUFFIX  _m323
-#elif defined (__AVR_ATmega324A__)
-# define _EEPROM_SUFFIX  _m324a
-#elif defined (__AVR_ATmega324P__)
-# define _EEPROM_SUFFIX  _m324p
-#elif defined (__AVR_ATmega324PA__)
-# define _EEPROM_SUFFIX  _m324pa
-#elif defined (__AVR_ATmega325__)
-# define _EEPROM_SUFFIX  _m325
-#elif defined (__AVR_ATmega325P__)
-# define _EEPROM_SUFFIX  _m325p
-#elif defined (__AVR_ATmega3250__)
-# define _EEPROM_SUFFIX  _m3250
-#elif defined (__AVR_ATmega3250P__)
-# define _EEPROM_SUFFIX  _m3250p
-#elif defined (__AVR_ATmega328__)
-# define _EEPROM_SUFFIX  _m328
-#elif defined (__AVR_ATmega328P__)
-# define _EEPROM_SUFFIX  _m328p
-#elif defined (__AVR_ATmega329__)
-# define _EEPROM_SUFFIX  _m329
-#elif defined (__AVR_ATmega329P__)
-# define _EEPROM_SUFFIX  _m329p
-#elif defined (__AVR_ATmega329PA__)
-# define _EEPROM_SUFFIX  _m329pa
-#elif defined (__AVR_ATmega3290__)
-# define _EEPROM_SUFFIX  _m3290
-#elif defined (__AVR_ATmega3290P__)
-# define _EEPROM_SUFFIX  _m3290p
-#elif defined (__AVR_ATmega32HVB__)
-# define _EEPROM_SUFFIX  _m32hvb
-#elif defined (__AVR_ATmega64HVE__)
-# define _EEPROM_SUFFIX  _m64hve
-#elif defined (__AVR_ATmega406__)
-# define _EEPROM_SUFFIX  _m406
-#elif defined (__AVR_ATmega16__)
-# define _EEPROM_SUFFIX  _m16
-#elif defined (__AVR_ATmega16A__)
-# define _EEPROM_SUFFIX  _m16a
-#elif defined (__AVR_ATmega161__)
-# define _EEPROM_SUFFIX  _m161
-#elif defined (__AVR_ATmega162__)
-# define _EEPROM_SUFFIX  _m162
-#elif defined (__AVR_ATmega163__)
-# define _EEPROM_SUFFIX  _m163
-#elif defined (__AVR_ATmega164__)
-# define _EEPROM_SUFFIX  _m164
-#elif defined (__AVR_ATmega164P__)
-# define _EEPROM_SUFFIX  _m164p
-#elif defined (__AVR_ATmega165__)
-# define _EEPROM_SUFFIX  _m165
-#elif defined (__AVR_ATmega165A__)
-# define _EEPROM_SUFFIX  _m165a
-#elif defined (__AVR_ATmega165P__)
-# define _EEPROM_SUFFIX  _m165p
-#elif defined (__AVR_ATmega168__)
-# define _EEPROM_SUFFIX  _m168
-#elif defined (__AVR_ATmega168A__)
-# define _EEPROM_SUFFIX  _m168a
-#elif defined (__AVR_ATmega168P__)
-# define _EEPROM_SUFFIX  _m168p
-#elif defined (__AVR_ATmega169__)
-# define _EEPROM_SUFFIX  _m169
-#elif defined (__AVR_ATmega169A__)
-# define _EEPROM_SUFFIX  _m169a
-#elif defined (__AVR_ATmega169P__)
-# define _EEPROM_SUFFIX  _m169p
-#elif defined (__AVR_ATmega169PA__)
-# define _EEPROM_SUFFIX  _m169pa
-#elif defined (__AVR_ATmega8HVA__)
-# define _EEPROM_SUFFIX  _m8hva
-#elif defined (__AVR_ATmega16HVA__)
-# define _EEPROM_SUFFIX  _m16hva
-#elif defined (__AVR_ATmega16HVA2__)
-# define _EEPROM_SUFFIX  _m16hva2
-#elif defined (__AVR_ATmega16HVB__)
-# define _EEPROM_SUFFIX  _m16hvb
-#elif defined (__AVR_ATmega8__)
-# define _EEPROM_SUFFIX  _m8
-#elif defined (__AVR_ATmega48__)
-# define _EEPROM_SUFFIX  _m48
-#elif defined (__AVR_ATmega48A__)
-# define _EEPROM_SUFFIX  _m48a
-#elif defined (__AVR_ATmega48P__)
-# define _EEPROM_SUFFIX  _m48p
-#elif defined (__AVR_ATmega88__)
-# define _EEPROM_SUFFIX  _m88
-#elif defined (__AVR_ATmega88A__)
-# define _EEPROM_SUFFIX  _m88a
-#elif defined (__AVR_ATmega88P__)
-# define _EEPROM_SUFFIX  _m88p
-#elif defined (__AVR_ATmega88PA__)
-# define _EEPROM_SUFFIX  _m88pa
-#elif defined (__AVR_ATmega8515__)
-# define _EEPROM_SUFFIX  _m8515
-#elif defined (__AVR_ATmega8535__)
-# define _EEPROM_SUFFIX  _m8535
-#elif defined (__AVR_AT90S8535__)
-# define _EEPROM_SUFFIX  _8535
-#elif defined (__AVR_AT90C8534__)
-# define _EEPROM_SUFFIX  _8534
-#elif defined (__AVR_AT90S8515__)
-# define _EEPROM_SUFFIX  _8515
-#elif defined (__AVR_AT90S4434__)
-# define _EEPROM_SUFFIX  _4434
-#elif defined (__AVR_AT90S4433__)
-# define _EEPROM_SUFFIX  _4433
-#elif defined (__AVR_AT90S4414__)
-# define _EEPROM_SUFFIX  _4414
-#elif defined (__AVR_ATtiny22__)
-# define _EEPROM_SUFFIX _tn22
-#elif defined (__AVR_ATtiny26__)
-# define _EEPROM_SUFFIX _tn26
-#elif defined (__AVR_AT90S2343__)
-# define _EEPROM_SUFFIX  _2343
-#elif defined (__AVR_AT90S2333__)
-# define _EEPROM_SUFFIX  _2333
-#elif defined (__AVR_AT90S2323__)
-# define _EEPROM_SUFFIX  _2323
-#elif defined (__AVR_AT90S2313__)
-# define _EEPROM_SUFFIX  _2313
-#elif defined (__AVR_ATtiny2313__)
-# define _EEPROM_SUFFIX _tn2313
-#elif defined (__AVR_ATtiny2313A__)
-# define _EEPROM_SUFFIX _tn2313a
-#elif defined (__AVR_ATtiny4313__)
-# define _EEPROM_SUFFIX _tn4313
-#elif defined (__AVR_ATtiny13__)
-# define _EEPROM_SUFFIX _tn13
-#elif defined (__AVR_ATtiny13A__)
-# define _EEPROM_SUFFIX _tn13a
-#elif defined (__AVR_ATtiny25__)
-# define _EEPROM_SUFFIX _tn25
-#elif defined (__AVR_ATtiny45__)
-# define _EEPROM_SUFFIX _tn45
-#elif defined (__AVR_ATtiny85__)
-# define _EEPROM_SUFFIX _tn85
-#elif defined (__AVR_ATtiny24__)
-# define _EEPROM_SUFFIX _tn24
-#elif defined (__AVR_ATtiny24A__)
-# define _EEPROM_SUFFIX _tn24a
-#elif defined (__AVR_ATtiny44__)
-# define _EEPROM_SUFFIX _tn44
-#elif defined (__AVR_ATtiny44A__)
-# define _EEPROM_SUFFIX _tn44a
-#elif defined (__AVR_ATtiny84__)
-# define _EEPROM_SUFFIX _tn84
-#elif defined (__AVR_ATtiny261__)
-# define _EEPROM_SUFFIX _tn261
-#elif defined (__AVR_ATtiny261A__)
-# define _EEPROM_SUFFIX _tn261a
-#elif defined (__AVR_ATtiny461__)
-# define _EEPROM_SUFFIX _tn461
-#elif defined (__AVR_ATtiny461A__)
-# define _EEPROM_SUFFIX _tn461a
-#elif defined (__AVR_ATtiny861__)
-# define _EEPROM_SUFFIX _tn861
-#elif defined (__AVR_ATtiny861A__)
-# define _EEPROM_SUFFIX _tn861a
-#elif defined (__AVR_ATtiny43U__)
-# define _EEPROM_SUFFIX _tn43u
-#elif defined (__AVR_ATtiny48__)
-# define _EEPROM_SUFFIX _tn48
-#elif defined (__AVR_ATtiny88__)
-# define _EEPROM_SUFFIX _tn88
-#elif defined (__AVR_ATtiny87__)
-# define _EEPROM_SUFFIX _tn87
-#elif defined (__AVR_ATtiny167__)
-# define _EEPROM_SUFFIX _tn167
-#elif defined (__AVR_AT90SCR100__)
-# define _EEPROM_SUFFIX _90scr100
-#elif defined (__AVR_ATxmega16A4__)
-# define _EEPROM_SUFFIX   _x16a4
-#elif defined (__AVR_ATxmega16D4__)
-# define _EEPROM_SUFFIX   _x16d4
-#elif defined (__AVR_ATxmega32A4__)
-# define _EEPROM_SUFFIX   _x32a4
-#elif defined (__AVR_ATxmega32D4__)
-# define _EEPROM_SUFFIX   _x32d4
-#elif defined (__AVR_ATxmega64A1__)
-# define _EEPROM_SUFFIX   _x64a1
-#elif defined (__AVR_ATxmega64A3__)
-# define _EEPROM_SUFFIX   _x64a3
-#elif defined (__AVR_ATxmega64D3__)
-# define _EEPROM_SUFFIX   _x64d3
-#elif defined (__AVR_ATxmega128A1__)
-# define _EEPROM_SUFFIX   _x128a1
-#elif defined (__AVR_ATxmega128A3__)
-# define _EEPROM_SUFFIX   _x128a3
-#elif defined (__AVR_ATxmega128D3__)
-# define _EEPROM_SUFFIX   _x128d3
-#elif defined (__AVR_ATxmega192A3__)
-# define _EEPROM_SUFFIX   _x192a3
-#elif defined (__AVR_ATxmega192D3__)
-# define _EEPROM_SUFFIX   _x192d3
-#elif defined (__AVR_ATxmega256A3__)
-# define _EEPROM_SUFFIX   _x256a3
-#elif defined (__AVR_ATxmega256A3B__)
-# define _EEPROM_SUFFIX   _x256a3b
-#elif defined (__AVR_ATxmega256D3__)
-# define _EEPROM_SUFFIX   _x256d3
-#elif defined (__AVR_ATA6289__)
-# define _EEPROM_SUFFIX _a6289
-/* avr1: the following only supported for assembler programs */
-#elif defined (__AVR_ATtiny28__)
-# define _EEPROM_SUFFIX _tn28
-#elif defined (__AVR_AT90S1200__)
-# define _EEPROM_SUFFIX  _1200
-#elif defined (__AVR_ATtiny15__)
-# define _EEPROM_SUFFIX _tn15
-#elif defined (__AVR_ATtiny12__)
-# define _EEPROM_SUFFIX _tn12
-#elif defined (__AVR_ATtiny11__)
-# define _EEPROM_SUFFIX _tn11
-#else
-# define _EEPROM_SUFFIX		_UNKNOWN
-#endif
-
-#define _EEPROM_CONCAT1(s1, s2)     s1 ## s2
-#define _EEPROM_CONCAT2(s1, s2)     _EEPROM_CONCAT1 (s1, s2)
-
-#define eeprom_read_byte      _EEPROM_CONCAT2 (__eerd_byte, _EEPROM_SUFFIX)
-#define eeprom_read_word      _EEPROM_CONCAT2 (__eerd_word, _EEPROM_SUFFIX)
-#define eeprom_read_dword     _EEPROM_CONCAT2 (__eerd_dword, _EEPROM_SUFFIX)
-#define eeprom_read_float     _EEPROM_CONCAT2 (__eerd_float, _EEPROM_SUFFIX)
-#define eeprom_read_block     _EEPROM_CONCAT2 (__eerd_block, _EEPROM_SUFFIX)
-
-#define eeprom_write_byte     _EEPROM_CONCAT2 (__eewr_byte, _EEPROM_SUFFIX)
-#define eeprom_write_word     _EEPROM_CONCAT2 (__eewr_word, _EEPROM_SUFFIX)
-#define eeprom_write_dword    _EEPROM_CONCAT2 (__eewr_dword, _EEPROM_SUFFIX)
-#define eeprom_write_float    _EEPROM_CONCAT2 (__eewr_float, _EEPROM_SUFFIX)
-#define eeprom_write_block    _EEPROM_CONCAT2 (__eewr_block, _EEPROM_SUFFIX)
-
-#define eeprom_update_byte    _EEPROM_CONCAT2 (__eeupd_byte, _EEPROM_SUFFIX)
-#define eeprom_update_word    _EEPROM_CONCAT2 (__eeupd_word, _EEPROM_SUFFIX)
-#define eeprom_update_dword   _EEPROM_CONCAT2 (__eeupd_dword, _EEPROM_SUFFIX)
-#define eeprom_update_float   _EEPROM_CONCAT2 (__eeupd_float, _EEPROM_SUFFIX)
-#define eeprom_update_block   _EEPROM_CONCAT2 (__eeupd_block, _EEPROM_SUFFIX)
-
-#endif	/* !__DOXYGEN__ */
-
-#ifndef	__ASSEMBLER__
-
-#include <stddef.h>	/* size_t */
-#include <stdint.h>
-
-/**
- *  @defgroup avr_eeprom EEPROM handling
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef	__ATTR_PURE__
-# ifdef	 __DOXYGEN__
-#  define __ATTR_PURE__
-# else
-#  define __ATTR_PURE__  __attribute__((__pure__))
-# endif
-#endif
-
-/** \def EEMEM
-    \ingroup avr_eeprom
-    Attribute expression causing a variable to be allocated within the
-    .eeprom section.	*/
-#define EEMEM __attribute__((section(".eeprom")))
-
-/** \def eeprom_is_ready
-    \ingroup avr_eeprom
-    \returns 1 if EEPROM is ready for a new read/write operation, 0 if not.
- */
-#if	defined (__DOXYGEN__)
-# define eeprom_is_ready()
-#elif	defined (__AVR_XMEGA__) && __AVR_XMEGA__
-# define eeprom_is_ready()	bit_is_clear (NVM_STATUS, NVM_NVMBUSY_bp)
-#elif	defined (DEECR)
-# define eeprom_is_ready()	bit_is_clear (DEECR, BSY)
-#elif	defined (EEPE)
-# define eeprom_is_ready()	bit_is_clear (EECR, EEPE)
-#else
-# define eeprom_is_ready()	bit_is_clear (EECR, EEWE)
-#endif
-
-
-/** \def eeprom_busy_wait
-    \ingroup avr_eeprom
-    Loops until the eeprom is no longer busy.
-    \returns Nothing.
- */
-#define eeprom_busy_wait() do {} while (!eeprom_is_ready())
-
-
-/** \ingroup avr_eeprom
-    Read one byte from EEPROM address \a __p.
- */
-uint8_t eeprom_read_byte (const uint8_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one 16-bit word (little endian) from EEPROM address \a __p.
- */
-uint16_t eeprom_read_word (const uint16_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one 32-bit double word (little endian) from EEPROM address \a __p.
- */
-uint32_t eeprom_read_dword (const uint32_t *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read one float value (little endian) from EEPROM address \a __p.
- */
-float eeprom_read_float (const float *__p) __ATTR_PURE__;
-
-/** \ingroup avr_eeprom
-    Read a block of \a __n bytes from EEPROM address \a __src to SRAM
-    \a __dst.
- */
-void eeprom_read_block (void *__dst, const void *__src, size_t __n);
-
-
-/** \ingroup avr_eeprom
-    Write a byte \a __value to EEPROM address \a __p.
- */
-void eeprom_write_byte (uint8_t *__p, uint8_t __value);
-
-/** \ingroup avr_eeprom
-    Write a word \a __value to EEPROM address \a __p.
- */
-void eeprom_write_word (uint16_t *__p, uint16_t __value);
-
-/** \ingroup avr_eeprom
-    Write a 32-bit double word \a __value to EEPROM address \a __p.
- */
-void eeprom_write_dword (uint32_t *__p, uint32_t __value);
-
-/** \ingroup avr_eeprom
-    Write a float \a __value to EEPROM address \a __p.
- */
-void eeprom_write_float (float *__p, float __value);
-
-/** \ingroup avr_eeprom
-    Write a block of \a __n bytes to EEPROM address \a __dst from \a __src.
-    \note The argument order is mismatch with common functions like strcpy().
- */
-void eeprom_write_block (const void *__src, void *__dst, size_t __n);
-
-
-/** \ingroup avr_eeprom
-    Update a byte \a __value to EEPROM address \a __p.
- */
-void eeprom_update_byte (uint8_t *__p, uint8_t __value);
-
-/** \ingroup avr_eeprom
-    Update a word \a __value to EEPROM address \a __p.
- */
-void eeprom_update_word (uint16_t *__p, uint16_t __value);
-
-/** \ingroup avr_eeprom
-    Update a 32-bit double word \a __value to EEPROM address \a __p.
- */
-void eeprom_update_dword (uint32_t *__p, uint32_t __value);
-
-/** \ingroup avr_eeprom
-    Update a float \a __value to EEPROM address \a __p.
- */
-void eeprom_update_float (float *__p, float __value);
-
-/** \ingroup avr_eeprom
-    Update a block of \a __n bytes to EEPROM address \a __dst from \a __src.
-    \note The argument order is mismatch with common functions like strcpy().
- */
-void eeprom_update_block (const void *__src, void *__dst, size_t __n);
-
-
-/** \name IAR C compatibility defines	*/
-/*@{*/
-
-/** \def _EEPUT
-    \ingroup avr_eeprom
-    Write a byte to EEPROM. Compatibility define for IAR C.	*/
-#define _EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
-
-/** \def __EEPUT
-    \ingroup avr_eeprom
-    Write a byte to EEPROM. Compatibility define for IAR C.	*/
-#define __EEPUT(addr, val) eeprom_write_byte ((uint8_t *)(addr), (uint8_t)(val))
-
-/** \def _EEGET
-    \ingroup avr_eeprom
-    Read a byte from EEPROM. Compatibility define for IAR C.	*/
-#define _EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-
-/** \def __EEGET
-    \ingroup avr_eeprom
-    Read a byte from EEPROM. Compatibility define for IAR C.	*/
-#define __EEGET(var, addr) (var) = eeprom_read_byte ((const uint8_t *)(addr))
-
-/*@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif	/* !__ASSEMBLER__ */
-#endif	/* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */
-
-/**@}*/
-#endif	/* !_AVR_EEPROM_H_ */
diff --git a/cpukit/score/cpu/avr/avr/fuse.h b/cpukit/score/cpu/avr/avr/fuse.h
deleted file mode 100644
index ba968ba..0000000
--- a/cpukit/score/cpu/avr/avr/fuse.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/fuse.h - Fuse API */
-
-#ifndef _AVR_FUSE_H_
-#define _AVR_FUSE_H_ 1
-
-/* This file must be explicitly included by <avr/io.h>. */
-#if !defined(_AVR_IO_H_)
-#error "You must #include <avr/io.h> and not <avr/fuse.h> by itself."
-#endif
-
-
-/** \file */
-/** \defgroup avr_fuse <avr/fuse.h>: Fuse Support
-
-    \par Introduction
-
-    The Fuse API allows a user to specify the fuse settings for the specific
-    AVR device they are compiling for. These fuse settings will be placed
-    in a special section in the ELF output file, after linking.
-
-    Programming tools can take advantage of the fuse information embedded in
-    the ELF file, by extracting this information and determining if the fuses
-    need to be programmed before programming the Flash and EEPROM memories.
-    This also allows a single ELF file to contain all the
-    information needed to program an AVR. 
-
-    To use the Fuse API, include the <avr/io.h> header file, which in turn
-    automatically includes the individual I/O header file and the <avr/fuse.h>
-    file. These other two files provides everything necessary to set the AVR
-    fuses.
-    
-    \par Fuse API
-    
-    Each I/O header file must define the FUSE_MEMORY_SIZE macro which is
-    defined to the number of fuse bytes that exist in the AVR device.
-    
-    A new type, __fuse_t, is defined as a structure. The number of fields in 
-    this structure are determined by the number of fuse bytes in the 
-    FUSE_MEMORY_SIZE macro.
-    
-    If FUSE_MEMORY_SIZE == 1, there is only a single field: byte, of type
-    unsigned char.
-    
-    If FUSE_MEMORY_SIZE == 2, there are two fields: low, and high, of type
-    unsigned char.
-    
-    If FUSE_MEMORY_SIZE == 3, there are three fields: low, high, and extended,
-    of type unsigned char.
-    
-    If FUSE_MEMORY_SIZE > 3, there is a single field: byte, which is an array
-    of unsigned char with the size of the array being FUSE_MEMORY_SIZE.
-    
-    A convenience macro, FUSEMEM, is defined as a GCC attribute for a 
-    custom-named section of ".fuse".
-    
-    A convenience macro, FUSES, is defined that declares a variable, __fuse, of
-    type __fuse_t with the attribute defined by FUSEMEM. This variable
-    allows the end user to easily set the fuse data.
-
-    \note If a device-specific I/O header file has previously defined FUSEMEM,
-    then FUSEMEM is not redefined. If a device-specific I/O header file has
-    previously defined FUSES, then FUSES is not redefined.
-
-    Each AVR device I/O header file has a set of defined macros which specify the
-    actual fuse bits available on that device. The AVR fuses have inverted
-    values, logical 1 for an unprogrammed (disabled) bit and logical 0 for a
-    programmed (enabled) bit. The defined macros for each individual fuse
-    bit represent this in their definition by a bit-wise inversion of a mask.
-    For example, the FUSE_EESAVE fuse in the ATmega128 is defined as:
-    \code
-    #define FUSE_EESAVE      ~_BV(3)
-    \endcode
-    \note The _BV macro creates a bit mask from a bit number. It is then 
-    inverted to represent logical values for a fuse memory byte.
-    
-    To combine the fuse bits macros together to represent a whole fuse byte,
-    use the bitwise AND operator, like so:
-    \code
-    (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN)
-    \endcode
-    
-    Each device I/O header file also defines macros that provide default values
-    for each fuse byte that is available. LFUSE_DEFAULT is defined for a Low
-    Fuse byte. HFUSE_DEFAULT is defined for a High Fuse byte. EFUSE_DEFAULT
-    is defined for an Extended Fuse byte.
-    
-    If FUSE_MEMORY_SIZE > 3, then the I/O header file defines macros that
-    provide default values for each fuse byte like so:
-    FUSE0_DEFAULT
-    FUSE1_DEFAULT
-    FUSE2_DEFAULT
-    FUSE3_DEFAULT
-    FUSE4_DEFAULT
-    ....
-    
-    \par API Usage Example
-    
-    Putting all of this together is easy. Using C99's designated initializers:
-    
-    \code
-    #include <avr/io.h>
-
-    FUSES = 
-    {
-        .low = LFUSE_DEFAULT,
-        .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
-        .extended = EFUSE_DEFAULT,
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    Or, using the variable directly instead of the FUSES macro,
-    
-    \code
-    #include <avr/io.h>
-
-    __fuse_t __fuse __attribute__((section (".fuse"))) = 
-    {
-        .low = LFUSE_DEFAULT,
-        .high = (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN),
-        .extended = EFUSE_DEFAULT,
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    If you are compiling in C++, you cannot use the designated intializers so
-    you must do:
-
-    \code
-    #include <avr/io.h>
-
-    FUSES = 
-    {
-        LFUSE_DEFAULT, // .low
-        (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_EESAVE & FUSE_SPIEN & FUSE_JTAGEN), // .high
-        EFUSE_DEFAULT, // .extended
-    };
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    
-    However there are a number of caveats that you need to be aware of to
-    use this API properly.
-    
-    Be sure to include <avr/io.h> to get all of the definitions for the API.
-    The FUSES macro defines a global variable to store the fuse data. This 
-    variable is assigned to its own linker section. Assign the desired fuse 
-    values immediately in the variable initialization.
-    
-    The .fuse section in the ELF file will get its values from the initial 
-    variable assignment ONLY. This means that you can NOT assign values to 
-    this variable in functions and the new values will not be put into the
-    ELF .fuse section.
-    
-    The global variable is declared in the FUSES macro has two leading 
-    underscores, which means that it is reserved for the "implementation",
-    meaning the library, so it will not conflict with a user-named variable.
-    
-    You must initialize ALL fields in the __fuse_t structure. This is because
-    the fuse bits in all bytes default to a logical 1, meaning unprogrammed. 
-    Normal uninitialized data defaults to all locgial zeros. So it is vital that
-    all fuse bytes are initialized, even with default data. If they are not,
-    then the fuse bits may not programmed to the desired settings.
-    
-    Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
-    your linker command line to have the correct device selected and to have 
-    the correct I/O header file included when you include <avr/io.h>.
-
-    You can print out the contents of the .fuse section in the ELF file by
-    using this command line:
-    \code
-    avr-objdump -s -j .fuse <ELF file>
-    \endcode
-    The section contents shows the address on the left, then the data going from
-    lower address to a higher address, left to right.
-
-*/
-
-#ifndef __ASSEMBLER__
-
-#ifndef FUSEMEM
-#define FUSEMEM  __attribute__((section (".fuse")))
-#endif
-
-#if FUSE_MEMORY_SIZE > 3
-
-typedef struct
-{
-    unsigned char byte[FUSE_MEMORY_SIZE];
-} __fuse_t;
-
-
-#elif FUSE_MEMORY_SIZE == 3
-
-typedef struct
-{
-    unsigned char low;
-    unsigned char high;
-    unsigned char extended;
-} __fuse_t;
-
-#elif FUSE_MEMORY_SIZE == 2
-
-typedef struct
-{
-    unsigned char low;
-    unsigned char high;
-} __fuse_t;
-
-#elif FUSE_MEMORY_SIZE == 1
-
-typedef struct
-{
-    unsigned char byte;
-} __fuse_t;
-
-#endif
-
-#ifndef FUSES
-#define FUSES __fuse_t __fuse FUSEMEM
-#endif
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* _AVR_FUSE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/interrupt.h b/cpukit/score/cpu/avr/avr/interrupt.h
deleted file mode 100644
index 8dd5e26..0000000
--- a/cpukit/score/cpu/avr/avr/interrupt.h
+++ /dev/null
@@ -1,343 +0,0 @@
-/* Copyright (c) 2002,2005,2007 Marek Michalkiewicz
-   Copyright (c) 2007, Dean Camera
-
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-#ifndef _AVR_INTERRUPT_H_
-#define _AVR_INTERRUPT_H_
-
-#include <avr/io.h>
-
-#if !defined(__DOXYGEN__) && !defined(__STRINGIFY)
-/* Auxiliary macro for ISR_ALIAS(). */
-#define __STRINGIFY(x) #x
-#endif /* !defined(__DOXYGEN__) */
-
-/** 
-\file 
-\@{ 
-*/
-
-
-/** \name Global manipulation of the interrupt flag
-
-    The global interrupt flag is maintained in the I bit of the status
-    register (SREG). 
-*/
-
-#if defined(__DOXYGEN__)
-/** \def sei()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Enables interrupts by setting the global interrupt mask. This function
-    actually compiles into a single line of assembly, so there is no function
-    call overhead. */
-#define sei()
-#else  /* !DOXYGEN */
-# define sei()  __asm__ __volatile__ ("sei" ::)
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def cli()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Disables all interrupts by clearing the global interrupt mask. This function
-    actually compiles into a single line of assembly, so there is no function
-    call overhead. */
-#define cli()
-#else  /* !DOXYGEN */
-# define cli()  __asm__ __volatile__ ("cli" ::)
-#endif /* DOXYGEN */
-
-
-/** \name Macros for writing interrupt handler functions */
-
-
-#if defined(__DOXYGEN__)
-/** \def ISR(vector [, attributes])
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Introduces an interrupt handler function (interrupt service
-    routine) that runs with global interrupts initially disabled
-    by default with no attributes specified.
-
-    The attributes are optional and alter the behaviour and resultant
-    generated code of the interrupt routine. Multiple attributes may
-    be used for a single function, with a space seperating each
-    attribute.
-
-    Valid attributes are ISR_BLOCK, ISR_NOBLOCK, ISR_NAKED and
-    ISR_ALIASOF(vect).
-
-    \c vector must be one of the interrupt vector names that are
-    valid for the particular MCU type.
-*/
-#  define ISR(vector, [attributes])
-#else  /* real code */
-
-#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 1) || (__GNUC__ > 4)
-#  define __INTR_ATTRS used, externally_visible
-#else /* GCC < 4.1 */
-#  define __INTR_ATTRS used
-#endif
-
-#ifdef __cplusplus
-#  define ISR(vector, ...)            \
-    extern "C" void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
-    void vector (void)
-#else
-#  define ISR(vector, ...)            \
-    void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
-    void vector (void)
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def SIGNAL(vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Introduces an interrupt handler function that runs with global interrupts
-    initially disabled.
-
-    This is the same as the ISR macro without optional attributes.
-    \deprecated Do not use SIGNAL() in new code. Use ISR() instead.
-*/
-#  define SIGNAL(vector)
-#else  /* real code */
-
-#ifdef __cplusplus
-#  define SIGNAL(vector)					\
-    extern "C" void vector(void) __attribute__ ((signal, __INTR_ATTRS));	\
-    void vector (void)
-#else
-#  define SIGNAL(vector)					\
-    void vector (void) __attribute__ ((signal, __INTR_ATTRS));		\
-    void vector (void)
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def EMPTY_INTERRUPT(vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Defines an empty interrupt handler function. This will not generate
-    any prolog or epilog code and will only return from the ISR. Do not
-    define a function body as this will define it for you.
-    Example:
-    \code EMPTY_INTERRUPT(ADC_vect);\endcode */
-#  define EMPTY_INTERRUPT(vector)
-#else  /* real code */
-
-#ifdef __cplusplus
-#  define EMPTY_INTERRUPT(vector)                \
-    extern "C" void vector(void) __attribute__ ((signal,naked,__INTR_ATTRS));    \
-    void vector (void) {  __asm__ __volatile__ ("reti" ::); }
-#else
-#  define EMPTY_INTERRUPT(vector)                \
-    void vector (void) __attribute__ ((signal,naked,__INTR_ATTRS));    \
-    void vector (void) { __asm__ __volatile__ ("reti" ::); }
-#endif
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def ISR_ALIAS(vector, target_vector)
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Aliases a given vector to another one in the same manner as the
-    ISR_ALIASOF attribute for the ISR() macro. Unlike the ISR_ALIASOF
-    attribute macro however, this is compatible for all versions of
-    GCC rather than just GCC version 4.2 onwards.
-
-    \note This macro creates a trampoline function for the aliased
-    macro.  This will result in a two cycle penalty for the aliased
-    vector compared to the ISR the vector is aliased to, due to the
-    JMP/RJMP opcode used.
-
-    \deprecated
-    For new code, the use of ISR(..., ISR_ALIASOF(...))  is
-    recommended.
-
-    Example:
-    \code
-    ISR(INT0_vect)
-    {
-        PORTB = 42;
-    }
-
-    ISR_ALIAS(INT1_vect, INT0_vect);
-    \endcode 
-*/
-#  define ISR_ALIAS(vector, target_vector)
-#else /* real code */
-
-#ifdef __cplusplus
-#  if defined(__AVR_MEGA__) && __AVR_MEGA__
-#    define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("jmp " __STRINGIFY(tgt) ::); }
-#  else /* !__AVR_MEGA */
-#    define ISR_ALIAS(vector, tgt) extern "C" void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("rjmp " __STRINGIFY(tgt) ::); }
-#  endif  /* __AVR_MEGA__ */
-#else	  /* !__cplusplus */
-#  if defined(__AVR_MEGA__) && __AVR_MEGA__
-#  define ISR_ALIAS(vector, tgt) void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("jmp " __STRINGIFY(tgt) ::); }
-#  else /* !__AVR_MEGA */
-#  define ISR_ALIAS(vector, tgt) void vector (void) \
-	__attribute__((signal, naked, __INTR_ATTRS)); \
-	void vector (void) { __asm__ volatile ("rjmp " __STRINGIFY(tgt) ::); }
-#  endif  /* __AVR_MEGA__ */
-#endif	/* __cplusplus */
-
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def reti()
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    Returns from an interrupt routine, enabling global interrupts. This should
-    be the last command executed before leaving an ISR defined with the ISR_NAKED
-    attribute.
-
-    This macro actually compiles into a single line of assembly, so there is
-    no function call overhead.
-*/
-#  define reti()
-#else  /* !DOXYGEN */
-#  define reti()  __asm__ __volatile__ ("reti" ::)
-#endif /* DOXYGEN */
-
-#if defined(__DOXYGEN__)
-/** \def BADISR_vect
-    \ingroup avr_interrupts
-
-    \code #include <avr/interrupt.h> \endcode
-
-    This is a vector which is aliased to __vector_default, the vector
-    executed when an ISR fires with no accompanying ISR handler. This
-    may be used along with the ISR() macro to create a catch-all for
-    undefined but used ISRs for debugging purposes.
-*/
-#  define BADISR_vect
-#else  /* !DOXYGEN */
-#  define BADISR_vect __vector_default
-#endif /* DOXYGEN */
-
-/** \name ISR attributes */
-
-#if defined(__DOXYGEN__)
-/** \def ISR_BLOCK
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    Identical to an ISR with no attributes specified. Global
-    interrupts are initially disabled by the AVR hardware when
-    entering the ISR, without the compiler modifying this state.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_BLOCK
-
-/** \def ISR_NOBLOCK
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    ISR runs with global interrupts initially enabled.  The interrupt
-    enable flag is activated by the compiler as early as possible
-    within the ISR to ensure minimal processing delay for nested
-    interrupts.
-
-    This may be used to create nested ISRs, however care should be
-    taken to avoid stack overflows, or to avoid infinitely entering
-    the ISR for those cases where the AVR hardware does not clear the
-    respective interrupt flag before entering the ISR.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_NOBLOCK
-
-/** \def ISR_NAKED
-    \ingroup avr_interrupts
-
-    \code# include <avr/interrupt.h> \endcode
-
-    ISR is created with no prologue or epilogue code. The user code is
-    responsible for preservation of the machine state including the
-    SREG register, as well as placing a reti() at the end of the
-    interrupt routine.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_NAKED
-
-/** \def ISR_ALIASOF(target_vector)
-    \ingroup avr_interrupts
-
-    \code#include <avr/interrupt.h>\endcode
-
-    The ISR is linked to another ISR, specified by the vect parameter.
-    This is compatible with GCC 4.2 and greater only.
-
-    Use this attribute in the attributes parameter of the ISR macro.
-*/
-#  define ISR_ALIASOF(target_vector)
-#else  /* !DOXYGEN */
-#  define ISR_BLOCK
-#  define ISR_NOBLOCK    __attribute__((interrupt))
-#  define ISR_NAKED      __attribute__((naked))
-#  define ISR_ALIASOF(v) __attribute__((alias(__STRINGIFY(v))))
-#endif /* DOXYGEN */
-
-/* \@} */
-
-#endif
diff --git a/cpukit/score/cpu/avr/avr/io.h b/cpukit/score/cpu/avr/avr/io.h
deleted file mode 100644
index 22ac57d..0000000
--- a/cpukit/score/cpu/avr/avr/io.h
+++ /dev/null
@@ -1,429 +0,0 @@
-/**
- * @file
- *
- * @brief AVR device-specific IO Definitions
- *
- * This header file includes the apropriate IO definitions for the
- * device that has been specified by the <tt>-mmcu=</tt> compiler
- *  command-line switch.  This is done by diverting to the appropriate
- *  file <tt><avr/io</tt><em>XXXX</em><tt>.h></tt> which should
- *  never be included directly.  Some register names common to all
- *  AVR devices are defined directly within <tt><avr/common.h></tt>,
- *  which is included in <tt><avr/io.h></tt>,
- *  but most of the details come from the respective include file.
- *
- *  Note that this file always includes the following files:
- *  \code
- *  #include <avr/sfr_defs.h>
- *  #include <avr/portpins.h>
- *  #include <avr/common.h>
- *  #include <avr/version.h>
- *  \endcode
- *  See \ref avr_sfr for more details about that header file.
- *
- *  Included are definitions of the IO register set and their
- *  respective bit values as specified in the Atmel documentation.
- *  Note that inconsistencies in naming conventions,
- *  so even identical functions sometimes get different names on
- *  different devices.
- *
- *  Also included are the specific names useable for interrupt
- *  function definitions as documented
- *  \ref avr_signames "here".
- *
- *  Finally, the following macros are defined:
- *
- *  - \b RAMEND
- *  <br>
- *  The last on-chip RAM address.
- *  <br>
- *  - \b XRAMEND
- *  <br>
- *  The last possible RAM location that is addressable. This is equal to
- *  RAMEND for devices that do not allow for external RAM. For devices
- *  that allow external RAM, this will be larger than RAMEND.
- *  <br>
- *  - \b E2END
- *  <br>
- *  The last EEPROM address.
- *  <br>
- *  - \b FLASHEND
- *  <br>
- *  The last byte address in the Flash program space.
- *  <br>
- *  - \b SPM_PAGESIZE
- *  <br>
- *  For devices with bootloader support, the flash pagesize
- *  (in bytes) to be used for the \c SPM instruction.
- *  - \b E2PAGESIZE
- *  <br>
- *  The size of the EEPROM page.
- */
-
-/*
- *  Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
- *  Copyright (c) 2007 Eric B. Weddington
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#define _AVR_IO_H_
-
-/**
- * @defgroup avr_io Input Output
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/sfr_defs.h>
-
-#if defined (__AVR_AT94K__)
-#  include <avr/ioat94k.h>
-#elif defined (__AVR_AT43USB320__)
-#  include <avr/io43u32x.h>
-#elif defined (__AVR_AT43USB355__)
-#  include <avr/io43u35x.h>
-#elif defined (__AVR_AT76C711__)
-#  include <avr/io76c711.h>
-#elif defined (__AVR_AT86RF401__)
-#  include <avr/io86r401.h>
-#elif defined (__AVR_AT90PWM1__)
-#  include <avr/io90pwm1.h>
-#elif defined (__AVR_AT90PWM2__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM2B__)
-#  include <avr/io90pwm2b.h>
-#elif defined (__AVR_AT90PWM3__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM3B__)
-#  include <avr/io90pwm3b.h>
-#elif defined (__AVR_AT90PWM216__)
-#  include <avr/io90pwm216.h>
-#elif defined (__AVR_AT90PWM316__)
-#  include <avr/io90pwm316.h>
-#elif defined (__AVR_AT90PWM81__)
-#  include <avr/io90pwm81.h>
-#elif defined (__AVR_ATmega8U2__)
-#  include <avr/iom8u2.h>
-#elif defined (__AVR_ATmega16M1__)
-#  include <avr/iom16m1.h>
-#elif defined (__AVR_ATmega16U2__)
-#  include <avr/iom16u2.h>
-#elif defined (__AVR_ATmega16U4__)
-#  include <avr/iom16u4.h>
-#elif defined (__AVR_ATmega32C1__)
-#  include <avr/iom32c1.h>
-#elif defined (__AVR_ATmega32M1__)
-#  include <avr/iom32m1.h>
-#elif defined (__AVR_ATmega32U2__)
-#  include <avr/iom32u2.h>
-#elif defined (__AVR_ATmega32U4__)
-#  include <avr/iom32u4.h>
-#elif defined (__AVR_ATmega32U6__)
-#  include <avr/iom32u6.h>
-#elif defined (__AVR_ATmega64C1__)
-#  include <avr/iom64c1.h>
-#elif defined (__AVR_ATmega64M1__)
-#  include <avr/iom64m1.h>
-#elif defined (__AVR_ATmega128__)
-#  include <avr/iom128.h>
-#elif defined (__AVR_ATmega1280__)
-#  include <avr/iom1280.h>
-#elif defined (__AVR_ATmega1281__)
-#  include <avr/iom1281.h>
-#elif defined (__AVR_ATmega1284P__)
-#  include <avr/iom1284p.h>
-#elif defined (__AVR_ATmega128RFA1__)
-#  include <avr/iom128rfa1.h>
-#elif defined (__AVR_ATmega2560__)
-#  include <avr/iom2560.h>
-#elif defined (__AVR_ATmega2561__)
-#  include <avr/iom2561.h>
-#elif defined (__AVR_AT90CAN32__)
-#  include <avr/iocan32.h>
-#elif defined (__AVR_AT90CAN64__)
-#  include <avr/iocan64.h>
-#elif defined (__AVR_AT90CAN128__)
-#  include <avr/iocan128.h>
-#elif defined (__AVR_AT90USB82__)
-#  include <avr/iousb82.h>
-#elif defined (__AVR_AT90USB162__)
-#  include <avr/iousb162.h>
-#elif defined (__AVR_AT90USB646__)
-#  include <avr/iousb646.h>
-#elif defined (__AVR_AT90USB647__)
-#  include <avr/iousb647.h>
-#elif defined (__AVR_AT90USB1286__)
-#  include <avr/iousb1286.h>
-#elif defined (__AVR_AT90USB1287__)
-#  include <avr/iousb1287.h>
-#elif defined (__AVR_ATmega64__)
-#  include <avr/iom64.h>
-#elif defined (__AVR_ATmega640__)
-#  include <avr/iom640.h>
-#elif defined (__AVR_ATmega644__) || defined (__AVR_ATmega644A__)
-#  include <avr/iom644.h>
-#elif defined (__AVR_ATmega644P__)
-#  include <avr/iom644p.h>
-#elif defined (__AVR_ATmega644PA__)
-#  include <avr/iom644pa.h>
-#elif defined (__AVR_ATmega645__) || defined (__AVR_ATmega645A__) || defined (__AVR_ATmega645P__)
-#  include <avr/iom645.h>
-#elif defined (__AVR_ATmega6450__) || defined (__AVR_ATmega6450A__) || defined (__AVR_ATmega6450P__)
-#  include <avr/iom6450.h>
-#elif defined (__AVR_ATmega649__) || defined (__AVR_ATmega649A__)
-#  include <avr/iom649.h>
-#elif defined (__AVR_ATmega6490__) || defined (__AVR_ATmega6490A__) || defined (__AVR_ATmega6490P__)
-#  include <avr/iom6490.h>
-#elif defined (__AVR_ATmega649P__)
-#  include <avr/iom649p.h>
-#elif defined (__AVR_ATmega64HVE__)
-#  include <avr/iom64hve.h>
-#elif defined (__AVR_ATmega103__)
-#  include <avr/iom103.h>
-#elif defined (__AVR_ATmega32__)
-#  include <avr/iom32.h>
-#elif defined (__AVR_ATmega323__)
-#  include <avr/iom323.h>
-#elif defined (__AVR_ATmega324P__) || defined (__AVR_ATmega324A__)
-#  include <avr/iom324.h>
-#elif defined (__AVR_ATmega324PA__)
-#  include <avr/iom324pa.h>
-#elif defined (__AVR_ATmega325__)
-#  include <avr/iom325.h>
-#elif defined (__AVR_ATmega325P__)
-#  include <avr/iom325.h>
-#elif defined (__AVR_ATmega3250__)
-#  include <avr/iom3250.h>
-#elif defined (__AVR_ATmega3250P__)
-#  include <avr/iom3250.h>
-#elif defined (__AVR_ATmega328P__) || defined (__AVR_ATmega328__)
-#  include <avr/iom328p.h>
-#elif defined (__AVR_ATmega329__)
-#  include <avr/iom329.h>
-#elif defined (__AVR_ATmega329P__) || defined (__AVR_ATmega329PA__)
-#  include <avr/iom329.h>
-#elif defined (__AVR_ATmega3290__)
-#  include <avr/iom3290.h>
-#elif defined (__AVR_ATmega3290P__)
-#  include <avr/iom3290.h>
-#elif defined (__AVR_ATmega32HVB__)
-#  include <avr/iom32hvb.h>
-#elif defined (__AVR_ATmega406__)
-#  include <avr/iom406.h>
-#elif defined (__AVR_ATmega16__)
-#  include <avr/iom16.h>
-#elif defined (__AVR_ATmega16A__)
-#  include <avr/iom16a.h>
-#elif defined (__AVR_ATmega161__)
-#  include <avr/iom161.h>
-#elif defined (__AVR_ATmega162__)
-#  include <avr/iom162.h>
-#elif defined (__AVR_ATmega163__)
-#  include <avr/iom163.h>
-#elif defined (__AVR_ATmega164P__) || defined (__AVR_ATmega164A__)
-#  include <avr/iom164.h>
-#elif defined (__AVR_ATmega165__) || defined (__AVR_ATmega165A__)
-#  include <avr/iom165.h>
-#elif defined (__AVR_ATmega165P__)
-#  include <avr/iom165p.h>
-#elif defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__)
-#  include <avr/iom168.h>
-#elif defined (__AVR_ATmega168P__)
-#  include <avr/iom168p.h>
-#elif defined (__AVR_ATmega169__) || defined (__AVR_ATmega169A__)
-#  include <avr/iom169.h>
-#elif defined (__AVR_ATmega169P__)
-#  include <avr/iom169p.h>
-#elif defined (__AVR_ATmega169PA__)
-#  include <avr/iom169pa.h>
-#elif defined (__AVR_ATmega8HVA__)
-#  include <avr/iom8hva.h>
-#elif defined (__AVR_ATmega16HVA__)
-#  include <avr/iom16hva.h>
-#elif defined (__AVR_ATmega16HVA2__)
-#  include <avr/iom16hva2.h>
-#elif defined (__AVR_ATmega16HVB__)
-#  include <avr/iom16hvb.h>
-#elif defined (__AVR_ATmega8__)
-#  include <avr/iom8.h>
-#elif defined (__AVR_ATmega48__) || defined (__AVR_ATmega48A__)
-#  include <avr/iom48.h>
-#elif defined (__AVR_ATmega48P__)
-#  include <avr/iom48p.h>
-#elif defined (__AVR_ATmega88__) || defined (__AVR_ATmega88A__)
-#  include <avr/iom88.h>
-#elif defined (__AVR_ATmega88P__)
-#  include <avr/iom88p.h>
-#elif defined (__AVR_ATmega88PA__)
-#  include <avr/iom88pa.h>
-#elif defined (__AVR_ATmega8515__)
-#  include <avr/iom8515.h>
-#elif defined (__AVR_ATmega8535__)
-#  include <avr/iom8535.h>
-#elif defined (__AVR_AT90S8535__)
-#  include <avr/io8535.h>
-#elif defined (__AVR_AT90C8534__)
-#  include <avr/io8534.h>
-#elif defined (__AVR_AT90S8515__)
-#  include <avr/io8515.h>
-#elif defined (__AVR_AT90S4434__)
-#  include <avr/io4434.h>
-#elif defined (__AVR_AT90S4433__)
-#  include <avr/io4433.h>
-#elif defined (__AVR_AT90S4414__)
-#  include <avr/io4414.h>
-#elif defined (__AVR_ATtiny22__)
-#  include <avr/iotn22.h>
-#elif defined (__AVR_ATtiny26__)
-#  include <avr/iotn26.h>
-#elif defined (__AVR_AT90S2343__)
-#  include <avr/io2343.h>
-#elif defined (__AVR_AT90S2333__)
-#  include <avr/io2333.h>
-#elif defined (__AVR_AT90S2323__)
-#  include <avr/io2323.h>
-#elif defined (__AVR_AT90S2313__)
-#  include <avr/io2313.h>
-#elif defined (__AVR_ATtiny2313__)
-#  include <avr/iotn2313.h>
-#elif defined (__AVR_ATtiny2313A__)
-#  include <avr/iotn2313a.h>
-#elif defined (__AVR_ATtiny13__)
-#  include <avr/iotn13.h>
-#elif defined (__AVR_ATtiny13A__)
-#  include <avr/iotn13a.h>
-#elif defined (__AVR_ATtiny25__)
-#  include <avr/iotn25.h>
-#elif defined (__AVR_ATtiny4313__)
-#  include <avr/iotn4313.h>
-#elif defined (__AVR_ATtiny45__)
-#  include <avr/iotn45.h>
-#elif defined (__AVR_ATtiny85__)
-#  include <avr/iotn85.h>
-#elif defined (__AVR_ATtiny24__)
-#  include <avr/iotn24.h>
-#elif defined (__AVR_ATtiny24A__)
-#  include <avr/iotn24a.h>
-#elif defined (__AVR_ATtiny44__)
-#  include <avr/iotn44.h>
-#elif defined (__AVR_ATtiny44A__)
-#  include <avr/iotn44a.h>
-#elif defined (__AVR_ATtiny84__)
-#  include <avr/iotn84.h>
-#elif defined (__AVR_ATtiny261__)
-#  include <avr/iotn261.h>
-#elif defined (__AVR_ATtiny261A__)
-#  include <avr/iotn261a.h>
-#elif defined (__AVR_ATtiny461__)
-#  include <avr/iotn461.h>
-#elif defined (__AVR_ATtiny461A__)
-#  include <avr/iotn461a.h>
-#elif defined (__AVR_ATtiny861__)
-#  include <avr/iotn861.h>
-#elif defined (__AVR_ATtiny861A__)
-#  include <avr/iotn861a.h>
-#elif defined (__AVR_ATtiny43U__)
-#  include <avr/iotn43u.h>
-#elif defined (__AVR_ATtiny48__)
-#  include <avr/iotn48.h>
-#elif defined (__AVR_ATtiny88__)
-#  include <avr/iotn88.h>
-#elif defined (__AVR_ATtiny87__)
-#  include <avr/iotn87.h>
-#elif defined (__AVR_ATtiny167__)
-#  include <avr/iotn167.h>
-#elif defined (__AVR_AT90SCR100__)
-#  include <avr/io90scr100.h>
-#elif defined (__AVR_ATxmega16A4__)
-#  include <avr/iox16a4.h>
-#elif defined (__AVR_ATxmega16D4__)
-#  include <avr/iox16d4.h>
-#elif defined (__AVR_ATxmega32A4__)
-#  include <avr/iox32a4.h>
-#elif defined (__AVR_ATxmega32D4__)
-#  include <avr/iox32d4.h>
-#elif defined (__AVR_ATxmega64A1__)
-#  include <avr/iox64a1.h>
-#elif defined (__AVR_ATxmega64A3__)
-#  include <avr/iox64a3.h>
-#elif defined (__AVR_ATxmega64D3__)
-#  include <avr/iox64d3.h>
-#elif defined (__AVR_ATxmega128A1__)
-#  include <avr/iox128a1.h>
-#elif defined (__AVR_ATxmega128A3__)
-#  include <avr/iox128a3.h>
-#elif defined (__AVR_ATxmega128D3__)
-#  include <avr/iox128d3.h>
-#elif defined (__AVR_ATxmega192A3__)
-#  include <avr/iox192a3.h>
-#elif defined (__AVR_ATxmega192D3__)
-#  include <avr/iox192d3.h>
-#elif defined (__AVR_ATxmega256A3__)
-#  include <avr/iox256a3.h>
-#elif defined (__AVR_ATxmega256A3B__)
-#  include <avr/iox256a3b.h>
-#elif defined (__AVR_ATxmega256D3__)
-#  include <avr/iox256d3.h>
-#elif defined (__AVR_ATA6289__)
-#  include <avr/ioa6289.h>
-/* avr1: the following only supported for assembler programs */
-#elif defined (__AVR_ATtiny28__)
-#  include <avr/iotn28.h>
-#elif defined (__AVR_AT90S1200__)
-#  include <avr/io1200.h>
-#elif defined (__AVR_ATtiny15__)
-#  include <avr/iotn15.h>
-#elif defined (__AVR_ATtiny12__)
-#  include <avr/iotn12.h>
-#elif defined (__AVR_ATtiny11__)
-#  include <avr/iotn11.h>
-#else
-#  if !defined(__COMPILING_AVR_LIBC__)
-#    warning "device type not defined"
-#  endif
-#endif
-
-#include <avr/portpins.h>
-
-#include <avr/common.h>
-
-#include <avr/version.h>
-
-/* Include fuse.h after individual IO header files. */
-#include <avr/fuse.h>
-
-/* Include lock.h after individual IO header files. */
-#include <avr/lock.h>
-
-/** @} */
-#endif /* _AVR_IO_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io1200.h b/cpukit/score/cpu/avr/avr/io1200.h
deleted file mode 100644
index ae2aa17..0000000
--- a/cpukit/score/cpu/avr/avr/io1200.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/**
- * @file avr/io1200.h
- *
- * @brief Definitions for AT90S1200
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO1200_H_
-#define _AVR_IO1200_H_ 1
-
-/**
- *  @defgroup Avr_io1200 AT90S1200 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io1200.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#ifndef __ASSEMBLER__
-#  warning "MCU not supported by the C compiler"
-#endif
-
-/* I/O registers */
-
-/* 0x00..0x07 reserved */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* 0x09..0x0F reserved */
-
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* 0x13..0x15 reserved */
-
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* 0x19..0x1B reserved */
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* 0x1F..0x20 reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22..0x31 reserved */
-
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* 0x3A reserved */
-
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3E reserved */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(3)
-#define SIG_COMPARATOR			_VECTOR(3)
-
-#define _VECTORS_SIZE 8
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT0	6
-
-/* TIMSK */
-#define TOIE0	1
-
-/* TIFR */
-#define TOV0	1
-
-/* MCUCR */
-#define SE	5
-#define SM	4
-#define ISC01	1
-#define ISC00	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* WDTCR */
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* EECR */
-#undef EEMWE
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB1 = AIN1
-   PB0 = AIN0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTD */
-#define PD6	6
-#define PD5	5
-#define PD4	4
-#define PD3	3
-#define PD2	2
-#define PD1	1
-#define PD0	0
-
-/* DDRD */
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* ACSR */
-#define ACD	7
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIS1	1
-#define ACIS0	0
-
-/* EEPROM Control Register */
-#define EERIE	3
-#define EEMWE	2
-#define EEWE	1
-#define EERE	0
-
-#undef ZH
-
-/* Last memory addresses */
-#define RAMEND		0x1F
-#define XRAMEND		0x0
-#define E2END		0x3F
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_RCEN  (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x90
-#define SIGNATURE_2 0x01
-
-
-/**@}*/
-#endif  /* _AVR_IO1200_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2313.h b/cpukit/score/cpu/avr/avr/io2313.h
deleted file mode 100644
index 1ca95a6..0000000
--- a/cpukit/score/cpu/avr/avr/io2313.h
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2313.h - definitions for AT90S2313 */
-
-#ifndef _AVR_IO2313_H_
-#define _AVR_IO2313_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2313.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Output Compare Register 1 */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3D SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT1_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP1_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF1_vect		_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(7)
-#define SIG_UART_RECV			_VECTOR(7)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(8)
-#define SIG_UART_DATA			_VECTOR(8)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(9)
-#define SIG_UART_TRANS			_VECTOR(9)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(10)
-#define SIG_COMPARATOR			_VECTOR(10)
-
-#define _VECTORS_SIZE 22
-
-/*
- *  The Register Bit names are represented by their bit number (0-7).
- */     
- 
-/* General Interrupt MaSK register */
-#define    INT1    7
-#define    INT0    6
- 
-/* General Interrupt Flag Register */
-#define    INTF1   7
-#define    INTF0   6
- 
-/* Timer/Counter Interrupt MaSK register */                 
-#define    TOIE1   7
-#define    OCIE1A  6
-#define    TICIE   3 /* old name */ 
-#define    TICIE1  3
-#define    TOIE0   1
- 
-/* Timer/Counter Interrupt Flag register */                   
-#define    TOV1    7
-#define    OCF1A   6
-#define    ICF1    3
-#define    TOV0    1
- 
-/* MCU general Control Register */ 
-#define    SE      5
-#define    SM      4
-#define    ISC11   3
-#define    ISC10   2
-#define    ISC01   1
-#define    ISC00   0
- 
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
- 
-/* Timer/Counter 1 Control Register */
-#define    COM1A1  7
-#define    COM1A0  6
-#define    PWM11   1
-#define    PWM10   0
- 
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1   7
-#define    ICES1   6
-#define    CTC1    3
-#define    CS12    2
-#define    CS11    1
-#define    CS10    0
-                        
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
- 
-/* EEPROM Control Register */
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
- 
-/* Data Register, Port B */  
-#define    PB7     7
-#define    PB6     6
-#define    PB5     5
-#define    PB4     4
-#define    PB3     3
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
- 
-/* Data Direction Register, Port B */
-#define    DDB7    7
-#define    DDB6    6
-#define    DDB5    5
-#define    DDB4    4
-#define    DDB3    3
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
- 
-/* Input Pins, Port B */
-#define    PINB7   7
-#define    PINB6   6
-#define    PINB5   5
-#define    PINB4   4
-#define    PINB3   3
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
- 
-/* Data Register, Port D */
-#define    PD6     6
-#define    PD5     5
-#define    PD4     4
-#define    PD3     3
-#define    PD2     2
-#define    PD1     1
-#define    PD0     0
- 
-/* Data Direction Register, Port D */
-#define    DDD6    6
-#define    DDD5    5
-#define    DDD4    4
-#define    DDD3    3
-#define    DDD2    2
-#define    DDD1    1
-#define    DDD0    0
- 
-/* Input Pins, Port D */
-#define    PIND6   6
-#define    PIND5   5
-#define    PIND4   4
-#define    PIND3   3
-#define    PIND2   2
-#define    PIND1   1
-#define    PIND0   0
- 
-/* UART Status Register */
-#define    RXC     7
-#define    TXC     6
-#define    UDRE    5
-#define    FE      4
-#define    DOR     3
- 
-/* UART Control Register */
-#define    RXCIE   7
-#define    TXCIE   6
-#define    UDRIE   5
-#define    RXEN    4
-#define    TXEN    3
-#define    CHR9    2
-#define    RXB8    1
-#define    TXB8    0
-       
-/* Analog Comparator Control and Status Register */ 
-#define    ACD     7
-#define    ACO     5
-#define    ACI     4
-#define    ACIE    3
-#define    ACIC    2
-#define    ACIS1   1
-#define    ACIS0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-       
-/* Constants */ 
-#define    RAMEND     0xDF
-#define    XRAMEND    RAMEND
-#define    E2END      0x7F
-#define    E2PAGESIZE 0
-#define    FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_FSTRT (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x01
-
-
-#endif  /* _AVR_IO2313_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2323.h b/cpukit/score/cpu/avr/avr/io2323.h
deleted file mode 100644
index 2bfe717..0000000
--- a/cpukit/score/cpu/avr/avr/io2323.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2323.h - definitions for AT90S2323 */
-
-#ifndef _AVR_IO2323_H_
-#define _AVR_IO2323_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2323.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-#define _VECTORS_SIZE 6
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt MaSK register */
-#define    INT0    6
-#define    INTF0   6
-
-/* General Interrupt Flag Register */
-#define    TOIE0   1
-#define    TOV0    1
-
-/* MCU general Control Register */
-#define    SE      5
-#define    SM      4
-#define    ISC01   1
-#define    ISC00   0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
-
-/*
-   PB2 = SCK/T0
-   PB1 = MISO/INT0
-   PB0 = MOSI
- */
-
-/* Data Register, Port B */
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
-
-/* Data Direction Register, Port B */
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
-
-/* Input Pins, Port B */
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-
-/* Constants */
-#define RAMEND     0xDF
-#define XRAMEND    RAMEND
-#define E2END      0x7F
-#define E2PAGESIZE 0
-#define FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_FSTRT (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x02
-
-
-#endif  /* _AVR_IO2323_H_ */
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x02
-
diff --git a/cpukit/score/cpu/avr/avr/io2333.h b/cpukit/score/cpu/avr/avr/io2333.h
deleted file mode 100644
index 63c7fab..0000000
--- a/cpukit/score/cpu/avr/avr/io2333.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io2333.h - definitions for AT90S2333 */
-
-#ifndef _AVR_IO2333_H_
-#define _AVR_IO2333_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2333.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* UART Baud Rate Register high */
-#define UBRRH	_SFR_IO8(0x03)
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control/Status Registers */
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(7)
-#define SIG_SPI				_VECTOR(7)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(8)
-#define SIG_UART_RECV			_VECTOR(8)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(9)
-#define SIG_UART_DATA			_VECTOR(9)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(10)
-#define SIG_UART_TRANS			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(12)
-#define SIG_EEPROM_READY		_VECTOR(12)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(13)
-#define SIG_COMPARATOR			_VECTOR(13)
-
-#define _VECTORS_SIZE 28
-/** @} */
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    WDRF        3
-#define    BORF        2
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1       7
-#define    OCIE1       6
-#define    TICIE1      3
-#define    TOIE0       1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1         6
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM11        7
-#define    COM10        6
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* SPI Control Register */
-#define    SPIE       7
-#define    SPE        6
-#define    DORD       5
-#define    MSTR       4
-#define    CPOL       3
-#define    CPHA       2
-#define    SPR1       1
-#define    SPR0       0
-
-/* SPI Status Register */
-#define    SPIF       7
-#define    WCOL       6
-
-/* UART Status Register */
-#define    RXC        7
-#define    TXC        6
-#define    UDRE       5
-#define    FE         4
-#define    DOR        3
-#define    MPCM       0
-
-/* UART Control Register */
-#define    RXCIE      7
-#define    TXCIE      6
-#define    UDRIE      5
-#define    RXEN       4
-#define    TXEN       3
-#define    CHR9       2
-#define    RXB8       1
-#define    TXB8       0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD        7
-#define    AINBG      6
-#define    ACO        5
-#define    ACI        4
-#define    ACIE       3
-#define    ACIC       2
-#define    ACIS1      1
-#define    ACIS0      0
-
-/* ADC MUX */
-#define    ACDBG      6
-#define    MUX2       2
-#define    MUX1       1
-#define    MUX0       0
-
-/* ADC Control and Status Register */
-#define    ADEN       7
-#define    ADSC       6
-#define    ADFR       5
-#define    ADIF       4
-#define    ADIE       3
-#define    ADPS2      2
-#define    ADPS1      1
-#define    ADPS0      0
-
-/* Data Register, Port B */
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* EEPROM Control Register */
-#define    EERIE     3
-#define    EEMWE     2
-#define    EEWE      1
-#define    EERE      0
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define    RAMEND   0xDF    /*Last On-Chip SRAM location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x7F
-#define    FLASHEND 0x7FF
-/** @} */
-
-#endif /* _AVR_IO2333_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2343.h b/cpukit/score/cpu/avr/avr/io2343.h
deleted file mode 100644
index bee4ad4..0000000
--- a/cpukit/score/cpu/avr/avr/io2343.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
- * @file avr/io2343.h
- *
- * @brief Definitions for AT90S2343
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO2343_H_
-#define _AVR_IO2343_H_ 1
-
-/**
- *  @defgroup Avr_io2343 AT90S2343 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io2343.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF0_vect		_VECTOR(2)
-#define SIG_OVERFLOW0			_VECTOR(2)
-
-#define _VECTORS_SIZE 6
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
- */
-
-/* General Interrupt MaSK register */
-#define    INT0    6
-#define    INTF0   6
-
-/* General Interrupt Flag Register */
-#define    TOIE0   1
-#define    TOV0    1
-
-/* MCU general Control Register */
-#define    SE      5
-#define    SM      4
-#define    ISC01   1
-#define    ISC00   0
-
-/* MCU Status Register */
-#define PORF    0
-#define EXTRF   1
-
-/* Timer/Counter 0 Control Register */
-#define    CS02    2
-#define    CS01    1
-#define    CS00    0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE   4
-#define    WDE     3
-#define    WDP2    2
-#define    WDP1    1
-#define    WDP0    0
-
-/*
-   PB3 = CLOCK
-   PB2 = SCK/T0
-   PB1 = MISO/INT0
-   PB0 = MOSI
- */
-
-/* Data Register, Port B */
-#define    PB4     4
-#define    PB3     3
-#define    PB2     2
-#define    PB1     1
-#define    PB0     0
-
-/* Data Direction Register, Port B */
-#define    DDB4    4
-#define    DDB3    3
-#define    DDB2    2
-#define    DDB1    1
-#define    DDB0    0
-
-/* Input Pins, Port B */
-#define    PINB4   4
-#define    PINB3   3
-#define    PINB2   2
-#define    PINB1   1
-#define    PINB0   0
-
-/* EEPROM Control Register */
-#define    EERIE   3
-#define    EEMWE   2
-#define    EEWE    1
-#define    EERE    0
-
-/* Constants */
-#define RAMEND     0xDF
-#define XRAMEND    RAMEND
-#define E2END      0x7F
-#define E2PAGESIZE 0
-#define FLASHEND   0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_RCEN (unsigned char)~_BV(0)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x03
-
-
-/**@}*/
-#endif /* _AVR_IO2343_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u32x.h b/cpukit/score/cpu/avr/avr/io43u32x.h
deleted file mode 100644
index ed36ff1..0000000
--- a/cpukit/score/cpu/avr/avr/io43u32x.h
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- * @file avr/io43u32x.h
- *
- * @brief Definitions for AT43USB32x
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2003,2005 Keith Gudger
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO43U32X_H_
-#define _AVR_IO43U32X_H_ 1
-
-/**
- *  @defgroup Avr_io43u32x AT43USB32x Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io43u32x.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* Input Pins, Port E */                  // new port for 43324/6
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C..0x1F reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt Mask register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* Interrupt vectors */
-
-#define SIG_INTERRUPT0		_VECTOR(1)
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_TIMER1_CAPT1	_VECTOR(3)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI				_VECTOR(8)
-#define SIG_UART_RECV		_VECTOR(9)
-#define SIG_UART_DATA    	_VECTOR(10)
-#define SIG_UART_TRANS     	_VECTOR(11)
-#define SIG_USB_INT         _VECTOR(12)
-
-#define _VECTORS_SIZE 52
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TICIE1       3
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TOIE1        7
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag Register */
-#define    ICF1         3
-#define    OCF1A        6
-#define    OCF1B        5
-#define    TOV1         7
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port E */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-
-/* Data Direction Register, Port E */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Input Pins, Port E */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Constants */
-#define    RAMEND   0x025F     /*Last On-Chip SRAM Location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x0000
-
-/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory,
-   but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now...  */
-#define    FLASHEND 0x0FFFF
-
-/**@}*/
-#endif /* _AVR_43USB32X_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u35x.h b/cpukit/score/cpu/avr/avr/io43u35x.h
deleted file mode 100644
index 66a06d8..0000000
--- a/cpukit/score/cpu/avr/avr/io43u35x.h
+++ /dev/null
@@ -1,440 +0,0 @@
-/* Copyright (c) 2003,2005 Keith Gudger
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io43u35x.h - definitions for AT43USB35x */
-
-#ifndef _AVR_IO43U35X_H_
-#define _AVR_IO43U35X_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io43u35x.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @name I/O Registers
- * 
- */
-/**@{**/
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x02)
-#endif
-#define ADCW  	_SFR_IO16(0x02)
-#define ADCL	_SFR_IO8(0x02)
-#define ADCH	_SFR_IO8(0x03)
-
-/* ADC Control and status register */
-#define ADCSR	_SFR_IO8(0x07)
-
-/* ADC Multiplexer select */
-#define ADMUX	_SFR_IO8(0x08)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* Input Pins, Port F */
-#define PINF	_SFR_IO8(0x04)
-
-/* Data Direction Register, Port F */
-#define DDRF    _SFR_IO8(0x05)
-
-/* Data Register, Port F */
-#define PORTF   _SFR_IO8(0x06)
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC    _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC    _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C..0x1F reserved */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt Mask register */
-#define GIMSK	_SFR_IO8(0x3B)
-/** @} */
-
-/**
- * @name Interrupt Vectors
- * 
- */
-/**@{**/
-#define SIG_INTERRUPT0		_VECTOR(1)  /* suspend/resume */
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_TIMER1_CAPT1	_VECTOR(3)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI				_VECTOR(8)
-/* 9, 10: reserved */
-#define SIG_ADC         	_VECTOR(11)
-#define SIG_USB_INT         _VECTOR(12)
-
-#define _VECTORS_SIZE 52
-/** @} */
-
-/*
- * The Register Bit names are represented by their bit number (0-7).
- */
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TICIE1       3
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TOIE1        7
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag Register */
-#define    ICF1         3
-#define    OCF1A        6
-#define    OCF1B        5
-#define    TOV1         7
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port F */
-#define    PF3          3
-#define    PF2          2
-#define    PF1          1
-#define    PF0          0
-
-/* Data Direction Register, Port F */
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-
-/* Input Pins, Port F */
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* ADC Multiplexer select */
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0  
-
-/**
- * @name Constants
- * 
- */
-/**@{**/
-#define    RAMEND   0x045F     /*Last On-Chip SRAM Location*/
-#define    XRAMEND  RAMEND
-#define    E2END    0x0000
-#define    FLASHEND 0x5FFF
-/** @} */
-
-#endif /* _AVR_43USB355_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4414.h b/cpukit/score/cpu/avr/avr/io4414.h
deleted file mode 100644
index 96c4000..0000000
--- a/cpukit/score/cpu/avr/avr/io4414.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90S4414
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io4414.h - definitions for AT90S4414 */
-
-#ifndef _AVR_IO4414_H_
-#define _AVR_IO4414_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4414.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io4414 AT90S4414 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR   _SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C..0x3D SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Compare MatchB */
-#define TIMER1_COMPB_vect		_VECTOR(5)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW1			_VECTOR(6)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(7)
-#define SIG_OVERFLOW0			_VECTOR(7)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(8)
-#define SIG_SPI				_VECTOR(8)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(9)
-#define SIG_UART_RECV			_VECTOR(9)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(10)
-#define SIG_UART_DATA			_VECTOR(10)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(11)
-#define SIG_UART_TRANS			_VECTOR(11)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-#define _VECTORS_SIZE 26
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* General Interrupt MaSK register */
-#define    INT1         7
-#define    INT0         6
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1        7
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TICIE1       3
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1A        6
-#define    OCF1B        5
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants        */
-#define RAMEND       0x15F    /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0xFF
-#define E2PAGESIZE   0
-#define FLASHEND     0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN (unsigned char)~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT (unsigned char)~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x01
-
-/** @} */
-
-#endif /* _AVR_IO4414_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4433.h b/cpukit/score/cpu/avr/avr/io4433.h
deleted file mode 100644
index 62cbb00..0000000
--- a/cpukit/score/cpu/avr/avr/io4433.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/**
- * @file avr/io4433.h
- *
- * @brief Definitions for AT90S4433
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2002, Marek Michalkiewicz
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO4433_H_
-#define _AVR_IO4433_H_ 1
-
-/**
- *  @defgroup Avr_io4433 AT90S4433 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4433.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* UART Baud Rate Register high */
-#define UBRRH	_SFR_IO8(0x03)
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control/Status Registers */
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1	_SFR_IO16(0x2A)
-#define OCR1L	_SFR_IO8(0x2A)
-#define OCR1H	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match */
-#define TIMER1_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW1			_VECTOR(5)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW0			_VECTOR(6)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(7)
-#define SIG_SPI				_VECTOR(7)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(8)
-#define SIG_UART_RECV			_VECTOR(8)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(9)
-#define SIG_UART_DATA			_VECTOR(9)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(10)
-#define SIG_UART_TRANS			_VECTOR(10)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(11)
-#define SIG_ADC				_VECTOR(11)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(12)
-#define SIG_EEPROM_READY		_VECTOR(12)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(13)
-#define SIG_COMPARATOR			_VECTOR(13)
-
-#define _VECTORS_SIZE 28
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    WDRF        3
-#define    BORF        2
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1       7
-#define    OCIE1       6
-#define    TICIE1      3
-#define    TOIE0       1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1         6
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM11        7
-#define    COM10        6
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* SPI Control Register */
-#define    SPIE       7
-#define    SPE        6
-#define    DORD       5
-#define    MSTR       4
-#define    CPOL       3
-#define    CPHA       2
-#define    SPR1       1
-#define    SPR0       0
-
-/* SPI Status Register */
-#define    SPIF       7
-#define    WCOL       6
-
-/* UART Status Register */
-#define    RXC        7
-#define    TXC        6
-#define    UDRE       5
-#define    FE         4
-#define    DOR        3
-#define    MPCM       0
-
-/* UART Control Register */
-#define    RXCIE      7
-#define    TXCIE      6
-#define    UDRIE      5
-#define    RXEN       4
-#define    TXEN       3
-#define    CHR9       2
-#define    RXB8       1
-#define    TXB8       0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD        7
-#define    AINBG      6
-#define    ACO        5
-#define    ACI        4
-#define    ACIE       3
-#define    ACIC       2
-#define    ACIS1      1
-#define    ACIS0      0
-
-/* ADC MUX */
-#define    ACDBG      6
-#define    MUX2       2
-#define    MUX1       1
-#define    MUX0       0
-
-/* ADC Control and Status Register */
-#define    ADEN       7
-#define    ADSC       6
-#define    ADFR       5
-#define    ADIF       4
-#define    ADIE       3
-#define    ADPS2      2
-#define    ADPS1      1
-#define    ADPS0      0
-
-/* Data Register, Port B */
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* EEPROM Control Register */
-#define    EERIE     3
-#define    EEMWE     2
-#define    EEWE      1
-#define    EERE      0
-
-/* Constants */
-#define RAMEND     0xDF    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0xFF
-#define E2PAGESIZE 0
-#define FLASHEND   0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)
-#define FUSE_BODEN (unsigned char)~_BV(3)
-#define FUSE_BODLEVEL (unsigned char)~_BV(4)
-#define FUSE_SPIEN (unsigned char)~_BV(5)
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x92
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IO4433_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4434.h b/cpukit/score/cpu/avr/avr/io4434.h
deleted file mode 100644
index 72bc726..0000000
--- a/cpukit/score/cpu/avr/avr/io4434.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/**
- * @file avr/io4434.h
- *
- * @brief Definitions for AT90S4434
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO4434_H_
-#define _AVR_IO4434_H_ 1
-
-/**
- *  @defgroup Avr_io4434 AT90S4434 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io4434.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR  	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO8(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Asynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control Register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2       7
-#define    TOIE2       6
-#define    TICIE1      5
-#define    OCIE1A      4
-#define    OCIE1B      3
-#define    TOIE1       2
-#define    TOIE0       0
-
-/* Timer/Counter Interrupt Flag register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SE           6
-#define    SM1          5
-#define    SM0          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control Register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Asynchronous mode Status Register */
-#define    AS2          3
-#define    TCN2UB       2
-#define    OCR2UB       1
-#define    TCR2UB       0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7      7
-#define    PA6      6
-#define    PA5      5
-#define    PA4      4
-#define    PA3      3
-#define    PA2      2
-#define    PA1      1
-#define    PA0      0
-
-/* Data Direction Register, Port A */
-#define    DDA7     7
-#define    DDA6     6
-#define    DDA5     5
-#define    DDA4     4
-#define    DDA3     3
-#define    DDA2     2
-#define    DDA1     1
-#define    DDA0     0
-
-/* Input Pins, Port A */
-#define    PINA7    7
-#define    PINA6    6
-#define    PINA5    5
-#define    PINA4    4
-#define    PINA3    3
-#define    PINA2    2
-#define    PINA1    1
-#define    PINA0    0
-
-/* Data Register, Port B */
-#define    PB7      7
-#define    PB6      6
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB7     7
-#define    DDB6     6
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB7    7
-#define    PINB6    6
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC7      7
-#define    PC6      6
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC7     7
-#define    DDC6     6
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC7    7
-#define    PINC6    6
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* SPI Control Register */
-#define    SPIE     7
-#define    SPE     6
-#define    DORD     5
-#define    MSTR     4
-#define    CPOL     3
-#define    CPHA     2
-#define    SPR1     1
-#define    SPR0     0
-
-/* SPI Status Register */
-#define    SPIF     7
-#define    WCOL     6
-
-/* UART Status Register */
-#define    RXC      7
-#define    TXC      6
-#define    UDRE     5
-#define    FE       4
-#define    DOR      3
-
-/* UART Control Register */
-#define    RXCIE    7
-#define    TXCIE    6
-#define    UDRIE    5
-#define    RXEN     4
-#define    TXEN     3
-#define    CHR9     2
-#define    RXB8     1
-#define    TXB8     0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD      7
-#define    ACO      5
-#define    ACI      4
-#define    ACIE     3
-#define    ACIC     2
-#define    ACIS1    1
-#define    ACIS0    0
-
-/* ADC MUX */
-#define    MUX2     2
-#define    MUX1     1
-#define    MUX0     0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0
-
-/* EEPROM Control Register */
-#define    EERIE    3
-#define    EEMWE    2
-#define    EEWE     1
-#define    EERE     0
-
-/* Constants */
-#define RAMEND     0x15F    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0xFF
-#define E2PAGESIZE 0
-#define FLASHEND   0xFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN ~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT ~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IO4434_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io76c711.h b/cpukit/score/cpu/avr/avr/io76c711.h
deleted file mode 100644
index e0c68e2..0000000
--- a/cpukit/score/cpu/avr/avr/io76c711.h
+++ /dev/null
@@ -1,511 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT76C711
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io76c711.h - definitions for AT76C711 */
-
-#ifndef _AVR_IO76C711_H_
-#define _AVR_IO76C711_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io76c711.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io76c711 AT76C711 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* 0x00-0x0C reserved */
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Peripheral Enable Register */
-#define PERIPHEN _SFR_IO8(0x13)
-
-/* Clock Control Register */
-#define CLK_CNTR _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* Port A */
-#define PINA	_SFR_IO8(0x19)
-#define DDRA	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* 0x1C-0x1F reserved */
-
-#define IRDAMOD	_SFR_IO8(0x20)
-
-#define WDTCR	_SFR_IO8(0x21)
-
-/* 0x22-0x25 reserved */
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* 0x30 reserved */
-
-/* Timer 0 */
-#define PRELD	_SFR_IO8(0x31)
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUSR	_SFR_IO8(0x34)
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TIFR	_SFR_IO8(0x36)
-#define TIMSK	_SFR_IO8(0x37)
-
-/* 0x38 reserved */
-
-#define EIMSK	_SFR_IO8(0x39)
-
-/* 0x3A-0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_SUSPEND_RESUME	_VECTOR(1)
-#define SIG_INTERRUPT0		_VECTOR(2)
-#define SIG_INPUT_CAPTURE1	_VECTOR(3)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(5)
-#define SIG_OVERFLOW1		_VECTOR(6)
-#define SIG_OVERFLOW0		_VECTOR(7)
-#define SIG_SPI			_VECTOR(8)
-#define SIG_TDMAC		_VECTOR(9)
-#define SIG_UART0		_VECTOR(10)
-#define SIG_RDMAC		_VECTOR(11)
-#define SIG_USB_HW		_VECTOR(12)
-#define SIG_UART1		_VECTOR(13)
-#define SIG_INTERRUPT1		_VECTOR(14)
-
-#define _VECTORS_SIZE 60
-
-/* Bit numbers */
-
-/* EIMSK */
-/* bits 7-4 reserved */
-#define POL1	3
-#define POL0	2
-#define INT1	1
-#define INT0	0
-
-/* TIMSK */
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B	5
-/* bit 4 reserved */
-#define TICIE1	3
-/* bit 2 reserved */
-#define TOIE0	1
-/* bit 0 reserved */
-
-/* TIFR */
-#define TOV1	7
-#define OCF1A	6
-#define OCF1B	5
-/* bit 4 reserved */
-#define ICF1	3
-/* bit 2 reserved */
-#define TOV0	1
-/* bit 0 reserved */
-
-/* MCUCR */
-/* bits 7-6 reserved */
-#define SE	5
-#define SM1	4
-#define SM0	3
-/* bits 2-0 reserved */
-
-/* MCUSR */
-/* bits 7-2 reserved */
-#define EXTRF	1
-#define PORF	0
-
-/* TCCR0 */
-/* bits 7-6 reserved */
-#define COM01	5
-#define COM00	4
-#define CTC0	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-/* bits 3-0 reserved */
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bits 5-4 reserved */
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* IRDAMOD */
-/* bits 7-3 reserved */
-#define POL	2
-#define MODE	1
-#define EN	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB2 = ICP
-   PB1 = T1
-   PB0 = T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTC */
-/* bits 7-4 reserved */
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/*
-   PD7 = INT1 / OC1B
-   PD6 = INT0 / OC1A
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* CLK_CNTR */
-/* bits 7-5 reserved */
-#define UOSC	4
-#define UCK	3
-#define IRCK	2
-/* bits 1-0 reserved */
-
-/* PERIPHEN */
-/* bits 7-3 reserved */
-#define IRDA	2
-#define UART	1
-#define USB	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-/* bits 5-0 reserved */
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */
-
-/* UART */
-#define UART0_BASE 0x2020
-#define UART1_BASE 0x2030
-/* offsets from the base address */
-#define US_RHR		0x00
-#define US_THR		0x00
-#define US_IER		0x01
-#define US_FCR		0x02
-#define US_PMR		0x03
-#define US_MR		0x04
-#define US_CSR		0x05
-#define US_CR		0x06
-#define US_BL		0x07
-#define US_BM		0x08
-#define US_RTO		0x09
-#define US_TTG		0x0A
-
-/* DMA */
-#define DMA_BASE 0x2000
-/* offsets from the base address */
-#define TXTADL		0x01
-#define TXPLL		0x03
-#define TXPLM		0x04
-#define TXTPLL		0x05
-#define TXTPLM		0x06
-#define RXTADL		0x07
-#define RXTADMEN	0x08
-#define RSPLL		0x09
-#define RXPLM		0x0A
-#define RXTPLL		0x0B
-#define RXTPLM		0x0C
-#define INTCST		0x0D
-/* XXX DPORG register mentioned on page 20, but undocumented */
-
-/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */
-#define PROGRAM_MEMORY_CONTROL_BIT 0x2040
-
-/* USB */
-#define USB_BASE 0x1000
-/* offsets from the base address */
-#define FRM_NUM_H	0x0FD
-#define FRM_NUM_L	0x0FC
-#define GLB_STATE	0x0FB
-#define SPRSR		0x0FA
-#define SPRSIE		0x0F9
-#define UISR		0x0F7
-#define UIAR		0x0F5
-#define FADDR		0x0F2
-#define ENDPPGPG	0x0F1
-#define ECR0		0x0EF
-#define ECR1		0x0EE
-#define ECR2		0x0ED
-#define ECR3		0x0EC
-#define ECR4		0x0EB
-#define ECR5		0x0EA
-#define ECR6		0x0E9
-#define ECR7		0x0E8
-#define CSR0		0x0DF
-#define CSR1		0x0DE
-#define CSR2		0x0DD
-#define CSR3		0x0DC
-#define CSR4		0x0DB
-#define CSR5		0x0DA
-#define CSR6		0x0D9
-#define CSR7		0x0D8
-#define FDR0		0x0CF
-#define FDR1		0x0CE
-#define FDR2		0x0CD
-#define FDR3		0x0CC
-#define FDR4		0x0CB
-#define FDR5		0x0CA
-#define FDR6		0x0C9
-#define FDR7		0x0C8
-#define FBYTE_CNT0_L	0x0BF
-#define FBYTE_CNT1_L	0x0BE
-#define FBYTE_CNT2_L	0x0BD
-#define FBYTE_CNT3_L	0x0BC
-#define FBYTE_CNT4_L	0x0BB
-#define FBYTE_CNT5_L	0x0BA
-#define FBYTE_CNT6_L	0x0B9
-#define FBYTE_CNT7_L	0x0B8
-#define FBYTE_CNT0_H	0x0AF
-#define FBYTE_CNT1_H	0x0AE
-#define FBYTE_CNT2_H	0x0AD
-#define FBYTE_CNT3_H	0x0AC
-#define FBYTE_CNT4_H	0x0AB
-#define FBYTE_CNT5_H	0x0AA
-#define FBYTE_CNT6_H	0x0A9
-#define FBYTE_CNT7_H	0x0A8
-#define SLP_MD_EN	0x100
-#define IRQ_EN		0x101
-#define IRQ_STAT	0x102
-#define SUSP_WUP	0x103
-#define PA_EN		0x104
-#define USB_DMA_ADL	0x105
-#define USB_DMA_ADH	0x106
-#define USB_DMA_PLR	0x107
-#define USB_DMA_EAD	0x108
-#define USB_DMA_PLT	0x109
-#define USB_DMA_EN	0x10A
-
-/* Last memory addresses */
-#define RAMEND		0x07FF
-#define XRAMEND		RAMEND
-#define E2END		0
-#define FLASHEND	0x3FFF
-
-/*
-   AT76C711 data space memory map (ranges not listed are reserved):
-   0x0000 - 0x001F - AVR registers
-   0x0020 - 0x005F - AVR I/O space
-   0x0060 - 0x07FF - AVR data SRAM
-   0x1000 - 0x1FFF - USB (not all locations used)
-   0x2000 - 0x201F - DMA controller
-   0x2020 - 0x202F - UART0
-   0x2030 - 0x203F - UART1 (IRDA)
-   0x2040          - the mysterious Program Memory Control bit (???)
-   0x3000 - 0x37FF - DPRAM
-   0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
-                     AVR devices did that as well (no need to use LPM!)
- */
-
-/** @} */
-
-#endif /* _AVR_IO76C711_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8515.h b/cpukit/score/cpu/avr/avr/io8515.h
deleted file mode 100644
index 305224d..0000000
--- a/cpukit/score/cpu/avr/avr/io8515.h
+++ /dev/null
@@ -1,485 +0,0 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io8515.h - definitions for AT90S8515 */
-
-#ifndef _AVR_IO8515_H_
-#define _AVR_IO8515_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8515.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR   _SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(3)
-#define SIG_INPUT_CAPTURE1		_VECTOR(3)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(4)
-
-/* Timer/Counter1 Compare MatchB */
-#define TIMER1_COMPB_vect		_VECTOR(5)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(5)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(6)
-#define SIG_OVERFLOW1			_VECTOR(6)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(7)
-#define SIG_OVERFLOW0			_VECTOR(7)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(8)
-#define SIG_SPI				_VECTOR(8)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(9)
-#define SIG_UART_RECV			_VECTOR(9)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(10)
-#define SIG_UART_DATA			_VECTOR(10)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(11)
-#define SIG_UART_TRANS			_VECTOR(11)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(12)
-#define SIG_COMPARATOR			_VECTOR(12)
-
-#define _VECTORS_SIZE 26
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* General Interrupt MaSK register */
-#define    INT1         7
-#define    INT0         6
-
-/* General Interrupt Flag Register */
-#define    INTF1        7
-#define    INTF0        6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    TOIE1        7
-#define    OCIE1A       6
-#define    OCIE1B       5
-#define    TICIE1       3
-#define    TOIE0        1
-
-/* Timer/Counter Interrupt Flag register */
-#define    TOV1         7
-#define    OCF1A        6
-#define    OCF1B        5
-#define    ICF1         3
-#define    TOV0         1
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM           4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Direction Register, Port C */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Input Pins, Port C */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants        */
-#define RAMEND       0x25F    /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x1FF
-#define E2PAGESIZE   0
-#define FLASHEND     0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN ~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT ~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x01
-
-
-#endif /* _AVR_IO8515_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8534.h b/cpukit/score/cpu/avr/avr/io8534.h
deleted file mode 100644
index c873a71..0000000
--- a/cpukit/score/cpu/avr/avr/io8534.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90C8534
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io8534.h - definitions for AT90C8534 */
-
-#ifndef _AVR_IO8534_
-#define _AVR_IO8534_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8534.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io8534 AT90C8534 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* 0x00..0x03 reserved */
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC Multiplexer Select Register */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* 0x08..0x0F reserved */
-
-/* General Interrupt Pin Register */
-#define GIPR	_SFR_IO8(0x10)
-
-/* 0x11..0x19 reserved */
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* 0x20..0x2B reserved */
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register */
-#define TCCR1	_SFR_IO8(0x2E)
-
-/* 0x2F..0x31 reserved */
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* 0x36..0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_INTERRUPT0		_VECTOR(1)
-#define SIG_INTERRUPT1		_VECTOR(2)
-#define SIG_OVERFLOW1		_VECTOR(3)
-#define SIG_OVERFLOW0		_VECTOR(4)
-#define SIG_ADC			_VECTOR(5)
-#define SIG_EEPROM_READY	_VECTOR(6)
-
-#define _VECTORS_SIZE 14
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-
-/* GIPR */
-#define IPIN1	3
-#define IPIN0	2
-
-/* TIMSK */
-#define TOIE1	2
-#define TOIE0	0
-
-/* TIFR */
-#define TOV1	2
-#define TOV0	0
-
-/* MCUCR */
-#define SE	6
-#define SM	5
-#define ISC1	2
-#define ISC0	0
-
-/* TCCR0 */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR1 */
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Last memory addresses */
-#define RAMEND		0x15F
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define FLASHEND	0x1FFF
-
-/** @} */
-
-#endif /* _AVR_IO8534_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8535.h b/cpukit/score/cpu/avr/avr/io8535.h
deleted file mode 100644
index cf31f00..0000000
--- a/cpukit/score/cpu/avr/avr/io8535.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/**
- * @file avr/io8535.h
- *
- * @brief Definitions for AT90S8535
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO8535_H_
-#define _AVR_IO8535_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io8535.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_io8535 AT90S8535 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* ADC Data register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and Status Register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC MUX */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR  	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Asynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control Register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-#define _VECTORS_SIZE 34
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* MCU general Status Register */
-#define    EXTRF       1
-#define    PORF        0
-
-/* General Interrupt MaSK register */
-#define    INT1        7
-#define    INT0        6
-
-/* General Interrupt Flag Register */
-#define    INTF1       7
-#define    INTF0       6
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2       7
-#define    TOIE2       6
-#define    TICIE1      5
-#define    OCIE1A      4
-#define    OCIE1B      3
-#define    TOIE1       2
-#define    TOIE0       0
-
-/* Timer/Counter Interrupt Flag register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SE           6
-#define    SM1          5
-#define    SM0          4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* Timer/Counter 0 Control Register */
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control Register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Asynchronous mode Status Register */
-#define    AS2          3
-#define    TCN2UB       2
-#define    OCR2UB       1
-#define    TCR2UB       0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7      7
-#define    PA6      6
-#define    PA5      5
-#define    PA4      4
-#define    PA3      3
-#define    PA2      2
-#define    PA1      1
-#define    PA0      0
-
-/* Data Direction Register, Port A */
-#define    DDA7     7
-#define    DDA6     6
-#define    DDA5     5
-#define    DDA4     4
-#define    DDA3     3
-#define    DDA2     2
-#define    DDA1     1
-#define    DDA0     0
-
-/* Input Pins, Port A */
-#define    PINA7    7
-#define    PINA6    6
-#define    PINA5    5
-#define    PINA4    4
-#define    PINA3    3
-#define    PINA2    2
-#define    PINA1    1
-#define    PINA0    0
-
-/* Data Register, Port B */
-#define    PB7      7
-#define    PB6      6
-#define    PB5      5
-#define    PB4      4
-#define    PB3      3
-#define    PB2      2
-#define    PB1      1
-#define    PB0      0
-
-/* Data Direction Register, Port B */
-#define    DDB7     7
-#define    DDB6     6
-#define    DDB5     5
-#define    DDB4     4
-#define    DDB3     3
-#define    DDB2     2
-#define    DDB1     1
-#define    DDB0     0
-
-/* Input Pins, Port B */
-#define    PINB7    7
-#define    PINB6    6
-#define    PINB5    5
-#define    PINB4    4
-#define    PINB3    3
-#define    PINB2    2
-#define    PINB1    1
-#define    PINB0    0
-
-/* Data Register, Port C */
-#define    PC7      7
-#define    PC6      6
-#define    PC5      5
-#define    PC4      4
-#define    PC3      3
-#define    PC2      2
-#define    PC1      1
-#define    PC0      0
-
-/* Data Direction Register, Port C */
-#define    DDC7     7
-#define    DDC6     6
-#define    DDC5     5
-#define    DDC4     4
-#define    DDC3     3
-#define    DDC2     2
-#define    DDC1     1
-#define    DDC0     0
-
-/* Input Pins, Port C */
-#define    PINC7    7
-#define    PINC6    6
-#define    PINC5    5
-#define    PINC4    4
-#define    PINC3    3
-#define    PINC2    2
-#define    PINC1    1
-#define    PINC0    0
-
-/* Data Register, Port D */
-#define    PD7      7
-#define    PD6      6
-#define    PD5      5
-#define    PD4      4
-#define    PD3      3
-#define    PD2      2
-#define    PD1      1
-#define    PD0      0
-
-/* Data Direction Register, Port D */
-#define    DDD7     7
-#define    DDD6     6
-#define    DDD5     5
-#define    DDD4     4
-#define    DDD3     3
-#define    DDD2     2
-#define    DDD1     1
-#define    DDD0     0
-
-/* Input Pins, Port D */
-#define    PIND7     7
-#define    PIND6     6
-#define    PIND5     5
-#define    PIND4     4
-#define    PIND3     3
-#define    PIND2     2
-#define    PIND1     1
-#define    PIND0     0
-
-/* SPI Control Register */
-#define    SPIE     7
-#define    SPE     6
-#define    DORD     5
-#define    MSTR     4
-#define    CPOL     3
-#define    CPHA     2
-#define    SPR1     1
-#define    SPR0     0
-
-/* SPI Status Register */
-#define    SPIF     7
-#define    WCOL     6
-
-/* UART Status Register */
-#define    RXC      7
-#define    TXC      6
-#define    UDRE     5
-#define    FE       4
-#define    DOR      3
-
-/* UART Control Register */
-#define    RXCIE    7
-#define    TXCIE    6
-#define    UDRIE    5
-#define    RXEN     4
-#define    TXEN     3
-#define    CHR9     2
-#define    RXB8     1
-#define    TXB8     0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD      7
-#define    ACO      5
-#define    ACI      4
-#define    ACIE     3
-#define    ACIC     2
-#define    ACIS1    1
-#define    ACIS0    0
-
-/* ADC MUX */
-#define    MUX2     2
-#define    MUX1     1
-#define    MUX0     0
-
-/* ADC Control and Status Register */
-#define    ADEN     7
-#define    ADSC     6
-#define    ADFR     5
-#define    ADIF     4
-#define    ADIE     3
-#define    ADPS2    2
-#define    ADPS1    1
-#define    ADPS0    0
-
-/* EEPROM Control Register */
-#define    EERIE    3
-#define    EEMWE    2
-#define    EEWE     1
-#define    EERE     0
-
-/* Constants */
-#define RAMEND     0x25F    /*Last On-Chip SRAM location*/
-#define XRAMEND    RAMEND
-#define E2END      0x1FF
-#define E2PAGESIZE 0
-#define FLASHEND   0x1FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_SPIEN (unsigned char)~_BV(1)  /* Serial Program Downloading Enabled */
-#define FUSE_FSTRT (unsigned char)~_BV(2)  /* Short Start-up time selected */
-#define LFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x03
-
-/** @} */
-#endif /* _AVR_IO8535_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io86r401.h b/cpukit/score/cpu/avr/avr/io86r401.h
deleted file mode 100644
index 56f2d56..0000000
--- a/cpukit/score/cpu/avr/avr/io86r401.h
+++ /dev/null
@@ -1,321 +0,0 @@
-/**
- * @file avr/io86r401.h
- *
- * @brief Definitions for AT86RF401
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Colin O'Flynn
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO86RF401_H_
-#define _AVR_IO86RF401_H_ 1
-
-/**
- *  @defgroup Avr_io86r401 AT86RF401 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io86r401.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#include <avr/sfr_defs.h>
-
-/* Status REGister */
-#define SREG    _SFR_IO8(0x3F)
-
-/* Stack Pointer */
-#define SP      _SFR_IO16(0x3D)
-#define SPH     _SFR_IO8(0x3E)
-#define SPL     _SFR_IO8(0x3D)
-
-/*Battery low configeration register */
-#define BL_CONFIG       _SFR_IO8(0x35)
-
-/*Button detect register*/
-#define B_DET           _SFR_IO8(0x34)
-
-/*AVR Configeration register*/
-#define AVR_CONFIG      _SFR_IO8(0x33)
-
-/* I/O registers */
-
-/*Data in register */
-#define IO_DATIN        _SFR_IO8(0x32)
-
-/*Data out register */
-#define IO_DATOUT       _SFR_IO8(0x31)
-
-/*IO Enable register */
-#define IO_ENAB         _SFR_IO8(0x30)
-
-/* Watchdog Timer Control Register */
-#define WDTCR           _SFR_IO8(0x22)
-
-/* Bit Timer Control Register */
-#define BTCR            _SFR_IO8(0x21)
-
-#define BTCNT           _SFR_IO8(0x20)
-
-/*
-NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
-you may want to remove the leading D.
-*/
-/* EEPROM Control Register */
-
-/* EEPROM Address Register */
-#define DEEAR           _SFR_IO8(0x1E)
-#define DEEARL          _SFR_IO8(0x1E)
-
-/* EEPROM Data Register */
-#define DEEDR           _SFR_IO8(0x1D)
-/* EEPROM Control Register */
-#define DEECR           _SFR_IO8(0x1C)
-
-/* Lock Detector Configuration Register 2 */
-#define LOCKDET2        _SFR_IO8(0x17)
-
-/* VCO Tuning Register*/
-#define VCOTUNE         _SFR_IO8(0x16)
-
-/* Power Attenuation Control Register */
-#define PWR_ATTEN       _SFR_IO8(0x14)
-
-/* Transmitter Control Register */
-#define TX_CNTL         _SFR_IO8(0x12)
-
-/* Lock Detector Configuration Register 1 */
-#define LOCKDET1        _SFR_IO8(0x10)
-
-
-/* Interrupt vectors */
-
-/* Transmission Done, Bit Timer Flag 2 Interrupt */
-#define TXDONE_vect			_VECTOR(1)
-#define SIG_TXDONE			_VECTOR(1)
-
-/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */
-#define TXEMPTY_vect			_VECTOR(2)
-#define SIG_TXBE			_VECTOR(2)
-
-#define _VECTORS_SIZE 12
-
-/*
- *  The Register Bit names are represented by their bit number (0-7).
- */
-
-/* Lock Detector Configuration Register 1 - LOCKDET1 */
-#define UPOK    4
-#define ENKO    3
-#define BOD     2
-#define CS1     1
-#define CS0     0
-
-/* Transmit Control Register - TX_CNTL */
-#define TXE     5
-#define TXK     4
-#define LOC     2
-
-/* Power Attenuation Control Register - PWR_ATTEN */
-#define PCC2        5
-#define PCC1        4
-#define PCC0        3
-#define PCF2        2
-#define PCF1        1
-#define PCF0        0
-
-/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/
-#define VCOVDET1        7
-#define VCOVDET0        6
-#define VCOTUNE4        4
-#define VCOTUNE3        3
-#define VCOTUNE2        2
-#define VCOTUNE1        1
-#define VCOTUNE0        0
-
-/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/
-#define EUD         7
-#define LAT         6
-#define ULC2        5
-#define ULC1        4
-#define ULC0        3
-#define LC2         2
-#define LC1         1
-#define LC0         0
-
-/* Data EEPROM Control Register - DEECR */
-#define BSY         3
-#define EEU         2
-#define EEL         1
-#define EER         0
-
-/* Data EEPROM Data Register - DEEDR */
-#define ED7         7
-#define ED6         6
-#define ED5         5
-#define ED4         4
-#define ED3         3
-#define ED2         2
-#define ED1         1
-#define ED0         0
-
-/* Data EEPROM Address Register - DEEAR */
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define BA2     2  /* B is not a typo! */
-#define BA1     1
-#define BA0     0
-
-/* Bit Timer Count Register - BTCNT */
-#define C7      7
-#define C6      6
-#define C5      5
-#define C4      4
-#define C3      3
-#define C2      2
-#define C1      1
-#define C0      0
-
-/* Bit Timer Control Register - BTCR */
-#define C9      7
-#define C8      6
-#define M1      5
-#define M0      4
-#define IE      3
-#define F2      2
-#define DATA    1
-#define F0      0
-
-/* Watchdog Timer Control Register - WDTCR */
-#define WDTOE       4
-#define WDE         3
-#define WDP2        2
-#define WDP1        1
-#define WDP0        0
-
-/* I/O Enable Register - IO_ENAB */
-#define BOHYST      6
-#define IOE5        5
-#define IOE4        4
-#define IOE3        3
-#define IOE2        2
-#define IOE1        1
-#define IOE0        0
-
-/* Note: No PORTB or whatever, this is the equivalent. */
-/* I/O Data Out Register - IO_DATOUT */
-#define IOO5     5
-#define IOO4     4
-#define IOO3     3
-#define IOO2     2
-#define IOO1     1
-#define IOO0     0
-
-/* Note: No PINB or whatever, this is the equivalent. */
-/* I/O Data In Register - IO_DATIN */
-#define IOI5     5
-#define IOI4     4
-#define IOI3     3
-#define IOI2     2
-#define IOI1     1
-#define IOI0     0
-
-/* AVR Configuration Register - AVR_CONFIG */
-#define ACS1    6
-#define ACS0    5
-#define TM      4
-#define BD      3
-#define BLI     2
-#define SLEEP   1
-#define BBM     0
-
-/* Button Detect Register - B_DET */
-#define BD5     5
-#define BD4     4
-#define BD3     3
-#define BD2     2
-#define BD1     1
-#define BD0     0
-
-/* Battery Low Configuration Register - BL_CONFIG */
-#define BL      7
-#define BLV     6
-#define BL5     5
-#define BL4     4
-#define BL3     3
-#define BL2     2
-#define BL1     1
-#define BL0     0
-
-/* Pointer definition   */
-#define XL      r26
-#define XH      r27
-#define YL      r28
-#define YH      r29
-#define ZL      r30
-#define ZH      r31
-
-/* Constants */
-#define RAMEND      0xDF
-#define XRAMEND     RAMEND
-#define E2END       0x7F
-#define E2PAGESIZE  0
-#define FLASHEND    0x07FF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 0
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x91
-#define SIGNATURE_2 0x81
-
-/**@}*/
-#endif  /* _AVR_IO86RF401_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm1.h b/cpukit/score/cpu/avr/avr/io90pwm1.h
deleted file mode 100644
index 6c3aad0..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm1.h
+++ /dev/null
@@ -1,1137 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM1
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2005, Andrey Pashchenko
-   Copyright (c) 2007, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iopwm1.h - definitions for AT90PWM1 device */
-
-#ifndef _AVR_IOPWM1_H_
-#define _AVR_IOPWM1_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iopwm1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm1 AT90PWM1 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Reserved [0x00..0x02] */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Reserved [0x06..0x08] */
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-/* PINE */
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-/* DDRE */
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-/* PORTE */
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-/* Reserved [0x0F..0x14] */
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-/* TIFR0 */
-#define OCF0B   2   /* Output Compare Flag 0B */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define TOV0    0   /* Overflow Flag */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-/* TIFR1 */
-#define ICF1    5   /* Input Capture Flag 1 */
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define TOV1    0   /* Overflow Flag */
-
-/* Reserved [0x17..0x18] */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-/* GPIOR1 */
-#define GPIOR17 7
-#define GPIOR16 6
-#define GPIOR15 5
-#define GPIOR14 4
-#define GPIOR13 3
-#define GPIOR12 2
-#define GPIOR11 1
-#define GPIOR10 0
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-/* GPIOR2 */
-#define GPIOR27 7
-#define GPIOR26 6
-#define GPIOR25 5
-#define GPIOR24 4
-#define GPIOR23 3
-#define GPIOR22 2
-#define GPIOR21 1
-#define GPIOR20 0
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-/* GPIOR3 */
-#define GPIOR37 7
-#define GPIOR36 6
-#define GPIOR35 5
-#define GPIOR34 4
-#define GPIOR33 3
-#define GPIOR32 2
-#define GPIOR31 1
-#define GPIOR30 0
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-/* EIFR */
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-/* EIMSK */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT0    0   /* External Interrupt Request 0 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-/* GPIOR0 */
-#define GPIOR07 7
-#define GPIOR06 6
-#define GPIOR05 5
-#define GPIOR04 4
-#define GPIOR03 3
-#define GPIOR02 2
-#define GPIOR01 1
-#define GPIOR00 0
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-/* EECR */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EERE    0   /* EEPROM Read Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-/* EEDR */
-#define EEDR7   7
-#define EEDR6   6
-#define EEDR5   5
-#define EEDR4   4
-#define EEDR3   3
-#define EEDR2   2
-#define EEDR1   1
-#define EEDR0   0
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-/* EEARH */
-#define EEAR11  3
-#define EEAR10  2
-#define EEAR9   1
-#define EEAR8   0
-/* EEARL */
-#define EEAR7   7
-#define EEAR6   6
-#define EEAR5   5
-#define EEAR4   4
-#define EEAR3   3
-#define EEAR2   2
-#define EEAR1   1
-#define EEAR0   0
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-/* GTCCR */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define PSRSYNC 0
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-/* TCCR0A */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define WGM01   1   /* Waveform Generation Mode */
-#define WGM00   0   /* Waveform Generation Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-/* TCCR0B */
-#define FOC0A   7   /* Force Output Compare A */
-#define FOC0B   6   /* Force Output Compare B */
-#define WGM02   3   /* Waveform Generation Mode */
-#define CS02    2   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS00    0   /* Clock Select */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-/* TCNT0 */
-#define TCNT07  7
-#define TCNT06  6
-#define TCNT05  5
-#define TCNT04  4
-#define TCNT03  3
-#define TCNT02  2
-#define TCNT01  1
-#define TCNT00  0
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-/* OCR0A */
-#define OCR0A7  7
-#define OCR0A6  6
-#define OCR0A5  5
-#define OCR0A4  4
-#define OCR0A3  3
-#define OCR0A2  2
-#define OCR0A1  1
-#define OCR0A0  0
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-/* OCR0B */
-#define OCR0B7  7
-#define OCR0B6  6
-#define OCR0B5  5
-#define OCR0B4  4
-#define OCR0B3  3
-#define OCR0B2  2
-#define OCR0B1  1
-#define OCR0B0  0
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-/* PLLCSR */
-#define PLLF    2
-#define PLLE    1   /* PLL Enable */
-#define PLOCK   0   /* PLL Lock Detector */
-
-/* Reserved [0x2A..0x2B] */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-/* SPCR */
-#define SPIE    7   /* SPI Interrupt Enable */
-#define SPE     6   /* SPI Enable */
-#define DORD    5   /* Data Order */
-#define MSTR    4   /* Master/Slave Select */
-#define CPOL    3   /* Clock polarity */
-#define CPHA    2   /* Clock Phase */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-/* SPSR */
-#define SPIF    7   /* SPI Interrupt Flag */
-#define WCOL    6   /* Write Collision Flag */
-#define SPI2X   0   /* Double SPI Speed Bit */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-/* SPDR */
-#define SPD7    7
-#define SPD6    6
-#define SPD5    5
-#define SPD4    4
-#define SPD3    3
-#define SPD2    2
-#define SPD1    1
-#define SPD0    0
-
-/* Reserved [0x2F] */
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-/* ACSR */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-
-/* Monitor Data Register */
-#define MONDR   _SFR_IO8(0x31)
-
-/* Monitor Stop Mode Control Register */
-#define MSMCR   _SFR_IO8(0x32)
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-/* SMCR */
-#define SM2     3   /* Sleep Mode Select bit2 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SE      0   /* Sleep Enable */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-/* MCUSR */
-#define WDRF    3   /* Watchdog Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define EXTRF   1   /* External Reset Flag */
-#define PORF    0   /* Power-on reset flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-/* MCUCR */
-#define SPIPS   7   /* SPI Pin Select */
-#define PUD     4   /* Pull-up disable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define IVCE    0   /* Interrupt Vector Change Enable */
-
-/* Reserved [0x36] */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-/* SPMCSR */
-#define SPMIE   7   /* SPM Interrupt Enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define PGWRT   2   /* Page Write */
-#define PGERS   1   /* Page Erase */
-#define SPMEN   0   /* Store Program Memory Enable */
-
-/* Reserved [0x38..0x3C] */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-/* WDTCSR */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDE     3   /* Watchdog Enable */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-/* CLKPR */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-
-/* Reserved [0x62..0x63] */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-/* PRR */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRADC   0   /* Power Reduction ADC */
-
-/* Reserved [0x65] */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-/* OSCCAL */
-#define CAL6    6
-#define CAL5    5
-#define CAL4    4
-#define CAL3    3
-#define CAL2    2
-#define CAL1    1
-#define CAL0    0
-
-/* Reserved [0x67..0x68] */
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-/* EICRA */
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Reserved [0x6A..0x6D] */
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-/* TIMSK0 */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE0   0   /* Overflow Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-/* TIMSK1 */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE1   0   /* Overflow Interrupt Enable */
-
-/* Reserved [0x70..0x75] */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0EN  7
-#define AMP0IS  6
-#define AMP0G1  5
-#define AMP0G0  4
-#define AMP0TS1 1
-#define AMP0TS0 0
-
-/* Reserved [0x77] */
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-/* ADCSRA */
-#define ADEN    7   /* ADC Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-/* ADCSRB */
-#define ADTS3   3   /* ADC Auto Trigger Source 2 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-/* ADMUX */
-#define REFS1   7   /* Reference Selection bit1 */
-#define REFS0   6   /* Reference Selection bit0 */
-#define ADLAR   5   /* Left Adjust Result */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-
-/* Reserved [0x7D] */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-/* DIDR0 */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC0D   0   /* ADC0 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-/* DIDR1 */
-#define ACMP0D  5
-#define AMP0PD  4
-#define AMP0ND  3
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC8D   0   /* ADC8 Digital input Disable */
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-/* TCCR1A */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define WGM11   1   /* Waveform Generation Mode */
-#define WGM10   0   /* Waveform Generation Mode */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-/* TCCR1B */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define WGM13   4   /* Waveform Generation Mode */
-#define WGM12   3   /* Waveform Generation Mode */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-/* TCCR1C */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-#define FOC1B   6   /* Force Output Compare for Channel B */
-
-/* Reserved [0x83] */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-/* TCNT1H */
-#define TCNT115 7
-#define TCNT114 6
-#define TCNT113 5
-#define TCNT112 4
-#define TCNT111 3
-#define TCNT110 2
-#define TCNT19  1
-#define TCNT18  0
-/* TCNT1L */
-#define TCNT17  7
-#define TCNT16  6
-#define TCNT15  5
-#define TCNT14  4
-#define TCNT13  3
-#define TCNT12  2
-#define TCNT11  1
-#define TCNT10  0
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-/* ICR1H */
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-/* ICR1L */
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-/* OCR1AH */
-#define OCR1A15 7
-#define OCR1A14 6
-#define OCR1A13 5
-#define OCR1A12 4
-#define OCR1A11 3
-#define OCR1A10 2
-#define OCR1A9  1
-#define OCR1A8  0
-/* OCR1AL */
-#define OCR1A7  7
-#define OCR1A6  6
-#define OCR1A5  5
-#define OCR1A4  4
-#define OCR1A3  3
-#define OCR1A2  2
-#define OCR1A1  1
-#define OCR1A0  0
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-/* OCR1BH */
-#define OCR1B15 7
-#define OCR1B14 6
-#define OCR1B13 5
-#define OCR1B12 4
-#define OCR1B11 3
-#define OCR1B10 2
-#define OCR1B9  1
-#define OCR1B8  0
-/* OCR1BL */
-#define OCR1B7  7
-#define OCR1B6  6
-#define OCR1B5  5
-#define OCR1B4  4
-#define OCR1B3  3
-#define OCR1B2  2
-#define OCR1B1  1
-#define OCR1B0  0
-
-/* Reserved [0x8C..0x9F] */
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-/* PIFR0 */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-/* PIM0 */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-
-/* Reserved [0xA2..0xA3] */
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-/* PIFR2 */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-/* PIM2 */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-
-/* Reserved [0xA6..0xAC] */
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-/* AC0CON */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-
-/* Reserved [0xB0..0xAE] */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-/* AC2CON */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-
-/* Reserved [0xB0..0xCF] */
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-/* PSOC0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-
-/* Reserved [0xD1] */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-/* PCNF0 */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-/* PCTL0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PRUN0   0   /* PSC 0 Run */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-/* PFRC0A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-/* PFRC0B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-
-#define PICR0L  _SFR_MEM8(0xDE)
-
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* Reserved [0xE0..0xEF] */
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-/* PSOC2 */
-#define POS23   7   /* PSCOUT23 Selection */
-#define POS22   6   /* PSCOUT22 Selection */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-/* POM2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-/* PCNF2 */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-/* PCTL2 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PRUN2   0   /* PSC 2 Run */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-/* PFRC2A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-/* PFRC2B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-
-#define PICR2L  _SFR_MEM8(0xFE)
-
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-
-/* Interrupt vectors */
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect			_VECTOR(1)
-#define SIG_PSC2_CAPTURE		_VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect			_VECTOR(2)
-#define SIG_PSC2_END_CYCLE		_VECTOR(2)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect			_VECTOR(5)
-#define SIG_PSC0_CAPTURE		_VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect			_VECTOR(6)
-#define SIG_PSC0_END_CYCLE		_VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect		_VECTOR(7)
-#define SIG_COMPARATOR0			_VECTOR(7)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect		_VECTOR(9)
-#define SIG_COMPARATOR2			_VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(10)
-#define SIG_INTERRUPT0			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1_A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1_B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0_A		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(18)
-#define SIG_ADC				_VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(19)
-#define SIG_INTERRUPT1			_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(24)
-#define SIG_INTERRUPT2			_VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(25)
-#define SIG_WDT				_VECTOR(25)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0_B		_VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(28)
-#define SIG_INTERRUPT3			_VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(31)
-#define SIG_SPM_READY			_VECTOR(31)
-
-#define _VECTORS_SIZE   64
-
-/* Constants */
-#define SPM_PAGESIZE    64
-
-#define RAMEND      0x02FF
-#define XRAMEND     RAMEND
-#define E2END       0x01FF
-#define FLASHEND    0x0FFF
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
-#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_PSCRV       (unsigned char)~_BV(4)
-#define FUSE_PSC0RB      (unsigned char)~_BV(5)
-#define FUSE_PSC2RB      (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-/** @} */
-
-#endif /* _AVR_IOPWM1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm216.h b/cpukit/score/cpu/avr/avr/io90pwm216.h
deleted file mode 100644
index c6befa4..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm216.h
+++ /dev/null
@@ -1,1197 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM216
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm216.h - definitions for AT90PWM216 */
-
-#ifndef _AVR_IO90PWM216_H_
-#define _AVR_IO90PWM216_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm216.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm216 AT90PWM216 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-#define PINE0   0
-#define PINE1   1
-#define PINE2   2
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE0    0
-#define DDE1    1
-#define DDE2    2
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-#define PE0     0
-#define PE1     1
-#define PE2     2
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0   /* Overflow Flag */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define OCF0B   2   /* Output Compare Flag 0B */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0   /* Overflow Flag */
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define ICF1    5   /* Input Capture Flag 1 */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-#define INTF2   2
-#define INTF3   3
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0   /* External Interrupt Request 0 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0   /* EEPROM Read Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEAR0   0
-#define EEAR1   1
-#define EEAR2   2
-#define EEAR3   3
-#define EEAR4   4
-#define EEAR5   5
-#define EEAR6   6
-#define EEAR7   7
-#define EEARH   _SFR_IO8(0x22)
-#define EEAR8   0
-#define EEAR9   1
-#define EEAR10  2
-#define EEAR11  3
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0   /* Waveform Generation Mode */
-#define WGM01   1   /* Waveform Generation Mode */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS02    2   /* Clock Select */
-#define WGM02   3   /* Waveform Generation Mode */
-#define FOC0B   6   /* Force Output Compare B */
-#define FOC0A   7   /* Force Output Compare A */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-#define OCR0A0  0
-#define OCR0A1  1
-#define OCR0A2  2
-#define OCR0A3  3
-#define OCR0A4  4
-#define OCR0A5  5
-#define OCR0A6  6
-#define OCR0A7  7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-#define OCR0B0  0
-#define OCR0B1  1
-#define OCR0B2  2
-#define OCR0B3  3
-#define OCR0B4  4
-#define OCR0B5  5
-#define OCR0B6  6
-#define OCR0B7  7
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0   /* PLL Lock Detector */
-#define PLLE    1   /* PLL Enable */
-#define PLLF    2   /* PLL Factor */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define CPHA    2   /* Clock Phase */
-#define CPOL    3   /* Clock polarity */
-#define MSTR    4   /* Master/Slave Select */
-#define DORD    5   /* Data Order */
-#define SPE     6   /* SPI Enable */
-#define SPIE    7   /* SPI Interrupt Enable */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0   /* Double SPI Speed Bit */
-#define WCOL    6   /* Write Collision Flag */
-#define SPIF    7   /* SPI Interrupt Flag */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-#define SPD0    0
-#define SPD1    1
-#define SPD2    2
-#define SPD3    3
-#define SPD4    4
-#define SPD5    5
-#define SPD6    6
-#define SPD7    7
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0   /* Sleep Enable */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM2     3   /* Sleep Mode Select bit2 */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0   /* Power-on reset flag */
-#define EXTRF   1   /* External Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define WDRF    3   /* Watchdog Reset Flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0   /* Interrupt Vector Change Enable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define PUD     4   /* Pull-up disable */
-#define SPIPS   7   /* SPI Pin Select */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0   /* Store Program Memory Enable */
-#define PGERS   1   /* Page Erase */
-#define PGWRT   2   /* Page Write */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define SPMIE   7   /* SPM Interrupt Enable */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDE     3   /* Watchdog Enable */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0   /* Power Reduction ADC */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define ISC20   4
-#define ISC21   5
-#define ISC30   6
-#define ISC31   7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0   /* Overflow Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0   /* Overflow Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0  4
-#define AMP0G1  5
-#define AMP0IS  6
-#define AMP0EN  7
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0  4
-#define AMP1G1  5
-#define AMP1IS  6
-#define AMP1EN  7
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADEN    7   /* ADC Enable */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADHSM   7   /* ADC High Speed Mode */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define ADLAR   5   /* Left Adjust Result */
-#define REFS0   6   /* Reference Selection bit0 */
-#define REFS1   7   /* Reference Selection bit1 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0   /* ADC0 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   0   /* ADC8 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define AMP0ND  3
-#define AMP0PD  4
-#define ACMP0D  5
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0   /* Waveform Generation Mode */
-#define WGM11   1   /* Waveform Generation Mode */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define WGM12   3   /* Waveform Generation Mode */
-#define WGM13   4   /* Waveform Generation Mode */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6   /* Force Output Compare for Channel B */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT10  0
-#define TCNT11  1
-#define TCNT12  2
-#define TCNT13  3
-#define TCNT14  4
-#define TCNT15  5
-#define TCNT16  6
-#define TCNT17  7
-#define TCNT1H  _SFR_MEM8(0x85)
-#define TCNT18  0
-#define TCNT19  1
-#define TCNT110 2
-#define TCNT111 3
-#define TCNT112 4
-#define TCNT113 5
-#define TCNT114 6
-#define TCNT115 7
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-#define ICR1H   _SFR_MEM8(0x87)
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1A0  0
-#define OCR1A1  1
-#define OCR1A2  2
-#define OCR1A3  3
-#define OCR1A4  4
-#define OCR1A5  5
-#define OCR1A6  6
-#define OCR1A7  7
-#define OCR1AH  _SFR_MEM8(0x89)
-#define OCR1A8  0
-#define OCR1A9  1
-#define OCR1A10 2
-#define OCR1A11 3
-#define OCR1A12 4
-#define OCR1A13 5
-#define OCR1A14 6
-#define OCR1A15 7
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1B0  0
-#define OCR1B1  1
-#define OCR1B2  2
-#define OCR1B3  3
-#define OCR1B4  4
-#define OCR1B5  5
-#define OCR1B6  6
-#define OCR1B7  7
-#define OCR1BH  _SFR_MEM8(0x8B)
-#define OCR1B8  0
-#define OCR1B9  1
-#define OCR1B10 2
-#define OCR1B11 3
-#define OCR1B12 4
-#define OCR1B13 5
-#define OCR1B14 6
-#define OCR1B15 7
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define POAC0B  7   /* PSC0 Output B Activity */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define POAC2B  7   /* PSC2 Output B Activity */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-#define DAEN    0   /* Digital to Analog Enable bit */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0   /* Multi-processor Communication Mode */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define UPE     2   /* USART Parity Error */
-#define DOR     3   /* Data OverRun */
-#define FE      4   /* Frame Error */
-#define UDRE    5   /* USART Data Register Empty */
-#define TXC     6   /* USART Transmit Complete */
-#define RXC     7   /* USART Receive Complete */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-#define TXB8    0   /* Transmit Data Bit 8 */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define UCSZ2   2   /* Character Size */
-#define TXEN    3   /* Transmitter Enable */
-#define RXEN    4   /* Receiver Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0   /* Clock Polarity */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCSZ1   2   /* Character Size bit1 */
-#define USBS    3   /* Stop Bit Select */
-#define UPM0    4   /* Parity Mode bit0 */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UMSEL   6   /* USART Mode Select */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-#define BODR    0   /* Bit Order */
-#define EMCH    1   /* Manchester mode */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EUSART  4   /* EUSART Enable Bit */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-#define STP0    0   /* Stop bits values bit0 */
-#define STP1    1   /* Stop bits values bit1 */
-#define F1617   2
-#define FEM     3   /* Frame Error Manchester */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-#define PRUN0   0   /* PSC 0 Run */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-#define PICR0L  _SFR_MEM8(0xDE)
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-#define PICR1L  _SFR_MEM8(0xEE)
-#define PICR1H  _SFR_MEM8(0xEF)
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define POS22   6   /* PSCOUT22 Selection */
-#define POS23   7   /* PSCOUT23 Selection */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-#define PRUN2   0   /* PSC 2 Run */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-#define PICR2L  _SFR_MEM8(0xFE)
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-
-
-/* Interrupt Vectors */
-/* Interrupt 0 is the reset vector. */
-
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect     _VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect       _VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect     _VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect       _VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect     _VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect       _VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect _VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect _VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect _VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect          _VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect   _VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect  _VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect  _VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect    _VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect _VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect    _VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect           _VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect          _VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect       _VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect      _VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect    _VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect      _VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect          _VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect           _VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect      _VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect  _VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect          _VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect     _VECTOR(31)
-
-#define _VECTORS_SIZE   (4 * 32)
-
-/* Constants */
-
-#define RAMEND         0x4FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x3FFF
-#define SPM_PAGESIZE   128
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV    (unsigned char)~_BV(4)
-#define FUSE_PSC0RB   (unsigned char)~_BV(5)
-#define FUSE_PSC1RB   (unsigned char)~_BV(6)
-#define FUSE_PSC2RB   (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x83
-
-/** @} */
-
-#endif /* _AVR_IO90PWM216_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm2b.h b/cpukit/score/cpu/avr/avr/io90pwm2b.h
deleted file mode 100644
index 22d0c1c..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm2b.h
+++ /dev/null
@@ -1,1404 +0,0 @@
-/**
- * @file avr/io90pwm2b.h
- *
- * @brief Definitions for AT90PWM2B
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2007 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm2b.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IO90PWM2B_H_
-#define _AVR_IO90PWM2B_H_ 1
-
-/**
- * @defgroup Avr_io90pwm2b AT90PWM2B Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define GPIOR3 _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0_0 0    /* Deprecated */
-#define OCR0_1 1    /* Deprecated */
-#define OCR0_2 2    /* Deprecated */
-#define OCR0_3 3    /* Deprecated */
-#define OCR0_4 4    /* Deprecated */
-#define OCR0_5 5    /* Deprecated */
-#define OCR0_6 6    /* Deprecated */
-#define OCR0_7 7    /* Deprecated */
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define ACCKDIV 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC1 6
-#define PRPSC2 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADASCR 4
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define PIFR0 _SFR_MEM8(0xA0)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define PSEI0 5
-#define POAC0A 6
-#define POAC0B 7
-
-#define PIM0 _SFR_MEM8(0xA1)
-#define PEOPE0 0
-#define PEVE0A 3
-#define PEVE0B 4
-#define PSEIE0 5
-
-#define PIFR1 _SFR_MEM8(0xA2)
-#define PEOP1 0
-#define PRN10 1
-#define PRN11 2
-#define PEV1A 3
-#define PEV1B 4
-#define PSEI1 5
-#define POAC1A 6
-#define POAC1B 7
-
-#define PIM1 _SFR_MEM8(0xA3)
-#define PEOPE1 0
-#define PEVE1A 3
-#define PEVE1B 4
-#define PSEIE1 5
-
-#define PIFR2 _SFR_MEM8(0xA4)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PIM2 _SFR_MEM8(0xA5)
-#define PEOPE2 0
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define DACON _SFR_MEM8(0xAA)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0xAB)
-
-#define DACL _SFR_MEM8(0xAB)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0xAC)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0xAD)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0xAE)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0xAF)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define UCSRA _SFR_MEM8(0xC0)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UCSRB _SFR_MEM8(0xC1)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRC _SFR_MEM8(0xC2)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL0 6
-
-#define UBRR _SFR_MEM16(0xC4)
-
-#define UBRRL _SFR_MEM8(0xC4)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRRH _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR _SFR_MEM8(0xC6)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define EUCSRA _SFR_MEM8(0xC8)
-#define URxS0 0
-#define URxS1 1
-#define URxS2 2
-#define URxS3 3
-#define UTxS0 4
-#define UTxS1 5
-#define UTxS2 6
-#define UTxS3 7
-
-#define EUCSRB _SFR_MEM8(0xC9)
-#define BODR 0
-#define EMCH 1
-#define EUSBS 3
-#define EUSART 4
-
-#define EUCSRC _SFR_MEM8(0xCA)
-#define STP0 0
-#define STP1 1
-#define F1617 2
-#define FEM 3
-
-#define MUBRR _SFR_MEM16(0xCC)
-
-#define MUBRRL _SFR_MEM8(0xCC)
-#define MUBRR0 0
-#define MUBRR1 1
-#define MUBRR2 2
-#define MUBRR3 3
-#define MUBRR4 4
-#define MUBRR5 5
-#define MUBRR6 6
-#define MUBRR7 7
-
-#define MUBRRH _SFR_MEM8(0xCD)
-#define MUBRR8 0
-#define MUBRR9 1
-#define MUBRR10 2
-#define MUBRR11 3
-#define MUBRR12 4
-#define MUBRR13 5
-#define MUBRR14 6
-#define MUBRR15 7
-
-#define EUDR _SFR_MEM8(0xCE)
-#define EUDR0 0
-#define EUDR1 1
-#define EUDR2 2
-#define EUDR3 3
-#define EUDR4 4
-#define EUDR5 5
-#define EUDR6 6
-#define EUDR7 7
-
-#define PSOC0 _SFR_MEM8(0xD0)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-
-#define OCR0SA _SFR_MEM16(0xD2)
-
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0xD3)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define OCR0RA _SFR_MEM16(0xD4)
-
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_MEM8(0xD5)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#define OCR0SB _SFR_MEM16(0xD6)
-
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_MEM8(0xD7)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_MEM16(0xD8)
-
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_MEM8(0xD9)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define PCNF0 _SFR_MEM8(0xDA)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_MEM8(0xDB)
-#define PRUN0 0
-#define PCCYC0 1
-#define PARUN0 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM0 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PFRC0A _SFR_MEM8(0xDC)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0xDD)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define PICR0 _SFR_MEM16(0xDE)
-
-#define PICR0L _SFR_MEM8(0xDE)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0xDF)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC1 _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-#define OCR1SA _SFR_MEM16(0xE2)
-
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SA_0 0
-#define OCR1SA_1 1
-#define OCR1SA_2 2
-#define OCR1SA_3 3
-#define OCR1SA_4 4
-#define OCR1SA_5 5
-#define OCR1SA_6 6
-#define OCR1SA_7 7
-
-#define OCR1SAH _SFR_MEM8(0xE3)
-#define OCR1SA_8 0
-#define OCR1SA_9 1
-#define OCR1SA_10 2
-#define OCR1SA_11 3
-
-#define OCR1RA _SFR_MEM16(0xE4)
-
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RA_0 0
-#define OCR1RA_1 1
-#define OCR1RA_2 2
-#define OCR1RA_3 3
-#define OCR1RA_4 4
-#define OCR1RA_5 5
-#define OCR1RA_6 6
-#define OCR1RA_7 7
-
-#define OCR1RAH _SFR_MEM8(0xE5)
-#define OCR1RA_8 0
-#define OCR1RA_9 1
-#define OCR1RA_10 2
-#define OCR1RA_11 3
-
-#define OCR1SB _SFR_MEM16(0xE6)
-
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SB_0 0
-#define OCR1SB_1 1
-#define OCR1SB_2 2
-#define OCR1SB_3 3
-#define OCR1SB_4 4
-#define OCR1SB_5 5
-#define OCR1SB_6 6
-#define OCR1SB_7 7
-
-#define OCR1SBH _SFR_MEM8(0xE7)
-#define OCR1SB_8 0
-#define OCR1SB_9 1
-#define OCR1SB_10 2
-#define OCR1SB_11 3
-
-#define OCR1RB _SFR_MEM16(0xE8)
-
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RB_0 0
-#define OCR1RB_1 1
-#define OCR1RB_2 2
-#define OCR1RB_3 3
-#define OCR1RB_4 4
-#define OCR1RB_5 5
-#define OCR1RB_6 6
-#define OCR1RB_7 7
-
-#define OCR1RBH _SFR_MEM8(0xE9)
-#define OCR1RB_8 0
-#define OCR1RB_9 1
-#define OCR1RB_10 2
-#define OCR1RB_11 3
-#define OCR1RB_12 4
-#define OCR1RB_13 5
-#define OCR1RB_14 6
-#define OCR1RB_15 7
-
-#define PCNF1 _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1 2
-#define PMODE10 3
-#define PMODE11 4
-#define PLOCK1 5
-#define PALOCK1 6
-#define PFIFTY1 7
-
-#define PCTL1 _SFR_MEM8(0xEB)
-#define PRUN1 0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1 5
-#define PPRE10 6
-#define PPRE11 7
-
-#define PFRC1A _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A 7
-
-#define PFRC1B _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B 7
-
-#define PICR1 _SFR_MEM16(0xEE)
-
-#define PICR1L _SFR_MEM8(0xEE)
-#define PICR1_0 0
-#define PICR1_1 1
-#define PICR1_2 2
-#define PICR1_3 3
-#define PICR1_4 4
-#define PICR1_5 5
-#define PICR1_6 6
-#define PICR1_7 7
-
-#define PICR1H _SFR_MEM8(0xEF)
-#define PICR1_8 0
-#define PICR1_9 1
-#define PICR1_10 2
-#define PICR1_11 3
-#define PCST1 7
-
-#define PSOC2 _SFR_MEM8(0xF0)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0xF1)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define OCR2SA _SFR_MEM16(0xF2)
-
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0xF3)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define OCR2RA _SFR_MEM16(0xF4)
-
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_MEM8(0xF5)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define OCR2SB _SFR_MEM16(0xF6)
-
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_MEM8(0xF7)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_MEM16(0xF8)
-
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_MEM8(0xF9)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define PCNF2 _SFR_MEM8(0xFA)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_MEM8(0xFB)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define PFRC2A _SFR_MEM8(0xFC)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0xFD)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR2 _SFR_MEM16(0xFE)
-
-#define PICR2L _SFR_MEM8(0xFE)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0xFF)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-#define PSC2_CAPT_vect      _VECTOR(1)   /* PSC2 Capture Event */
-#define PSC2_EC_vect        _VECTOR(2)   /* PSC2 End Cycle */
-#define PSC1_CAPT_vect      _VECTOR(3)   /* PSC1 Capture Event */
-#define PSC1_EC_vect        _VECTOR(4)   /* PSC1 End Cycle */
-#define PSC0_CAPT_vect      _VECTOR(5)   /* PSC0 Capture Event */
-#define PSC0_EC_vect        _VECTOR(6)   /* PSC0 End Cycle */
-#define ANALOG_COMP_0_vect  _VECTOR(7)   /* Analog Comparator 0 */
-#define ANALOG_COMP_1_vect  _VECTOR(8)   /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect  _VECTOR(9)   /* Analog Comparator 2 */
-#define INT0_vect           _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect    _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect   _VECTOR(13)  /* Timer/Counter Compare Match B */
-/* Vector 14, Reserved */
-#define TIMER1_OVF_vect     _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_OVF_vect     _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define ADC_vect            _VECTOR(18)  /* ADC Conversion Complete */
-#define INT1_vect           _VECTOR(19)  /* External Interrupt Request 1 */
-#define SPI_STC_vect        _VECTOR(20)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect       _VECTOR(21)  /* USART, Rx Complete */
-#define USART_UDRE_vect     _VECTOR(22)  /* USART Data Register Empty */
-#define USART_TX_vect       _VECTOR(23)  /* USART, Tx Complete */
-#define INT2_vect           _VECTOR(24)  /* External Interrupt Request 2 */
-#define WDT_vect            _VECTOR(25)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect       _VECTOR(26)  /* EEPROM Ready */
-#define TIMER0_COMPB_vect   _VECTOR(27)  /* Timer Counter 0 Compare Match B */
-#define INT3_vect           _VECTOR(28)  /* External Interrupt Request 3 */
-/* Vector 29, Reserved */
-/* Vector 30, Reserved */
-#define SPM_READY_vect      _VECTOR(31)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE 64
-
-
-
-/* Memory Sizes */
-#define RAMEND         0x2FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x1FFF
-#define SPM_PAGESIZE   32
-
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6) /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV   (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC1RB  (unsigned char)~_BV(6)  /* PSC1 Reset Behaviour */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x83
-
-
-/** @} */
-#endif /* _AVR_IO90PWM2B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm316.h b/cpukit/score/cpu/avr/avr/io90pwm316.h
deleted file mode 100644
index fbc1256..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm316.h
+++ /dev/null
@@ -1,1223 +0,0 @@
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm316.h - definitions for AT90PWM316 */
-
-#ifndef _AVR_IO90PWM316_H_
-#define _AVR_IO90PWM316_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm316.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-#define PINE0   0
-#define PINE1   1
-#define PINE2   2
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE0    0
-#define DDE1    1
-#define DDE2    2
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-#define PE0     0
-#define PE1     1
-#define PE2     2
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0   /* Overflow Flag */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define OCF0B   2   /* Output Compare Flag 0B */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0   /* Overflow Flag */
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define ICF1    5   /* Input Capture Flag 1 */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-#define INTF0   0
-#define INTF1   1
-#define INTF2   2
-#define INTF3   3
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0   /* External Interrupt Request 0 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0   /* EEPROM Read Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-#define EEDR0   0
-#define EEDR1   1
-#define EEDR2   2
-#define EEDR3   3
-#define EEDR4   4
-#define EEDR5   5
-#define EEDR6   6
-#define EEDR7   7
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEAR0   0
-#define EEAR1   1
-#define EEAR2   2
-#define EEAR3   3
-#define EEAR4   4
-#define EEAR5   5
-#define EEAR6   6
-#define EEAR7   7
-#define EEARH   _SFR_IO8(0x22)
-#define EEAR8   0
-#define EEAR9   1
-#define EEAR10  2
-#define EEAR11  3
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-#define WGM00   0   /* Waveform Generation Mode */
-#define WGM01   1   /* Waveform Generation Mode */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-#define CS00    0   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS02    2   /* Clock Select */
-#define WGM02   3   /* Waveform Generation Mode */
-#define FOC0B   6   /* Force Output Compare B */
-#define FOC0A   7   /* Force Output Compare A */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-#define TCNT00  0
-#define TCNT01  1
-#define TCNT02  2
-#define TCNT03  3
-#define TCNT04  4
-#define TCNT05  5
-#define TCNT06  6
-#define TCNT07  7
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-#define OCR0A0  0
-#define OCR0A1  1
-#define OCR0A2  2
-#define OCR0A3  3
-#define OCR0A4  4
-#define OCR0A5  5
-#define OCR0A6  6
-#define OCR0A7  7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-#define OCR0B0  0
-#define OCR0B1  1
-#define OCR0B2  2
-#define OCR0B3  3
-#define OCR0B4  4
-#define OCR0B5  5
-#define OCR0B6  6
-#define OCR0B7  7
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-#define PLOCK   0   /* PLL Lock Detector */
-#define PLLE    1   /* PLL Enable */
-#define PLLF    2   /* PLL Factor */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define CPHA    2   /* Clock Phase */
-#define CPOL    3   /* Clock polarity */
-#define MSTR    4   /* Master/Slave Select */
-#define DORD    5   /* Data Order */
-#define SPE     6   /* SPI Enable */
-#define SPIE    7   /* SPI Interrupt Enable */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0   /* Double SPI Speed Bit */
-#define WCOL    6   /* Write Collision Flag */
-#define SPIF    7   /* SPI Interrupt Flag */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-#define SPD0    0
-#define SPD1    1
-#define SPD2    2
-#define SPD3    3
-#define SPD4    4
-#define SPD5    5
-#define SPD6    6
-#define SPD7    7
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0   /* Sleep Enable */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM2     3   /* Sleep Mode Select bit2 */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0   /* Power-on reset flag */
-#define EXTRF   1   /* External Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define WDRF    3   /* Watchdog Reset Flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-#define IVCE    0   /* Interrupt Vector Change Enable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define PUD     4   /* Pull-up disable */
-#define SPIPS   7   /* SPI Pin Select */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0   /* Store Program Memory Enable */
-#define PGERS   1   /* Page Erase */
-#define PGWRT   2   /* Page Write */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define SPMIE   7   /* SPM Interrupt Enable */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDE     3   /* Watchdog Enable */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC   0   /* Power Reduction ADC */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-#define CAL0    0
-#define CAL1    1
-#define CAL2    2
-#define CAL3    3
-#define CAL4    4
-#define CAL5    5
-#define CAL6    6
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define ISC20   4
-#define ISC21   5
-#define ISC30   6
-#define ISC31   7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0   /* Overflow Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0   /* Overflow Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0  4
-#define AMP0G1  5
-#define AMP0IS  6
-#define AMP0EN  7
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0  4
-#define AMP1G1  5
-#define AMP1IS  6
-#define AMP1EN  7
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADEN    7   /* ADC Enable */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADHSM   7   /* ADC High Speed Mode */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define ADLAR   5   /* Left Adjust Result */
-#define REFS0   6   /* Reference Selection bit0 */
-#define REFS1   7   /* Reference Selection bit1 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0   /* ADC0 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-#define ADC8D   0   /* ADC8 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define AMP0ND  3
-#define AMP0PD  4
-#define ACMP0D  5
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-#define WGM10   0   /* Waveform Generation Mode */
-#define WGM11   1   /* Waveform Generation Mode */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define WGM12   3   /* Waveform Generation Mode */
-#define WGM13   4   /* Waveform Generation Mode */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6   /* Force Output Compare for Channel B */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT10  0
-#define TCNT11  1
-#define TCNT12  2
-#define TCNT13  3
-#define TCNT14  4
-#define TCNT15  5
-#define TCNT16  6
-#define TCNT17  7
-#define TCNT1H  _SFR_MEM8(0x85)
-#define TCNT18  0
-#define TCNT19  1
-#define TCNT110 2
-#define TCNT111 3
-#define TCNT112 4
-#define TCNT113 5
-#define TCNT114 6
-#define TCNT115 7
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-#define ICR1H   _SFR_MEM8(0x87)
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1A0  0
-#define OCR1A1  1
-#define OCR1A2  2
-#define OCR1A3  3
-#define OCR1A4  4
-#define OCR1A5  5
-#define OCR1A6  6
-#define OCR1A7  7
-#define OCR1AH  _SFR_MEM8(0x89)
-#define OCR1A8  0
-#define OCR1A9  1
-#define OCR1A10 2
-#define OCR1A11 3
-#define OCR1A12 4
-#define OCR1A13 5
-#define OCR1A14 6
-#define OCR1A15 7
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1B0  0
-#define OCR1B1  1
-#define OCR1B2  2
-#define OCR1B3  3
-#define OCR1B4  4
-#define OCR1B5  5
-#define OCR1B6  6
-#define OCR1B7  7
-#define OCR1BH  _SFR_MEM8(0x8B)
-#define OCR1B8  0
-#define OCR1B9  1
-#define OCR1B10 2
-#define OCR1B11 3
-#define OCR1B12 4
-#define OCR1B13 5
-#define OCR1B14 6
-#define OCR1B15 7
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define POAC0B  7   /* PSC0 Output B Activity */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-#define PEOP1   0
-#define PRN10   1
-#define PRN11   2
-#define PEV1A   3
-#define PEV1B   4
-#define PSEI1   5
-#define POAC1A  6
-#define POAC1B  7
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define POAC2B  7   /* PSC2 Output B Activity */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-#define DAEN    0   /* Digital to Analog Enable bit */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0   /* Multi-processor Communication Mode */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define UPE     2   /* USART Parity Error */
-#define DOR     3   /* Data OverRun */
-#define FE      4   /* Frame Error */
-#define UDRE    5   /* USART Data Register Empty */
-#define TXC     6   /* USART Transmit Complete */
-#define RXC     7   /* USART Receive Complete */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-#define TXB8    0   /* Transmit Data Bit 8 */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define UCSZ2   2   /* Character Size */
-#define TXEN    3   /* Transmitter Enable */
-#define RXEN    4   /* Receiver Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0   /* Clock Polarity */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCSZ1   2   /* Character Size bit1 */
-#define USBS    3   /* Stop Bit Select */
-#define UPM0    4   /* Parity Mode bit0 */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UMSEL   6   /* USART Mode Select */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-#define BODR    0   /* Bit Order */
-#define EMCH    1   /* Manchester mode */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EUSART  4   /* EUSART Enable Bit */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-#define STP0    0   /* Stop bits values bit0 */
-#define STP1    1   /* Stop bits values bit1 */
-#define F1617   2
-#define FEM     3   /* Frame Error Manchester */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-#define PRUN0   0   /* PSC 0 Run */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-#define PICR0L  _SFR_MEM8(0xDE)
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1     2
-#define PMODE10  3
-#define PMODE11  4
-#define PLOCK1   5
-#define PALOCK1  6
-#define PFIFTY1  7
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-#define PRUN1  0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1  5
-#define PPRE10 6
-#define PPRE11 7
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A  7
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B  7
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-#define PICR1L  _SFR_MEM8(0xEE)
-#define PICR1H  _SFR_MEM8(0xEF)
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define POS22   6   /* PSCOUT22 Selection */
-#define POS23   7   /* PSCOUT23 Selection */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-#define PRUN2   0   /* PSC 2 Run */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-#define PICR2L  _SFR_MEM8(0xFE)
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-
-
-/* Interrupt Vectors */
-/* Interrupt 0 is the reset vector. */
-
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect     _VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect       _VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect     _VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect       _VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect     _VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect       _VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect _VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect _VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect _VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect          _VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect   _VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect  _VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect  _VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect    _VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect _VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect    _VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect           _VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect          _VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect       _VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect      _VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect    _VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect      _VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect          _VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect           _VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect      _VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect  _VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect          _VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect     _VECTOR(31)
-
-#define _VECTORS_SIZE   (4 * 32)
-
-/* Constants */
-
-#define RAMEND         0x4FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x3FFF
-#define SPM_PAGESIZE   128
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV    (unsigned char)~_BV(4)
-#define FUSE_PSC0RB   (unsigned char)~_BV(5)
-#define FUSE_PSC1RB   (unsigned char)~_BV(6)
-#define FUSE_PSC2RB   (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x83
-
-
-#endif /* _AVR_IO90PWM316_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm3b.h b/cpukit/score/cpu/avr/avr/io90pwm3b.h
deleted file mode 100644
index 5b1a753..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm3b.h
+++ /dev/null
@@ -1,1408 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM3B
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/io90pwm3b.h - definitions for AT90PWM3B */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm3b.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IO90PWM3B_H_
-#define _AVR_IO90PWM3B_H_ 1
-
-/**
- * @defgroup AvrDef_io90pwm3b AT90PWM3B Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-      
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define GPIOR1 _SFR_IO8(0x19)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1A)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define GPIOR3 _SFR_IO8(0x1B)
-#define GPIOR30 0
-#define GPIOR31 1
-#define GPIOR32 2
-#define GPIOR33 3
-#define GPIOR34 4
-#define GPIOR35 5
-#define GPIOR36 6
-#define GPIOR37 7
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSR10 0
-#define PSRSYNC 0
-#define ICPSEL1 2
-#define TSM 3
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define OCR0_0 0    /* Deprecated */
-#define OCR0_1 1    /* Deprecated */
-#define OCR0_2 2    /* Deprecated */
-#define OCR0_3 3    /* Deprecated */
-#define OCR0_4 4    /* Deprecated */
-#define OCR0_5 5    /* Deprecated */
-#define OCR0_6 6    /* Deprecated */
-#define OCR0_7 7    /* Deprecated */
-
-#define PLLCSR _SFR_IO8(0x29)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF 2
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define AC0O 0
-#define AC1O 1
-#define AC2O 2
-#define AC0IF 4
-#define AC1IF 5
-#define AC2IF 6
-#define ACCKDIV 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define SPIPS 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM0 3
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC1 6
-#define PRPSC2 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1TS0 0
-#define AMP1TS1 1
-#define AMP1G0 4
-#define AMP1G1 5
-#define AMP1IS 6
-#define AMP1EN 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADASCR 4
-#define ADHSM 7
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define ADC8D 0
-#define ADC9D 1
-#define ADC10D 2
-#define AMP0ND 3
-#define AMP0PD 4
-#define ACMP0D 5
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define PIFR0 _SFR_MEM8(0xA0)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define PSEI0 5
-#define POAC0A 6
-#define POAC0B 7
-
-#define PIM0 _SFR_MEM8(0xA1)
-#define PEOPE0 0
-#define PEVE0A 3
-#define PEVE0B 4
-#define PSEIE0 5
-
-#define PIFR1 _SFR_MEM8(0xA2)
-#define PEOP1 0
-#define PRN10 1
-#define PRN11 2
-#define PEV1A 3
-#define PEV1B 4
-#define PSEI1 5
-#define POAC1A 6
-#define POAC1B 7
-
-#define PIM1 _SFR_MEM8(0xA3)
-#define PEOPE1 0
-#define PEVE1A 3
-#define PEVE1B 4
-#define PSEIE1 5
-
-#define PIFR2 _SFR_MEM8(0xA4)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PIM2 _SFR_MEM8(0xA5)
-#define PEOPE2 0
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define DACON _SFR_MEM8(0xAA)
-#define DAEN 0
-#define DAOE 1
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DAC _SFR_MEM16(0xAB)
-
-#define DACL _SFR_MEM8(0xAB)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_MEM8(0xAC)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define AC0CON _SFR_MEM8(0xAD)
-#define AC0M0 0
-#define AC0M1 1
-#define AC0M2 2
-#define AC0IS0 4
-#define AC0IS1 5
-#define AC0IE 6
-#define AC0EN 7
-
-#define AC1CON _SFR_MEM8(0xAE)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1ICE 3
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0xAF)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define UCSRA _SFR_MEM8(0xC0)
-#define MPCM 0
-#define U2X 1
-#define UPE 2
-#define DOR 3
-#define FE 4
-#define UDRE 5
-#define TXC 6
-#define RXC 7
-
-#define UCSRB _SFR_MEM8(0xC1)
-#define TXB8 0
-#define RXB8 1
-#define UCSZ2 2
-#define TXEN 3
-#define RXEN 4
-#define UDRIE 5
-#define TXCIE 6
-#define RXCIE 7
-
-#define UCSRC _SFR_MEM8(0xC2)
-#define UCPOL 0
-#define UCSZ0 1
-#define UCSZ1 2
-#define USBS 3
-#define UPM0 4
-#define UPM1 5
-#define UMSEL0 6
-
-#define UBRR _SFR_MEM16(0xC4)
-
-#define UBRRL _SFR_MEM8(0xC4)
-#define UBRR0 0
-#define UBRR1 1
-#define UBRR2 2
-#define UBRR3 3
-#define UBRR4 4
-#define UBRR5 5
-#define UBRR6 6
-#define UBRR7 7
-
-#define UBRRH _SFR_MEM8(0xC5)
-#define UBRR8 0
-#define UBRR9 1
-#define UBRR10 2
-#define UBRR11 3
-
-#define UDR _SFR_MEM8(0xC6)
-#define UDR0 0
-#define UDR1 1
-#define UDR2 2
-#define UDR3 3
-#define UDR4 4
-#define UDR5 5
-#define UDR6 6
-#define UDR7 7
-
-#define EUCSRA _SFR_MEM8(0xC8)
-#define URxS0 0
-#define URxS1 1
-#define URxS2 2
-#define URxS3 3
-#define UTxS0 4
-#define UTxS1 5
-#define UTxS2 6
-#define UTxS3 7
-
-#define EUCSRB _SFR_MEM8(0xC9)
-#define BODR 0
-#define EMCH 1
-#define EUSBS 3
-#define EUSART 4
-
-#define EUCSRC _SFR_MEM8(0xCA)
-#define STP0 0
-#define STP1 1
-#define F1617 2
-#define FEM 3 
-
-#define MUBRR _SFR_MEM16(0xCC)
-
-#define MUBRRL _SFR_MEM8(0xCC)
-#define MUBRR0 0
-#define MUBRR1 1
-#define MUBRR2 2
-#define MUBRR3 3
-#define MUBRR4 4
-#define MUBRR5 5
-#define MUBRR6 6
-#define MUBRR7 7
-
-#define MUBRRH _SFR_MEM8(0xCD)
-#define MUBRR8 0
-#define MUBRR9 1
-#define MUBRR10 2
-#define MUBRR11 3
-#define MUBRR12 4
-#define MUBRR13 5
-#define MUBRR14 6
-#define MUBRR15 7
-
-#define EUDR _SFR_MEM8(0xCE)
-#define EUDR0 0
-#define EUDR1 1
-#define EUDR2 2
-#define EUDR3 3
-#define EUDR4 4
-#define EUDR5 5
-#define EUDR6 6
-#define EUDR7 7
-
-#define PSOC0 _SFR_MEM8(0xD0)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-
-#define OCR0SA _SFR_MEM16(0xD2)
-
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0xD3)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define OCR0RA _SFR_MEM16(0xD4)
-
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_MEM8(0xD5)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#define OCR0SB _SFR_MEM16(0xD6)
-
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_MEM8(0xD7)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_MEM16(0xD8)
-
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_MEM8(0xD9)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define PCNF0 _SFR_MEM8(0xDA)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_MEM8(0xDB)
-#define PRUN0 0
-#define PCCYC0 1
-#define PARUN0 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM0 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PFRC0A _SFR_MEM8(0xDC)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0xDD)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define PICR0 _SFR_MEM16(0xDE)
-
-#define PICR0L _SFR_MEM8(0xDE)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0xDF)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC1 _SFR_MEM8(0xE0)
-#define POEN1A 0
-#define POEN1B 2
-#define PSYNC1_0 4
-#define PSYNC1_1 5
-
-#define OCR1SA _SFR_MEM16(0xE2)
-
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SA_0 0
-#define OCR1SA_1 1
-#define OCR1SA_2 2
-#define OCR1SA_3 3
-#define OCR1SA_4 4
-#define OCR1SA_5 5
-#define OCR1SA_6 6
-#define OCR1SA_7 7
-
-#define OCR1SAH _SFR_MEM8(0xE3)
-#define OCR1SA_8 0
-#define OCR1SA_9 1
-#define OCR1SA_10 2
-#define OCR1SA_11 3
-
-#define OCR1RA _SFR_MEM16(0xE4)
-
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RA_0 0
-#define OCR1RA_1 1
-#define OCR1RA_2 2
-#define OCR1RA_3 3
-#define OCR1RA_4 4
-#define OCR1RA_5 5
-#define OCR1RA_6 6
-#define OCR1RA_7 7
-
-#define OCR1RAH _SFR_MEM8(0xE5)
-#define OCR1RA_8 0
-#define OCR1RA_9 1
-#define OCR1RA_10 2
-#define OCR1RA_11 3
-
-#define OCR1SB _SFR_MEM16(0xE6)
-
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SB_0 0
-#define OCR1SB_1 1
-#define OCR1SB_2 2
-#define OCR1SB_3 3
-#define OCR1SB_4 4
-#define OCR1SB_5 5
-#define OCR1SB_6 6
-#define OCR1SB_7 7
-
-#define OCR1SBH _SFR_MEM8(0xE7)
-#define OCR1SB_8 0
-#define OCR1SB_9 1
-#define OCR1SB_10 2
-#define OCR1SB_11 3
-
-#define OCR1RB _SFR_MEM16(0xE8)
-
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RB_0 0
-#define OCR1RB_1 1
-#define OCR1RB_2 2
-#define OCR1RB_3 3
-#define OCR1RB_4 4
-#define OCR1RB_5 5
-#define OCR1RB_6 6
-#define OCR1RB_7 7
-
-#define OCR1RBH _SFR_MEM8(0xE9)
-#define OCR1RB_8 0
-#define OCR1RB_9 1
-#define OCR1RB_10 2
-#define OCR1RB_11 3
-#define OCR1RB_12 4
-#define OCR1RB_13 5
-#define OCR1RB_14 6
-#define OCR1RB_15 7
-
-#define PCNF1 _SFR_MEM8(0xEA)
-#define PCLKSEL1 1
-#define POP1 2
-#define PMODE10 3
-#define PMODE11 4
-#define PLOCK1 5
-#define PALOCK1 6
-#define PFIFTY1 7
-
-#define PCTL1 _SFR_MEM8(0xEB)
-#define PRUN1 0
-#define PCCYC1 1
-#define PARUN1 2
-#define PAOC1A 3
-#define PAOC1B 4
-#define PBFM1 5
-#define PPRE10 6
-#define PPRE11 7
-
-#define PFRC1A _SFR_MEM8(0xEC)
-#define PRFM1A0 0
-#define PRFM1A1 1
-#define PRFM1A2 2
-#define PRFM1A3 3
-#define PFLTE1A 4
-#define PELEV1A 5
-#define PISEL1A 6
-#define PCAE1A 7
-
-#define PFRC1B _SFR_MEM8(0xED)
-#define PRFM1B0 0
-#define PRFM1B1 1
-#define PRFM1B2 2
-#define PRFM1B3 3
-#define PFLTE1B 4
-#define PELEV1B 5
-#define PISEL1B 6
-#define PCAE1B 7
-
-#define PICR1 _SFR_MEM16(0xEE)
-
-#define PICR1L _SFR_MEM8(0xEE)
-#define PICR1_0 0
-#define PICR1_1 1
-#define PICR1_2 2
-#define PICR1_3 3
-#define PICR1_4 4
-#define PICR1_5 5
-#define PICR1_6 6
-#define PICR1_7 7
-
-#define PICR1H _SFR_MEM8(0xEF)
-#define PICR1_8 0
-#define PICR1_9 1
-#define PICR1_10 2
-#define PICR1_11 3
-#define PCST1 7
-
-#define PSOC2 _SFR_MEM8(0xF0)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0xF1)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define OCR2SA _SFR_MEM16(0xF2)
-
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0xF3)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define OCR2RA _SFR_MEM16(0xF4)
-
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_MEM8(0xF5)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define OCR2SB _SFR_MEM16(0xF6)
-
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_MEM8(0xF7)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_MEM16(0xF8)
-
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_MEM8(0xF9)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define PCNF2 _SFR_MEM8(0xFA)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_MEM8(0xFB)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define PFRC2A _SFR_MEM8(0xFC)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0xFD)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR2 _SFR_MEM16(0xFE)
-
-#define PICR2L _SFR_MEM8(0xFE)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0xFF)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-
-
-/* Interrupt Vectors */
-/* Interrupt vector 0 is the reset vector. */
-#define PSC2_CAPT_vect      _VECTOR(1)   /* PSC2 Capture Event */
-#define PSC2_EC_vect        _VECTOR(2)   /* PSC2 End Cycle */
-#define PSC1_CAPT_vect      _VECTOR(3)   /* PSC1 Capture Event */
-#define PSC1_EC_vect        _VECTOR(4)   /* PSC1 End Cycle */
-#define PSC0_CAPT_vect      _VECTOR(5)   /* PSC0 Capture Event */
-#define PSC0_EC_vect        _VECTOR(6)   /* PSC0 End Cycle */
-#define ANALOG_COMP_0_vect  _VECTOR(7)   /* Analog Comparator 0 */
-#define ANALOG_COMP_1_vect  _VECTOR(8)   /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect  _VECTOR(9)   /* Analog Comparator 2 */
-#define INT0_vect           _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect    _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect   _VECTOR(12)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect   _VECTOR(13)  /* Timer/Counter Compare Match B */
-/* Vector 14, Reserved */
-#define TIMER1_OVF_vect     _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect   _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_OVF_vect     _VECTOR(17)  /* Timer/Counter0 Overflow */
-#define ADC_vect            _VECTOR(18)  /* ADC Conversion Complete */
-#define INT1_vect           _VECTOR(19)  /* External Interrupt Request 1 */
-#define SPI_STC_vect        _VECTOR(20)  /* SPI Serial Transfer Complete */
-#define USART_RX_vect       _VECTOR(21)  /* USART, Rx Complete */
-#define USART_UDRE_vect     _VECTOR(22)  /* USART Data Register Empty */
-#define USART_TX_vect       _VECTOR(23)  /* USART, Tx Complete */
-#define INT2_vect           _VECTOR(24)  /* External Interrupt Request 2 */
-#define WDT_vect            _VECTOR(25)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect       _VECTOR(26)  /* EEPROM Ready */
-#define TIMER0_COMPB_vect   _VECTOR(27)  /* Timer Counter 0 Compare Match B */
-#define INT3_vect           _VECTOR(28)  /* External Interrupt Request 3 */
-/* Vector 29, Reserved */
-/* Vector 30, Reserved */
-#define SPM_READY_vect      _VECTOR(31)  /* Store Program Memory Read */
-
-#define _VECTORS_SIZE 64
-
-
-
-/* Memory Sizes */
-#define RAMEND         0x2FF
-#define XRAMSIZE       0
-#define XRAMEND        RAMEND
-#define E2END          0x1FF
-#define E2PAGESIZE     4
-#define FLASHEND       0x1FFF
-#define SPM_PAGESIZE   32
-
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
-
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_PSCRV   (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC1RB  (unsigned char)~_BV(6)  /* PSC1 Reset Behaviour */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x83
-
-/** @} */
-
-#endif /* _AVR_IO90PWM3B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm81.h b/cpukit/score/cpu/avr/avr/io90pwm81.h
deleted file mode 100644
index b2faea8..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwm81.h
+++ /dev/null
@@ -1,1040 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM81
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwm81.h - definitions for AT90PWM81 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwm81.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_io90pwm81 AT90PWM81 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#ifndef _AVR_AT90PWM81_H_
-#define _AVR_AT90PWM81_H_ 1
-
-
-/* Registers and associated bit numbers. */
-
-#define ACSR _SFR_IO8(0x00)
-#define AC1O 1
-#define AC2O 2
-#define AC3O 3
-#define AC1IF 5
-#define AC2IF 6
-#define AC3IF 7
-
-#define TIMSK1 _SFR_IO8(0x01)
-#define TOIE1 0
-#define ICIE1 5
-
-#define TIFR1 _SFR_IO8(0x02)
-#define TOV1 0
-#define ICF1 5
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define ADCSRA _SFR_IO8(0x06)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_IO8(0x07)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ADTS3 3
-#define ADSSEN 4
-#define ADNCDIS 6
-#define ADHSM 7
-
-#define ADMUX _SFR_IO8(0x08)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-
-#define PIM0 _SFR_IO8(0x0F)
-#define PEOPE0 0
-#define PEOEPE0 1
-#define PEVE0A 3
-#define PEVE0B 4
-
-#define PIFR0 _SFR_IO8(0x10)
-#define PEOP0 0
-#define PRN00 1
-#define PRN01 2
-#define PEV0A 3
-#define PEV0B 4
-#define POAC0A 6
-#define POAC0B 7
-
-#define PCNF0 _SFR_IO8(0x11)
-#define PCLKSEL0 1
-#define POP0 2
-#define PMODE00 3
-#define PMODE01 4
-#define PLOCK0 5
-#define PALOCK0 6
-#define PFIFTY0 7
-
-#define PCTL0 _SFR_IO8(0x12)
-#define PRUN0 0
-#define PCCYC0 1
-#define PBFM00 2
-#define PAOC0A 3
-#define PAOC0B 4
-#define PBFM01 5
-#define PPRE00 6
-#define PPRE01 7
-
-#define PIM2 _SFR_IO8(0x13)
-#define PEOPE2 0
-#define PEOEPE2 1
-#define PEVE2A 3
-#define PEVE2B 4
-#define PSEIE2 5
-
-#define PIFR2 _SFR_IO8(0x14)
-#define PEOP2 0
-#define PRN20 1
-#define PRN21 2
-#define PEV2A 3
-#define PEV2B 4
-#define PSEI2 5
-#define POAC2A 6
-#define POAC2B 7
-
-#define PCNF2 _SFR_IO8(0x15)
-#define POME2 0
-#define PCLKSEL2 1
-#define POP2 2
-#define PMODE20 3
-#define PMODE21 4
-#define PLOCK2 5
-#define PALOCK2 6
-#define PFIFTY2 7
-
-#define PCTL2 _SFR_IO8(0x16)
-#define PRUN2 0
-#define PCCYC2 1
-#define PARUN2 2
-#define PAOC2A 3
-#define PAOC2B 4
-#define PBFM2 5
-#define PPRE20 6
-#define PPRE21 7
-
-#define SPCR _SFR_IO8(0x17)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x18)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define GPIOR0 _SFR_IO8(0x19)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define GPIOR1 _SFR_IO8(0x1A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x1B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define EECR _SFR_IO8(0x1C)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-#define EEPAGE 6
-#define NVMBSY 7
-
-#define EEDR _SFR_IO8(0x1D)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x1E)
-
-#define EEARL _SFR_IO8(0x1E)
-#define EEARL0 0
-#define EEARL1 1
-#define EEARL2 2
-#define EEARL3 3
-#define EEARL4 4
-#define EEARL5 5
-#define EEARL6 6
-#define EEARL7 7
-
-#define EEARH _SFR_IO8(0x1F)
-#define EEAR8 0
-
-#define EIFR _SFR_IO8(0x20)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x21)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define OCR0SB _SFR_IO16(0x22)
-
-#define OCR0SBL _SFR_IO8(0x22)
-#define OCR0SB_0 0
-#define OCR0SB_1 1
-#define OCR0SB_2 2
-#define OCR0SB_3 3
-#define OCR0SB_4 4
-#define OCR0SB_5 5
-#define OCR0SB_6 6
-#define OCR0SB_7 7
-
-#define OCR0SBH _SFR_IO8(0x23)
-#define OCR0SB_8 0
-#define OCR0SB_9 1
-#define OCR0SB_00 2
-#define OCR0SB_01 3
-
-#define OCR0RB _SFR_IO16(0x24)
-
-#define OCR0RBL _SFR_IO8(0x24)
-#define OCR0RB_0 0
-#define OCR0RB_1 1
-#define OCR0RB_2 2
-#define OCR0RB_3 3
-#define OCR0RB_4 4
-#define OCR0RB_5 5
-#define OCR0RB_6 6
-#define OCR0RB_7 7
-
-#define OCR0RBH _SFR_IO8(0x25)
-#define OCR0RB_8 0
-#define OCR0RB_9 1
-#define OCR0RB_00 2
-#define OCR0RB_01 3
-#define OCR0RB_02 4
-#define OCR0RB_03 5
-#define OCR0RB_04 6
-#define OCR0RB_05 7
-
-#define OCR2SB _SFR_IO16(0x26)
-
-#define OCR2SBL _SFR_IO8(0x26)
-#define OCR2SB_0 0
-#define OCR2SB_1 1
-#define OCR2SB_2 2
-#define OCR2SB_3 3
-#define OCR2SB_4 4
-#define OCR2SB_5 5
-#define OCR2SB_6 6
-#define OCR2SB_7 7
-
-#define OCR2SBH _SFR_IO8(0x27)
-#define OCR2SB_8 0
-#define OCR2SB_9 1
-#define OCR2SB_10 2
-#define OCR2SB_11 3
-
-#define OCR2RB _SFR_IO16(0x28)
-
-#define OCR2RBL _SFR_IO8(0x28)
-#define OCR2RB_0 0
-#define OCR2RB_1 1
-#define OCR2RB_2 2
-#define OCR2RB_3 3
-#define OCR2RB_4 4
-#define OCR2RB_5 5
-#define OCR2RB_6 6
-#define OCR2RB_7 7
-
-#define OCR2RBH _SFR_IO8(0x29)
-#define OCR2RB_8 0
-#define OCR2RB_9 1
-#define OCR2RB_10 2
-#define OCR2RB_11 3
-#define OCR2RB_12 4
-#define OCR2RB_13 5
-#define OCR2RB_14 6
-#define OCR2RB_15 7
-
-#define OCR0RA _SFR_IO16(0x2A)
-
-#define OCR0RAL _SFR_IO8(0x2A)
-#define OCR0RA_0 0
-#define OCR0RA_1 1
-#define OCR0RA_2 2
-#define OCR0RA_3 3
-#define OCR0RA_4 4
-#define OCR0RA_5 5
-#define OCR0RA_6 6
-#define OCR0RA_7 7
-
-#define OCR0RAH _SFR_IO8(0x2B)
-#define OCR0RA_8 0
-#define OCR0RA_9 1
-#define OCR0RA_00 2
-#define OCR0RA_01 3
-
-#ifndef __ASSEMBLER__
-#define ADC _SFR_IO16(0x2C)
-#endif
-#define ADCW _SFR_IO16(0x2C)
-
-#define ADCL _SFR_IO8(0x2C)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_IO8(0x2D)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define OCR2RA _SFR_IO16(0x2E)
-
-#define OCR2RAL _SFR_IO8(0x2E)
-#define OCR2RA_0 0
-#define OCR2RA_1 1
-#define OCR2RA_2 2
-#define OCR2RA_3 3
-#define OCR2RA_4 4
-#define OCR2RA_5 5
-#define OCR2RA_6 6
-#define OCR2RA_7 7
-
-#define OCR2RAH _SFR_IO8(0x2F)
-#define OCR2RA_8 0
-#define OCR2RA_9 1
-#define OCR2RA_10 2
-#define OCR2RA_11 3
-
-#define DWDR _SFR_IO8(0x31)
-
-#define MSMCR _SFR_IO8(0x32)
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define CKRC81 2
-#define RSTDIS 3
-#define PUD 4
-
-#define SPDR _SFR_IO8(0x36)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define DAC _SFR_IO16(0x38)
-
-#define DACL _SFR_IO8(0x38)
-#define DACL0 0
-#define DACL1 1
-#define DACL2 2
-#define DACL3 3
-#define DACL4 4
-#define DACL5 5
-#define DACL6 6
-#define DACL7 7
-
-#define DACH _SFR_IO8(0x39)
-#define DACH0 0
-#define DACH1 1
-#define DACH2 2
-#define DACH3 3
-#define DACH4 4
-#define DACH5 5
-#define DACH6 6
-#define DACH7 7
-
-#define TCNT1 _SFR_IO16(0x3A)
-
-#define TCNT1L _SFR_IO8(0x3A)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_IO8(0x3B)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define OCR0SA _SFR_MEM16(0x60)
-
-#define OCR0SAL _SFR_MEM8(0x60)
-#define OCR0SA_0 0
-#define OCR0SA_1 1
-#define OCR0SA_2 2
-#define OCR0SA_3 3
-#define OCR0SA_4 4
-#define OCR0SA_5 5
-#define OCR0SA_6 6
-#define OCR0SA_7 7
-
-#define OCR0SAH _SFR_MEM8(0x61)
-#define OCR0SA_8 0
-#define OCR0SA_9 1
-#define OCR0SA_00 2
-#define OCR0SA_01 3
-
-#define PFRC0A _SFR_MEM8(0x62)
-#define PRFM0A0 0
-#define PRFM0A1 1
-#define PRFM0A2 2
-#define PRFM0A3 3
-#define PFLTE0A 4
-#define PELEV0A 5
-#define PISEL0A 6
-#define PCAE0A 7
-
-#define PFRC0B _SFR_MEM8(0x63)
-#define PRFM0B0 0
-#define PRFM0B1 1
-#define PRFM0B2 2
-#define PRFM0B3 3
-#define PFLTE0B 4
-#define PELEV0B 5
-#define PISEL0B 6
-#define PCAE0B 7
-
-#define OCR2SA _SFR_MEM16(0x64)
-
-#define OCR2SAL _SFR_MEM8(0x64)
-#define OCR2SA_0 0
-#define OCR2SA_1 1
-#define OCR2SA_2 2
-#define OCR2SA_3 3
-#define OCR2SA_4 4
-#define OCR2SA_5 5
-#define OCR2SA_6 6
-#define OCR2SA_7 7
-
-#define OCR2SAH _SFR_MEM8(0x65)
-#define OCR2SA_8 0
-#define OCR2SA_9 1
-#define OCR2SA_10 2
-#define OCR2SA_11 3
-
-#define PFRC2A _SFR_MEM8(0x66)
-#define PRFM2A0 0
-#define PRFM2A1 1
-#define PRFM2A2 2
-#define PRFM2A3 3
-#define PFLTE2A 4
-#define PELEV2A 5
-#define PISEL2A 6
-#define PCAE2A 7
-
-#define PFRC2B _SFR_MEM8(0x67)
-#define PRFM2B0 0
-#define PRFM2B1 1
-#define PRFM2B2 2
-#define PRFM2B3 3
-#define PFLTE2B 4
-#define PELEV2B 5
-#define PISEL2B 6
-#define PCAE2B 7
-
-#define PICR0 _SFR_MEM16(0x68)
-
-#define PICR0L _SFR_MEM8(0x68)
-#define PICR0_0 0
-#define PICR0_1 1
-#define PICR0_2 2
-#define PICR0_3 3
-#define PICR0_4 4
-#define PICR0_5 5
-#define PICR0_6 6
-#define PICR0_7 7
-
-#define PICR0H _SFR_MEM8(0x69)
-#define PICR0_8 0
-#define PICR0_9 1
-#define PICR0_10 2
-#define PICR0_11 3
-#define PCST0 7
-
-#define PSOC0 _SFR_MEM8(0x6A)
-#define POEN0A 0
-#define POEN0B 2
-#define PSYNC00 4
-#define PSYNC01 5
-#define PISEL0B1 6
-#define PISEL0A1 7
-
-#define PICR2 _SFR_MEM16(0x6C)
-
-#define PICR2L _SFR_MEM8(0x6C)
-#define PICR2_0 0
-#define PICR2_1 1
-#define PICR2_2 2
-#define PICR2_3 3
-#define PICR2_4 4
-#define PICR2_5 5
-#define PICR2_6 6
-#define PICR2_7 7
-
-#define PICR2H _SFR_MEM8(0x6D)
-#define PICR2_8 0
-#define PICR2_9 1
-#define PICR2_10 2
-#define PICR2_11 3
-#define PCST2 7
-
-#define PSOC2 _SFR_MEM8(0x6E)
-#define POEN2A 0
-#define POEN2C 1
-#define POEN2B 2
-#define POEN2D 3
-#define PSYNC2_0 4
-#define PSYNC2_1 5
-#define POS22 6
-#define POS23 7
-
-#define POM2 _SFR_MEM8(0x6F)
-#define POMV2A0 0
-#define POMV2A1 1
-#define POMV2A2 2
-#define POMV2A3 3
-#define POMV2B0 4
-#define POMV2B1 5
-#define POMV2B2 6
-#define POMV2B3 7
-
-#define PCNFE2 _SFR_MEM8(0x70)
-#define PISEL2B1 0
-#define PISEL2A1 1
-#define PELEV2B1 2
-#define PELEV2A1 3
-#define PBFM21 4
-#define PASDLK20 5
-#define PASDLK21 6
-#define PASDLK22 7
-
-#define PASDLY2 _SFR_MEM8(0x71)
-#define PASDLY2_0 0
-#define PASDLY2_1 1
-#define PASDLY2_2 2
-#define PASDLY2_3 3
-#define PASDLY2_4 4
-#define PASDLY2_5 5
-#define PASDLY2_6 6
-#define PASDLY2_7 7
-
-#define DACON _SFR_MEM8(0x76)
-#define DAEN 0
-#define DALA 2
-#define DATS0 4
-#define DATS1 5
-#define DATS2 6
-#define DAATE 7
-
-#define DIDR0 _SFR_MEM8(0x77)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC7D 6
-#define ADC8D 7
-
-#define DIDR1 _SFR_MEM8(0x78)
-#define ADC9D 0
-#define ADC10D 1
-#define AMP0PD 2
-#define ACMP1MD 3
-
-#define AMP0CSR _SFR_MEM8(0x79)
-#define AMP0TS0 0
-#define AMP0TS1 1
-#define AMP0GS 3
-#define AMP0G0 4
-#define AMP0G1 5
-#define AMP0IS 6
-#define AMP0EN 7
-
-#define AC1ECON _SFR_MEM8(0x7A)
-#define AC1H0 0
-#define AC1H1 1
-#define AC1H2 2
-#define AC1ICE 3
-#define AC1OE 4
-#define AC1OI 5
-
-#define AC2ECON _SFR_MEM8(0x7B)
-#define AC2H0 0
-#define AC2H1 1
-#define AC2H2 2
-#define AC2OE 4
-#define AC2OI 5
-
-#define AC3ECON _SFR_MEM8(0x7C)
-#define AC3H0 0
-#define AC3H1 1
-#define AC3H2 2
-#define AC3OE 4
-#define AC3OI 5
-
-#define AC1CON _SFR_MEM8(0x7D)
-#define AC1M0 0
-#define AC1M1 1
-#define AC1M2 2
-#define AC1IS0 4
-#define AC1IS1 5
-#define AC1IE 6
-#define AC1EN 7
-
-#define AC2CON _SFR_MEM8(0x7E)
-#define AC2M0 0
-#define AC2M1 1
-#define AC2M2 2
-#define AC2IS0 4
-#define AC2IS1 5
-#define AC2IE 6
-#define AC2EN 7
-
-#define AC3CON _SFR_MEM8(0x7F)
-#define AC3M0 0
-#define AC3M1 1
-#define AC3M2 2
-#define AC3OEA 3
-#define AC3IS0 4
-#define AC3IS1 5
-#define AC3IE 6
-#define AC3EN 7
-
-#define BGCRR _SFR_MEM8(0x80)
-#define BGCR0 0
-#define BGCR1 1
-#define BGCR2 2
-#define BGCR3 3
-
-#define BGCCR _SFR_MEM8(0x81)
-#define BGCC0 0
-#define BGCC1 1
-#define BGCC2 2
-#define BGCC3 3
-
-#define WDTCSR _SFR_MEM8(0x82)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x83)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define CLKCSR _SFR_MEM8(0x84)
-#define CLKC0 0
-#define CLKC1 1
-#define CLKC2 2
-#define CLKC3 3
-#define CLKRDY 4
-#define CLKCCE 7
-
-#define CLKSELR _SFR_MEM8(0x85)
-#define CKSEL0 0
-#define CKSEL1 1
-#define CKSEL2 2
-#define CKSEL3 3
-#define CSUT0 4
-#define CSUT1 5
-#define COUT 6
-
-#define PRR _SFR_MEM8(0x86)
-#define PRADC 0
-#define PRSPI 2
-#define PRTIM1 4
-#define PRPSC0 5
-#define PRPSC2 7
-
-#define PLLCSR _SFR_MEM8(0x87)
-#define PLOCK 0
-#define PLLE 1
-#define PLLF0 2
-#define PLLF1 3
-#define PLLF2 4
-#define PLLF3 5
-
-#define OSCCAL _SFR_MEM8(0x88)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define EICRA _SFR_MEM8(0x89)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define TCCR1B _SFR_MEM8(0x8A)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define ICR1 _SFR_MEM16(0x8C)
-
-#define ICR1L _SFR_MEM8(0x8C)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x8D)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define PSC2_CAPT_vect_num  1
-#define PSC2_CAPT_vect      _VECTOR(1)  /* PSC2 Capture Event */
-#define PSC2_EC_vect_num  2
-#define PSC2_EC_vect      _VECTOR(2)  /* PSC2 End Cycle */
-#define PSC2_EEC_vect_num  3
-#define PSC2_EEC_vect      _VECTOR(3)  /* PSC2 End Of Enhanced Cycle */
-#define PSC0_CAPT_vect_num  4
-#define PSC0_CAPT_vect      _VECTOR(4)  /* PSC0 Capture Event */
-#define PSC0_EC_vect_num  5
-#define PSC0_EC_vect      _VECTOR(5)  /* PSC0 End Cycle */
-#define PSC0_EEC_vect_num  6
-#define PSC0_EEC_vect      _VECTOR(6)  /* PSC0 End Of Enhanced Cycle */
-#define ANALOG_COMP_1_vect_num  7
-#define ANALOG_COMP_1_vect      _VECTOR(7)  /* Analog Comparator 1 */
-#define ANALOG_COMP_2_vect_num  8
-#define ANALOG_COMP_2_vect      _VECTOR(8)  /* Analog Comparator 2 */
-#define ANALOG_COMP_3_vect_num  9
-#define ANALOG_COMP_3_vect      _VECTOR(9)  /* Analog Comparator 3 */
-#define INT0_vect_num  10
-#define INT0_vect      _VECTOR(10)  /* External Interrupt Request 0 */
-#define TIMER1_CAPT_vect_num  11
-#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
-#define TIMER1_OVF_vect_num  12
-#define TIMER1_OVF_vect      _VECTOR(12)  /* Timer/Counter1 Overflow */
-#define ADC_vect_num  13
-#define ADC_vect      _VECTOR(13)  /* ADC Conversion Complete */
-#define INT1_vect_num  14
-#define INT1_vect      _VECTOR(14)  /* External Interrupt Request 1 */
-#define SPI_STC_vect_num  15
-#define SPI_STC_vect      _VECTOR(15)  /* SPI Serial Transfer Complet */
-#define INT2_vect_num  16
-#define INT2_vect      _VECTOR(16)  /* External Interrupt Request 2 */
-#define WDT_vect_num  17
-#define WDT_vect      _VECTOR(17)  /* Watchdog Timeout Interrupt */
-#define EE_READY_vect_num  18
-#define EE_READY_vect      _VECTOR(18)  /* EEPROM Ready */
-#define SPM_READY_vect_num  19
-#define SPM_READY_vect      _VECTOR(19)  /* Store Program Memory Read */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (20 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x0100)
-#define RAMSIZE      (256)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x1FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0x1FFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock Output */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN  (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown out detector trigger level */
-#define FUSE_PSCINRB  (unsigned char)~_BV(3)  /* PSC2 & PSC0 Input Reset Behavior */
-#define FUSE_PSCRV  (unsigned char)~_BV(4)  /* PSCOUT Reset Value */
-#define FUSE_PSC0RB  (unsigned char)~_BV(5)  /* PSC0 Reset Behaviour */
-#define FUSE_PSC2RBA  (unsigned char)~_BV(6)  /* PSC2 Rest Behavior for out OUT22 & 23 */
-#define FUSE_PSC2RB  (unsigned char)~_BV(7)  /* PSC2 Reset Behaviour */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x88
-
-/** @} */
-
-#endif /* _AVR_AT90PWM81_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/io90pwmx.h b/cpukit/score/cpu/avr/avr/io90pwmx.h
deleted file mode 100644
index b66b65c..0000000
--- a/cpukit/score/cpu/avr/avr/io90pwmx.h
+++ /dev/null
@@ -1,1387 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for AT90PWM2(B) and AT90PWM3(B)
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2005, Andrey Pashchenko
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */
-
-#ifndef _AVR_IO90PWMX_H_
-#define _AVR_IO90PWMX_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90pwmX.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup io90pwmx AT90PWM2(B) and AT90PWM3(B) Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Port B Input Pins Address */
-#define PINB    _SFR_IO8(0x03)
-/* PINB */
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-/* Port B Data Direction Register */
-#define DDRB    _SFR_IO8(0x04)
-/* DDRB */
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-/* Port B Data Register */
-#define PORTB   _SFR_IO8(0x05)
-/* PORTB */
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-/* Port C Input Pins Address */
-#define PINC    _SFR_IO8(0x06)
-/* PINC */
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-/* Port C Data Direction Register */
-#define DDRC    _SFR_IO8(0x07)
-/* DDRC */
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-/* Port C Data Register */
-#define PORTC   _SFR_IO8(0x08)
-/* PORTC */
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-/* Port D Input Pins Address */
-#define PIND    _SFR_IO8(0x09)
-/* PIND */
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-/* Port D Data Direction Register */
-#define DDRD    _SFR_IO8(0x0A)
-/* DDRD */
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-/* Port D Data Register */
-#define PORTD   _SFR_IO8(0x0B)
-/* PORTD */
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-/* Port E Input Pins Address */
-#define PINE    _SFR_IO8(0x0C)
-/* PINE */
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-/* Port E Data Direction Register */
-#define DDRE    _SFR_IO8(0x0D)
-/* DDRE */
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-/* Port E Data Register */
-#define PORTE   _SFR_IO8(0x0E)
-/* PORTE */
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-/* Timer/Counter 0 Interrupt Flag Register */
-#define TIFR0   _SFR_IO8(0x15)
-/* TIFR0 */
-#define OCF0B   2   /* Output Compare Flag 0B */
-#define OCF0A   1   /* Output Compare Flag 0A */
-#define TOV0    0   /* Overflow Flag */
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1   _SFR_IO8(0x16)
-/* TIFR1 */
-#define ICF1    5   /* Input Capture Flag 1 */
-#define OCF1B   2   /* Output Compare Flag 1B*/
-#define OCF1A   1   /* Output Compare Flag 1A*/
-#define TOV1    0   /* Overflow Flag */
-
-/* General Purpose I/O Register 1 */
-#define GPIOR1  _SFR_IO8(0x19)
-/* GPIOR1 */
-#define GPIOR17 7
-#define GPIOR16 6
-#define GPIOR15 5
-#define GPIOR14 4
-#define GPIOR13 3
-#define GPIOR12 2
-#define GPIOR11 1
-#define GPIOR10 0
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2  _SFR_IO8(0x1A)
-/* GPIOR2 */
-#define GPIOR27 7
-#define GPIOR26 6
-#define GPIOR25 5
-#define GPIOR24 4
-#define GPIOR23 3
-#define GPIOR22 2
-#define GPIOR21 1
-#define GPIOR20 0
-
-/* General Purpose I/O Register 3 */
-#define GPIOR3  _SFR_IO8(0x1B)
-/* GPIOR3 */
-#define GPIOR37 7
-#define GPIOR36 6
-#define GPIOR35 5
-#define GPIOR34 4
-#define GPIOR33 3
-#define GPIOR32 2
-#define GPIOR31 1
-#define GPIOR30 0
-
-/* External Interrupt Flag Register */
-#define EIFR    _SFR_IO8(0x1C)
-/* EIFR */
-#define INTF3   3
-#define INTF2   2
-#define INTF1   1
-#define INTF0   0
-
-/* External Interrupt Mask Register */
-#define EIMSK   _SFR_IO8(0x1D)
-/* EIMSK */
-#define INT3    3   /* External Interrupt Request 3 Enable */
-#define INT2    2   /* External Interrupt Request 2 Enable */
-#define INT1    1   /* External Interrupt Request 1 Enable */
-#define INT0    0   /* External Interrupt Request 0 Enable */
-
-/* General Purpose I/O Register 0 */
-#define GPIOR0  _SFR_IO8(0x1E)
-/* GPIOR0 */
-#define GPIOR07 7
-#define GPIOR06 6
-#define GPIOR05 5
-#define GPIOR04 4
-#define GPIOR03 3
-#define GPIOR02 2
-#define GPIOR01 1
-#define GPIOR00 0
-
-/* EEPROM Control Register */
-#define EECR    _SFR_IO8(0x1F)
-/* EECR */
-#define EERIE   3   /* EEPROM Ready Interrupt Enable */
-#define EEMWE   2   /* EEPROM Master Write Enable */
-#define EEWE    1   /* EEPROM Write Enable */
-#define EERE    0   /* EEPROM Read Enable */
-
-/* EEPROM Data Register */
-#define EEDR    _SFR_IO8(0x20)
-/* EEDR */
-#define EEDR7   7
-#define EEDR6   6
-#define EEDR5   5
-#define EEDR4   4
-#define EEDR3   3
-#define EEDR2   2
-#define EEDR1   1
-#define EEDR0   0
-
-/* The EEPROM Address Registers */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0x22)
-/* EEARH */
-#define EEAR11  3
-#define EEAR10  2
-#define EEAR9   1
-#define EEAR8   0
-/* EEARL */
-#define EEAR7   7
-#define EEAR6   6
-#define EEAR5   5
-#define EEAR4   4
-#define EEAR3   3
-#define EEAR2   2
-#define EEAR1   1
-#define EEAR0   0
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* General Timer/Counter Control Register */
-#define GTCCR   _SFR_IO8(0x23)
-/* GTCCR */
-#define TSM     7   /* Timer/Counter Synchronization Mode */
-#define ICPSEL1 6   /* Timer1 Input Capture Selection Bit */
-#define PSR10   0   /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */
-
-/* Timer/Counter Control Register A */
-#define TCCR0A  _SFR_IO8(0x24)
-/* TCCR0A */
-#define COM0A1  7   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0A0  6   /* Compare Output Mode, Phase Correct PWM Mode */
-#define COM0B1  5   /* Compare Output Mode, Fast PWm */
-#define COM0B0  4   /* Compare Output Mode, Fast PWm */
-#define WGM01   1   /* Waveform Generation Mode */
-#define WGM00   0   /* Waveform Generation Mode */
-
-/* Timer/Counter Control Register B */
-#define TCCR0B  _SFR_IO8(0x25)
-/* TCCR0B */
-#define FOC0A   7   /* Force Output Compare A */
-#define FOC0B   6   /* Force Output Compare B */
-#define WGM02   3   /* Waveform Generation Mode */
-#define CS02    2   /* Clock Select */
-#define CS01    1   /* Clock Select */
-#define CS00    0   /* Clock Select */
-
-/* Timer/Counter0 Register */
-#define TCNT0   _SFR_IO8(0x26)
-/* TCNT0 */
-#define TCNT07  7
-#define TCNT06  6
-#define TCNT05  5
-#define TCNT04  4
-#define TCNT03  3
-#define TCNT02  2
-#define TCNT01  1
-#define TCNT00  0
-
-/* Timer/Counter0 Output Compare Register A */
-#define OCR0A   _SFR_IO8(0x27)
-/* OCR0A */
-#define OCR0A7  7
-#define OCR0A6  6
-#define OCR0A5  5
-#define OCR0A4  4
-#define OCR0A3  3
-#define OCR0A2  2
-#define OCR0A1  1
-#define OCR0A0  0
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B   _SFR_IO8(0x28)
-/* OCR0B */
-#define OCR0B7  7
-#define OCR0B6  6
-#define OCR0B5  5
-#define OCR0B4  4
-#define OCR0B3  3
-#define OCR0B2  2
-#define OCR0B1  1
-#define OCR0B0  0
-
-/* PLL Control and Status Register */
-#define PLLCSR  _SFR_IO8(0x29)
-/* PLLCSR */
-#define PCKE    2   /* PCK Enable */
-/* Bit 2 has been renamed in later versions of the datasheet. */
-#define PLLF    2   /* PLL Factor */
-#define PLLE    1   /* PLL Enable */
-#define PLOCK   0   /* PLL Lock Detector */
-
-/* SPI Control Register */
-#define SPCR    _SFR_IO8(0x2C)
-/* SPCR */
-#define SPIE    7   /* SPI Interrupt Enable */
-#define SPE     6   /* SPI Enable */
-#define DORD    5   /* Data Order */
-#define MSTR    4   /* Master/Slave Select */
-#define CPOL    3   /* Clock polarity */
-#define CPHA    2   /* Clock Phase */
-#define SPR1    1   /* SPI Clock Rate Select 1 */
-#define SPR0    0   /* SPI Clock Rate Select 0 */
-
-/* SPI Status Register */
-#define SPSR    _SFR_IO8(0x2D)
-/* SPSR */
-#define SPIF    7   /* SPI Interrupt Flag */
-#define WCOL    6   /* Write Collision Flag */
-#define SPI2X   0   /* Double SPI Speed Bit */
-
-/* SPI Data Register */
-#define SPDR    _SFR_IO8(0x2E)
-/* SPDR */
-#define SPD7    7
-#define SPD6    6
-#define SPD5    5
-#define SPD4    4
-#define SPD3    3
-#define SPD2    2
-#define SPD1    1
-#define SPD0    0
-
-/* Analog Comparator Status Register */
-#define ACSR    _SFR_IO8(0x30)
-/* ACSR */
-#define ACCKDIV 7   /* Analog Comparator Clock Divider */
-#define AC2IF   6   /* Analog Comparator 2 Interrupt Flag Bit */
-#define AC1IF   5   /* Analog Comparator 1 Interrupt Flag Bit */
-#define AC0IF   4   /* Analog Comparator 0 Interrupt Flag Bit */
-#define AC2O    2   /* Analog Comparator 2 Output Bit */
-#define AC1O    1   /* Analog Comparator 1 Output Bit */
-#define AC0O    0   /* Analog Comparator 0 Output Bit */
-
-/* Monitor Data Register */
-#define MONDR   _SFR_IO8(0x31)
-
-/* Monitor Stop Mode Control Register */
-#define MSMCR   _SFR_IO8(0x32)
-
-/* Sleep Mode Control Register */
-#define SMCR    _SFR_IO8(0x33)
-/* SMCR */
-#define SM2     3   /* Sleep Mode Select bit2 */
-#define SM1     2   /* Sleep Mode Select bit1 */
-#define SM0     1   /* Sleep Mode Select bit0 */
-#define SE      0   /* Sleep Enable */
-
-/* MCU Status Register */
-#define MCUSR   _SFR_IO8(0x34)
-/* MCUSR */
-#define WDRF    3   /* Watchdog Reset Flag */
-#define BORF    2   /* Brown-out Reset Flag */
-#define EXTRF   1   /* External Reset Flag */
-#define PORF    0   /* Power-on reset flag */
-
-/* MCU Control Register */
-#define MCUCR   _SFR_IO8(0x35)
-/* MCUCR */
-#define SPIPS   7   /* SPI Pin Select */
-#define PUD     4   /* Pull-up disable */
-#define IVSEL   1   /* Interrupt Vector Select */
-#define IVCE    0   /* Interrupt Vector Change Enable */
-
-/* Store Program Memory Control Register */
-#define SPMCSR  _SFR_IO8(0x37)
-/* SPMCSR */
-#define SPMIE   7   /* SPM Interrupt Enable */
-#define RWWSB   6   /* Read While Write Section Busy */
-#define RWWSRE  4   /* Read While Write section read enable */
-#define BLBSET  3   /* Boot Lock Bit Set */
-#define PGWRT   2   /* Page Write */
-#define PGERS   1   /* Page Erase */
-#define SPMEN   0   /* Store Program Memory Enable */
-
-/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
-/* 0x3F SREG      [defined in <avr/io.h>] */
-
-/* Watchdog Timer Control Register */
-#define WDTCSR  _SFR_MEM8(0x60)
-/* WDTCSR */
-#define WDIF    7   /* Watchdog Timeout Interrupt Flag */
-#define WDIE    6   /* Watchdog Timeout Interrupt Enable */
-#define WDP3    5   /* Watchdog Timer Prescaler bit3 */
-#define WDCE    4   /* Watchdog Change Enable */
-#define WDE     3   /* Watchdog Enable */
-#define WDP2    2   /* Watchdog Timer Prescaler bit2 */
-#define WDP1    1   /* Watchdog Timer Prescaler bit1 */
-#define WDP0    0   /* Watchdog Timer Prescaler bit0 */
-
-/* Clock Prescaler Register */
-#define CLKPR   _SFR_MEM8(0x61)
-/* CLKPR */
-#define CLKPCE  7   /* Clock Prescaler Change Enable */
-#define CLKPS3  3   /* Clock Prescaler Select bit3 */
-#define CLKPS2  2   /* Clock Prescaler Select bit2 */
-#define CLKPS1  1   /* Clock Prescaler Select bit1 */
-#define CLKPS0  0   /* Clock Prescaler Select bit0 */
-
-/* Power Reduction Register */
-#define PRR     _SFR_MEM8(0x64)
-/* PRR */
-#define PRPSC2  7   /* Power Reduction PSC2 */
-#define PRPSC1  6   /* Power Reduction PSC1 */
-#define PRPSC0  5   /* Power Reduction PSC0 */
-#define PRTIM1  4   /* Power Reduction Timer/Counter1 */
-#define PRTIM0  3   /* Power Reduction Timer/Counter0 */
-#define PRSPI   2   /* Power Reduction Serial Peripheral Interface */
-#define PRUSART 1   /* Power Reduction USART */
-#define PRADC   0   /* Power Reduction ADC */
-
-/* Oscillator Calibration Value */
-#define OSCCAL  _SFR_MEM8(0x66)
-/* OSCCAL */
-#define CAL6    6
-#define CAL5    5
-#define CAL4    4
-#define CAL3    3
-#define CAL2    2
-#define CAL1    1
-#define CAL0    0
-
-/* External Interrupt Control Register A */
-#define EICRA   _SFR_MEM8(0x69)
-/* EICRA */
-#define ISC31   7
-#define ISC30   6
-#define ISC21   5
-#define ISC20   4
-#define ISC11   3
-#define ISC10   2
-#define ISC01   1
-#define ISC00   0
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0  _SFR_MEM8(0x6E)
-/* TIMSK0 */
-#define OCIE0B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE0A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE0   0   /* Overflow Interrupt Enable */
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1  _SFR_MEM8(0x6F)
-/* TIMSK1 */
-#define ICIE1   5   /* Input Capture Interrupt Enable */
-#define OCIE1B  2   /* Output Compare Match B Interrupt Enable */
-#define OCIE1A  1   /* Output Compare Match A Interrupt Enable */
-#define TOIE1   0   /* Overflow Interrupt Enable */
-
-/* Amplifier 0 Control and Status register */
-#define AMP0CSR _SFR_MEM8(0x76)
-#define AMP0EN  7
-#define AMP0IS  6
-#define AMP0G1  5
-#define AMP0G0  4
-#define AMP0TS1 1
-#define AMP0TS0 0
-
-/* Amplifier 1 Control and Status register */
-#define AMP1CSR _SFR_MEM8(0x77)
-#define AMP1EN  7
-#define AMP1IS  6
-#define AMP1G1  5
-#define AMP1G0  4
-#define AMP1TS1 1
-#define AMP1TS0 0
-
-/* ADC Result Data Register */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-/* ADC Control and Status Register A */
-#define ADCSRA  _SFR_MEM8(0x7A)
-/* ADCSRA */
-#define ADEN    7   /* ADC Enable */
-#define ADSC    6   /* ADC Start Conversion */
-#define ADATE   5   /* ADC Auto Trigger Enable */
-#define ADIF    4   /* ADC Interrupt Flag */
-#define ADIE    3   /* ADC Interrupt Enable */
-#define ADPS2   2   /* ADC Prescaler Select bit2 */
-#define ADPS1   1   /* ADC Prescaler Select bit1 */
-#define ADPS0   0   /* ADC Prescaler Select bit0 */
-
-/* ADC Control and Status Register B */
-#define ADCSRB  _SFR_MEM8(0x7B)
-/* ADCSRB */
-#define ADHSM   7   /* ADC High Speed Mode */
-#define ADASCR  4
-#define ADTS3   3   /* ADC Auto Trigger Source 3 */
-#define ADTS2   2   /* ADC Auto Trigger Source 2 */
-#define ADTS1   1   /* ADC Auto Trigger Source 1 */
-#define ADTS0   0   /* ADC Auto Trigger Source 0 */
-
-/* ADC multiplexer Selection Register */
-#define ADMUX   _SFR_MEM8(0x7C)
-/* ADMUX */
-#define REFS1   7   /* Reference Selection bit1 */
-#define REFS0   6   /* Reference Selection bit0 */
-#define ADLAR   5   /* Left Adjust Result */
-#define MUX3    3   /* Analog Channel and Gain Selection bit3 */
-#define MUX2    2   /* Analog Channel and Gain Selection bit2 */
-#define MUX1    1   /* Analog Channel and Gain Selection bit1 */
-#define MUX0    0   /* Analog Channel and Gain Selection bit0 */
-
-/* Digital Input Disable Register 0 */
-#define DIDR0   _SFR_MEM8(0x7E)
-/* DIDR0 */
-#define ADC7D   7   /* ADC7 Digital input Disable */
-#define ADC6D   6   /* ADC6 Digital input Disable */
-#define ADC5D   5   /* ADC5 Digital input Disable */
-#define ADC4D   4   /* ADC4 Digital input Disable */
-#define ADC3D   3   /* ADC3 Digital input Disable */
-#define ADC2D   2   /* ADC2 Digital input Disable */
-#define ADC1D   1   /* ADC1 Digital input Disable */
-#define ADC0D   0   /* ADC0 Digital input Disable */
-
-/* Digital Input Disable Register 1 */
-#define DIDR1   _SFR_MEM8(0x7F)
-/* DIDR1 */
-#define ACMP0D  5
-#define AMP0PD  4
-#define AMP0ND  3
-#define ADC10D  2   /* ADC10 Digital input Disable */
-#define ADC9D   1   /* ADC9 Digital input Disable */
-#define ADC8D   0   /* ADC8 Digital input Disable */
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A  _SFR_MEM8(0x80)
-/* TCCR1A */
-#define COM1A1  7   /* Comparet Ouput Mode 1A, bit 1 */
-#define COM1A0  6   /* Comparet Ouput Mode 1A, bit 0 */
-#define COM1B1  5   /* Compare Output Mode 1B, bit 1 */
-#define COM1B0  4   /* Compare Output Mode 1B, bit 0 */
-#define WGM11   1   /* Waveform Generation Mode */
-#define WGM10   0   /* Waveform Generation Mode */
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B  _SFR_MEM8(0x81)
-/* TCCR1B */
-#define ICNC1   7   /* Input Capture 1 Noise Canceler */
-#define ICES1   6   /* Input Capture 1 Edge Select */
-#define WGM13   4   /* Waveform Generation Mode */
-#define WGM12   3   /* Waveform Generation Mode */
-#define CS12    2   /* Prescaler source of Timer/Counter 1 */
-#define CS11    1   /* Prescaler source of Timer/Counter 1 */
-#define CS10    0   /* Prescaler source of Timer/Counter 1 */
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C  _SFR_MEM8(0x82)
-/* TCCR1C */
-#define FOC1A   7   /* Force Output Compare for Channel A */
-#define FOC1B   6   /* Force Output Compare for Channel B */
-
-/* Timer/Counter1 */
-#define TCNT1   _SFR_MEM16(0x84)
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-/* TCNT1H */
-#define TCNT115 7
-#define TCNT114 6
-#define TCNT113 5
-#define TCNT112 4
-#define TCNT111 3
-#define TCNT110 2
-#define TCNT19  1
-#define TCNT18  0
-/* TCNT1L */
-#define TCNT17  7
-#define TCNT16  6
-#define TCNT15  5
-#define TCNT14  4
-#define TCNT13  3
-#define TCNT12  2
-#define TCNT11  1
-#define TCNT10  0
-
-/* Input Capture Register 1 */
-#define ICR1    _SFR_MEM16(0x86)
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-/* ICR1H */
-#define ICR115  7
-#define ICR114  6
-#define ICR113  5
-#define ICR112  4
-#define ICR111  3
-#define ICR110  2
-#define ICR19   1
-#define ICR18   0
-/* ICR1L */
-#define ICR17   7
-#define ICR16   6
-#define ICR15   5
-#define ICR14   4
-#define ICR13   3
-#define ICR12   2
-#define ICR11   1
-#define ICR10   0
-
-/* Output Compare Register 1 A */
-#define OCR1A   _SFR_MEM16(0x88)
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-/* OCR1AH */
-#define OCR1A15 7
-#define OCR1A14 6
-#define OCR1A13 5
-#define OCR1A12 4
-#define OCR1A11 3
-#define OCR1A10 2
-#define OCR1A9  1
-#define OCR1A8  0
-/* OCR1AL */
-#define OCR1A7  7
-#define OCR1A6  6
-#define OCR1A5  5
-#define OCR1A4  4
-#define OCR1A3  3
-#define OCR1A2  2
-#define OCR1A1  1
-#define OCR1A0  0
-
-/* Output Compare Register 1 B */
-#define OCR1B   _SFR_MEM16(0x8A)
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-/* OCR1BH */
-#define OCR1B15 7
-#define OCR1B14 6
-#define OCR1B13 5
-#define OCR1B12 4
-#define OCR1B11 3
-#define OCR1B10 2
-#define OCR1B9  1
-#define OCR1B8  0
-/* OCR1BL */
-#define OCR1B7  7
-#define OCR1B6  6
-#define OCR1B5  5
-#define OCR1B4  4
-#define OCR1B3  3
-#define OCR1B2  2
-#define OCR1B1  1
-#define OCR1B0  0
-
-/* PSC0 Interrupt Flag Register */
-#define PIFR0   _SFR_MEM8(0xA0)
-/* PIFR0 */
-#define POAC0B  7   /* PSC0 Output B Activity */
-#define POAC0A  6   /* PSC0 Output A Activity */
-#define PSEI0   5   /* PSC0 Synchro Error Interrupt */
-#define PEV0B   4   /* PSC0 External Event B Interrupt */
-#define PEV0A   3   /* PSC0 External Event A Interrupt */
-#define PRN01   2   /* PSC0 Ramp Number bit1 */
-#define PRN00   1   /* PSC0 Ramp Number bit0 */
-#define PEOP0   0   /* End Of PSC0 Interrupt */
-
-/* PSC0 Interrupt Mask Register */
-#define PIM0    _SFR_MEM8(0xA1)
-/* PIM0 */
-#define PSEIE0  5   /* PSC0 Synchro Error Interrupt Enable */
-#define PEVE0B  4   /* PSC0 External Event B Interrupt Enable */
-#define PEVE0A  3   /* PSC0 External Event A Interrupt Enable */
-#define PEOPE0  0   /* PSC0 End Of Cycle Interrupt Enable */
-
-/* PSC1 Interrupt Flag Register */
-#define PIFR1   _SFR_MEM8(0xA2)
-/* PIFR1 */
-#define POAC1B  7   /* PSC1 Output B Activity */
-#define POAC1A  6   /* PSC1 Output A Activity */
-#define PSEI1   5   /* PSC1 Synchro Error Interrupt */
-#define PEV1B   4   /* PSC1 External Event B Interrupt */
-#define PEV1A   3   /* PSC1 External Event A Interrupt */
-#define PRN11   2   /* PSC1 Ramp Number bit1 */
-#define PRN10   1   /* PSC1 Ramp Number bit0 */
-#define PEOP1   0   /* End Of PSC1 Interrupt */
-
-/* PSC1 Interrupt Mask Register */
-#define PIM1    _SFR_MEM8(0xA3)
-/* PIM1 */
-#define PSEIE1  5   /* PSC1 Synchro Error Interrupt Enable */
-#define PEVE1B  4   /* PSC1 External Event B Interrupt Enable */
-#define PEVE1A  3   /* PSC1 External Event A Interrupt Enable */
-#define PEOPE1  0   /* PSC1 End Of Cycle Interrupt Enable */
-
-/* PSC2 Interrupt Flag Register */
-#define PIFR2   _SFR_MEM8(0xA4)
-/* PIFR2 */
-#define POAC2B  7   /* PSC2 Output B Activity */
-#define POAC2A  6   /* PSC2 Output A Activity */
-#define PSEI2   5   /* PSC2 Synchro Error Interrupt */
-#define PEV2B   4   /* PSC2 External Event B Interrupt */
-#define PEV2A   3   /* PSC2 External Event A Interrupt */
-#define PRN21   2   /* PSC2 Ramp Number bit1 */
-#define PRN20   1   /* PSC2 Ramp Number bit0 */
-#define PEOP2   0   /* End Of PSC2 Interrupt */
-
-/* PSC2 Interrupt Mask Register */
-#define PIM2    _SFR_MEM8(0xA5)
-/* PIM2 */
-#define PSEIE2  5   /* PSC2 Synchro Error Interrupt Enable */
-#define PEVE2B  4   /* PSC2 External Event B Interrupt Enable */
-#define PEVE2A  3   /* PSC2 External Event A Interrupt Enable */
-#define PEOPE2  0   /* PSC2 End Of Cycle Interrupt Enable */
-
-/* Digital to Analog Conversion Control Register */
-#define DACON   _SFR_MEM8(0xAA)
-/* DACON */
-#define DAATE   7   /* DAC Auto Trigger Enable bit */
-#define DATS2   6   /* DAC Trigger Selection bit2 */
-#define DATS1   5   /* DAC Trigger Selection bit1 */
-#define DATS0   4   /* DAC Trigger Selection bit0 */
-#define DALA    2   /* Digital to Analog Left Adjust */
-#define DAOE    1   /* Digital to Analog Output Enable bit */
-#define DAEN    0   /* Digital to Analog Enable bit */
-
-/* Digital to Analog Converter input Register */
-#define DAC     _SFR_MEM16(0xAB)
-#define DACL    _SFR_MEM8(0xAB)
-#define DACH    _SFR_MEM8(0xAC)
-
-/* Analog Comparator 0 Control Register */
-#define AC0CON  _SFR_MEM8(0xAD)
-/* AC0CON */
-#define AC0EN   7   /* Analog Comparator 0 Enable Bit */
-#define AC0IE   6   /* Analog Comparator 0 Interrupt Enable bit */
-#define AC0IS1  5   /* Analog Comparator 0 Interrupt Select bit1 */
-#define AC0IS0  4   /* Analog Comparator 0 Interrupt Select bit0 */
-#define AC0M2   2   /* Analog Comparator 0 Multiplexer register bit2 */
-#define AC0M1   1   /* Analog Comparator 0 Multiplexer register bit1 */
-#define AC0M0   0   /* Analog Comparator 0 Multiplexer register bit0 */
-
-/* Analog Comparator 1 Control Register */
-#define AC1CON  _SFR_MEM8(0xAE)
-/* AC1CON */
-#define AC1EN   7   /* Analog Comparator 1 Enable Bit */
-#define AC1IE   6   /* Analog Comparator 1 Interrupt Enable bit */
-#define AC1IS1  5   /* Analog Comparator 1 Interrupt Select bit1 */
-#define AC1IS0  4   /* Analog Comparator 1 Interrupt Select bit0 */
-#define AC1ICE  3   /* Analog Comparator 1 Interrupt Capture Enable bit */
-#define AC1M2   2   /* Analog Comparator 1 Multiplexer register bit2 */
-#define AC1M1   1   /* Analog Comparator 1 Multiplexer register bit1 */
-#define AC1M0   0   /* Analog Comparator 1 Multiplexer register bit0 */
-
-/* Analog Comparator 2 Control Register */
-#define AC2CON  _SFR_MEM8(0xAF)
-/* AC2CON */
-#define AC2EN   7   /* Analog Comparator 2 Enable Bit */
-#define AC2IE   6   /* Analog Comparator 2 Interrupt Enable bit */
-#define AC2IS1  5   /* Analog Comparator 2 Interrupt Select bit1 */
-#define AC2IS0  4   /* Analog Comparator 2 Interrupt Select bit0 */
-#define AC2M2   2   /* Analog Comparator 2 Multiplexer register bit2 */
-#define AC2M1   1   /* Analog Comparator 2 Multiplexer register bit1 */
-#define AC2M0   0   /* Analog Comparator 2 Multiplexer register bit0 */
-
-/* USART Control and Status Register A */
-#define UCSRA   _SFR_MEM8(0xC0)
-/* UCSRA */
-#define RXC     7   /* USART Receive Complete */
-#define TXC     6   /* USART Transmit Complete */
-#define UDRE    5   /* USART Data Register Empty */
-#define FE      4   /* Frame Error */
-#define DOR     3   /* Data OverRun */
-#define UPE     2   /* USART Parity Error */
-#define U2X     1   /* Double the USART Transmission Speed */
-#define MPCM    0   /* Multi-processor Communication Mode */
-
-/* USART Control and Status Register B */
-#define UCSRB   _SFR_MEM8(0xC1)
-/* UCSRB */
-#define RXCIE   7   /* RX Complete Interrupt Enable */
-#define TXCIE   6   /* TX Complete Interrupt Enable */
-#define UDRIE   5   /* USART Data Register Empty Interrupt Enable */
-#define RXEN    4   /* Receiver Enable */
-#define TXEN    3   /* Transmitter Enable */
-#define UCSZ2   2   /* Character Size */
-#define RXB8    1   /* Receive Data Bit 8 */
-#define TXB8    0   /* Transmit Data Bit 8 */
-
-/* USART Control and Status Register C */
-#define UCSRC   _SFR_MEM8(0xC2)
-/* UCSRC */
-#define UMSEL   6   /* USART Mode Select */
-#define UPM1    5   /* Parity Mode bit1 */
-#define UPM0    4   /* Parity Mode bit0 */
-#define USBS    3   /* Stop Bit Select */
-#define UCSZ1   2   /* Character Size bit1 */
-#define UCSZ0   1   /* Character Size bit0 */
-#define UCPOL   0   /* Clock Polarity */
-
-/* USART Baud Rate Register */
-#define UBRR    _SFR_MEM16(0xC4)
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-/* USART I/O Data Register */
-#define UDR     _SFR_MEM8(0xC6)
-
-/* EUSART Control and Status Register A */
-#define EUCSRA  _SFR_MEM8(0xC8)
-/* EUCSRA */
-#define UTxS3   7   /* EUSART Transmit Character Size bit3 */
-#define UTxS2   6   /* EUSART Transmit Character Size bit2 */
-#define UTxS1   5   /* EUSART Transmit Character Size bit1 */
-#define UTxS0   4   /* EUSART Transmit Character Size bit0 */
-#define URxS3   3   /* EUSART Receive Character Size bit3 */
-#define URxS2   2   /* EUSART Receive Character Size bit2 */
-#define URxS1   1   /* EUSART Receive Character Size bit1 */
-#define URxS0   0   /* EUSART Receive Character Size bit0 */
-
-/* EUSART Control and Status Register B */
-#define EUCSRB  _SFR_MEM8(0xC9)
-/* EUCSRB */
-#define EUSART  4   /* EUSART Enable Bit */
-#define EUSBS   3   /* EUSBS Enable Bit */
-#define EMCH    1   /* Manchester mode */
-#define BODR    0   /* Bit Order */
-
-/* EUSART Control and Status Register C */
-#define EUCSRC  _SFR_MEM8(0xCA)
-/* EUCSRC */
-#define FEM     3   /* Frame Error Manchester */
-#define F1617   2
-#define STP1    1   /* Stop bits values bit1 */
-#define STP0    0   /* Stop bits values bit0 */
-
-/* Manchester receiver Baud Rate Registers */
-#define MUBRR   _SFR_MEM16(0xCC)
-#define MUBRRL  _SFR_MEM8(0xCC)
-#define MUBRRH  _SFR_MEM8(0xCD)
-
-/* EUSART I/O Data Register */
-#define EUDR    _SFR_MEM8(0xCE)
-
-/* PSC 0 Synchro and Output Configuration */
-#define PSOC0   _SFR_MEM8(0xD0)
-/* PSOC0 */
-#define PSYNC01 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC00 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN0B  2   /* PSC 0 OUT Part B Output Enable */
-#define POEN0A  0   /* PSC 0 OUT Part A Output Enable */
-
-/* Output Compare SA Registers */
-#define OCR0SA  _SFR_MEM16(0xD2)
-#define OCR0SAL _SFR_MEM8(0xD2)
-#define OCR0SAH _SFR_MEM8(0xD3)
-
-/* Output Compare RA Registers */
-#define OCR0RA  _SFR_MEM16(0xD4)
-#define OCR0RAL _SFR_MEM8(0xD4)
-#define OCR0RAH _SFR_MEM8(0xD5)
-
-/* Output Compare SB Registers */
-#define OCR0SB  _SFR_MEM16(0xD6)
-#define OCR0SBL _SFR_MEM8(0xD6)
-#define OCR0SBH _SFR_MEM8(0xD7)
-
-/* Output Compare RB Registers */
-#define OCR0RB  _SFR_MEM16(0xD8)
-#define OCR0RBL _SFR_MEM8(0xD8)
-#define OCR0RBH _SFR_MEM8(0xD9)
-
-/* PSC 0 Configuration Register */
-#define PCNF0   _SFR_MEM8(0xDA)
-/* PCNF0 */
-#define PFIFTY0  7  /* PSC 0 Fifty */
-#define PALOCK0  6  /* PSC 0 Autolock */
-#define PLOCK0   5  /* PSC 0 Lock */
-#define PMODE01  4  /* PSC 0 Mode bit1 */
-#define PMODE00  3  /* PSC 0 Mode bit0 */
-#define POP0     2  /* PSC 0 Output Polarity */
-#define PCLKSEL0 1  /* PSC 0 Input Clock Select */
-
-/* PSC 0 Control Register */
-#define PCTL0   _SFR_MEM8(0xDB)
-/* PCTL0 */
-#define PPRE01  7   /* PSC 0 Prescaler Select bit1 */
-#define PPRE00  6   /* PSC 0 Prescaler Select bit0 */
-#define PBFM0   5   /* Balance Flank Width Modulation */
-#define PAOC0B  4   /* PSC 0 Asynchronous Output Control B */
-#define PAOC0A  3   /* PSC 0 Asynchronous Output Control A */
-#define PARUN0  2   /* PSC 0 Autorun */
-#define PCCYC0  1   /* PSC 0 Complete Cycle */
-#define PRUN0   0   /* PSC 0 Run */
-
-/* PSC 0 Input A Control Register */
-#define PFRC0A  _SFR_MEM8(0xDC)
-/* PFRC0A */
-#define PCAE0A  7   /* PSC 0 Capture Enable Input Part A */
-#define PISEL0A 6   /* PSC 0 Input Select for Part A */
-#define PELEV0A 5   /* PSC 0 Edge Level Selector of Input Part A */
-#define PFLTE0A 4   /* PSC 0 Filter Enable on Input Part A */
-#define PRFM0A3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0A2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0A1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0A0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input B Control Register */
-#define PFRC0B  _SFR_MEM8(0xDD)
-/* PFRC0B */
-#define PCAE0B  7   /* PSC 0 Capture Enable Input Part B */
-#define PISEL0B 6   /* PSC 0 Input Select for Part B */
-#define PELEV0B 5   /* PSC 0 Edge Level Selector of Input Part B */
-#define PFLTE0B 4   /* PSC 0 Filter Enable on Input Part B */
-#define PRFM0B3 3   /* PSC 0 Fault Mode bit3 */
-#define PRFM0B2 2   /* PSC 0 Fault Mode bit2 */
-#define PRFM0B1 1   /* PSC 0 Fault Mode bit1 */
-#define PRFM0B0 0   /* PSC 0 Fault Mode bit0 */
-
-/* PSC 0 Input Capture Registers */
-#define PICR0   _SFR_MEM16(0xDE)
-
-#define PICR0L  _SFR_MEM8(0xDE)
-
-#define PICR0H  _SFR_MEM8(0xDF)
-#define PCST0   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-/* PSC 1 Synchro and Output Configuration */
-#define PSOC1   _SFR_MEM8(0xE0)
-/* PSOC1 */
-#define PSYNC11 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC10 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN1B  2   /* PSC 1 OUT Part B Output Enable */
-#define POEN1A  0   /* PSC 1 OUT Part A Output Enable */
-
-/* Output Compare SA Registers */
-#define OCR1SA  _SFR_MEM16(0xE2)
-#define OCR1SAL _SFR_MEM8(0xE2)
-#define OCR1SAH _SFR_MEM8(0xE3)
-
-/* Output Compare RA Registers */
-#define OCR1RA  _SFR_MEM16(0xE4)
-#define OCR1RAL _SFR_MEM8(0xE4)
-#define OCR1RAH _SFR_MEM8(0xE5)
-
-/* Output Compare SB Registers */
-#define OCR1SB  _SFR_MEM16(0xE6)
-#define OCR1SBL _SFR_MEM8(0xE6)
-#define OCR1SBH _SFR_MEM8(0xE7)
-
-/* Output Compare RB Registers */
-#define OCR1RB  _SFR_MEM16(0xE8)
-#define OCR1RBL _SFR_MEM8(0xE8)
-#define OCR1RBH _SFR_MEM8(0xE9)
-
-/* PSC 1 Configuration Register */
-#define PCNF1   _SFR_MEM8(0xEA)
-/* PCNF1 */
-#define PFIFTY1  7  /* PSC 1 Fifty */
-#define PALOCK1  6  /* PSC 1 Autolock */
-#define PLOCK1   5  /* PSC 1 Lock */
-#define PMODE11  4  /* PSC 1 Mode bit1 */
-#define PMODE10  3  /* PSC 1 Mode bit0 */
-#define POP1     2  /* PSC 1 Output Polarity */
-#define PCLKSEL1 1  /* PSC 1 Input Clock Select */
-
-/* PSC 1 Control Register */
-#define PCTL1   _SFR_MEM8(0xEB)
-/* PCTL1 */
-#define PPRE11  7   /* PSC 1 Prescaler Select bit1 */
-#define PPRE10  6   /* PSC 1 Prescaler Select bit0 */
-#define PBFM1   5   /* Balance Flank Width Modulation */
-#define PAOC1B  4   /* PSC 1 Asynchronous Output Control B */
-#define PAOC1A  3   /* PSC 1 Asynchronous Output Control A */
-#define PARUN1  2   /* PSC 1 Autorun */
-#define PCCYC1  1   /* PSC 1 Complete Cycle */
-#define PRUN1   0   /* PSC 1 Run */
-
-/* PSC 1 Input A Control Register */
-#define PFRC1A  _SFR_MEM8(0xEC)
-/* PFRC1A */
-#define PCAE1A  7   /* PSC 1 Capture Enable Input Part A */
-#define PISEL1A 6   /* PSC 1 Input Select for Part A */
-#define PELEV1A 5   /* PSC 1 Edge Level Selector of Input Part A */
-#define PFLTE1A 4   /* PSC 1 Filter Enable on Input Part A */
-#define PRFM1A3 3   /* PSC 1 Fault Mode bit3 */
-#define PRFM1A2 2   /* PSC 1 Fault Mode bit2 */
-#define PRFM1A1 1   /* PSC 1 Fault Mode bit1 */
-#define PRFM1A0 0   /* PSC 1 Fault Mode bit0 */
-
-/* PSC 1 Input B Control Register */
-#define PFRC1B  _SFR_MEM8(0xED)
-/* PFRC1B */
-#define PCAE1B  7   /* PSC 1 Capture Enable Input Part B */
-#define PISEL1B 6   /* PSC 1 Input Select for Part B */
-#define PELEV1B 5   /* PSC 1 Edge Level Selector of Input Part B */
-#define PFLTE1B 4   /* PSC 1 Filter Enable on Input Part B */
-#define PRFM1B3 3   /* PSC 1 Fault Mode bit3 */
-#define PRFM1B2 2   /* PSC 1 Fault Mode bit2 */
-#define PRFM1B1 1   /* PSC 1 Fault Mode bit1 */
-#define PRFM1B0 0   /* PSC 1 Fault Mode bit0 */
-
-/* PSC 1 Input Capture Registers */
-#define PICR1   _SFR_MEM16(0xEE)
-
-#define PICR1L  _SFR_MEM8(0xEE)
-
-#define PICR1H  _SFR_MEM8(0xEF)
-#define PCST1   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-/* PSC 2 Synchro and Output Configuration */
-#define PSOC2   _SFR_MEM8(0xF0)
-/* PSOC2 */
-#define POS23   7   /* PSCOUT23 Selection */
-#define POS22   6   /* PSCOUT22 Selection */
-#define PSYNC21 5   /* Synchronization Out for ADC Selection bit1 */
-#define PSYNC20 4   /* Synchronization Out for ADC Selection bit0 */
-#define POEN2D  3   /* PSCOUT23 Output Enable */
-#define POEN2B  2   /* PSC 2 OUT Part B Output Enable */
-#define POEN2C  1   /* PSCOUT22 Output Enable */
-#define POEN2A  0   /* PSC 2 OUT Part A Output Enable */
-
-/* PSC 2 Output Matrix */
-#define POM2    _SFR_MEM8(0xF1)
-/* POM2 */
-#define POMV2B3 7   /* Output Matrix Output B Ramp 3 */
-#define POMV2B2 6   /* Output Matrix Output B Ramp 2 */
-#define POMV2B1 5   /* Output Matrix Output B Ramp 1 */
-#define POMV2B0 4   /* Output Matrix Output B Ramp 0 */
-#define POMV2A3 3   /* Output Matrix Output A Ramp 3 */
-#define POMV2A2 2   /* Output Matrix Output A Ramp 2 */
-#define POMV2A1 1   /* Output Matrix Output A Ramp 1 */
-#define POMV2A0 0   /* Output Matrix Output A Ramp 0 */
-
-/* Output Compare SA Registers */
-#define OCR2SA  _SFR_MEM16(0xF2)
-#define OCR2SAL _SFR_MEM8(0xF2)
-#define OCR2SAH _SFR_MEM8(0xF3)
-
-/* Output Compare RA Registers */
-#define OCR2RA  _SFR_MEM16(0xF4)
-#define OCR2RAL _SFR_MEM8(0xF4)
-#define OCR2RAH _SFR_MEM8(0xF5)
-
-/* Output Compare SB Registers */
-#define OCR2SB  _SFR_MEM16(0xF6)
-#define OCR2SBL _SFR_MEM8(0xF6)
-#define OCR2SBH _SFR_MEM8(0xF7)
-
-/* Output Compare RB Registers */
-#define OCR2RB  _SFR_MEM16(0xF8)
-#define OCR2RBL _SFR_MEM8(0xF8)
-#define OCR2RBH _SFR_MEM8(0xF9)
-
-/* PSC 2 Configuration Register */
-#define PCNF2   _SFR_MEM8(0xFA)
-/* PCNF2 */
-#define PFIFTY2  7  /* PSC 2 Fifty */
-#define PALOCK2  6  /* PSC 2 Autolock */
-#define PLOCK2   5  /* PSC 2 Lock */
-#define PMODE21  4  /* PSC 2 Mode bit1 */
-#define PMODE20  3  /* PSC 2 Mode bit0 */
-#define POP2     2  /* PSC 2 Output Polarity */
-#define PCLKSEL2 1  /* PSC 2 Input Clock Select */
-#define POME2    0  /* PSC 2 Output Matrix Enable */
-
-/* PSC 2 Control Register */
-#define PCTL2   _SFR_MEM8(0xFB)
-/* PCTL2 */
-#define PPRE21  7   /* PSC 2 Prescaler Select bit1 */
-#define PPRE20  6   /* PSC 2 Prescaler Select bit0 */
-#define PBFM2   5   /* Balance Flank Width Modulation */
-#define PAOC2B  4   /* PSC 2 Asynchronous Output Control B */
-#define PAOC2A  3   /* PSC 2 Asynchronous Output Control A */
-#define PARUN2  2   /* PSC 2 Autorun */
-#define PCCYC2  1   /* PSC 2 Complete Cycle */
-#define PRUN2   0   /* PSC 2 Run */
-
-/* PSC 2 Input A Control Register */
-#define PFRC2A  _SFR_MEM8(0xFC)
-/* PFRC2A */
-#define PCAE2A  7   /* PSC 2 Capture Enable Input Part A */
-#define PISEL2A 6   /* PSC 2 Input Select for Part A */
-#define PELEV2A 5   /* PSC 2 Edge Level Selector of Input Part A */
-#define PFLTE2A 4   /* PSC 2 Filter Enable on Input Part A */
-#define PRFM2A3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2A2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2A1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2A0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input B Control Register */
-#define PFRC2B  _SFR_MEM8(0xFD)
-/* PFRC2B */
-#define PCAE2B  7   /* PSC 2 Capture Enable Input Part B */
-#define PISEL2B 6   /* PSC 2 Input Select for Part B */
-#define PELEV2B 5   /* PSC 2 Edge Level Selector of Input Part B */
-#define PFLTE2B 4   /* PSC 2 Filter Enable on Input Part B */
-#define PRFM2B3 3   /* PSC 2 Fault Mode bit3 */
-#define PRFM2B2 2   /* PSC 2 Fault Mode bit2 */
-#define PRFM2B1 1   /* PSC 2 Fault Mode bit1 */
-#define PRFM2B0 0   /* PSC 2 Fault Mode bit0 */
-
-/* PSC 2 Input Capture Registers */
-#define PICR2   _SFR_MEM16(0xFE)
-
-#define PICR2L  _SFR_MEM8(0xFE)
-
-#define PICR2H  _SFR_MEM8(0xFF)
-#define PCST2   7   /* PSC Capture Software Trig bit */
-                    /* not implemented on AT90PWM2/AT90PWM3 */
-
-
-/* Interrupt vectors */
-/* PSC2 Capture Event */
-#define PSC2_CAPT_vect			_VECTOR(1)
-#define SIG_PSC2_CAPTURE		_VECTOR(1)
-
-/* PSC2 End Cycle */
-#define PSC2_EC_vect			_VECTOR(2)
-#define SIG_PSC2_END_CYCLE		_VECTOR(2)
-
-/* PSC1 Capture Event */
-#define PSC1_CAPT_vect			_VECTOR(3)
-#define SIG_PSC1_CAPTURE		_VECTOR(3)
-
-/* PSC1 End Cycle */
-#define PSC1_EC_vect			_VECTOR(4)
-#define SIG_PSC1_END_CYCLE		_VECTOR(4)
-
-/* PSC0 Capture Event */
-#define PSC0_CAPT_vect			_VECTOR(5)
-#define SIG_PSC0_CAPTURE		_VECTOR(5)
-
-/* PSC0 End Cycle */
-#define PSC0_EC_vect			_VECTOR(6)
-#define SIG_PSC0_END_CYCLE		_VECTOR(6)
-
-/* Analog Comparator 0 */
-#define ANALOG_COMP_0_vect		_VECTOR(7)
-#define SIG_COMPARATOR0			_VECTOR(7)
-
-/* Analog Comparator 1 */
-#define ANALOG_COMP_1_vect		_VECTOR(8)
-#define SIG_COMPARATOR1			_VECTOR(8)
-
-/* Analog Comparator 2 */
-#define ANALOG_COMP_2_vect		_VECTOR(9)
-#define SIG_COMPARATOR2			_VECTOR(9)
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(10)
-#define SIG_INTERRUPT0			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1_A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1_B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMP_A_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0A		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0_A		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(18)
-#define SIG_ADC				_VECTOR(18)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(19)
-#define SIG_INTERRUPT1			_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* USART, Rx Complete */
-#define USART_RX_vect			_VECTOR(21)
-#define SIG_USART_RECV			_VECTOR(21)
-#define SIG_UART_RECV			_VECTOR(21)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(22)
-#define SIG_USART_DATA			_VECTOR(22)
-#define SIG_UART_DATA			_VECTOR(22)
-
-/* USART, Tx Complete */
-#define USART_TX_vect			_VECTOR(23)
-#define SIG_USART_TRANS			_VECTOR(23)
-#define SIG_UART_TRANS			_VECTOR(23)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(24)
-#define SIG_INTERRUPT2			_VECTOR(24)
-
-/* Watchdog Timeout Interrupt */
-#define WDT_vect			_VECTOR(25)
-#define SIG_WDT				_VECTOR(25)
-#define SIG_WATCHDOG_TIMEOUT		_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer Counter 0 Compare Match B */
-#define TIMER0_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0B		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE0_B		_VECTOR(27)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(28)
-#define SIG_INTERRUPT3			_VECTOR(28)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(31)
-#define SIG_SPM_READY			_VECTOR(31)
-
-#define _VECTORS_SIZE   64
-
-/* Constants */
-#define SPM_PAGESIZE    64
-
-#define RAMEND      0x02FF
-#define XRAMEND     RAMEND
-#define E2END       0x01FF
-#define E2PAGESIZE  4
-#define FLASHEND    0x0FFF
-
-
-/* Fuse Information */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1  (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2  (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0    (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1    (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT   (unsigned char)~_BV(6)  /* Oscillator output option */
-#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)
-#define FUSE_EESAVE     (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN      (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN       (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL   (unsigned char)~_BV(7)  /* External Reset Diasble */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_PSCRV       (unsigned char)~_BV(4)
-#define FUSE_PSC0RB      (unsigned char)~_BV(5)
-#define FUSE_PSC1RB      (unsigned char)~_BV(6)
-#define FUSE_PSC2RB      (unsigned char)~_BV(7)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-/** @} */
-
-#endif /* _AVR_IO90PWMX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90scr100.h b/cpukit/score/cpu/avr/avr/io90scr100.h
deleted file mode 100644
index cb9f592..0000000
--- a/cpukit/score/cpu/avr/avr/io90scr100.h
+++ /dev/null
@@ -1,1708 +0,0 @@
-/**
- * @file avr/io90scr100.h
- *
- * @brief Definitions for AT90SCR100
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2009 Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "io90scr100.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_AT90SCR100_H_
-#define _AVR_AT90SCR100_H_ 1
-
-/**
- *  @defgroup Avr_io90scr100 AT90SCR100 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers. */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define PINE _SFR_IO8(0x0C)
-#define PINE0 0
-#define PINE1 1
-#define PINE2 2
-#define PINE3 3
-#define PINE4 4
-#define PINE5 5
-#define PINE6 6
-#define PINE7 7
-
-#define DDRE _SFR_IO8(0x0D)
-#define DDE0 0
-#define DDE1 1
-#define DDE2 2
-#define DDE3 3
-#define DDE4 4
-#define DDE5 5
-#define DDE6 6
-#define DDE7 7
-
-#define PORTE _SFR_IO8(0x0E)
-#define PORTE0 0
-#define PORTE1 1
-#define PORTE2 2
-#define PORTE3 3
-#define PORTE4 4
-#define PORTE5 5
-#define PORTE6 6
-#define PORTE7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define EIRR _SFR_IO8(0x1A)
-#define INTD2 2
-#define INTD3 3
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-#define INTF3 3
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-#define INT3 3
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PLLCR _SFR_MEM8(0x62)
-#define ON 0
-#define LOCK 1
-#define PLLMUX 7
-
-#define SMONCR _SFR_MEM8(0x63)
-#define SMONEN 0
-#define SMONIE 1
-#define SMONIF 4
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRUSBH 0
-#define PRUSB 1
-#define PRHSSPI 2
-#define PRSCI 3
-#define PRAES 4
-#define PRKB 5
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-#define ISC30 6
-#define ISC31 7
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define PCMSK3 _SFR_MEM8(0x73)
-
-#define LEDCR _SFR_MEM8(0x75)
-#define LED00 0
-#define LED01 1
-#define LED10 2
-#define LED11 3
-#define LED20 4
-#define LED21 5
-#define lED30 6
-#define LED31 7
-
-#define AESCR _SFR_MEM8(0x78)
-#define AESGO 0
-#define ENCRYPT 1
-#define KS 3
-#define KEYGN 4
-#define AUTOKEY 5
-#define AESIF 6
-#define AESIE 7
-
-#define AESACR _SFR_MEM8(0x79)
-#define KD 0
-#define AUTOINC 1
-#define MANINC 2
-#define XOR 3
-
-#define AESADDR _SFR_MEM8(0x7A)
-#define ADDR0 0
-#define ADDR1 1
-#define ADDR2 2
-#define ADDR3 3
-#define ADDR4 4
-#define ADDR5 5
-#define ADDR6 6
-#define ADDR7 7
-
-#define AESDR _SFR_MEM8(0x7B)
-#define DATA0 0
-#define DATA1 1
-#define DATA2 2
-#define DATA3 3
-#define DATA4 4
-#define DATA5 5
-#define DATA6 6
-#define DATA7 7
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define KBLSR _SFR_MEM8(0x8D)
-#define KBLS0 0
-#define KBLS1 1
-#define KBLS2 2
-#define KBLS3 3
-#define KBLS4 4
-#define KBLS5 5
-#define KBLS6 6
-#define KBLS7 7
-
-#define KBER _SFR_MEM8(0x8E)
-#define KBE0 0
-#define KBE1 1
-#define KBE2 2
-#define KBE3 3
-#define KBE4 4
-#define KBE5 5
-#define KBE6 6
-#define KBE7 7
-
-#define KBFR _SFR_MEM8(0x8F)
-#define KBF0 0
-#define KBF1 1
-#define KBF2 2
-#define KBF3 3
-#define KBF4 4
-#define KBF5 5
-#define KBF6 6
-#define KBF7 7
-
-#define RDWDR _SFR_MEM8(0x90)
-#define RDD0 0
-#define RDD1 1
-#define RDD2 2
-#define RDD3 3
-#define RDD4 4
-#define RDD5 5
-#define RDD6 6
-#define RDD7 7
-
-#define LFSR0 _SFR_MEM8(0x91)
-#define LFSD0 0
-#define LFSD1 1
-#define LFSD2 2
-#define LFSD3 3
-#define LFSD4 4
-#define LFSD5 5
-#define LFSD6 6
-#define LFSD7 7
-
-#define LFSR1 _SFR_MEM8(0x92)
-#define LFSD8 0
-#define LFSD9 1
-#define LFSD10 2
-#define LFSD11 3
-#define LFSD12 4
-#define LFSD13 5
-#define LFSD14 6
-#define LFSD15 7
-
-#define LFSR2 _SFR_MEM8(0x93)
-#define LFSD16 0
-#define LFSD17 1
-#define LFSD18 2
-#define LFSD19 3
-#define LFSD20 4
-#define LFSD21 5
-#define LFSD22 6
-#define LFSD23 7
-
-#define LFSR3 _SFR_MEM8(0x94)
-#define LFSD24 0
-#define LFSD25 1
-#define LFSD26 2
-#define LFSD27 3
-#define LFSD28 4
-#define LFSD29 5
-#define LFSD30 6
-#define LFSD31 7
-
-#define RNGCR _SFR_MEM8(0x95)
-#define ROSCE 0
-
-#define UHSR _SFR_MEM8(0x99)
-#define SPEED 3
-
-#define UPINT _SFR_MEM8(0x9A)
-#define PINT0 0
-#define PINT1 1
-#define PINT2 2
-#define PINT3 3
-
-#define UPBCX _SFR_MEM16(0x9B)
-
-#define UPBCXL _SFR_MEM8(0x9B)
-#define PBYTCT0 0
-#define PBYTCT1 1
-#define PBYTCT2 2
-#define PBYTCT3 3
-#define PBYTCT4 4
-#define PBYTCT5 5
-#define PBYTCT6 6
-#define PBYTCT7 7
-
-#define UPBCXH _SFR_MEM8(0x9C)
-#define PBYTCT8 0
-#define PBYTCT9 1
-#define PBYTCT10 2
-
-#define UPERRX _SFR_MEM8(0x9D)
-#define DATATGL 0
-#define DATAPID 1
-#define PID 2
-#define PTIMEOUT 3
-#define CRC16 4
-#define COUNTER0 5
-#define COUNTER1 6
-
-#define UHCR _SFR_MEM8(0x9E)
-#define SOFEN 0
-#define RESET 1
-#define RESUME 2
-#define FRZCLK 4
-#define PAD0 5
-#define PAD1 6
-#define UHEN 7
-
-#define UHINT _SFR_MEM8(0x9F)
-#define DCONNI 0
-#define DDISCI 1
-#define RSTI 2
-#define RSMEDI 3
-#define RXRSMI 4
-#define HSOFI 5
-#define HWUPI 6
-
-#define UHIEN _SFR_MEM8(0xA0)
-#define DCONNE 0
-#define DDISCE 1
-#define RSTE 2
-#define RSMEDE 3
-#define RXRSME 4
-#define HSOFE 5
-#define HWUPE 6
-
-#define UHADDR _SFR_MEM8(0xA1)
-#define HADDR0 0
-#define HADDR1 1
-#define HADDR2 2
-#define HADDR3 3
-#define HADDR4 4
-#define HADDR5 5
-#define HADDR6 6
-
-#define UHFNUM _SFR_MEM16(0xA2)
-
-#define UHFNUML _SFR_MEM8(0xA2)
-#define FNUM0 0
-#define FNUM1 1
-#define FNUM2 2
-#define FNUM3 3
-#define FNUM4 4
-#define FNUM5 5
-#define FNUM6 6
-#define FNUM7 7
-
-#define UHFNUMH _SFR_MEM8(0xA3)
-#define FNUM8 0
-#define FNUM9 1
-#define FNUM10 2
-
-#define UHFLEN _SFR_MEM8(0xA4)
-#define FLEN0 0
-#define FLEN1 1
-#define FLEN2 2
-#define FLEN3 3
-#define FLEN4 4
-#define FLEN5 5
-#define FLEN6 6
-#define FLEN7 7
-
-#define UPINRQX _SFR_MEM8(0xA5)
-#define INRQ0 0
-#define INRQ1 1
-#define INRQ2 2
-#define INRQ3 3
-#define INRQ4 4
-#define INRQ5 5
-#define INRQ6 6
-#define INRQ7 7
-
-#define UPINTX _SFR_MEM8(0xA6)
-#define RXINI 0
-#define RXSTALLI 1
-#define TXOUTI 2
-#define TXSTPI 3
-#define PERRI 4
-#define RWAL 5
-#define NAKEDI 6
-#define FIFOCON 7
-
-#define UPNUM _SFR_MEM8(0xA7)
-#define PNUM0 0
-#define PNUM1 1
-
-#define UPRST _SFR_MEM8(0xA8)
-#define P0RST 0
-#define P1RST 1
-#define P2RST 2
-#define P3RST 3
-
-#define UPCRX _SFR_MEM8(0xA9)
-#define PEN 0
-#define RSTDT 3
-#define INMODE 5
-#define PFREEZE 6
-
-#define UPCFG0X _SFR_MEM8(0xAA)
-#define PEPNUM0 0
-#define PEPNUM1 1
-#define PEPNUM2 2
-#define PEPNUM3 3
-#define PTOKEN0 4
-#define PTOKEN1 5
-#define PTYPE0 6
-#define PTYPE1 7
-
-#define UPCFG1X _SFR_MEM8(0xAB)
-#define ALLOC 1
-#define PBK0 2
-#define PBK1 3
-#define PSIZE0 4
-#define PSIZE1 5
-#define PSIZE2 6
-
-#define UPSTAX _SFR_MEM8(0xAC)
-#define NBUSYBK0 0
-#define NBUSYBK1 1
-#define DTSEQ0 2
-#define DTSEQ1 3
-#define UNDERFI 5
-#define OVERFI 6
-#define CFGOK 7
-
-#define UPCFG2X _SFR_MEM8(0xAD)
-#define INTFRQ0 0
-#define INTFRQ1 1
-#define INTFRQ2 2
-#define INTFRQ3 3
-#define INTFRQ4 4
-#define INTFRQ5 5
-#define INTFRQ6 6
-#define INTFRQ7 7
-
-#define UPIENX _SFR_MEM8(0xAE)
-#define RXINE 0
-#define RXSTALLE 1
-#define TXOUTE 2
-#define TXSTPE 3
-#define PERRE 4
-#define NAKEDE 6
-#define FLERRE 7
-
-#define UPDATX _SFR_MEM8(0xAF)
-#define PDAT0 0
-#define PDAT1 1
-#define PDAT2 2
-#define PDAT3 3
-#define PDAT4 4
-#define PDAT5 5
-#define PDAT6 6
-#define PDAT7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2A0 0
-#define OCR2A1 1
-#define OCR2A2 2
-#define OCR2A3 3
-#define OCR2A4 4
-#define OCR2A5 5
-#define OCR2A6 6
-#define OCR2A7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2B0 0
-#define OCR2B1 1
-#define OCR2B2 2
-#define OCR2B3 3
-#define OCR2B4 4
-#define OCR2B5 5
-#define OCR2B6 6
-#define OCR2B7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR00 0
-#define UBRR01 1
-#define UBRR02 2
-#define UBRR03 3
-#define UBRR04 4
-#define UBRR05 5
-#define UBRR06 6
-#define UBRR07 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR08 0
-#define UBRR09 1
-#define UBRR010 2
-#define UBRR011 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR00 0
-#define UDR01 1
-#define UDR02 2
-#define UDR03 3
-#define UDR04 4
-#define UDR05 5
-#define UDR06 6
-#define UDR07 7
-
-#define USBENUM _SFR_MEM8(0xCA)
-#define USBENUM0 0
-#define USBENUM1 1
-#define USBENUM2 2
-
-#define USBCSEX _SFR_MEM8(0xCB)
-#define TXC 0
-#define RCVD 1
-#define RXSETUP 2
-#define STSENT 3
-#define TXPB 4
-#define FSTALL 5
-#define IERR 6
-
-#define USBDBCEX _SFR_MEM8(0xCC)
-#define BCT0 0
-#define BCT1 1
-#define BCT2 2
-#define BCT3 3
-#define BCT4 4
-#define BCT5 5
-#define BCT6 6
-#define BCT7 7
-
-#define USBFCEX _SFR_MEM8(0xCD)
-#define EPTYP0 0
-#define EPTYP1 1
-#define EPDIR 2
-#define EPE 7
-
-#define HSSPITO _SFR_MEM16(0xD1)
-
-#define HSSPITOL _SFR_MEM8(0xD1)
-#define HSSPITOD0 0
-#define HSSPITOD1 1
-#define HSSPITOD2 2
-#define HSSPITOD3 3
-#define HSSPITOD4 4
-#define HSSPITOD5 5
-#define HSSPITOD6 6
-#define HSSPITOD7 7
-
-#define HSSPITOH _SFR_MEM8(0xD2)
-#define HSSPITOD8 0
-#define HSSPITOD9 1
-#define HSSPITOD10 2
-#define HSSPITOD11 3
-#define HSSPITOD12 4
-#define HSSPITOD13 5
-#define HSSPITOD14 6
-#define HSSPITOD15 7
-
-#define HSSPICNT _SFR_MEM8(0xD3)
-#define HSSPICNTD0 0
-#define HSSPICNTD1 1
-#define HSSPICNTD2 2
-#define HSSPICNTD3 3
-#define HSSPICNTD4 4
-
-#define HSSPIIER _SFR_MEM8(0xD4)
-#define NSSIE 4
-#define RCVOFIE 5
-#define BTDIE 6
-#define TIMEOUTIE 7
-
-#define HSSPIGTR _SFR_MEM8(0xD5)
-#define HSSPIGTD0 0
-#define HSSPIGTD1 1
-#define HSSPIGTD2 2
-#define HSSPIGTD3 3
-#define HSSPIGTD4 4
-#define HSSPIGTD5 5
-#define HSSPIGTD6 6
-#define HSSPIGTD7 7
-
-#define HSSPIRDR _SFR_MEM8(0xD6)
-#define HSSPIRDD0 0
-#define HSSPIRDD1 1
-#define HSSPIRDD2 2
-#define HSSPIRDD3 3
-#define HSSPIRDD4 4
-#define HSSPIRDD5 5
-#define HSSPIRDD6 6
-#define HSSPIRDD7 7
-
-#define HSSPITDR _SFR_MEM8(0xD7)
-#define HSSPITDD0 0
-#define HSSPITDD1 1
-#define HSSPITDD2 2
-#define HSSPITDD3 3
-#define HSSPITDD4 4
-#define HSSPITDD5 5
-#define HSSPITDD6 6
-#define HSSPITDD7 7
-
-#define HSSPISR _SFR_MEM8(0xD8)
-#define SPICKRDY 0
-#define TXBUFE 1
-#define RXBUFF 2
-#define NSS 3
-#define DPRAMRDY 4
-
-#define HSSPICFG _SFR_MEM8(0xD9)
-#define HSSPIEN 0
-#define HSMSTR 1
-#define HSCPOL 2
-#define HSCPHA 3
-#define DPRAM 4
-#define SPICKDIV0 5
-#define SPICKDIV1 6
-#define SPICKDIV2 7
-
-#define HSSPIIR _SFR_MEM8(0xDA)
-#define NSSFE 3
-#define NSSRE 4
-#define RCVOF 5
-#define BTD 6
-#define TIMEOUT 7
-
-#define HSSPICR _SFR_MEM8(0xDB)
-#define CS 0
-#define RETTO 1
-#define STTTO 2
-
-#define HSSPIDMACS _SFR_MEM8(0xDC)
-#define HSSPIDMAR 0
-#define HSSPIDMADIR 1
-#define HSSPIDMAERR 2
-
-#define HSSPIDMAD _SFR_MEM16(0xDD)
-
-#define HSSPIDMADL _SFR_MEM8(0xDD)
-#define HSSPIDMAD0 0
-#define HSSPIDMAD1 1
-#define HSSPIDMAD2 2
-#define HSSPIDMAD3 3
-#define HSSPIDMAD4 4
-#define HSSPIDMAD5 5
-#define HSSPIDMAD6 6
-#define HSSPIDMAD7 7
-
-#define HSSPIDMADH _SFR_MEM8(0xDE)
-#define HSSPIDMAD8 0
-#define HSSPIDMAD9 1
-#define HSSPIDMAD10 2
-#define HSSPIDMAD11 3
-#define HSSPIDMAD12 4
-#define HSSPIDMAD13 5
-
-#define HSSPIDMAB _SFR_MEM8(0xDF)
-#define HSSPIDMAB0 0
-#define HSSPIDMAB1 1
-#define HSSPIDMAB2 2
-#define HSSPIDMAB3 3
-#define HSSPIDMAB4 4
-
-#define USBCR _SFR_MEM8(0xE0)
-#define USBE 1
-#define UPUC 5
-#define URMWU 7
-
-#define USBPI _SFR_MEM8(0xE1)
-#define SUSI 0
-#define RESI 1
-#define RMWUI 2
-#define SOFI 3
-#define FEURI 4
-
-#define USBPIM _SFR_MEM8(0xE2)
-#define SUSIM 0
-#define RESIM 1
-#define RMWUIM 2
-#define SOFIM 3
-
-#define USBEI _SFR_MEM8(0xE3)
-#define EP0I 0
-#define EP1I 1
-#define EP2I 2
-#define EP3I 3
-#define EP4I 4
-#define EP5I 5
-#define EP6I 6
-#define EP7I 7
-
-#define USBEIM _SFR_MEM8(0xE4)
-#define EP0IM 0
-#define EP1IM 1
-#define EP2IM 2
-#define EP3IM 3
-#define EP4IM 4
-#define EP5IM 5
-#define EP6IM 6
-#define EP7IM 7
-
-#define USBRSTE _SFR_MEM8(0xE5)
-#define RSTE0 0
-#define RSTE1 1
-#define RSTE2 2
-#define RSTE3 3
-#define RSTE4 4
-#define RSTE5 5
-#define RSTE6 6
-#define RST7 7
-
-#define USBGS _SFR_MEM8(0xE6)
-#define FAF 0
-#define FCF 1
-#define RMWUE 2
-#define RSMON 3
-
-#define USBFA _SFR_MEM8(0xE7)
-#define FADD0 0
-#define FADD1 1
-#define FADD2 2
-#define FADD3 3
-#define FADD4 4
-#define FADD5 5
-#define FADD6 6
-
-#define USBFN _SFR_MEM16(0xE8)
-
-#define USBFNL _SFR_MEM8(0xE8)
-#define FN0 0
-#define FN1 1
-#define FN2 2
-#define FN3 3
-#define FN4 4
-#define FN5 5
-#define FN6 6
-#define FN7 7
-
-#define USBFNH _SFR_MEM8(0xE9)
-#define FN8 0
-#define FN9 1
-#define FN10 2
-#define FNERR 3
-#define FNEND 4
-
-#define USBDMACS _SFR_MEM8(0xEA)
-#define USBDMAR 0
-#define USBDMADIR 1
-#define USBDMAERR 2
-#define EPS0 4
-#define EPS1 5
-#define EPS2 6
-
-#define USBDMAD _SFR_MEM16(0xEB)
-
-#define USBDMADL _SFR_MEM8(0xEB)
-#define USBDMAD0 0
-#define USBDMAD1 1
-#define USBDMAD2 2
-#define USBDMAD3 3
-#define USBDMAD4 4
-#define USBDMAD5 5
-#define USBDMAD6 6
-#define USBDMAD7 7
-
-#define USBDMADH _SFR_MEM8(0xEC)
-#define USBDMAD8 0
-#define USBDMAD9 1
-#define USBDMAD10 2
-#define USBDMAD11 3
-#define USBDMAD12 4
-#define USBDMAD13 5
-
-#define USBDMAB _SFR_MEM8(0xED)
-#define USBDMAB0 0
-#define USBDMAB1 1
-#define USBDMAB2 2
-#define USBDMAB3 3
-#define USBDMAB4 4
-#define USBDMAB5 5
-#define USBDMAB6 6
-
-#define DCCR _SFR_MEM8(0xEF)
-#define DCBUSY 5
-#define DCRDY 6
-#define DCON 7
-
-#define SCICLK _SFR_MEM8(0xF0)
-#define SCICLK0 0
-#define SCICLK1 1
-#define SCICLK2 2
-#define SCICLK3 3
-#define SCICLK4 4
-#define SCICLK5 5
-
-#define SCWT0 _SFR_MEM8(0xF1)
-#define WT0 0
-#define WT1 1
-#define WT2 2
-#define WT3 3
-#define WT4 4
-#define WT5 5
-#define WT6 6
-#define WT7 7
-
-#define SCWT1 _SFR_MEM8(0xF2)
-#define WT8 0
-#define WT9 1
-#define WT10 2
-#define WT11 3
-#define WT12 4
-#define WT13 5
-#define WT14 6
-#define WT15 7
-
-#define SCWT2 _SFR_MEM8(0xF3)
-#define WT16 0
-#define WT17 1
-#define WT18 2
-#define WT19 3
-#define WT20 4
-#define WT21 5
-#define WT22 6
-#define WT23 7
-
-#define SCWT3 _SFR_MEM8(0xF4)
-#define WT24 0
-#define WT25 1
-#define WT26 2
-#define WT27 3
-#define WT28 4
-#define WT29 5
-#define WT30 6
-#define WT31 7
-
-#define SCGT _SFR_MEM16(0xF5)
-
-#define SCGTL _SFR_MEM8(0xF5)
-#define GT0 0
-#define GT1 1
-#define GT2 2
-#define GT3 3
-#define GT4 4
-#define GT5 5
-#define GT6 6
-#define GT7 7
-
-#define SCGTH _SFR_MEM8(0xF6)
-#define GT8 0
-
-#define SCETU _SFR_MEM16(0xF7)
-
-#define SCETUL _SFR_MEM8(0xF7)
-#define ETU0 0
-#define ETU1 1
-#define ETU2 2
-#define ETU3 3
-#define ETU4 4
-#define ETU5 5
-#define ETU6 6
-#define ETU7 7
-
-#define SCETUH _SFR_MEM8(0xF8)
-#define ETU8 0
-#define ETU9 1
-#define ETU10 2
-#define COMP 7
-
-#define SCIBUF _SFR_MEM8(0xF9)
-#define SCIBUFD0 0
-#define SCIBUFD1 1
-#define SCIBUFD2 2
-#define SCIBUFD3 3
-#define SCIBUFD4 4
-#define SCIBUFD5 5
-#define SCIBUFD6 6
-#define SCIBUFD7 7
-
-#define SCSR _SFR_MEM8(0xFA)
-#define CPRESRES 3
-#define CREPSEL 4
-#define BGTEN 6
-
-#define SCIER _SFR_MEM8(0xFB)
-#define ESCPI 0
-#define ESCRI 1
-#define ESCTI 2
-#define ESCWTI 3
-#define EVCARDER 4
-#define CARDINE 6
-#define ESCTBI 7
-
-#define SCIIR _SFR_MEM8(0xFC)
-#define SCPI 0
-#define SCRI 1
-#define SCTI 2
-#define SCWTI 3
-#define VCARDERR 4
-#define SCTBI 7
-
-#define SCISR _SFR_MEM8(0xFD)
-#define SCPE 0
-#define SCRC 1
-#define SCTC 2
-#define SCWTO 3
-#define VCARDOK 4
-#define CARDIN 6
-#define SCTBE 7
-
-#define SCCON _SFR_MEM8(0xFE)
-#define CARDVCC 0
-#define CARDRST 1
-#define CARDCLK 2
-#define CARDIO 3
-#define CARDC4 4
-#define CARDC8 5
-#define CLK 7
-
-#define SCICR _SFR_MEM8(0xFF)
-#define CONV 0
-#define CREP 1
-#define WTEN 2
-#define UART 3
-#define VCARD0 4
-#define VCARD1 5
-#define CARDDET 6
-#define SCIRESET 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect_num  3
-#define INT2_vect      _VECTOR(3)  /* External Interrupt Request 2 */
-#define INT3_vect_num  4
-#define INT3_vect      _VECTOR(4)  /* External Interrupt Request 3 */
-#define PCINT0_vect_num  5
-#define PCINT0_vect      _VECTOR(5)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  6
-#define PCINT1_vect      _VECTOR(6)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  7
-#define PCINT2_vect      _VECTOR(7)  /* Pin Change Interrupt Request 2 */
-#define WDT_vect_num  8
-#define WDT_vect      _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect_num  9
-#define TIMER2_COMPA_vect      _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect_num  10
-#define TIMER2_COMPB_vect      _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect_num  11
-#define TIMER2_OVF_vect      _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect_num  12
-#define TIMER1_CAPT_vect      _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect_num  13
-#define TIMER1_COMPA_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect_num  14
-#define TIMER1_COMPB_vect      _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect_num  15
-#define TIMER1_OVF_vect      _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect_num  16
-#define TIMER0_COMPA_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect_num  17
-#define TIMER0_COMPB_vect      _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect_num  18
-#define TIMER0_OVF_vect      _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect_num  19
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect_num  20
-#define USART0_RX_vect      _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect_num  21
-#define USART0_UDRE_vect      _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect_num  22
-#define USART0_TX_vect      _VECTOR(22)  /* USART0, Tx Complete */
-#define SUPPLY_MON_vect_num  23
-#define SUPPLY_MON_vect      _VECTOR(23)  /* Supply Monitor Interruption */
-#define RFU_vect_num  24
-#define RFU_vect      _VECTOR(24)  /* Reserved for Future Use */
-#define EE_READY_vect_num  25
-#define EE_READY_vect      _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect_num  26
-#define TWI_vect      _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect_num  27
-#define SPM_READY_vect      _VECTOR(27)  /* Store Program Memory Read */
-#define KEYBOARD_vect_num  28
-#define KEYBOARD_vect      _VECTOR(28)  /* Keyboard Input Changed */
-#define AES_Operation_vect_num  29
-#define AES_Operation_vect      _VECTOR(29)  /* AES Block Operation Ended */
-#define HSSPI_vect_num  30
-#define HSSPI_vect      _VECTOR(30)  /* High-Speed SPI Interruption */
-#define USB_Endpoint_vect_num  31
-#define USB_Endpoint_vect      _VECTOR(31)  /* USB Endpoint Related Interruption */
-#define USB_Protocol_vect_num  32
-#define USB_Protocol_vect      _VECTOR(32)  /* USB Protocol Related Interruption */
-#define SCIB_vect_num  33
-#define SCIB_vect      _VECTOR(33)  /* Smart Card Reader Interface */
-#define USBHost_Control_vect_num  34
-#define USBHost_Control_vect      _VECTOR(34)  /* USB Host Controller Interrupt */
-#define USBHost_Pipe_vect_num  35
-#define USBHost_Pipe_vect      _VECTOR(35)  /* USB Host Pipe Interrupt */
-#define CPRES_vect_num  36
-#define CPRES_vect      _VECTOR(36)  /* Card Presence Detection */
-#define PCINT3_vect_num  37
-#define PCINT3_vect      _VECTOR(37)  /* Pin Change Interrupt Request 3 */
-
-#define _VECTOR_SIZE 4 /* Size of individual vector. */
-#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (256)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (4096)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (0x0)
-#define XRAMSIZE     (0)
-#define XRAMEND      (RAMEND)
-#define E2END        (0x7FF)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (0xFFFF)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0  (unsigned char)~_BV(0)  /* Clock Selection */
-#define FUSE_CKSEL3  (unsigned char)~_BV(3)  /* Clock Selection */
-#define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define LFUSE_DEFAULT (FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-/* Extended Fuse Byte */
-#define FUSE_BODENABLE  (unsigned char)~_BV(0)  /* Brown-out Detector Enable Signal */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0xC1
-
-
-/**@}*/
-#endif /* _AVR_AT90SCR100_H_ */
diff --git a/cpukit/score/cpu/avr/avr/ioa6289.h b/cpukit/score/cpu/avr/avr/ioa6289.h
deleted file mode 100644
index d51e3a9..0000000
--- a/cpukit/score/cpu/avr/avr/ioa6289.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/**
- * @file avr/ioa6289.h
- *
- * @brief Definitions for ATA6289
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2008 Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *     distribution.
- *
- *   * Neither the name of the copyright holders nor the names of
- *     contributors may be used to endorse or promote products derived
- *     from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioa6289.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_ATA6289_H_
-#define _AVR_ATA6289_H_ 1
-
-/**
- * @defgroup Avr_ioa6289 ATA6289 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers. */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-
-#define DDRC _SFR_IO8(0x07)
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define CMCR _SFR_IO8(0x0F)
-#define CMM0 0
-#define CMM1 1
-#define SRCD 2
-#define CMONEN 3
-#define CCS 4
-#define ECINS 5
-#define CMCCE 7
-
-#define CMSR _SFR_IO8(0x10)
-#define ECF 0
-
-#define T2CRA _SFR_IO8(0x11)
-#define T2OTM 0
-#define T2CTM 1
-#define T2CR 2
-#define T2CRM 3
-#define T2CPRM 4
-#define T2ICS 5
-#define T2TS 6
-#define T2E 7
-
-#define T2CRB _SFR_IO8(0x12)
-#define T2SCE 0
-
-#define T3CRA _SFR_IO8(0x14)
-#define T3AC 0
-#define T3SCE 1
-#define T3CR 2
-#define T3TS 6
-#define T3E 7
-
-#define VMCSR _SFR_IO8(0x16)
-#define VMEN 0
-#define VMLS0 1
-#define VMLS1 2
-#define VMLS2 3
-#define VMIM 4
-#define VMF 5
-#define BODPD 6
-#define BODLS 7
-
-#define PCIFR _SFR_IO8(0x17)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define LFFR _SFR_IO8(0x18)
-#define LFWPF 0
-#define LFBF 1
-#define LFEDF 2
-#define LFRF 3
-
-#define SSFR _SFR_IO8(0x19)
-#define MSENF 0
-#define MSENO 1
-
-#define T10IFR _SFR_IO8(0x1A)
-#define T0F 0
-#define T1F 1
-
-#define T2IFR _SFR_IO8(0x1B)
-#define T2OFF 0
-#define T2COF 1
-#define T2ICF 2
-#define T2RXF 3
-#define T2TXF 4
-#define T2TCF 5
-
-#define T3IFR _SFR_IO8(0x1C)
-#define T3OFF 0
-#define T3COAF 1
-#define T3COBF 2
-#define T3ICF 3
-
-#define EIFR _SFR_IO8(0x1D)
-#define INTF0 0
-#define INTF1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEWE 1
-#define EEMWE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define PCICR _SFR_IO8(0x23)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EIMSK _SFR_IO8(0x24)
-#define INT0 0
-#define INT1 1
-
-#define SVCR _SFR_IO8(0x27)
-#define SVCS0 0
-#define SVCS1 1
-#define SVCS2 2
-#define SVCS3 3
-#define SVCS4 4
-
-#define SCR _SFR_IO8(0x28)
-#define SMS 0
-#define SEN0 1
-#define SEN1 2
-#define SMEN 3
-
-#define SCCR _SFR_IO8(0x29)
-#define SRCC0 0
-#define SRCC1 1
-#define SCCS0 2
-#define SCCS1 3
-#define SCCS2 4
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define T2MDR _SFR_IO8(0x2F)
-#define T2MDR0 0
-#define T2MDR1 1
-#define T2MDR2 2
-#define T2MDR3 3
-#define T2MDR4 4
-#define T2MDR5 5
-#define T2MDR6 6
-#define T2MDR7 7
-
-#define LFRR _SFR_IO8(0x30)
-#define LFRR0 0
-#define LFRR1 1
-#define LFRR2 2
-#define LFRR3 3
-#define LFRR4 4
-#define LFRR5 5
-#define LFRR6 6
-
-#define LFCDR _SFR_IO8(0x32)
-#define LFDO 0
-#define LFRST 6
-#define LFSCE 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define TSRF 5
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-
-#define LFRB _SFR_IO8(0x36)
-#define LFRB0 0
-#define LFRB1 1
-#define LFRB2 2
-#define LFRB3 3
-#define LFRB4 4
-#define LFRB5 5
-#define LFRB6 6
-#define LFRB7 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define T1CR _SFR_IO8(0x38)
-#define T1PS0 0
-#define T1PS1 1
-#define T1PS2 2
-#define T1CS0 3
-#define T1CS1 4
-#define T1CS2 5
-#define T1IE 7
-
-#define T0CR _SFR_IO8(0x39)
-#define T0PAS0 0
-#define T0PAS1 1
-#define T0PAS2 2
-#define T0IE 3
-#define T0PR 4
-#define T0PBS0 5
-#define T0PBS1 6
-#define T0PBS2 7
-
-#define CMIMR _SFR_IO8(0x3B)
-#define ECIE 0
-
-#define CLKPR _SFR_IO8(0x3C)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLTPS0 3
-#define CLTPS1 4
-#define CLTPS2 5
-#define CLPCE 7
-
-#define WDTCR _SFR_MEM8(0x60)
-#define WDPS0 0
-#define WDPS1 1
-#define WDPS2 2
-#define WDE 3
-#define WDCE 4
-
-#define SIMSK _SFR_MEM8(0x61)
-#define MSIE 0
-
-#define TSCR _SFR_MEM8(0x64)
-#define TSSD 0
-
-#define SRCCAL _SFR_MEM8(0x65)
-#define SCAL0 0
-#define SCAL1 1
-#define SCAL2 2
-#define SCAL3 3
-#define SCAL4 4
-#define SCAL5 5
-#define SCAL6 6
-#define SCAL7 7
-
-#define FRCCAL _SFR_MEM8(0x66)
-#define FCAL0 0
-#define FCAL1 1
-#define FCAL2 2
-#define FCAL3 3
-#define FCAL4 4
-#define FCAL5 5
-#define FCAL6 6
-#define FCAL7 7
-
-#define MSVCAL _SFR_MEM8(0x67)
-#define VRCAL0 0
-#define VRCAL1 1
-#define VRCAL2 2
-#define VRCAL3 3
-#define VRCAL4 4
-#define VRCAL5 5
-#define VRCAL6 6
-#define VRCAL7 7
-
-#define BGCAL _SFR_MEM8(0x68)
-#define BGCAL0 0
-#define BGCAL1 1
-#define BGCAL2 2
-#define BGCAL3 3
-#define BGCAL4 4
-#define BGCAL5 5
-#define BGCAL6 6
-#define BGCAL7 7
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6A)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6B)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-
-#define PCMSK2 _SFR_MEM8(0x6C)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define T2ICR _SFR_MEM16(0x6E)
-
-#define T2ICRL _SFR_MEM8(0x6E)
-#define T2ICRL0 0
-#define T2ICRL1 1
-#define T2ICRL2 2
-#define T2ICRL3 3
-#define T2ICRL4 4
-#define T2ICRL5 5
-#define T2ICRL6 6
-#define T2ICRL7 7
-
-#define T2ICRH _SFR_MEM8(0x6F)
-#define T2ICRH0 0
-#define T2ICRH1 1
-#define T2ICRH2 2
-#define T2ICRH3 3
-#define T2ICRH4 4
-#define T2ICRH5 5
-#define T2ICRH6 6
-#define T2ICRH7 7
-
-#define T2COR _SFR_MEM16(0x70)
-
-#define T2CORL _SFR_MEM8(0x70)
-#define T2CORL0 0
-#define T2CORL1 1
-#define T2CORL2 2
-#define T2CORL3 3
-#define T2CORL4 4
-#define T2CORL5 5
-#define T2CORL6 6
-#define T2CORL7 7
-
-#define T2CORH _SFR_MEM8(0x71)
-#define T2CORH0 0
-#define T2CORH1 1
-#define T2CORH2 2
-#define T2CORH3 3
-#define T2CORH4 4
-#define T2CORH5 5
-#define T2CORH6 6
-#define T2CORH7 7
-
-#define T2MRA _SFR_MEM8(0x72)
-#define T2CS0 0
-#define T2CS1 1
-#define T2CS2 2
-#define T2CE0 3
-#define T2CE1 4
-#define T2CNC 5
-#define T2TP0 6
-#define T2TP1 7
-
-#define T2MRB _SFR_MEM8(0x73)
-#define T2M0 0
-#define T2M1 1
-#define T2M2 2
-#define T2M3 3
-#define T2TOP 4
-#define T2CPOL 6
-#define T2SSIE 7
-
-#define T2IMR _SFR_MEM8(0x74)
-#define T2OIM 0
-#define T2CIM 1
-#define T2CPIM 2
-#define T2RXIM 3
-#define T2TXIM 4
-#define T2TCIM 5
-
-#define T3ICR _SFR_MEM16(0x76)
-
-#define T3ICRL _SFR_MEM8(0x76)
-#define T3ICRL0 0
-#define T3ICRL1 1
-#define T3ICRL2 2
-#define T3ICRL3 3
-#define T3ICRL4 4
-#define T3ICRL5 5
-#define T3ICRL6 6
-#define T3ICRL7 7
-
-#define T3ICRH _SFR_MEM8(0x77)
-#define T3ICRH0 0
-#define T3ICRH1 1
-#define T3ICRH2 2
-#define T3ICRH3 3
-#define T3ICRH4 4
-#define T3ICRH5 5
-#define T3ICRH6 6
-#define T3ICRH7 7
-
-#define T3CORA _SFR_MEM16(0x78)
-
-#define T3CORAL _SFR_MEM8(0x78)
-#define T3CORAL0 0
-#define T3CORAL1 1
-#define T3CORAL2 2
-#define T3CORAL3 3
-#define T3CORAL4 4
-#define T3CORAL5 5
-#define T3CORAL6 6
-#define T3CORAL7 7
-
-#define T3CORAH _SFR_MEM8(0x79)
-#define T3CORAH0 0
-#define T3CORAH1 1
-#define T3CORAH2 2
-#define T3CORAH3 3
-#define T3CORAH4 4
-#define T3CORAH5 5
-#define T3CORAH6 6
-#define T3CORAH7 7
-
-#define T3CORB _SFR_MEM16(0x7A)
-
-#define T3CORBL _SFR_MEM8(0x7A)
-#define T3CORBL0 0
-#define T3CORBL1 1
-#define T3CORBL2 2
-#define T3CORBL3 3
-#define T3CORBL4 4
-#define T3CORBL5 5
-#define T3CORBL6 6
-#define T3CORBL7 7
-
-#define T3CORBH _SFR_MEM8(0x7B)
-#define T3CORBH0 0
-#define T3CORBH1 1
-#define T3CORBH2 2
-#define T3CORBH3 3
-#define T3CORBH4 4
-#define T3CORBH5 5
-#define T3CORBH6 6
-#define T3CORBH7 7
-
-#define T3MRA _SFR_MEM8(0x7C)
-#define T3CS0 0
-#define T3CS1 1
-#define T3CS2 2
-#define T3CE0 3
-#define T3CE1 4
-#define T3CNC 5
-#define T3ICS0 6
-#define T3ICS1 7
-
-#define T3MRB _SFR_MEM8(0x7D)
-#define T3M0 0
-#define T3M1 1
-#define T3M2 2
-#define T3TOP 4
-
-#define T3CRB _SFR_MEM8(0x7E)
-#define T3CTMA 0
-#define T3SAMA 1
-#define T3CRMA 2
-#define T3CTMB 3
-#define T3SAMB 4
-#define T3CRMB 5
-#define T3CPRM 6
-
-#define T3IMR _SFR_MEM8(0x7F)
-#define T3OIM 0
-#define T3CAIM 1
-#define T3CBIM 2
-#define T3CPIM 3
-
-#define LFIMR _SFR_MEM8(0x81)
-#define LFWIM 0
-#define LFBIM 1
-#define LFEIM 2
-
-#define LFRCR _SFR_MEM8(0x82)
-#define LFEN 0
-#define LFBM 1
-#define LFWM0 2
-#define LFWM1 3
-#define LFRSS 4
-#define LFCS0 5
-#define LFCS1 6
-#define LFCS2 7
-
-#define LFHCR _SFR_MEM8(0x83)
-#define LFHCR0 0
-#define LFHCR1 1
-#define LFHCR2 2
-#define LFHCR3 3
-#define LFHCR4 4
-#define LFHCR5 5
-#define LFHCR6 6
-
-#define LFIDC _SFR_MEM16(0x84)
-
-#define LFIDCL _SFR_MEM8(0x84)
-#define LFIDCL_0 0
-#define LFIDCL_1 1
-#define LFIDCL_2 2
-#define LFIDCL_3 3
-#define LFIDCL_4 4
-#define LFIDCL_5 5
-#define LFIDCL_6 6
-#define LFIDCL_7 7
-
-#define LFIDCH _SFR_MEM8(0x85)
-#define LFIDCH_8 0
-#define LFIDCH_9 1
-#define LFIDCH_10 2
-#define LFIDCH_11 3
-#define LFIDCH_12 4
-#define LFIDCH_13 5
-#define LFIDCH_14 6
-#define LFIDCH_15 7
-
-#define LFCAL _SFR_MEM16(0x86)
-
-#define LFCALL _SFR_MEM8(0x86)
-#define LFCAL_00 0
-#define LFCAL_01 1
-#define LFCAL_02 2
-#define LFCAL_03 3
-#define LFCAL_04 4
-#define LFCAL_05 5
-#define LFCAL_06 6
-#define LFCAL_07 7
-
-#define LFCALH _SFR_MEM8(0x87)
-#define LFCAL_08 0
-#define LFCAL_09 1
-#define LFCAL_10 2
-#define LFCAL_11 3
-#define LFCAL_12 4
-#define LFCAL_13 5
-#define LFCAL_14 6
-#define LFCAL_15 7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-#define INT0_vect_num  1
-#define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect_num  2
-#define INT1_vect      _VECTOR(2)  /* External Interrupt Request 1 */
-#define PCINT0_vect_num  3
-#define PCINT0_vect      _VECTOR(3)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect_num  4
-#define PCINT1_vect      _VECTOR(4)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect_num  5
-#define PCINT2_vect      _VECTOR(5)  /* Pin Change Interrupt Request 2 */
-#define INTVM_vect_num  6
-#define INTVM_vect      _VECTOR(6)  /* Voltage Monitor Interrupt */
-#define SENINT_vect_num  7
-#define SENINT_vect      _VECTOR(7)  /* Sensor Interface Interrupt */
-#define INTT0_vect_num  8
-#define INTT0_vect      _VECTOR(8)  /* Timer0 Interval Interrupt */
-#define LFWP_vect_num  9
-#define LFWP_vect      _VECTOR(9)  /* LF-Receiver Wake-up Interrupt */
-#define T3CAP_vect_num  10
-#define T3CAP_vect      _VECTOR(10)  /* Timer/Counter3 Capture Event */
-#define T3COMA_vect_num  11
-#define T3COMA_vect      _VECTOR(11)  /* Timer/Counter3 Compare Match A */
-#define T3COMB_vect_num  12
-#define T3COMB_vect      _VECTOR(12)  /* Timer/Counter3 Compare Match B */
-#define T3OVF_vect_num  13
-#define T3OVF_vect      _VECTOR(13)  /* Timer/Counter3 Overflow */
-#define T2CAP_vect_num  14
-#define T2CAP_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
-#define T2COM_vect_num  15
-#define T2COM_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match */
-#define T2OVF_vect_num  16
-#define T2OVF_vect      _VECTOR(16)  /* Timer/Counter2 Overflow */
-#define SPISTC_vect_num  17
-#define SPISTC_vect      _VECTOR(17)  /* SPI Serial Transfer Complete */
-#define LFRXB_vect_num  18
-#define LFRXB_vect      _VECTOR(18)  /* LF Receive Buffer Interrupt */
-#define INTT1_vect_num  19
-#define INTT1_vect      _VECTOR(19)  /* Timer1 Interval Interrupt */
-#define T2RXB_vect_num  20
-#define T2RXB_vect      _VECTOR(20)  /* Timer2 SSI Receive Buffer Interrupt */
-#define T2TXB_vect_num  21
-#define T2TXB_vect      _VECTOR(21)  /* Timer2 SSI Transmit Buffer Interrupt */
-#define T2TXC_vect_num  22
-#define T2TXC_vect      _VECTOR(22)  /* Timer2 SSI Transmit Complete Interrupt */
-#define LFREOB_vect_num  23
-#define LFREOB_vect      _VECTOR(23)  /* LF-Receiver End of Burst Interrupt */
-#define EXCM_vect_num  24
-#define EXCM_vect      _VECTOR(24)  /* External Input Clock break down Interrupt */
-#define EEREADY_vect_num  25
-#define EEREADY_vect      _VECTOR(25)  /* EEPROM Ready Interrupt */
-#define SPM_RDY_vect_num  26
-#define SPM_RDY_vect      _VECTOR(26)  /* Store Program Memory Ready */
-
-#define _VECTOR_SIZE 2 /* Size of individual vector. */
-#define _VECTORS_SIZE (27 * _VECTOR_SIZE)
-
-
-/* Constants */
-#define SPM_PAGESIZE (64)
-#define RAMSTART     (0x100)
-#define RAMSIZE      (512)
-#define RAMEND       (RAMSTART + RAMSIZE - 1)
-#define XRAMSTART    (NA)
-#define XRAMSIZE     (0)
-#define XRAMEND      RAMEND
-#define E2END        (320 - 1)
-#define E2PAGESIZE   (4)
-#define FLASHEND     (8192 - 1)
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_TSRDI ~_BV(0)  /* Disable Temperature shutdown Reset  */
-#define FUSE_BODEN ~_BV(1)  /* Enable Brown-out detection */
-#define FUSE_FRCFS ~_BV(2)  /* Fast RC-Oscillator Frequency select */
-#define FUSE_WDRCON ~_BV(3)  /* Enable Watchdog RC-Oscillator */
-#define FUSE_SUT0 ~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1 ~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT ~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 ~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST ~_BV(0)  /* Select reset vector */
-#define FUSE_BOOTSZ0 ~_BV(1)  /* Boot size select */
-#define FUSE_BOOTSZ1 ~_BV(2)  /* Boot size select */
-#define FUSE_EESAVE ~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON ~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN ~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN ~_BV(6)  /* debugWIRE Enable */
-#define FUSE_EELOCK ~_BV(7)  /* Upper EEPROM Locked (disabled) */
-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x93
-#define SIGNATURE_2 0x82
-
-
-/** @} */
-#endif /* _AVR_ATA6289_H_ */
diff --git a/cpukit/score/cpu/avr/avr/ioat94k.h b/cpukit/score/cpu/avr/avr/ioat94k.h
deleted file mode 100644
index dc0cab6..0000000
--- a/cpukit/score/cpu/avr/avr/ioat94k.h
+++ /dev/null
@@ -1,569 +0,0 @@
-/**
- * @file avr/ioat94k.h
- *
- * @brief Definitions for AT94K Series FPSLIC(tm)
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002 Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOAT94K_H_
-#define _AVR_IOAT94K_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "ioat94k.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- *  @defgroup Avr_ioat94k AT94K Series FPSLIC(tm) Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* I/O registers */
-
-/* UART1 Baud Rate Register */
-#define UBRR1	_SFR_IO8(0x00)
-
-/* UART1 Control and Status Registers */
-#define UCSR1B	_SFR_IO8(0x01)
-#define UCSR1A	_SFR_IO8(0x02)
-
-/* UART1 I/O Data Register */
-#define UDR1	_SFR_IO8(0x03)
-
-/* 0x04 reserved */
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x05)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x06)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x07)
-
-/* On Chip Debug Register (reserved) */
-#define OCDR    _SFR_IO8(0x08)
-
-/* UART0 Baud Rate Register */
-#define UBRR0	_SFR_IO8(0x09)
-
-/* UART0 Control and Status Registers */
-#define UCSR0B	_SFR_IO8(0x0A)
-#define UCSR0A	_SFR_IO8(0x0B)
-
-/* UART0 I/O Data Register */
-#define UDR0	_SFR_IO8(0x0C)
-
-/* 0x0D..0x0F reserved */
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* FPGA I/O Select Control Register */
-#define FISCR	_SFR_IO8(0x13)
-
-/* FPGA I/O Select Registers A, B, C, D */
-#define FISUA	_SFR_IO8(0x14)
-#define FISUB	_SFR_IO8(0x15)
-#define FISUC	_SFR_IO8(0x16)
-#define FISUD	_SFR_IO8(0x17)
-
-/* FPGA Cache Logic(R) registers (top secret, under NDA) */
-#define FPGAX	_SFR_IO8(0x18)
-#define FPGAY	_SFR_IO8(0x19)
-#define FPGAZ	_SFR_IO8(0x1A)
-#define FPGAD	_SFR_IO8(0x1B)
-
-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
-
-/* 2-wire Serial Bit Rate Register */
-#define TWBR	_SFR_IO8(0x1C)
-
-/* 2-wire Serial Status Register */
-#define TWSR	_SFR_IO8(0x1D)
-
-/* 2-wire Serial (Slave) Address Register */
-#define TWAR	_SFR_IO8(0x1E)
-
-/* 2-wire Serial Data Register */
-#define TWDR	_SFR_IO8(0x1F)
-
-/* UART Baud Register High */
-#define UBRRH	_SFR_IO8(0x20)
-#define UBRRHI	UBRRH           /* New name in datasheet (1138F-FPSLI-06/02) */
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x22)
-
-/* Timer/Counter2 (8-bit) */
-#define TCNT2	_SFR_IO8(0x23)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* Asynchronous mode StatuS Register */
-#define ASSR	_SFR_IO8(0x26)
-
-/* Timer/Counter2 Control Register */
-#define TCCR2	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare RegisterB */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare RegisterA */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR	_SFR_IO8(0x30)
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* 0x34 reserved */
-
-/* MCU Control/Status Register */
-#define MCUR	_SFR_IO8(0x35)
-
-/* 2-wire Serial Control Register */
-#define TWCR	_SFR_IO8(0x36)
-
-/* 0x37 reserved */
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* Software Control Register */
-#define SFTCR	_SFR_IO8(0x3A)
-
-/* External Interrupt Mask/Flag Register */
-#define EIMF	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-#define SIG_FPGA_INTERRUPT0     _VECTOR(1)   /* FPGA_INT0  */
-#define SIG_INTERRUPT0          _VECTOR(2)   /* EXT_INT0   */
-#define SIG_FPGA_INTERRUPT1     _VECTOR(3)   /* FPGA_INT1  */
-#define SIG_INTERRUPT1          _VECTOR(4)   /* EXT_INT1   */
-#define SIG_FPGA_INTERRUPT2     _VECTOR(5)   /* FPGA_INT2  */
-#define SIG_INTERRUPT2          _VECTOR(6)   /* EXT_INT2   */
-#define SIG_FPGA_INTERRUPT3     _VECTOR(7)   /* FPGA_INT3  */
-#define SIG_INTERRUPT3          _VECTOR(8)   /* EXT_INT3   */
-#define SIG_OUTPUT_COMPARE2     _VECTOR(9)   /* TIM2_COMP  */
-#define SIG_OVERFLOW2           _VECTOR(10)  /* TIM2_OVF   */
-#define SIG_INPUT_CAPTURE1      _VECTOR(11)  /* TIM1_CAPT  */
-#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)  /* TIM1_COMPA */
-#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)  /* TIM1_COMPB */
-#define SIG_OVERFLOW1           _VECTOR(14)  /* TIM1_OVF   */
-#define SIG_OUTPUT_COMPARE0     _VECTOR(15)  /* TIM0_COMP  */
-#define SIG_OVERFLOW0           _VECTOR(16)  /* TIM0_OVF   */
-#define SIG_FPGA_INTERRUPT4     _VECTOR(17)  /* FPGA_INT4  */
-#define SIG_FPGA_INTERRUPT5     _VECTOR(18)  /* FPGA_INT5  */
-#define SIG_FPGA_INTERRUPT6     _VECTOR(19)  /* FPGA_INT6  */
-#define SIG_FPGA_INTERRUPT7     _VECTOR(20)  /* FPGA_INT7  */
-#define SIG_UART0_RECV          _VECTOR(21)  /* UART0_RXC  */
-#define SIG_UART0_DATA          _VECTOR(22)  /* UART0_DRE  */
-#define SIG_UART0_TRANS         _VECTOR(23)  /* UART0_TXC  */
-#define SIG_FPGA_INTERRUPT8     _VECTOR(24)  /* FPGA_INT8  */
-#define SIG_FPGA_INTERRUPT9     _VECTOR(25)  /* FPGA_INT9  */
-#define SIG_FPGA_INTERRUPT10    _VECTOR(26)  /* FPGA_INT10 */
-#define SIG_FPGA_INTERRUPT11    _VECTOR(27)  /* FPGA_INT11 */
-#define SIG_UART1_RECV          _VECTOR(28)  /* UART1_RXC  */
-#define SIG_UART1_DATA          _VECTOR(29)  /* UART1_DRE  */
-#define SIG_UART1_TRANS         _VECTOR(30)  /* UART1_TXC  */
-#define SIG_FPGA_INTERRUPT12    _VECTOR(31)  /* FPGA_INT12 */
-#define SIG_FPGA_INTERRUPT13    _VECTOR(32)  /* FPGA_INT13 */
-#define SIG_FPGA_INTERRUPT14    _VECTOR(33)  /* FPGA_INT14 */
-#define SIG_FPGA_INTERRUPT15    _VECTOR(34)  /* FPGA_INT15 */
-#define SIG_2WIRE_SERIAL        _VECTOR(35)  /* TWS_INT    */
-
-#define _VECTORS_SIZE 144
-
-/* Bit numbers (SFRs alphabetically sorted) */
-
-/* ASSR */
-#define AS2           3
-#define TCN2UB        2
-#define OCR2UB        1
-#define TCR2UB        0
-
-/* DDRD */
-#define DDD7          7
-#define DDD6          6
-#define DDD5          5
-#define DDD4          4
-#define DDD3          3
-#define DDD2          2
-#define DDD1          1
-#define DDD0          0
-
-/* DDRE */
-#define DDE7          7
-#define DDE6          6
-#define DDE5          5
-#define DDE4          4
-#define DDE3          3
-#define DDE2          2
-#define DDE1          1
-#define DDE0          0
-
-/* EIMF */
-#define INTF3         7
-#define INTF2         6
-#define INTF1         5
-#define INTF0         4
-#define INT3          3
-#define INT2          2
-#define INT1          1
-#define INT0          0
-
-/* FISCR */
-#define FIADR         7
-#define XFIS1         1
-#define XFIS0         0
-
-/* FISUA */
-#define FIF3          7
-#define FIF2          6
-#define FIF1          5
-#define FIF0          4
-#define FINT3         3
-#define FINT2         2
-#define FINT1         1
-#define FINT0         0
-
-/* FISUB */
-#define FIF7          7
-#define FIF6          6
-#define FIF5          5
-#define FIF4          4
-#define FINT7         3
-#define FINT6         2
-#define FINT5         1
-#define FINT4         0
-
-/* FISUC */
-#define FIF11         7
-#define FIF10         6
-#define FIF9          5
-#define FIF8          4
-#define FINT11        3
-#define FINT10        2
-#define FINT9         1
-#define FINT8         0
-
-/* FISUD */
-#define FIF15         7
-#define FIF14         6
-#define FIF13         5
-#define FIF12         4
-#define FINT15        3
-#define FINT14        2
-#define FINT13        1
-#define FINT12        0
-
-/* MCUR */
-#define JTRF          7
-#define JTD           6
-#define SE            5
-#define SM1           4
-#define SM0           3
-#define PORF          2
-#define WDRF          1
-#define EXTRF         0
-
-/* OCDR (reserved) */
-#define IDRD          7
-
-/* PIND */
-#define PIND7         7
-#define PIND6         6
-#define PIND5         5
-#define PIND4         4
-#define PIND3         3
-#define PIND2         2
-#define PIND1         1
-#define PIND0         0
-
-/* PINE */
-#define PINE7         7
-#define PINE6         6
-#define PINE5         5
-#define PINE4         4
-#define PINE3         3
-#define PINE2         2
-#define PINE1         1
-#define PINE0         0
-
-/* PORTD */
-#define PD7        7
-#define PD6        6
-#define PD5        5
-#define PD4        4
-#define PD3        3
-#define PD2        2
-#define PD1        1
-#define PD0        0
-
-/* PORTE */
-/*
-   PE7 = IC1  / INT3 (alternate)
-   PE6 = OC1A / INT2 (alternate)
-   PE5 = OC1B / INT1 (alternate)
-   PE4 = ET11 / INT0 (alternate)
-   PE3 = OC2  / RX1  (alternate)
-   PE2 =      / TX1  (alternate)
-   PE1 = OC0  / RX0  (alternate)
-   PE0 = ET0  / TX0  (alternate)
- */
-#define PE7        7
-#define PE6        6
-#define PE5        5
-#define PE4        4
-#define PE3        3
-#define PE2        2
-#define PE1        1
-#define PE0        0
-
-/* SFIOR */
-#define PSR2          1
-#define PSR10         0
-
-/* SFTCR */
-#define FMXOR         3
-#define WDTS          2
-#define DBG           1
-#define SRST          0
-
-/* TCCR0 */
-#define FOC0          7
-#define PWM0          6
-#define COM01         5
-#define COM00         4
-#define CTC0          3
-#define CS02          2
-#define CS01          1
-#define CS00          0
-
-/* TCCR1A */
-#define COM1A1        7
-#define COM1A0        6
-#define COM1B1        5
-#define COM1B0        4
-#define FOC1A         3
-#define FOC1B         2
-#define PWM11         1
-#define PWM10         0
-
-/* TCCR1B */
-#define ICNC1         7
-#define ICES1         6
-#define ICPE          5
-#define CTC1          3
-#define CS12          2
-#define CS11          1
-#define CS10          0
-
-/* TCCR2 */
-#define FOC2          7
-#define PWM2          6
-#define COM21         5
-#define COM20         4
-#define CTC2          3
-#define CS22          2
-#define CS21          1
-#define CS20          0
-
-/* TIFR */
-#define TOV1          7
-#define OCF1A         6
-#define OCF1B         5
-#define TOV2          4
-#define ICF1          3
-#define OCF2          2
-#define TOV0          1
-#define OCF0          0
-
-/* TIMSK */
-#define TOIE1         7
-#define OCIE1A        6
-#define OCIE1B        5
-#define TOIE2         4
-#define TICIE1        3
-#define OCIE2         2
-#define TOIE0         1
-#define OCIE0         0
-
-/* TWAR */
-/* #define TWA           1 */ /* TWA is bits 7:1 */
-#define TWGCE         0
-
-/* TWCR */
-#define TWINT         7
-#define TWEA          6
-#define TWSTA         5
-#define TWSTO         4
-#define TWWC          3
-#define TWEN          2
-#define TWIE          0
-
-/* TWSR */
-#define TWS7          7
-#define TWS6          6
-#define TWS5          5
-#define TWS4          4
-#define TWS3          3
-
-/* UBRRHI
-   Bits 11..8 of UART1 are bits 7..4 of UBRRHI.
-   Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */
-/* #define UBRRHI1       4 */
-/* #define UBRRHI0       0 */
-
-/* UCSR0A */
-#define RXC0          7
-#define TXC0          6
-#define UDRE0         5
-#define FE0           4
-#define OR0           3
-#define U2X0          1
-#define MPCM0         0
-
-/* UCSR0B */
-#define RXCIE0        7
-#define TXCIE0        6
-#define UDRIE0        5
-#define RXEN0         4
-#define TXEN0         3
-#define CHR90         2
-#define RXB80         1
-#define TXB80         0
-
-/* UCSR1A */
-#define RXC1          7
-#define TXC1          6
-#define UDRE1         5
-#define FE1           4
-#define OR1           3
-#define U2X1          1
-#define MPCM1         0
-
-/* UCSR1B */
-#define RXCIE1        7
-#define TXCIE1        6
-#define UDRIE1        5
-#define RXEN1         4
-#define TXEN1         3
-#define CHR91         2
-#define RXB81         1
-#define TXB81         0
-
-/* WDTCR */
-#define WDTOE         4
-#define WDE           3
-#define WDP2          2
-#define WDP1          1
-#define WDP0          0
-
-/*
-   Last memory addresses - depending on configuration, it is possible
-   to have 20K-32K of program memory and 4K-16K of data memory
-   (all in the same 36K total of SRAM, loaded from external EEPROM).
- */
-
-#ifndef RAMEND
-#define RAMEND 0x0FFF
-#endif
-
-#ifndef XRAMEND
-#define XRAMEND RAMEND
-#endif
-
-#define E2END 0
-
-#ifndef FLASHEND
-#define FLASHEND 0x7FFF
-#endif
-
-/**@}*/
-#endif /* _AVR_IOAT94K_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan128.h b/cpukit/score/cpu/avr/avr/iocan128.h
deleted file mode 100644
index d7996f0..0000000
--- a/cpukit/score/cpu/avr/avr/iocan128.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright (c) 2004,2005, Colin O'Flynn <coflynn at newae.com>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iocan128.h - definitions for CAN128 */
-
-#ifndef _AVR_IOCAN128_H_
-#define _AVR_IOCAN128_H_ 1
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x0FFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x81
-
-
-#endif  /* _AVR_IOCAN128_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan32.h b/cpukit/score/cpu/avr/avr/iocan32.h
deleted file mode 100644
index 512b45d..0000000
--- a/cpukit/score/cpu/avr/avr/iocan32.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- * @file iocan32.h
- *
- * @brief Definitions for CAN32
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004,2005, Anatoly Sokolov <aesok at pautinka.net>
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOCAN32_H_
-#define _AVR_IOCAN32_H_ 1
-
-/**
- * @defgroup AvrDef_CAN32 CAN32 Defintions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x08FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x03FF
-#define E2PAGESIZE   8
-#define FLASHEND     0x7FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x81
-
-
-/** @} */
-#endif  /* _AVR_IOCAN32_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan64.h b/cpukit/score/cpu/avr/avr/iocan64.h
deleted file mode 100644
index d7525c0..0000000
--- a/cpukit/score/cpu/avr/avr/iocan64.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok at pautinka.net>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iocan64.h - definitions for CAN64 */
-
-#ifndef _AVR_IOCAN64_H_
-#define _AVR_IOCAN64_H_ 1
-
-#include <avr/iocanxx.h>
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND      0xFFFF
-#define E2END        0x07FF
-#define E2PAGESIZE   8
-#define FLASHEND     0xFFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x96
-#define SIGNATURE_2 0x81
-
-
-#endif  /* _AVR_IOCAN64_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocanxx.h b/cpukit/score/cpu/avr/avr/iocanxx.h
deleted file mode 100644
index a593539..0000000
--- a/cpukit/score/cpu/avr/avr/iocanxx.h
+++ /dev/null
@@ -1,1990 +0,0 @@
-/**
- * @file iocanxx.h
- *
- * @brief Definitions for AT90CAN32, AT90CAN64 and AT90CAN128
- *
- * This file should only be included from <avr/io.h>, never directly.
- *
- * This file is based largely on:
- * - iom128.h by Peter Jansen (bit defines)
- * - iom169.h by Juergen Schilling <juergen.schilling at honeywell.com>
- *   (register addresses)
- * - AT90CAN128 Datasheet (bit defines and register addresses)
- * - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need
- *   to change)
- */
-
-/*
- *   Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn at newae.com>
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOCANXX_H_
-#define _AVR_IOCANXX_H_ 1
-
-/**
- *  @defgroup Avr_iocanxx AT90CAN32, AT90CAN64, AT90CAN128 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iocanxx.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers and bit definitions. */
-
-/* RegDef:  Port A */
-#define PINA   _SFR_IO8(0x00)
-#define DDRA   _SFR_IO8(0x01)
-#define PORTA  _SFR_IO8(0x02)
-
-/* RegDef:  Port B */
-#define PINB   _SFR_IO8(0x03)
-#define DDRB   _SFR_IO8(0x04)
-#define PORTB  _SFR_IO8(0x05)
-
-/* RegDef:  Port C */
-#define PINC   _SFR_IO8(0x06)
-#define DDRC   _SFR_IO8(0x07)
-#define PORTC  _SFR_IO8(0x08)
-
-/* RegDef:  Port D */
-#define PIND   _SFR_IO8(0x09)
-#define DDRD   _SFR_IO8(0x0A)
-#define PORTD  _SFR_IO8(0x0B)
-
-/* RegDef:  Port E */
-#define PINE   _SFR_IO8(0x0C)
-#define DDRE   _SFR_IO8(0x0D)
-#define PORTE  _SFR_IO8(0x0E)
-
-/* RegDef:  Port F */
-#define PINF   _SFR_IO8(0x0F)
-#define DDRF   _SFR_IO8(0x10)
-#define PORTF  _SFR_IO8(0x11)
-
-/* RegDef:  Port G */
-#define PING   _SFR_IO8(0x12)
-#define DDRG   _SFR_IO8(0x13)
-#define PORTG  _SFR_IO8(0x14)
-
-/* RegDef:  Timer/Counter 0 interrupt Flag Register */
-#define TIFR0  _SFR_IO8(0x15)
-
-/* RegDef:  Timer/Counter 1 interrupt Flag Register */
-#define TIFR1  _SFR_IO8(0x16)
-
-/* RegDef:  Timer/Counter 2 interrupt Flag Register */
-#define TIFR2  _SFR_IO8(0x17)
-
-/* RegDef:  Timer/Counter 3 interrupt Flag Register */
-#define TIFR3  _SFR_IO8(0x18)
-
-/* RegDef:  External Interrupt Flag Register */
-#define EIFR   _SFR_IO8(0x1C)
-
-/* RegDef:  External Interrupt Mask Register */
-#define EIMSK  _SFR_IO8(0x1D)
-
-/* RegDef:  General Purpose I/O Register 0 */
-#define GPIOR0 _SFR_IO8(0x1E)
-
-/* RegDef:  EEPROM Control Register */
-#define EECR   _SFR_IO8(0x1F)
-
-/* RegDef:  EEPROM Data Register */
-#define EEDR   _SFR_IO8(0x20)
-
-/* RegDef:  EEPROM Address Register */
-#define EEAR   _SFR_IO16(0x21)
-#define EEARL  _SFR_IO8(0x21)
-#define EEARH  _SFR_IO8(0x22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* RegDef:  General Timer/Counter Control Register */
-#define GTCCR  _SFR_IO8(0x23)
-
-/* RegDef:  Timer/Counter Control Register A */
-#define TCCR0A _SFR_IO8(0x24)
-
-/* RegDef:  Timer/Counter Register */
-#define TCNT0  _SFR_IO8(0x26)
-
-/* RegDef:  Output Compare Register A */
-#define OCR0A  _SFR_IO8(0x27)
-
-/* RegDef:  General Purpose I/O Register 1 */
-#define GPIOR1 _SFR_IO8(0x2A)
-
-/* RegDef:  General Purpose I/O Register 2 */
-#define GPIOR2 _SFR_IO8(0x2B)
-
-/* RegDef:  SPI Control Register */
-#define SPCR   _SFR_IO8(0x2C)
-
-/* RegDef:  SPI Status Register */
-#define SPSR   _SFR_IO8(0x2D)
-
-/* RegDef:  SPI Data Register */
-#define SPDR   _SFR_IO8(0x2E)
-
-/* RegDef:  Analog Comperator Control and Status Register */
-#define ACSR   _SFR_IO8(0x30)
-
-/* RegDef:  On-chip Debug Register */
-#define OCDR   _SFR_IO8(0x31)
-
-/* RegDef:  Sleep Mode Control Register */
-#define SMCR   _SFR_IO8(0x33)
-
-/* RegDef:  MCU Status Register */
-#define MCUSR  _SFR_IO8(0x34)
-
-/* RegDef:  MCU Control Rgeister */
-#define MCUCR  _SFR_IO8(0x35)
-
-/* RegDef:  Store Program Memory Control and Status Register */
-#define SPMCSR _SFR_IO8(0x37)
-
-/* RegDef:  RAMPZ register. */
-#define RAMPZ  _SFR_IO8(0x3B)
-
-/* RegDef:  Watchdog Timer Control Register */
-#define WDTCR  _SFR_MEM8(0x60)
-
-/* RegDef:  Clock Prescale Register */
-#define CLKPR  _SFR_MEM8(0x61)
-
-/* RegDef:  Oscillator Calibration Register */
-#define OSCCAL _SFR_MEM8(0x66)
-
-/* RegDef:  External Interrupt Control Register A */
-#define EICRA  _SFR_MEM8(0x69)
-
-/* RegDef:  External Interrupt Control Register B */
-#define EICRB  _SFR_MEM8(0x6A)
-
-/* RegDef:  Timer/Counter 0 Interrupt Mask Register */
-#define TIMSK0 _SFR_MEM8(0x6E)
-
-/* RegDef:  Timer/Counter 1 Interrupt Mask Register */
-#define TIMSK1 _SFR_MEM8(0x6F)
-
-/* RegDef:  Timer/Counter 2 Interrupt Mask Register */
-#define TIMSK2 _SFR_MEM8(0x70)
-
-/* RegDef:  Timer/Counter 3 Interrupt Mask Register */
-#define TIMSK3 _SFR_MEM8(0x71)
-
-/* RegDef:  External Memory Control Register A */
-#define XMCRA _SFR_MEM8(0x74)
-
-/* RegDef:  External Memory Control Register A */
-#define XMCRB _SFR_MEM8(0x75)
-
-/* RegDef:  ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC    _SFR_MEM16(0x78)
-#endif
-#define ADCW   _SFR_MEM16(0x78)
-#define ADCL   _SFR_MEM8(0x78)
-#define ADCH   _SFR_MEM8(0x79)
-
-/* RegDef:  ADC Control and Status Register A */
-#define ADCSRA _SFR_MEM8(0x7A)
-
-/* RegDef:  ADC Control and Status Register B */
-#define ADCSRB _SFR_MEM8(0x7B)
-
-/* RegDef:  ADC Multiplex Selection Register */
-#define ADMUX  _SFR_MEM8(0x7C)
-
-/* RegDef:  Digital Input Disable Register 0 */
-#define DIDR0  _SFR_MEM8(0x7E)
-
-/* RegDef:  Digital Input Disable Register 1 */
-#define DIDR1  _SFR_MEM8(0x7F)
-
-/* RegDef:  Timer/Counter1 Control Register A */
-#define TCCR1A _SFR_MEM8(0x80)
-
-/* RegDef:  Timer/Counter1 Control Register B */
-#define TCCR1B _SFR_MEM8(0x81)
-
-/* RegDef:  Timer/Counter1 Control Register C */
-#define TCCR1C _SFR_MEM8(0x82)
-
-/* RegDef:  Timer/Counter1 Register */
-#define TCNT1  _SFR_MEM16(0x84)
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1H _SFR_MEM8(0x85)
-
-/* RegDef:  Timer/Counter1 Input Capture Register */
-#define ICR1   _SFR_MEM16(0x86)
-#define ICR1L  _SFR_MEM8(0x86)
-#define ICR1H  _SFR_MEM8(0x87)
-
-/* RegDef:  Timer/Counter1 Output Compare Register A */
-#define OCR1A  _SFR_MEM16(0x88)
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AH _SFR_MEM8(0x89)
-
-/* RegDef:  Timer/Counter1 Output Compare Register B */
-#define OCR1B  _SFR_MEM16(0x8A)
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BH _SFR_MEM8(0x8B)
-
-/* RegDef:  Timer/Counter1 Output Compare Register C */
-#define OCR1C  _SFR_MEM16(0x8C)
-#define OCR1CL _SFR_MEM8(0x8C)
-#define OCR1CH _SFR_MEM8(0x8D)
-
-/* RegDef:  Timer/Counter3 Control Register A */
-#define TCCR3A _SFR_MEM8(0x90)
-
-/* RegDef:  Timer/Counter3 Control Register B */
-#define TCCR3B _SFR_MEM8(0x91)
-
-/* RegDef:  Timer/Counter3 Control Register C */
-#define TCCR3C _SFR_MEM8(0x92)
-
-/* RegDef:  Timer/Counter3 Register */
-#define TCNT3  _SFR_MEM16(0x94)
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3H _SFR_MEM8(0x95)
-
-/* RegDef:  Timer/Counter3 Input Capture Register */
-#define ICR3   _SFR_MEM16(0x96)
-#define ICR3L  _SFR_MEM8(0x96)
-#define ICR3H  _SFR_MEM8(0x97)
-
-/* RegDef:  Timer/Counter3 Output Compare Register A */
-#define OCR3A  _SFR_MEM16(0x98)
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AH _SFR_MEM8(0x99)
-
-/* RegDef:  Timer/Counter3 Output Compare Register B */
-#define OCR3B  _SFR_MEM16(0x9A)
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3BH _SFR_MEM8(0x9B)
-
-/* RegDef:  Timer/Counter3 Output Compare Register C */
-#define OCR3C  _SFR_MEM16(0x9C)
-#define OCR3CL _SFR_MEM8(0x9C)
-#define OCR3CH _SFR_MEM8(0x9D)
-
-/* RegDef:  Timer/Counter2 Control Register A */
-#define TCCR2A _SFR_MEM8(0xB0)
-
-/* RegDef:  Timer/Counter2 Register */
-#define TCNT2  _SFR_MEM8(0xB2)
-
-/* RegDef:  Timer/Counter2 Output Compare Register */
-#define OCR2A  _SFR_MEM8(0xB3)
-
-/* RegDef:  Asynchronous Status Register */
-#define ASSR   _SFR_MEM8(0xB6)
-
-/* RegDef:  TWI Bit Rate Register */
-#define TWBR   _SFR_MEM8(0xB8)
-
-/* RegDef:  TWI Status Register */
-#define TWSR   _SFR_MEM8(0xB9)
-
-/* RegDef:  TWI (Slave) Address Register */
-#define TWAR   _SFR_MEM8(0xBA)
-
-/* RegDef:  TWI Data Register */
-#define TWDR   _SFR_MEM8(0xBB)
-
-/* RegDef:  TWI Control Register */
-#define TWCR   _SFR_MEM8(0xBC)
-
-/* RegDef:  USART0 Control and Status Register A */
-#define UCSR0A _SFR_MEM8(0xC0)
-
-/* RegDef:  USART0 Control and Status Register B */
-#define UCSR0B _SFR_MEM8(0xC1)
-
-/* RegDef:  USART0 Control and Status Register C */
-#define UCSR0C _SFR_MEM8(0xC2)
-
-/* RegDef:  USART0 Baud Rate Register */
-#define UBRR0  _SFR_MEM16(0xC4)
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0H _SFR_MEM8(0xC5)
-
-/* RegDef:  USART0 I/O Data Register */
-#define UDR0   _SFR_MEM8(0xC6)
-
-/* RegDef:  USART1 Control and Status Register A */
-#define UCSR1A _SFR_MEM8(0xC8)
-
-/* RegDef:  USART1 Control and Status Register B */
-#define UCSR1B _SFR_MEM8(0xC9)
-
-/* RegDef:  USART1 Control and Status Register C */
-#define UCSR1C _SFR_MEM8(0xCA)
-
-/* RegDef:  USART1 Baud Rate Register */
-#define UBRR1  _SFR_MEM16(0xCC)
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1H _SFR_MEM8(0xCD)
-
-/* RegDef:  USART1 I/O Data Register */
-#define UDR1   _SFR_MEM8(0xCE)
-
-/* RegDef:  CAN General Control Register*/
-#define CANGCON _SFR_MEM8(0xD8)
-
-/* RegDef:  CAN General Status Register*/
-#define CANGSTA _SFR_MEM8(0xD9)
-
-/* RegDef:  CAN General Interrupt Register*/
-#define CANGIT _SFR_MEM8(0xDA)
-
-/* RegDef:  CAN General Interrupt Enable Register*/
-#define CANGIE _SFR_MEM8(0xDB)
-
-/* RegDef:  CAN Enable MOb Register*/
-#define CANEN2 _SFR_MEM8(0xDC)
-
-/* RegDef:  CAN Enable MOb Register*/
-#define CANEN1 _SFR_MEM8(0xDD)
-
-/* RegDef:  CAN Enable Interrupt MOb Register*/
-#define CANIE2 _SFR_MEM8(0xDE)
-
-/* RegDef:  CAN Enable Interrupt MOb Register*/
-#define CANIE1 _SFR_MEM8(0xDF)
-
-/* RegDef:  CAN Status Interrupt MOb Register*/
-/*
- * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT
- * register.
- */
-#define CANSIT  _SFR_MEM16(0xE0)
-#define CANSIT2 _SFR_MEM8(0xE0)
-#define CANSIT1 _SFR_MEM8(0xE1)
-
-/* RegDef:  CAN Bit Timing Register 1*/
-#define CANBT1 _SFR_MEM8(0xE2)
-
-/* RegDef:  CAN Bit Timing Register 2*/
-#define CANBT2 _SFR_MEM8(0xE3)
-
-/* RegDef:  CAN Bit Timing Register 3*/
-#define CANBT3 _SFR_MEM8(0xE4)
-
-/* RegDef:  CAN Timer Control Register*/
-#define CANTCON _SFR_MEM8(0xE5)
-
-/* RegDef:  CAN Timer Register*/
-#define CANTIM _SFR_MEM16(0xE6)
-#define CANTIML _SFR_MEM8(0xE6)
-#define CANTIMH _SFR_MEM8(0xE7)
-
-/* RegDef:  CAN TTC Timer Register*/
-#define CANTTC _SFR_MEM16(0xE8)
-#define CANTTCL _SFR_MEM8(0xE8)
-#define CANTTCH _SFR_MEM8(0xE9)
-
-/* RegDef:  CAN Transmitt Error Counter Register*/
-#define CANTEC _SFR_MEM8(0xEA)
-
-/* RegDef:  CAN Receive Error Counter Register*/
-#define CANREC _SFR_MEM8(0xEB)
-
-/* RegDef:  CAN Highest Priority MOb Register*/
-#define CANHPMOB _SFR_MEM8(0xEC)
-
-/* RegDef:  CAN Page MOb Register*/
-#define CANPAGE _SFR_MEM8(0xED)
-
-/* RegDef:  CAN MOb Status Register*/
-#define CANSTMOB _SFR_MEM8(0xEE)
-
-/* RegDef:  CAN MOb Control and DLC Register*/
-#define CANCDMOB _SFR_MEM8(0xEF)
-
-/* RegDef:  CAN Identifier Tag Registers*/
-#define CANIDT  _SFR_MEM32(0xF0)
-
-#define CANIDT4 _SFR_MEM8(0xF0)
-#define CANIDT3 _SFR_MEM8(0xF1)
-#define CANIDT2 _SFR_MEM8(0xF2)
-#define CANIDT1 _SFR_MEM8(0xF3)
-
-/* RegDef:  CAN Identifier Mask Registers */
-#define CANIDM  _SFR_MEM32(0xF4)
-
-#define CANIDM4 _SFR_MEM8(0xF4)
-#define CANIDM3 _SFR_MEM8(0xF5)
-#define CANIDM2 _SFR_MEM8(0xF6)
-#define CANIDM1 _SFR_MEM8(0xF7)
-
-/* RegDef:  CAN TTC Timer Register*/
-#define CANSTM _SFR_MEM16(0xF8)
-#define CANSTML _SFR_MEM8(0xF8)
-#define CANSTMH _SFR_MEM8(0xF9)
-
-/* RegDef:  CAN Message Register*/
-#define CANMSG _SFR_MEM8(0xFA)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* CAN Transfer Complete or Error */
-#define CANIT_vect			_VECTOR(18)
-#define SIG_CAN_INTERRUPT1		_VECTOR(18)
-
-/* CAN Timer Overrun */
-#define OVRIT_vect			_VECTOR(19)
-#define SIG_CAN_OVERFLOW1		_VECTOR(19)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(20)
-#define SIG_SPI				_VECTOR(20)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(21)
-#define SIG_UART0_RECV			_VECTOR(21)
-#define SIG_USART0_RECV			_VECTOR(21)
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect		_VECTOR(22)
-#define SIG_UART0_DATA			_VECTOR(22)
-#define SIG_USART0_DATA			_VECTOR(22)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(23)
-#define SIG_UART0_TRANS			_VECTOR(23)
-#define SIG_USART0_TRANS		_VECTOR(23)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(24)
-#define SIG_COMPARATOR			_VECTOR(24)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(25)
-#define SIG_ADC				_VECTOR(25)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(26)
-#define SIG_EEPROM_READY		_VECTOR(26)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(27)
-#define SIG_INPUT_CAPTURE3		_VECTOR(27)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(28)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(28)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(29)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(29)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(30)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(30)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(31)
-#define SIG_OVERFLOW3			_VECTOR(31)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(32)
-#define SIG_UART1_RECV			_VECTOR(32)
-#define SIG_USART1_RECV			_VECTOR(32)
-
-/* USART1, Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(33)
-#define SIG_UART1_DATA			_VECTOR(33)
-#define SIG_USART1_DATA			_VECTOR(33)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(34)
-#define SIG_UART1_TRANS			_VECTOR(34)
-#define SIG_USART1_TRANS		_VECTOR(34)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(35)
-#define SIG_2WIRE_SERIAL		_VECTOR(35)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(36)
-#define SIG_SPM_READY			_VECTOR(36)
-
-#define _VECTORS_SIZE 148
-
-/* The Register Bit names are represented by their bit number (0-7). */
-
-/* Register Bits [ASSR]  */
-/* Asynchronous Status Register */
-#define    EXCLK      4
-#define    AS2        3
-#define    TCN2UB     2
-#define    OCR2UB     1
-#define    TCR2UB     0
-/* End Register Bits */
-
-/* Register Bits [TWCR] */
-/* 2-wire Control Register - TWCR */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-/* End Register Bits */
-
-/* Register Bits [TWAR]  */
-/* 2-wire Address Register - TWAR */
-#define    TWA6         7
-#define    TWA5         6
-#define    TWA4         5
-#define    TWA3         4
-#define    TWA2         3
-#define    TWA1         2
-#define    TWA0         1
-#define    TWGCE        0
-/* End Register Bits */
-
-/* Register Bits [TWSR]  */
-/* 2-wire Status Register - TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-/* End Register Bits */
-
-/* Register Bits [XMCRB]  */
-/* External Memory Control Register B - XMCRB */
-#define    XMBK         7
-#define    XMM2         2
-#define    XMM1         1
-#define    XMM0         0
-/* End Register Bits */
-
-/* Register Bits [XMCRA]  */
-/* External Memory Control Register A - XMCRA */
-#define    SRE         7
-#define    SRL2        6
-#define    SRL1        5
-#define    SRL0        4
-#define    SRW11       3
-#define    SRW10       2
-#define    SRW01       1
-#define    SRW00       0
-/* End Register Bits */
-
-/* Register Bits [RAMPZ]  */
-/* RAM Page Z select register - RAMPZ */
-#define     RAMPZ0      0
-/* End Register Bits */
-
-/* Register Bits [EICRA]  */
-/* External Interrupt Control Register A - EICRA */
-#define    ISC31        7
-#define    ISC30        6
-#define    ISC21        5
-#define    ISC20        4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-/* End Register Bits */
-
-/* Register Bits [EICRB]  */
-/* External Interrupt Control Register B - EICRB */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-/* End Register Bits */
-
-/* Register Bits [SPMCSR]  */
-/* Store Program Memory Control Register - SPMCSR, SPMCR */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-/* End Register Bits */
-
-/* Register Bits [EIMSK]  */
-/* External Interrupt MaSK register - EIMSK */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-/* End Register Bits */
-
-/* Register Bits [EIFR]  */
-/* External Interrupt Flag Register - EIFR */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-#define    INTF3        3
-#define    INTF2        2
-#define    INTF1        1
-#define    INTF0        0
-/* End Register Bits */
-
-/* Register Bits [TCCR2]  */
-/* Timer/Counter 2 Control Register - TCCR2 */
-#define    FOC2A        7
-#define    WGM20        6
-#define    COM2A1       5
-#define    COM2A0       4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-/* End Register Bits */
-
-/* Register Bits [TCCR1A]  */
-/* Timer/Counter 1 Control and Status Register A - TCCR1A */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    COM1C1       3
-#define    COM1C0       2
-#define    WGM11        1
-#define    WGM10        0
-/* End Register Bits */
-
-/* Register Bits [TCCR3A]  */
-/* Timer/Counter 3 Control and Status Register A - TCCR3A */
-#define    COM3A1       7
-#define    COM3A0       6
-#define    COM3B1       5
-#define    COM3B0       4
-#define    COM3C1       3
-#define    COM3C0       2
-#define    WGM31        1
-#define    WGM30        0
-/* End Register Bits */
-
-/* Register Bits [TCCR1B]  */
-/* Timer/Counter 1 Control and Status Register B - TCCR1B */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-/* End Register Bits */
-
-/* Register Bits [TCCR3B]  */
-/* Timer/Counter 3 Control and Status Register B - TCCR3B */
-#define    ICNC3        7
-#define    ICES3        6
-#define    WGM33        4
-#define    WGM32        3
-#define    CS32         2
-#define    CS31         1
-#define    CS30         0
-/* End Register Bits */
-
-/* Register Bits [TCCR3C]  */
-/* Timer/Counter 3 Control Register C - TCCR3C */
-#define    FOC3A        7
-#define    FOC3B        6
-#define    FOC3C        5
-/* End Register Bits */
-
-/* Register Bits [TCCR1C]  */
-/* Timer/Counter 1 Control Register C - TCCR1C */
-#define    FOC1A        7
-#define    FOC1B        6
-#define    FOC1C        5
-/* End Register Bits */
-
-/* Register Bits [OCDR]  */
-/* On-chip Debug Register - OCDR */
-#define    IDRD         7
-#define    OCDR7        7
-#define    OCDR6        6
-#define    OCDR5        5
-#define    OCDR4        4
-#define    OCDR3        3
-#define    OCDR2        2
-#define    OCDR1        1
-#define    OCDR0        0
-/* End Register Bits */
-
-/* Register Bits [WDTCR]  */
-/* Watchdog Timer Control Register - WDTCR */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-/* End Register Bits */
-
-/* Register Bits [SPSR]  */
-/* SPI Status Register - SPSR */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-/* End Register Bits */
-
-/* Register Bits [SPCR]  */
-/* SPI Control Register - SPCR */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-/* End Register Bits */
-
-/* Register Bits [UCSR1C]  */
-/* USART1 Register C - UCSR1C */
-#define    UMSEL1       6
-#define    UPM11        5
-#define    UPM10        4
-#define    USBS1        3
-#define    UCSZ11       2
-#define    UCSZ10       1
-#define    UCPOL1       0
-/* End Register Bits */
-
-/* Register Bits [UCSR0C]  */
-/* USART0 Register C - UCSR0C */
-#define    UMSEL0       6
-#define    UPM01        5
-#define    UPM00        4
-#define    USBS0        3
-#define    UCSZ01       2
-#define    UCSZ00       1
-#define    UCPOL0       0
-/* End Register Bits */
-
-/* Register Bits [UCSR1A]  */
-/* USART1 Status Register A - UCSR1A */
-#define    RXC1         7
-#define    TXC1         6
-#define    UDRE1        5
-#define    FE1          4
-#define    DOR1         3
-#define    UPE1         2
-#define    U2X1         1
-#define    MPCM1        0
-/* End Register Bits */
-
-/* Register Bits [UCSR0A]  */
-/* USART0 Status Register A - UCSR0A */
-#define    RXC0         7
-#define    TXC0         6
-#define    UDRE0        5
-#define    FE0          4
-#define    DOR0         3
-#define    UPE0         2
-#define    U2X0         1
-#define    MPCM0        0
-/* End Register Bits */
-
-/* Register Bits [UCSR1B]  */
-/* USART1 Control Register B - UCSR1B */
-#define    RXCIE1       7
-#define    TXCIE1       6
-#define    UDRIE1       5
-#define    RXEN1        4
-#define    TXEN1        3
-#define    UCSZ12       2
-#define    RXB81        1
-#define    TXB81        0
-/* End Register Bits */
-
-/* Register Bits [UCSR0B]  */
-/* USART0 Control Register B - UCSR0B */
-#define    RXCIE0       7
-#define    TXCIE0       6
-#define    UDRIE0       5
-#define    RXEN0        4
-#define    TXEN0        3
-#define    UCSZ02       2
-#define    RXB80        1
-#define    TXB80        0
-/* End Register Bits */
-
-/* Register Bits [ACSR]  */
-/* Analog Comparator Control and Status Register - ACSR */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-/* End Register Bits */
-
-/* Register Bits [ADCSRA]  */
-/* ADC Control and status register - ADCSRA */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADATE        5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-/* End Register Bits */
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-/* Register Bits [ADCSRB]  */
-/* ADC Control and status register - ADCSRB */
-#define    ACME         6
-#define    ADTS2        2
-#define    ADTS1        1
-#define    ADTS0        0
-/* End Register Bits */
-
-/* Register Bits [ADMUX]  */
-/* ADC Multiplexer select - ADMUX */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-/* End Register Bits */
-
-/* Register Bits [DIDR0]  */
-/* Digital Input Disable Register 0 */
-#define    ADC7D        7
-#define    ADC6D        6
-#define    ADC5D        5
-#define    ADC4D        4
-#define    ADC3D        3
-#define    ADC2D        2
-#define    ADC1D        1
-#define    ADC0D        0
-/* End Register Bits */
-
-/* Register Bits [DIDR1]  */
-/* Digital Input Disable Register 1 */
-#define    AIN1D        1
-#define    AIN0D        0
-/* End Register Bits */
-
-/* Register Bits [PORTA]  */
-/* Port A Data Register - PORTA */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-/* End Register Bits */
-
-/* Register Bits [DDRA]  */
-/* Port A Data Direction Register - DDRA */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-/* End Register Bits */
-
-/* Register Bits [PINA]  */
-/* Port A Input Pins - PINA */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-/* End Register Bits */
-
-/* Register Bits [PORTB]  */
-/* Port B Data Register - PORTB */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-/* End Register Bits */
-
-/* Register Bits [DDRB]  */
-/* Port B Data Direction Register - DDRB */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-/* End Register Bits */
-
-/* Register Bits [PINB]  */
-/* Port B Input Pins - PINB */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-/* End Register Bits */
-
-/* Register Bits [PORTC]  */
-/* Port C Data Register - PORTC */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-/* End Register Bits */
-
-/* Register Bits [DDRC]  */
-/* Port C Data Direction Register - DDRC */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-/* End Register Bits */
-
-/* Register Bits [PINC]  */
-/* Port C Input Pins - PINC */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-/* End Register Bits */
-
-/* Register Bits [PORTD]  */
-/* Port D Data Register - PORTD */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-/* End Register Bits */
-
-/* Register Bits [DDRD]  */
-/* Port D Data Direction Register - DDRD */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-/* End Register Bits */
-
-/* Register Bits [PIND]  */
-/* Port D Input Pins - PIND */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-/* End Register Bits */
-
-/* Register Bits [PORTE]  */
-/* Port E Data Register - PORTE */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-/* End Register Bits */
-
-/* Register Bits [DDRE]  */
-/* Port E Data Direction Register - DDRE */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-/* End Register Bits */
-
-/* Register Bits [PINE]  */
-/* Port E Input Pins - PINE */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-/* End Register Bits */
-
-/* Register Bits [PORTF]  */
-/* Port F Data Register - PORTF */
-#define    PF7          7
-#define    PF6          6
-#define    PF5          5
-#define    PF4          4
-#define    PF3          3
-#define    PF2          2
-#define    PF1          1
-#define    PF0          0
-/* End Register Bits */
-
-/* Register Bits [DDRF]  */
-/* Port F Data Direction Register - DDRF */
-#define    DDF7         7
-#define    DDF6         6
-#define    DDF5         5
-#define    DDF4         4
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-#define    DDF0         0
-/* End Register Bits */
-
-/* Register Bits [PINF]  */
-/* Port F Input Pins - PINF */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-/* End Register Bits */
-
-/* Register Bits [PORTG]  */
-/* Port G Data Register - PORTG */
-#define    PG4          4
-#define    PG3          3
-#define    PG2          2
-#define    PG1          1
-#define    PG0          0
-/* End Register Bits */
-
-/* Register Bits [DDRG]  */
-/* Port G Data Direction Register - DDRG */
-#define    DDG4         4
-#define    DDG3         3
-#define    DDG2         2
-#define    DDG1         1
-#define    DDG0         0
-/* End Register Bits */
-
-/* Register Bits [PING]  */
-/* Port G Input Pins - PING */
-#define    PING4        4
-#define    PING3        3
-#define    PING2        2
-#define    PING1        1
-#define    PING0        0
-/* End Register Bits */
-
-
-/* Register Bits [TIFR0]  */
-/* Timer/Counter 0 interrupt Flag Register */
-#define    OCF0A        1
-#define    TOV0         0
-/* End Register Bits */
-
-/* Register Bits [TIFR1]  */
-/* Timer/Counter 1 interrupt Flag Register */
-#define    ICF1       5
-#define    OCF1C      3
-#define    OCF1B      2
-#define    OCF1A      1
-#define    TOV1       0
-/* End Register Bits */
-
-/* Register Bits [TIFR2]  */
-/* Timer/Counter 2 interrupt Flag Register */
-#define    OCF2A      1
-#define    TOV2       0
-/* End Register Bits */
-
-/* Register Bits [TIFR3]  */
-/* Timer/Counter 3 interrupt Flag Register */
-#define    ICF3       5
-#define    OCF3C      3
-#define    OCF3B      2
-#define    OCF3A      1
-#define    TOV3       0
-/* End Register Bits */
-
-/* Register Bits [GPIOR0]  */
-/* General Purpose I/O Register 0 */
-#define    GPIOR07     7
-#define    GPIOR06     6
-#define    GPIOR05     5
-#define    GPIOR04     4
-#define    GPIOR03     3
-#define    GPIOR02     2
-#define    GPIOR01     1
-#define    GPIOR00     0
-/* End Register Bits */
-
-/* Register Bits [GPIOR1]  */
-/* General Purpose I/O Register 1 */
-#define    GPIOR17     7
-#define    GPIOR16     6
-#define    GPIOR15     5
-#define    GPIOR14     4
-#define    GPIOR13     3
-#define    GPIOR12     2
-#define    GPIOR11     1
-#define    GPIOR10     0
-/* End Register Bits */
-
-/* Register Bits [GPIOR2]  */
-/* General Purpose I/O Register 2 */
-#define    GPIOR27     7
-#define    GPIOR26     6
-#define    GPIOR25     5
-#define    GPIOR24     4
-#define    GPIOR23     3
-#define    GPIOR22     2
-#define    GPIOR21     1
-#define    GPIOR20     0
-/* End Register Bits */
-
-/* Register Bits [EECR]  */
-/* EEPROM Control Register */
-#define    EERIE       3
-#define    EEMWE       2
-#define    EEWE        1
-#define    EERE        0
-/* End Register Bits */
-
-/* Register Bits [EEDR]  */
-/* EEPROM Data Register */
-#define    EEDR7     7
-#define    EEDR6     6
-#define    EEDR5     5
-#define    EEDR4     4
-#define    EEDR3     3
-#define    EEDR2     2
-#define    EEDR1     1
-#define    EEDR0     0
-/* End Register Bits */
-
-/* Register Bits [EEARL]  */
-/* EEPROM Address Register */
-#define    EEAR7     7
-#define    EEAR6     6
-#define    EEAR5     5
-#define    EEAR4     4
-#define    EEAR3     3
-#define    EEAR2     2
-#define    EEAR1     1
-#define    EEAR0     0
-/* End Register Bits */
-
-/* Register Bits [EEARH]  */
-/* EEPROM Address Register */
-#define    EEAR11    3
-#define    EEAR10    2
-#define    EEAR9     1
-#define    EEAR8     0
-/* End Register Bits */
-
-/* Register Bits [GTCCR]  */
-/* General Timer/Counter Control Register  */
-#define    TSM      7
-#define    PSR2     1
-#define    PSR310   0
-/* End Register Bits */
-
-/* Register Bits [TCCR0A]  */
-/* Timer/Counter Control Register A */
-/* ALSO COVERED IN GENERIC SECTION */
-#define    FOC0A    7
-#define    WGM00    6
-#define    COM0A1   5
-#define    COM0A0   4
-#define    WGM01    3
-#define    CS02     2
-#define    CS01     1
-#define    CS00     0
-/* End Register Bits */
-
-/* Register Bits [OCR0A]  */
-/* Output Compare Register A */
-#define    OCR0A7     7
-#define    OCR0A6     6
-#define    OCR0A5     5
-#define    OCR0A4     4
-#define    OCR0A3     3
-#define    OCR0A2     2
-#define    OCR0A1     1
-#define    OCR0A0     0
-/* End Register Bits */
-
-
-/* Register Bits [SPIDR]  */
-/* SPI Data Register */
-#define    SPD7     7
-#define    SPD6     6
-#define    SPD5     5
-#define    SPD4     4
-#define    SPD3     3
-#define    SPD2     2
-#define    SPD1     1
-#define    SPD0     0
-/* End Register Bits */
-
-/* Register Bits [SMCR]  */
-/* Sleep Mode Control Register */
-#define    SM2     3
-#define    SM1     2
-#define    SM0     1
-#define    SE      0
-/* End Register Bits */
-
-/* Register Bits [MCUSR]  */
-/* MCU Status Register */
-#define    JTRF    4
-#define    WDRF    3
-#define    BORF    2
-#define    EXTRF   1
-#define    PORF    0
-/* End Register Bits */
-
-/* Register Bits [MCUCR]  */
-/* MCU Control Register */
-#define    JTD     7
-#define    PUD     4
-#define    IVSEL   1
-#define    IVCE    0
-/* End Register Bits */
-
-/* Register Bits [CLKPR]  */
-/* Clock Prescale Register */
-#define    CLKPCE     7
-#define    CLKPS3     3
-#define    CLKPS2     2
-#define    CLKPS1     1
-#define    CLKPS0     0
-/* End Register Bits */
-
-/* Register Bits [OSCCAL]  */
-/* Oscillator Calibration Register */
-#define    CAL6     6
-#define    CAL5     5
-#define    CAL4     4
-#define    CAL3     3
-#define    CAL2     2
-#define    CAL1     1
-#define    CAL0     0
-/* End Register Bits */
-
-/* Register Bits [TIMSK0]  */
-/* Timer/Counter 0 interrupt mask Register */
-#define    OCIE0A      1
-#define    TOIE0       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK1]  */
-/* Timer/Counter 1 interrupt mask Register */
-#define    ICIE1       5
-#define    OCIE1C      3
-#define    OCIE1B      2
-#define    OCIE1A      1
-#define    TOIE1       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK2]  */
-/* Timer/Counter 2 interrupt mask Register */
-#define    OCIE2A      1
-#define    TOIE2       0
-/* End Register Bits */
-
-/* Register Bits [TIMSK3]  */
-/* Timer/Counter 3 interrupt mask Register */
-#define    ICIE3       5
-#define    OCIE3C      3
-#define    OCIE3B      2
-#define    OCIE3A      1
-#define    TOIE3       0
-/* End Register Bits */
-
-//Begin CAN specific parts
-
-/* Register Bits [CANGCON]  */
-/* CAN General Control Register */
-#define    ABRQ       7
-#define    OVRQ       6
-#define    TTC        5
-#define    SYNTTC     4
-#define    LISTEN     3
-#define    TEST       2
-#define    ENASTB     1
-#define    SWRES      0
-/* End Register Bits */
-
-/* Register Bits [CANGSTA]  */
-/* CAN General Status Register */
-#define    OVFG       6
-#define    OVRG       6
-#define    TXBSY      4
-#define    RXBSY      3
-#define    ENFG       2
-#define    BOFF       1
-#define    ERRP       0
-/* End Register Bits */
-
-/* Register Bits [CANGIT]  */
-/* CAN General Interrupt Register */
-#define    CANIT      7
-#define    BOFFIT     6
-#define    OVRTIM     5
-#define    BXOK       4
-#define    SERG       3
-#define    CERG       2
-#define    FERG       1
-#define    AERG       0
-/* End Register Bits */
-
-/* Register Bits [CANGIE]  */
-/* CAN General Interrupt Enable */
-#define    ENIT        7
-#define    ENBOFF      6
-#define    ENRX        5
-#define    ENTX        4
-#define    ENERR       3
-#define    ENBX        2
-#define    ENERG       1
-#define    ENOVRT      0
-/* End Register Bits */
-
-/* Register Bits [CANEN2]  */
-/* CAN Enable MOb Register */
-#define    ENMOB7      7
-#define    ENMOB6      6
-#define    ENMOB5      5
-#define    ENMOB4      4
-#define    ENMOB3      3
-#define    ENMOB2      2
-#define    ENMOB1      1
-#define    ENMOB0      0
-/* End Register Bits */
-
-/* Register Bits [CANEN1]  */
-/* CAN Enable MOb Register */
-#define    ENMOB14      6
-#define    ENMOB13      5
-#define    ENMOB12      4
-#define    ENMOB11      3
-#define    ENMOB10      2
-#define    ENMOB9       1
-#define    ENMOB8       0
-/* End Register Bits */
-
-/* Register Bits [CANIE2]  */
-/* CAN Interrupt Enable MOb Register */
-#define    IEMOB7      7
-#define    IEMOB6      6
-#define    IEMOB5      5
-#define    IEMOB4      4
-#define    IEMOB3      3
-#define    IEMOB2      2
-#define    IEMOB1      1
-#define    IEMOB0      0
-/* End Register Bits */
-
-/* Register Bits [CANIE1]  */
-/* CAN Interrupt Enable MOb Register */
-#define    IEMOB14      6
-#define    IEMOB13      5
-#define    IEMOB12      4
-#define    IEMOB11      3
-#define    IEMOB10      2
-#define    IEMOB9       1
-#define    IEMOB8       0
-/* End Register Bits */
-
-/* Register Bits [CANSIT2]  */
-/* CAN Status Interrupt MOb Register */
-#define    SIT7      7
-#define    SIT6      6
-#define    SIT5      5
-#define    SIT4      4
-#define    SIT3      3
-#define    SIT2      2
-#define    SIT1      1
-#define    SIT0      0
-/* End Register Bits */
-
-/* Register Bits [CANSIT1]  */
-/* CAN Status Interrupt MOb Register */
-#define    SIT14      6
-#define    SIT13      5
-#define    SIT12      4
-#define    SIT11      3
-#define    SIT10      2
-#define    SIT9       1
-#define    SIT8       0
-/* End Register Bits */
-
-/* Register Bits [CANBT1]  */
-/* Bit Timing Register 1 */
-#define    BRP5       6
-#define    BRP4       5
-#define    BRP3       4
-#define    BRP2       3
-#define    BRP1       2
-#define    BRP0       1
-/* End Register Bits */
-
-/* Register Bits [CANBT2]  */
-/* Bit Timing Register 2 */
-#define    SJW1       6
-#define    SJW0       5
-#define    PRS2       3
-#define    PRS1       2
-#define    PRS0       1
-/* End Register Bits */
-
-/* Register Bits [CANBT3]  */
-/* Bit Timing Register 3 */
-#define    PHS22      6
-#define    PHS21      5
-#define    PHS20      4
-#define    PHS12      3
-#define    PHS11      2
-#define    PHS10      1
-#define    SMP        0
-/* End Register Bits */
-
-/* Register Bits [CANTCON]  */
-/* CAN Timer Control Register */
-#define    TPRSC7      7
-#define    TPRSC6      6
-#define    TPRSC5      5
-#define    TPRSC4      4
-#define    TPRSC3      3
-#define    TPRSC2      2
-#define    TPRSC1      1
-#define    TPRSC0      0
-/* End Register Bits */
-
-/* Register Bits [CANTIML]  */
-/* CAN Timer Register Low */
-#define    CANTIM7      7
-#define    CANTIM6      6
-#define    CANTIM5      5
-#define    CANTIM4      4
-#define    CANTIM3      3
-#define    CANTIM2      2
-#define    CANTIM1      1
-#define    CANTIM0      0
-/* End Register Bits */
-
-/* Register Bits [CANTIMH]  */
-/* CAN Timer Register High */
-#define    CANTIM15     7
-#define    CANTIM14     6
-#define    CANTIM13     5
-#define    CANTIM12     4
-#define    CANTIM11     3
-#define    CANTIM10     2
-#define    CANTIM9      1
-#define    CANTIM8      0
-/* End Register Bits */
-
-/* Register Bits [CANTTCL]  */
-/* CAN TTC Timer Register Low */
-#define    TIMTTC7      7
-#define    TIMTTC6      6
-#define    TIMTTC5      5
-#define    TIMTTC4      4
-#define    TIMTTC3      3
-#define    TIMTTC2      2
-#define    TIMTTC1      1
-#define    TIMTTC0      0
-/* End Register Bits */
-
-/* Register Bits [CANTTCH]  */
-/* CAN TTC Timer Register High */
-#define    TIMTTC15     7
-#define    TIMTTC14     6
-#define    TIMTTC13     5
-#define    TIMTTC12     4
-#define    TIMTTC11     3
-#define    TIMTTC10     2
-#define    TIMTTC9      1
-#define    TIMTTC8      0
-/* End Register Bits */
-
-/* Register Bits [CANTEC]  */
-/* CAN Transmitt Error Counter */
-#define    TEC7      7
-#define    TEC6      6
-#define    TEC5      5
-#define    TEC4      4
-#define    TEC3      3
-#define    TEC2      2
-#define    TEC1      1
-#define    TEC0      0
-/* End Register Bits */
-
-/* Register Bits [CANREC]  */
-/* CAN Receive Error Counter */
-#define    REC7      7
-#define    REC6      6
-#define    REC5      5
-#define    REC4      4
-#define    REC3      3
-#define    REC2      2
-#define    REC1      1
-#define    REC0      0
-/* End Register Bits */
-
-/* Register Bits [CANHPMOB]  */
-/* Highest Priority MOb */
-#define    HPMOB3     7
-#define    HPMOB2     6
-#define    HPMOB1     5
-#define    HPMOB0     4
-#define    CGP3       3
-#define    CGP2       2
-#define    CGP1       1
-#define    CGP0       0
-/* End Register Bits */
-
-/* Register Bits [CANPAGE]  */
-/* CAN Page MOb Register */
-#define    MOBNB3     7
-#define    MOBNB2     6
-#define    MOBNB1     5
-#define    MOBNB0     4
-#define    AINC       3
-#define    INDX2      2
-#define    INDX1      1
-#define    INDX0      0
-/* End Register Bits */
-
-/* Register Bits [CANSTMOB]  */
-/* CAN MOb Status Register */
-#define    DLCW       7
-#define    TXOK       6
-#define    RXOK       5
-#define    BERR       4
-#define    SERR       3
-#define    CERR       2
-#define    FERR       1
-#define    AERR       0
-/* End Register Bits */
-
-/* Register Bits [CANCDMOB]  */
-/* CAN MOb Control and DLC Register */
-#define    CONMOB1    7
-#define    CONMOB0    6
-#define    RPLV       5
-#define    IDE        4
-#define    DLC3       3
-#define    DLC2       2
-#define    DLC1       1
-#define    DLC0       0
-/* End Register Bits */
-
-/* Register Bits [CANIDT4]  */
-/* CAN Identifier Tag Register 4 */
-#define    IDT4       7
-#define    IDT3       6
-#define    IDT2       5
-#define    IDT1       4
-#define    IDT0       3
-#define    RTRTAG     2
-#define    RB1TAG     1
-#define    RB0TAG     0
-/* End Register Bits */
-
-/* Register Bits [CANIDT3]  */
-/* CAN Identifier Tag Register 3 */
-#define    IDT12      7
-#define    IDT11      6
-#define    IDT10      5
-#define    IDT9       4
-#define    IDT8       3
-#define    IDT7       2
-#define    IDT6       1
-#define    IDT5       0
-/* End Register Bits */
-
-/* Register Bits [CANIDT2]  */
-/* CAN Identifier Tag Register 2 */
-#define    IDT20      7
-#define    IDT19      6
-#define    IDT18      5
-#define    IDT17      4
-#define    IDT16      3
-#define    IDT15      2
-#define    IDT14      1
-#define    IDT13      0
-/* End Register Bits */
-
-/* Register Bits [CANIDT1]  */
-/* CAN Identifier Tag Register 1 */
-#define    IDT28      7
-#define    IDT27      6
-#define    IDT26      5
-#define    IDT25      4
-#define    IDT24      3
-#define    IDT23      2
-#define    IDT22      1
-#define    IDT21      0
-/* End Register Bits */
-
-/* Register Bits [CANIDM4]  */
-/* CAN Identifier Mask Register 4 */
-#define    IDMSK4       7
-#define    IDMSK3       6
-#define    IDMSK2       5
-#define    IDMSK1       4
-#define    IDMSK0       3
-#define    RTRMSK       2
-#define    IDEMSK       0
-/* End Register Bits */
-
-/* Register Bits [CANIDM3]  */
-/* CAN Identifier Mask Register 3 */
-#define    IDMSK12      7
-#define    IDMSK11      6
-#define    IDMSK10      5
-#define    IDMSK9       4
-#define    IDMSK8       3
-#define    IDMSK7       2
-#define    IDMSK6       1
-#define    IDMSK5       0
-/* End Register Bits */
-
-/* Register Bits [CANIDM2]  */
-/* CAN Identifier Mask Register 2 */
-#define    IDMSK20      7
-#define    IDMSK19      6
-#define    IDMSK18      5
-#define    IDMSK17      4
-#define    IDMSK16      3
-#define    IDMSK15      2
-#define    IDMSK14      1
-#define    IDMSK13      0
-/* End Register Bits */
-
-/* Register Bits [CANIDM1]  */
-/* CAN Identifier Mask Register 1 */
-#define    IDMSK28      7
-#define    IDMSK27      6
-#define    IDMSK26      5
-#define    IDMSK25      4
-#define    IDMSK24      3
-#define    IDMSK23      2
-#define    IDMSK22      1
-#define    IDMSK21      0
-/* End Register Bits */
-
-/* Register Bits [CANSTML]  */
-/* CAN Timer Register of some sort, low*/
-#define    TIMSTM7       7
-#define    TIMSTM6       6
-#define    TIMSTM5       5
-#define    TIMSTM4       4
-#define    TIMSTM3       3
-#define    TIMSTM2       2
-#define    TIMSTM1       1
-#define    TIMSTM0       0
-/* End Register Bits */
-
-/* Register Bits [CANSTMH]  */
-/* CAN Timer Register of some sort, high */
-#define    TIMSTM15       7
-#define    TIMSTM14       6
-#define    TIMSTM13       5
-#define    TIMSTM12       4
-#define    TIMSTM11       3
-#define    TIMSTM10       2
-#define    TIMSTM9        1
-#define    TIMSTM8        0
-/* End Register Bits */
-
-/* Register Bits [CANMSG]  */
-/* CAN Message Register */
-#define    MSG7           7
-#define    MSG6           6
-#define    MSG5           5
-#define    MSG4           4
-#define    MSG3           3
-#define    MSG2           2
-#define    MSG1           1
-#define    MSG0           0
-/* End Register Bits */
-
-/* Begin Verbatim */
-
-/* Timer/Counter Control Register (generic) */
-#define    FOC          7
-#define    WGM0         6
-#define    COM1         5
-#define    COM0         4
-#define    WGM1         3
-#define    CS2          2
-#define    CS1          1
-#define    CS0          0
-
-/* Timer/Counter Control Register A (generic) */
-#define    COMA1        7
-#define    COMA0        6
-#define    COMB1        5
-#define    COMB0        4
-#define    COMC1        3
-#define    COMC0        2
-#define    WGMA1        1
-#define    WGMA0        0
-
-/* Timer/Counter Control and Status Register B (generic) */
-#define    ICNC         7
-#define    ICES         6
-#define    WGMB3        4
-#define    WGMB2        3
-#define    CSB2         2
-#define    CSB1         1
-#define    CSB0         0
-
-/* Timer/Counter Control Register C (generic) */
-#define    FOCA         7
-#define    FOCB         6
-#define    FOCC         5
-
-/* Port Data Register (generic) */
-#define    PORT7        7
-#define    PORT6        6
-#define    PORT5        5
-#define    PORT4        4
-#define    PORT3        3
-#define    PORT2        2
-#define    PORT1        1
-#define    PORT0        0
-
-/* Port Data Direction Register (generic) */
-#define    DD7          7
-#define    DD6          6
-#define    DD5          5
-#define    DD4          4
-#define    DD3          3
-#define    DD2          2
-#define    DD1          1
-#define    DD0          0
-
-/* Port Input Pins (generic) */
-#define    PIN7         7
-#define    PIN6         6
-#define    PIN5         5
-#define    PIN4         4
-#define    PIN3         3
-#define    PIN2         2
-#define    PIN1         1
-#define    PIN0         0
-
-/* USART Status Register A (generic) */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    UPE          2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART Control Register B (generic) */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ         2
-#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
-#define    RXB8         1
-#define    TXB8         0
-
-/* USART Register C (generic) */
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* End Verbatim */
-
-/**@}*/
-#endif  /* _AVR_IOCANXX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom103.h b/cpukit/score/cpu/avr/avr/iom103.h
deleted file mode 100644
index 6ca791b..0000000
--- a/cpukit/score/cpu/avr/avr/iom103.h
+++ /dev/null
@@ -1,687 +0,0 @@
-/**
- * @file avr/iom103.h
- *
- * @brief Definitions for ATmega103
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2002, Marek Michalkiewicz
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright
- *     notice, this list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright
- *     notice, this list of conditions and the following disclaimer in
- *     the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- *  POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM103_H_
-#define _AVR_IOM103_H_ 1
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom103.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/**
- * @defgroup AvrDef_iom103 ATmega103 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* I/O registers */
-
-/* Input Pins, Port F */
-#define PINF	_SFR_IO8(0x00)
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03)
-
-/* ADC Data Register */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-
-/* ADC Control and status register */
-#define ADCSR	_SFR_IO8(0x06)
-
-/* ADC Multiplexer select */
-#define ADMUX	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART Baud Rate Register */
-#define UBRR	_SFR_IO8(0x09)
-
-/* UART Control Register */
-#define UCR	_SFR_IO8(0x0A)
-
-/* UART Status Register */
-#define USR	_SFR_IO8(0x0B)
-
-/* UART I/O Data Register */
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2	_SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control register */
-#define TCCR2	_SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define ASSR	_SFR_IO8(0x30)
-
-/* Output Compare Register 0 */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x36)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK	_SFR_IO8(0x37)
-
-/* Èxternal Interrupt Flag Register */
-#define EIFR	_SFR_IO8(0x38)
-
-/* External Interrupt MaSK register */
-#define EIMSK	_SFR_IO8(0x39)
-
-/* External Interrupt Control Register */
-#define EICR	_SFR_IO8(0x3A)
-
-/* RAM Page Z select register */
-#define RAMPZ	_SFR_IO8(0x3B)
-
-/* XDIV Divide control register */
-#define XDIV	_SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(14)
-#define SIG_OVERFLOW1			_VECTOR(14)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(15)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* UART, Rx Complete */
-#define UART_RX_vect			_VECTOR(18)
-#define SIG_UART_RECV			_VECTOR(18)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(19)
-#define SIG_UART_DATA			_VECTOR(19)
-
-/* UART, Tx Complete */
-#define UART_TX_vect			_VECTOR(20)
-#define SIG_UART_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-#define _VECTORS_SIZE 96
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* XDIV Divide control register*/
-#define    XDIVEN       7
-#define    XDIV6        6
-#define    XDIV5        5
-#define    XDIV4        4
-#define    XDIV3        3
-#define    XDIV2        2
-#define    XDIV1        1
-#define    XDIV0        0
-
-/* RAM Page Z select register */
-#define     RAMPZ0      0
-
-/* External Interrupt Control Register */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-
-/* External Interrupt MaSK register */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-
-/* Èxternal Interrupt Flag Register */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-
-/* Timer/Counter Interrupt MaSK register */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag Register */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* MCU general Control Register */
-#define    SRE          7
-#define    SRW          6
-#define    SE           5
-#define    SM1          4
-#define    SM0          3
-
-/* MCU Status Register */
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter 0 Control Register */
-#define    PWM0         6
-#define    COM01        5
-#define    COM00        4
-#define    CTC0         3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define    AS0          3
-#define    TCN0UB       2
-#define    OCR0UB       1
-#define    TCR0UB       0
-
-/* Timer/Counter 1 Control Register */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    PWM11        1
-#define    PWM10        0
-
-/* Timer/Counter 1 Control and Status Register */
-#define    ICNC1        7
-#define    ICES1        6
-#define    CTC1         3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 2 Control register */
-#define    PWM2         6
-#define    COM21        5
-#define    COM20        4
-#define    CTC2         3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Watchdog Timer Control Register */
-#define    WDTOE        4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/* Data Register, Port A */
-#define    PA7          7
-#define    PA6          6
-#define    PA5          5
-#define    PA4          4
-#define    PA3          3
-#define    PA2          2
-#define    PA1          1
-#define    PA0          0
-
-/* Data Direction Register, Port A */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Input Pins, Port A */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Data Register, Port B */
-#define    PB7          7
-#define    PB6          6
-#define    PB5          5
-#define    PB4          4
-#define    PB3          3
-#define    PB2          2
-#define    PB1          1
-#define    PB0          0
-
-/* Data Direction Register, Port B */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Input Pins, Port B */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Data Register, Port C */
-#define    PC7          7
-#define    PC6          6
-#define    PC5          5
-#define    PC4          4
-#define    PC3          3
-#define    PC2          2
-#define    PC1          1
-#define    PC0          0
-
-/* Data Register, Port D */
-#define    PD7          7
-#define    PD6          6
-#define    PD5          5
-#define    PD4          4
-#define    PD3          3
-#define    PD2          2
-#define    PD1          1
-#define    PD0          0
-
-/* Data Direction Register, Port D */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Input Pins, Port D */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Data Register, Port E */
-#define    PE7          7
-#define    PE6          6
-#define    PE5          5
-#define    PE4          4
-#define    PE3          3
-#define    PE2          2
-#define    PE1          1
-#define    PE0          0
-
-/* Data Direction Register, Port E */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Input Pins, Port E */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* Input Pins, Port F */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* SPI Status Register */
-#define    SPIF         7
-#define    WCOL         6
-
-/* SPI Control Register */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* UART Status Register */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-
-/* UART Control Register */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    CHR9         2
-#define    RXB8         1
-#define    TXB8         0
-
-/* Analog Comparator Control and Status Register */
-#define    ACD          7
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Control and status register */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADFR         5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* ADC Multiplexer select */
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define RAMEND     0x0FFF     /*Last On-Chip SRAM Location*/
-#define XRAMEND    0xFFFF
-#define E2END      0x0FFF
-#define E2PAGESIZE 0
-#define FLASHEND   0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 1
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0 (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1 (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_BODEN (unsigned char)~_BV(6)  /* Brown out detector enable */
-#define FUSE_BODLEVEL (unsigned char)~_BV(7)  /* Brown out detector trigger level */
-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x01
-
-/** @} */
-#endif /* _AVR_IOM103_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom128.h b/cpukit/score/cpu/avr/avr/iom128.h
deleted file mode 100644
index 7eeb3f5..0000000
--- a/cpukit/score/cpu/avr/avr/iom128.h
+++ /dev/null
@@ -1,1215 +0,0 @@
-/**
- * @file avr/iom128.h
- *
- * @brief Definitions for ATmega128
- *
- * This file should only be included from <avr/io.h>, never directly.
- *
- *  As of 2002-08-27:
- *  - This should be up to date with data sheet 2467E-AVR-05/02
- */
-
-/*
- *  Copyright (c) 2002, Peter Jansen
- *  Copyright (c) 2007, Atmel Corporation
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM128_H_
-#define _AVR_IOM128_H_ 1
-
-/**
- *  @defgroup Avr_iom128 ATmega128 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom128.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* Input Pins, Port F */
-#define PINF      _SFR_IO8(0x00)
-
-/* Input Pins, Port E */
-#define PINE      _SFR_IO8(0x01)
-
-/* Data Direction Register, Port E */
-#define DDRE      _SFR_IO8(0x02)
-
-/* Data Register, Port E */
-#define PORTE     _SFR_IO8(0x03)
-
-/* ADC Data Register */
-#define ADCW      _SFR_IO16(0x04) /* for backwards compatibility */
-#ifndef __ASSEMBLER__
-#define ADC       _SFR_IO16(0x04)
-#endif
-#define ADCL      _SFR_IO8(0x04)
-#define ADCH      _SFR_IO8(0x05)
-
-/* ADC Control and status register */
-#define ADCSR     _SFR_IO8(0x06)
-#define ADCSRA    _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* ADC Multiplexer select */
-#define ADMUX     _SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR      _SFR_IO8(0x08)
-
-/* USART0 Baud Rate Register Low */
-#define UBRR0L    _SFR_IO8(0x09)
-
-/* USART0 Control and Status Register B */
-#define UCSR0B    _SFR_IO8(0x0A)
-
-/* USART0 Control and Status Register A */
-#define UCSR0A    _SFR_IO8(0x0B)
-
-/* USART0 I/O Data Register */
-#define UDR0      _SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR      _SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR      _SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR      _SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND      _SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD      _SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD     _SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC      _SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC      _SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC     _SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB      _SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB      _SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB     _SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA      _SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA      _SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA     _SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR      _SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR      _SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR      _SFR_IO16(0x1E)
-#define EEARL     _SFR_IO8(0x1E)
-#define EEARH     _SFR_IO8(0x1F)
-
-/* Special Function I/O Register */
-#define SFIOR     _SFR_IO8(0x20)
-
-/* Watchdog Timer Control Register */
-#define WDTCR     _SFR_IO8(0x21)
-
-/* On-chip Debug Register */
-#define OCDR      _SFR_IO8(0x22)
-
-/* Timer2 Output Compare Register */
-#define OCR2      _SFR_IO8(0x23)
-
-/* Timer/Counter 2 */
-#define TCNT2     _SFR_IO8(0x24)
-
-/* Timer/Counter 2 Control register */
-#define TCCR2     _SFR_IO8(0x25)
-
-/* T/C 1 Input Capture Register */
-#define ICR1      _SFR_IO16(0x26)
-#define ICR1L     _SFR_IO8(0x26)
-#define ICR1H     _SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare Register B */
-#define OCR1B     _SFR_IO16(0x28)
-#define OCR1BL    _SFR_IO8(0x28)
-#define OCR1BH    _SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare Register A */
-#define OCR1A     _SFR_IO16(0x2A)
-#define OCR1AL    _SFR_IO8(0x2A)
-#define OCR1AH    _SFR_IO8(0x2B)
-
-/* Timer/Counter 1 */
-#define TCNT1     _SFR_IO16(0x2C)
-#define TCNT1L    _SFR_IO8(0x2C)
-#define TCNT1H    _SFR_IO8(0x2D)
-
-/* Timer/Counter 1 Control and Status Register */
-#define TCCR1B    _SFR_IO8(0x2E)
-
-/* Timer/Counter 1 Control Register */
-#define TCCR1A    _SFR_IO8(0x2F)
-
-/* Timer/Counter 0 Asynchronous Control & Status Register */
-#define ASSR      _SFR_IO8(0x30)
-
-/* Output Compare Register 0 */
-#define OCR0      _SFR_IO8(0x31)
-
-/* Timer/Counter 0 */
-#define TCNT0     _SFR_IO8(0x32)
-
-/* Timer/Counter 0 Control Register */
-#define TCCR0     _SFR_IO8(0x33)
-
-/* MCU Status Register */
-#define MCUSR     _SFR_IO8(0x34)
-#define MCUCSR    _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* MCU general Control Register */
-#define MCUCR     _SFR_IO8(0x35)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR      _SFR_IO8(0x36)
-
-/* Timer/Counter Interrupt MaSK register */
-#define TIMSK     _SFR_IO8(0x37)
-
-/* External Interrupt Flag Register */
-#define EIFR      _SFR_IO8(0x38)
-
-/* External Interrupt MaSK register */
-#define EIMSK     _SFR_IO8(0x39)
-
-/* External Interrupt Control Register B */
-#define EICRB     _SFR_IO8(0x3A)
-
-/* RAM Page Z select register */
-#define RAMPZ     _SFR_IO8(0x3B)
-
-/* XDIV Divide control register */
-#define XDIV      _SFR_IO8(0x3C)
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Extended I/O registers */
-
-/* Data Direction Register, Port F */
-#define DDRF      _SFR_MEM8(0x61)
-
-/* Data Register, Port F */
-#define PORTF     _SFR_MEM8(0x62)
-
-/* Input Pins, Port G */
-#define PING      _SFR_MEM8(0x63)
-
-/* Data Direction Register, Port G */
-#define DDRG      _SFR_MEM8(0x64)
-
-/* Data Register, Port G */
-#define PORTG     _SFR_MEM8(0x65)
-
-/* Store Program Memory Control and Status Register */
-#define SPMCR     _SFR_MEM8(0x68)
-#define SPMCSR    _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */
-
-/* External Interrupt Control Register A */
-#define EICRA     _SFR_MEM8(0x6A)
-
-/* External Memory Control Register B */
-#define XMCRB     _SFR_MEM8(0x6C)
-
-/* External Memory Control Register A */
-#define XMCRA     _SFR_MEM8(0x6D)
-
-/* Oscillator Calibration Register */
-#define OSCCAL    _SFR_MEM8(0x6F)
-
-/* 2-wire Serial Interface Bit Rate Register */
-#define TWBR      _SFR_MEM8(0x70)
-
-/* 2-wire Serial Interface Status Register */
-#define TWSR      _SFR_MEM8(0x71)
-
-/* 2-wire Serial Interface Address Register */
-#define TWAR      _SFR_MEM8(0x72)
-
-/* 2-wire Serial Interface Data Register */
-#define TWDR      _SFR_MEM8(0x73)
-
-/* 2-wire Serial Interface Control Register */
-#define TWCR      _SFR_MEM8(0x74)
-
-/* Time Counter 1 Output Compare Register C */
-#define OCR1C     _SFR_MEM16(0x78)
-#define OCR1CL    _SFR_MEM8(0x78)
-#define OCR1CH    _SFR_MEM8(0x79)
-
-/* Timer/Counter 1 Control Register C */
-#define TCCR1C    _SFR_MEM8(0x7A)
-
-/* Extended Timer Interrupt Flag Register */
-#define ETIFR     _SFR_MEM8(0x7C)
-
-/* Extended Timer Interrupt Mask Register */
-#define ETIMSK    _SFR_MEM8(0x7D)
-
-/* Timer/Counter 3 Input Capture Register */
-#define ICR3      _SFR_MEM16(0x80)
-#define ICR3L     _SFR_MEM8(0x80)
-#define ICR3H     _SFR_MEM8(0x81)
-
-/* Timer/Counter 3 Output Compare Register C */
-#define OCR3C     _SFR_MEM16(0x82)
-#define OCR3CL    _SFR_MEM8(0x82)
-#define OCR3CH    _SFR_MEM8(0x83)
-
-/* Timer/Counter 3 Output Compare Register B */
-#define OCR3B     _SFR_MEM16(0x84)
-#define OCR3BL    _SFR_MEM8(0x84)
-#define OCR3BH    _SFR_MEM8(0x85)
-
-/* Timer/Counter 3 Output Compare Register A */
-#define OCR3A     _SFR_MEM16(0x86)
-#define OCR3AL    _SFR_MEM8(0x86)
-#define OCR3AH    _SFR_MEM8(0x87)
-
-/* Timer/Counter 3 Counter Register */
-#define TCNT3     _SFR_MEM16(0x88)
-#define TCNT3L    _SFR_MEM8(0x88)
-#define TCNT3H    _SFR_MEM8(0x89)
-
-/* Timer/Counter 3 Control Register B */
-#define TCCR3B    _SFR_MEM8(0x8A)
-
-/* Timer/Counter 3 Control Register A */
-#define TCCR3A    _SFR_MEM8(0x8B)
-
-/* Timer/Counter 3 Control Register C */
-#define TCCR3C    _SFR_MEM8(0x8C)
-
-/* USART0 Baud Rate Register High */
-#define UBRR0H    _SFR_MEM8(0x90)
-
-/* USART0 Control and Status Register C */
-#define UCSR0C    _SFR_MEM8(0x95)
-
-/* USART1 Baud Rate Register High */
-#define UBRR1H    _SFR_MEM8(0x98)
-
-/* USART1 Baud Rate Register Low*/
-#define UBRR1L    _SFR_MEM8(0x99)
-
-/* USART1 Control and Status Register B */
-#define UCSR1B    _SFR_MEM8(0x9A)
-
-/* USART1 Control and Status Register A */
-#define UCSR1A    _SFR_MEM8(0x9B)
-
-/* USART1 I/O Data Register */
-#define UDR1      _SFR_MEM8(0x9C)
-
-/* USART1 Control and Status Register C */
-#define UCSR1C    _SFR_MEM8(0x9D)
-
-/* Interrupt vectors */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* External Interrupt Request 3 */
-#define INT3_vect			_VECTOR(4)
-#define SIG_INTERRUPT3			_VECTOR(4)
-
-/* External Interrupt Request 4 */
-#define INT4_vect			_VECTOR(5)
-#define SIG_INTERRUPT4			_VECTOR(5)
-
-/* External Interrupt Request 5 */
-#define INT5_vect			_VECTOR(6)
-#define SIG_INTERRUPT5			_VECTOR(6)
-
-/* External Interrupt Request 6 */
-#define INT6_vect			_VECTOR(7)
-#define SIG_INTERRUPT6			_VECTOR(7)
-
-/* External Interrupt Request 7 */
-#define INT7_vect			_VECTOR(8)
-#define SIG_INTERRUPT7			_VECTOR(8)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(9)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(9)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(10)
-#define SIG_OVERFLOW2			_VECTOR(10)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(11)
-#define SIG_INPUT_CAPTURE1		_VECTOR(11)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(12)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(12)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(13)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(14)
-#define SIG_OVERFLOW1			_VECTOR(14)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(15)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(15)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(16)
-#define SIG_OVERFLOW0			_VECTOR(16)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(17)
-#define SIG_SPI				_VECTOR(17)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(18)
-#define SIG_USART0_RECV			_VECTOR(18)
-#define SIG_UART0_RECV			_VECTOR(18)
-
-/* USART0 Data Register Empty */
-#define USART0_UDRE_vect		_VECTOR(19)
-#define SIG_USART0_DATA			_VECTOR(19)
-#define SIG_UART0_DATA			_VECTOR(19)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(20)
-#define SIG_USART0_TRANS		_VECTOR(20)
-#define SIG_UART0_TRANS			_VECTOR(20)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(21)
-#define SIG_ADC				_VECTOR(21)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(22)
-#define SIG_EEPROM_READY		_VECTOR(22)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(23)
-#define SIG_COMPARATOR			_VECTOR(23)
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect		_VECTOR(24)
-#define SIG_OUTPUT_COMPARE1C		_VECTOR(24)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(25)
-#define SIG_INPUT_CAPTURE3		_VECTOR(25)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(26)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(26)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(27)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(27)
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect		_VECTOR(28)
-#define SIG_OUTPUT_COMPARE3C		_VECTOR(28)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(29)
-#define SIG_OVERFLOW3			_VECTOR(29)
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect			_VECTOR(30)
-#define SIG_USART1_RECV			_VECTOR(30)
-#define SIG_UART1_RECV			_VECTOR(30)
-
-/* USART1, Data Register Empty */
-#define USART1_UDRE_vect		_VECTOR(31)
-#define SIG_USART1_DATA			_VECTOR(31)
-#define SIG_UART1_DATA			_VECTOR(31)
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect			_VECTOR(32)
-#define SIG_USART1_TRANS		_VECTOR(32)
-#define SIG_UART1_TRANS			_VECTOR(32)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(33)
-#define SIG_2WIRE_SERIAL		_VECTOR(33)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(34)
-#define SIG_SPM_READY			_VECTOR(34)
-
-#define _VECTORS_SIZE 140
-
-/*
-   The Register Bit names are represented by their bit number (0-7).
-*/
-
-/* 2-wire Control Register - TWCR */
-#define    TWINT        7
-#define    TWEA         6
-#define    TWSTA        5
-#define    TWSTO        4
-#define    TWWC         3
-#define    TWEN         2
-#define    TWIE         0
-
-/* 2-wire Address Register - TWAR */
-#define    TWA6         7
-#define    TWA5         6
-#define    TWA4         5
-#define    TWA3         4
-#define    TWA2         3
-#define    TWA1         2
-#define    TWA0         1
-#define    TWGCE        0
-
-/* 2-wire Status Register - TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-#define    TWPS1        1
-#define    TWPS0        0
-
-/* External Memory Control Register A - XMCRA */
-#define    SRL2         6
-#define    SRL1         5
-#define    SRL0         4
-#define    SRW01        3
-#define    SRW00        2
-#define    SRW11        1
-
-/* External Memory Control Register B - XMCRA */
-#define    XMBK         7
-#define    XMM2         2
-#define    XMM1         1
-#define    XMM0         0
-
-/* XDIV Divide control register - XDIV */
-#define    XDIVEN       7
-#define    XDIV6        6
-#define    XDIV5        5
-#define    XDIV4        4
-#define    XDIV3        3
-#define    XDIV2        2
-#define    XDIV1        1
-#define    XDIV0        0
-
-/* RAM Page Z select register - RAMPZ */
-#define     RAMPZ0      0
-
-/* External Interrupt Control Register A - EICRA */
-#define    ISC31        7
-#define    ISC30        6
-#define    ISC21        5
-#define    ISC20        4
-#define    ISC11        3
-#define    ISC10        2
-#define    ISC01        1
-#define    ISC00        0
-
-/* External Interrupt Control Register B - EICRB */
-#define    ISC71        7
-#define    ISC70        6
-#define    ISC61        5
-#define    ISC60        4
-#define    ISC51        3
-#define    ISC50        2
-#define    ISC41        1
-#define    ISC40        0
-
-/* Store Program Memory Control Register - SPMCSR, SPMCR */
-#define    SPMIE        7
-#define    RWWSB        6
-#define    RWWSRE       4
-#define    BLBSET       3
-#define    PGWRT        2
-#define    PGERS        1
-#define    SPMEN        0
-
-/* External Interrupt MaSK register - EIMSK */
-#define    INT7         7
-#define    INT6         6
-#define    INT5         5
-#define    INT4         4
-#define    INT3         3
-#define    INT2         2
-#define    INT1         1
-#define    INT0         0
-
-/* External Interrupt Flag Register - EIFR */
-#define    INTF7        7
-#define    INTF6        6
-#define    INTF5        5
-#define    INTF4        4
-#define    INTF3        3
-#define    INTF2        2
-#define    INTF1        1
-#define    INTF0        0
-
-/* Timer/Counter Interrupt MaSK register - TIMSK */
-#define    OCIE2        7
-#define    TOIE2        6
-#define    TICIE1       5
-#define    OCIE1A       4
-#define    OCIE1B       3
-#define    TOIE1        2
-#define    OCIE0        1
-#define    TOIE0        0
-
-/* Timer/Counter Interrupt Flag Register - TIFR */
-#define    OCF2         7
-#define    TOV2         6
-#define    ICF1         5
-#define    OCF1A        4
-#define    OCF1B        3
-#define    TOV1         2
-#define    OCF0         1
-#define    TOV0         0
-
-/* Extended Timer Interrupt MaSK register - ETIMSK */
-#define    TICIE3       5
-#define    OCIE3A       4
-#define    OCIE3B       3
-#define    TOIE3        2
-#define    OCIE3C       1
-#define    OCIE1C       0
-
-/* Extended Timer Interrupt Flag Register - ETIFR */
-#define    ICF3         5
-#define    OCF3A        4
-#define    OCF3B        3
-#define    TOV3         2
-#define    OCF3C        1
-#define    OCF1C        0
-
-/* MCU general Control Register - MCUCR */
-#define    SRE          7
-#define    SRW          6
-#define    SRW10        6       /* new name in datasheet (2467E-AVR-05/02) */
-#define    SE           5
-#define    SM1          4
-#define    SM0          3
-#define    SM2          2
-#define    IVSEL        1
-#define    IVCE         0
-
-/* MCU Status Register - MCUSR, MCUCSR */
-#define    JTD          7
-#define    JTRF         4
-#define    WDRF         3
-#define    BORF         2
-#define    EXTRF        1
-#define    PORF         0
-
-/* Timer/Counter Control Register (generic) */
-#define    FOC          7
-#define    WGM0         6
-#define    COM1         5
-#define    COM0         4
-#define    WGM1         3
-#define    CS2          2
-#define    CS1          1
-#define    CS0          0
-
-/* Timer/Counter 0 Control Register - TCCR0 */
-#define    FOC0         7
-#define    WGM00        6
-#define    COM01        5
-#define    COM00        4
-#define    WGM01        3
-#define    CS02         2
-#define    CS01         1
-#define    CS00         0
-
-/* Timer/Counter 2 Control Register - TCCR2 */
-#define    FOC2         7
-#define    WGM20        6
-#define    COM21        5
-#define    COM20        4
-#define    WGM21        3
-#define    CS22         2
-#define    CS21         1
-#define    CS20         0
-
-/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */
-#define    AS0          3
-#define    TCN0UB       2
-#define    OCR0UB       1
-#define    TCR0UB       0
-
-/* Timer/Counter Control Register A (generic) */
-#define    COMA1        7
-#define    COMA0        6
-#define    COMB1        5
-#define    COMB0        4
-#define    COMC1        3
-#define    COMC0        2
-#define    WGMA1        1
-#define    WGMA0        0
-
-/* Timer/Counter 1 Control and Status Register A - TCCR1A */
-#define    COM1A1       7
-#define    COM1A0       6
-#define    COM1B1       5
-#define    COM1B0       4
-#define    COM1C1       3
-#define    COM1C0       2
-#define    WGM11        1
-#define    WGM10        0
-
-/* Timer/Counter 3 Control and Status Register A - TCCR3A */
-#define    COM3A1       7
-#define    COM3A0       6
-#define    COM3B1       5
-#define    COM3B0       4
-#define    COM3C1       3
-#define    COM3C0       2
-#define    WGM31        1
-#define    WGM30        0
-
-/* Timer/Counter Control and Status Register B (generic) */
-#define    ICNC         7
-#define    ICES         6
-#define    WGMB3        4
-#define    WGMB2        3
-#define    CSB2         2
-#define    CSB1         1
-#define    CSB0         0
-
-/* Timer/Counter 1 Control and Status Register B - TCCR1B */
-#define    ICNC1        7
-#define    ICES1        6
-#define    WGM13        4
-#define    WGM12        3
-#define    CS12         2
-#define    CS11         1
-#define    CS10         0
-
-/* Timer/Counter 3 Control and Status Register B - TCCR3B */
-#define    ICNC3        7
-#define    ICES3        6
-#define    WGM33        4
-#define    WGM32        3
-#define    CS32         2
-#define    CS31         1
-#define    CS30         0
-
-/* Timer/Counter Control Register C (generic) */
-#define    FOCA         7
-#define    FOCB         6
-#define    FOCC         5
-
-/* Timer/Counter 3 Control Register C - TCCR3C */
-#define    FOC3A        7
-#define    FOC3B        6
-#define    FOC3C        5
-
-/* Timer/Counter 1 Control Register C - TCCR1C */
-#define    FOC1A        7
-#define    FOC1B        6
-#define    FOC1C        5
-
-/* On-chip Debug Register - OCDR */
-#define    IDRD         7
-#define    OCDR7        7
-#define    OCDR6        6
-#define    OCDR5        5
-#define    OCDR4        4
-#define    OCDR3        3
-#define    OCDR2        2
-#define    OCDR1        1
-#define    OCDR0        0
-
-/* Watchdog Timer Control Register - WDTCR */
-#define    WDCE         4
-#define    WDE          3
-#define    WDP2         2
-#define    WDP1         1
-#define    WDP0         0
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-/* Special Function I/O Register - SFIOR */
-#define    TSM          7
-#define    ACME         3
-#define    PUD          2
-#define    PSR0         1
-#define    PSR321       0
-
-/* SPI Status Register - SPSR */
-#define    SPIF         7
-#define    WCOL         6
-#define    SPI2X        0
-
-/* SPI Control Register - SPCR */
-#define    SPIE         7
-#define    SPE          6
-#define    DORD         5
-#define    MSTR         4
-#define    CPOL         3
-#define    CPHA         2
-#define    SPR1         1
-#define    SPR0         0
-
-/* USART Register C (generic) */
-#define    UMSEL        6
-#define    UPM1         5
-#define    UPM0         4
-#define    USBS         3
-#define    UCSZ1        2
-#define    UCSZ0        1
-#define    UCPOL        0
-
-/* USART1 Register C - UCSR1C */
-#define    UMSEL1       6
-#define    UPM11        5
-#define    UPM10        4
-#define    USBS1        3
-#define    UCSZ11       2
-#define    UCSZ10       1
-#define    UCPOL1       0
-
-/* USART0 Register C - UCSR0C */
-#define    UMSEL0       6
-#define    UPM01        5
-#define    UPM00        4
-#define    USBS0        3
-#define    UCSZ01       2
-#define    UCSZ00       1
-#define    UCPOL0       0
-
-/* USART Status Register A (generic) */
-#define    RXC          7
-#define    TXC          6
-#define    UDRE         5
-#define    FE           4
-#define    DOR          3
-#define    UPE          2
-#define    U2X          1
-#define    MPCM         0
-
-/* USART1 Status Register A - UCSR1A */
-#define    RXC1         7
-#define    TXC1         6
-#define    UDRE1        5
-#define    FE1          4
-#define    DOR1         3
-#define    UPE1         2
-#define    U2X1         1
-#define    MPCM1        0
-
-/* USART0 Status Register A - UCSR0A */
-#define    RXC0         7
-#define    TXC0         6
-#define    UDRE0        5
-#define    FE0          4
-#define    DOR0         3
-#define    UPE0         2
-#define    U2X0         1
-#define    MPCM0        0
-
-/* USART Control Register B (generic) */
-#define    RXCIE        7
-#define    TXCIE        6
-#define    UDRIE        5
-#define    RXEN         4
-#define    TXEN         3
-#define    UCSZ         2
-#define    UCSZ2        2       /* new name in datasheet (2467E-AVR-05/02) */
-#define    RXB8         1
-#define    TXB8         0
-
-/* USART1 Control Register B - UCSR1B */
-#define    RXCIE1       7
-#define    TXCIE1       6
-#define    UDRIE1       5
-#define    RXEN1        4
-#define    TXEN1        3
-#define    UCSZ12       2
-#define    RXB81        1
-#define    TXB81        0
-
-/* USART0 Control Register B - UCSR0B */
-#define    RXCIE0       7
-#define    TXCIE0       6
-#define    UDRIE0       5
-#define    RXEN0        4
-#define    TXEN0        3
-#define    UCSZ02       2
-#define    RXB80        1
-#define    TXB80        0
-
-/* Analog Comparator Control and Status Register - ACSR */
-#define    ACD          7
-#define    ACBG         6
-#define    ACO          5
-#define    ACI          4
-#define    ACIE         3
-#define    ACIC         2
-#define    ACIS1        1
-#define    ACIS0        0
-
-/* ADC Control and status register - ADCSRA */
-#define    ADEN         7
-#define    ADSC         6
-#define    ADFR         5
-#define    ADIF         4
-#define    ADIE         3
-#define    ADPS2        2
-#define    ADPS1        1
-#define    ADPS0        0
-
-/* ADC Multiplexer select - ADMUX */
-#define    REFS1        7
-#define    REFS0        6
-#define    ADLAR        5
-#define    MUX4         4
-#define    MUX3         3
-#define    MUX2         2
-#define    MUX1         1
-#define    MUX0         0
-
-/* Port A Data Register - PORTA */
-#define    PA7       7
-#define    PA6       6
-#define    PA5       5
-#define    PA4       4
-#define    PA3       3
-#define    PA2       2
-#define    PA1       1
-#define    PA0       0
-
-/* Port A Data Direction Register - DDRA */
-#define    DDA7         7
-#define    DDA6         6
-#define    DDA5         5
-#define    DDA4         4
-#define    DDA3         3
-#define    DDA2         2
-#define    DDA1         1
-#define    DDA0         0
-
-/* Port A Input Pins - PINA */
-#define    PINA7        7
-#define    PINA6        6
-#define    PINA5        5
-#define    PINA4        4
-#define    PINA3        3
-#define    PINA2        2
-#define    PINA1        1
-#define    PINA0        0
-
-/* Port B Data Register - PORTB */
-#define    PB7       7
-#define    PB6       6
-#define    PB5       5
-#define    PB4       4
-#define    PB3       3
-#define    PB2       2
-#define    PB1       1
-#define    PB0       0
-
-/* Port B Data Direction Register - DDRB */
-#define    DDB7         7
-#define    DDB6         6
-#define    DDB5         5
-#define    DDB4         4
-#define    DDB3         3
-#define    DDB2         2
-#define    DDB1         1
-#define    DDB0         0
-
-/* Port B Input Pins - PINB */
-#define    PINB7        7
-#define    PINB6        6
-#define    PINB5        5
-#define    PINB4        4
-#define    PINB3        3
-#define    PINB2        2
-#define    PINB1        1
-#define    PINB0        0
-
-/* Port C Data Register - PORTC */
-#define    PC7       7
-#define    PC6       6
-#define    PC5       5
-#define    PC4       4
-#define    PC3       3
-#define    PC2       2
-#define    PC1       1
-#define    PC0       0
-
-/* Port C Data Direction Register - DDRC */
-#define    DDC7         7
-#define    DDC6         6
-#define    DDC5         5
-#define    DDC4         4
-#define    DDC3         3
-#define    DDC2         2
-#define    DDC1         1
-#define    DDC0         0
-
-/* Port C Input Pins - PINC */
-#define    PINC7        7
-#define    PINC6        6
-#define    PINC5        5
-#define    PINC4        4
-#define    PINC3        3
-#define    PINC2        2
-#define    PINC1        1
-#define    PINC0        0
-
-/* Port D Data Register - PORTD */
-#define    PD7       7
-#define    PD6       6
-#define    PD5       5
-#define    PD4       4
-#define    PD3       3
-#define    PD2       2
-#define    PD1       1
-#define    PD0       0
-
-/* Port D Data Direction Register - DDRD */
-#define    DDD7         7
-#define    DDD6         6
-#define    DDD5         5
-#define    DDD4         4
-#define    DDD3         3
-#define    DDD2         2
-#define    DDD1         1
-#define    DDD0         0
-
-/* Port D Input Pins - PIND */
-#define    PIND7        7
-#define    PIND6        6
-#define    PIND5        5
-#define    PIND4        4
-#define    PIND3        3
-#define    PIND2        2
-#define    PIND1        1
-#define    PIND0        0
-
-/* Port E Data Register - PORTE */
-#define    PE7       7
-#define    PE6       6
-#define    PE5       5
-#define    PE4       4
-#define    PE3       3
-#define    PE2       2
-#define    PE1       1
-#define    PE0       0
-
-/* Port E Data Direction Register - DDRE */
-#define    DDE7         7
-#define    DDE6         6
-#define    DDE5         5
-#define    DDE4         4
-#define    DDE3         3
-#define    DDE2         2
-#define    DDE1         1
-#define    DDE0         0
-
-/* Port E Input Pins - PINE */
-#define    PINE7        7
-#define    PINE6        6
-#define    PINE5        5
-#define    PINE4        4
-#define    PINE3        3
-#define    PINE2        2
-#define    PINE1        1
-#define    PINE0        0
-
-/* Port F Data Register - PORTF */
-#define    PF7       7
-#define    PF6       6
-#define    PF5       5
-#define    PF4       4
-#define    PF3       3
-#define    PF2       2
-#define    PF1       1
-#define    PF0       0
-
-/* Port F Data Direction Register - DDRF */
-#define    DDF7         7
-#define    DDF6         6
-#define    DDF5         5
-#define    DDF4         4
-#define    DDF3         3
-#define    DDF2         2
-#define    DDF1         1
-#define    DDF0         0
-
-/* Port F Input Pins - PINF */
-#define    PINF7        7
-#define    PINF6        6
-#define    PINF5        5
-#define    PINF4        4
-#define    PINF3        3
-#define    PINF2        2
-#define    PINF1        1
-#define    PINF0        0
-
-/* Port G Data Register - PORTG */
-#define    PG4       4
-#define    PG3       3
-#define    PG2       2
-#define    PG1       1
-#define    PG0       0
-
-/* Port G Data Direction Register - DDRG */
-#define    DDG4         4
-#define    DDG3         3
-#define    DDG2         2
-#define    DDG1         1
-#define    DDG0         0
-
-/* Port G Input Pins - PING */
-#define    PING4        4
-#define    PING3        3
-#define    PING2        2
-#define    PING1        1
-#define    PING0        0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND     0x10FF     /* Last On-Chip SRAM Location */
-#define XRAMEND    0xFFFF
-#define E2END      0x0FFF
-#define E2PAGESIZE 8
-#define FLASHEND   0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_WDTON       (unsigned char)~_BV(0)
-#define FUSE_M103C       (unsigned char)~_BV(1)
-#define EFUSE_DEFAULT (FUSE_M103C)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x02
-
-
-/**@}*/
-#endif /* _AVR_IOM128_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1280.h b/cpukit/score/cpu/avr/avr/iom1280.h
deleted file mode 100644
index a6aff36..0000000
--- a/cpukit/score/cpu/avr/avr/iom1280.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega1280
- */
-
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom1280.h - definitions for ATmega1280 */
-
-#ifndef _AVR_IOM1280_H_
-#define _AVR_IOM1280_H_ 1
-
-#include <avr/iomxx0_1.h>
-
-/**
- * @defgroup AvrDef_iom1280 ATmega1280 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x03
-
-/** @} */
-
-#endif /* _AVR_IOM1280_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1281.h b/cpukit/score/cpu/avr/avr/iom1281.h
deleted file mode 100644
index 8b764c6..0000000
--- a/cpukit/score/cpu/avr/avr/iom1281.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/**
- * @file avr/iom1281.h
- *
- * @brief Definitions for ATmega1281
- */
-
-/*
- *  Copyright (c) 2005 Anatoly Sokolov
- *  All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_IOM1281_H_
-#define _AVR_IOM1281_H_ 1
-
-/**
- *  @defgroup Avr_iom1281 ATmega1281 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomxx0_1.h>
-
-/* Constants */
-#define SPM_PAGESIZE    256
-#define RAMEND          0x21FF
-#define XRAMEND         0xFFFF
-#define E2END           0xFFF
-#define E2PAGESIZE      8
-#define FLASHEND        0x1FFFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x04
-
-/**@}*/
-#endif /* _AVR_IOM1281_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1284p.h b/cpukit/score/cpu/avr/avr/iom1284p.h
deleted file mode 100644
index 3076de2..0000000
--- a/cpukit/score/cpu/avr/avr/iom1284p.h
+++ /dev/null
@@ -1,1141 +0,0 @@
-/**
- * @file avr/iom1284p.h
- *
- * @brief Definitions for ATmega1284P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom1284p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM1284P_H_
-#define _AVR_IOM1284P_H_ 1
-
-/**
- *  @defgroup Avr_iom1284p ATmega1284P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define ICF3 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRUSART1 4
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRTIM3 0
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define ICIE3 5
-
-#define PCMSK3 _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-
-#define INT0_vect         _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect         _VECTOR(3)  /* External Interrupt Request 2 */
-#define PCINT0_vect       _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect       _VECTOR(6)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect       _VECTOR(7)  /* Pin Change Interrupt Request 3 */
-#define WDT_vect          _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect   _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect    _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect  _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect    _VECTOR(22)  /* USART0, Tx Complete */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define ADC_vect          _VECTOR(24)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect          _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(27)  /* Store Program Memory Read */
-#define USART1_RX_vect    _VECTOR(28)  /* USART1 RX complete */
-#define USART1_UDRE_vect  _VECTOR(29)  /* USART1 Data Register Empty */
-#define USART1_TX_vect    _VECTOR(30)  /* USART1 TX complete */
-#define TIMER3_CAPT_vect  _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_OVF_vect   _VECTOR(34)  /* Timer/Counter3 Overflow */
-
-#define _VECTORS_SIZE (35 * 4)
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x40FF    /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0xFFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x05
-
-/**@}*/
-#endif  /* _AVR_IOM1284P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom128rfa1.h b/cpukit/score/cpu/avr/avr/iom128rfa1.h
deleted file mode 100644
index 480ae20..0000000
--- a/cpukit/score/cpu/avr/avr/iom128rfa1.h
+++ /dev/null
@@ -1,5372 +0,0 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */
-
-#ifndef _AVR_IOM128RFA1_H_
-#define _AVR_IOM128RFA1_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom128rfa1.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-#include <avr/sfr_defs.h>
-
-#ifndef __ASSEMBLER__
-#  define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr))
-#  define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type)
-#  define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type)
-#endif /* __ASSEMBLER__ */
-
-/*
- * USAGE:
- *
- * simple register assignment:
- * TIFR1 = 0x17
- * subregister assignment:
- * TIFR1_struct.ocf1a = 1
- * (subregister names are converted to small letters)
- */
-
-
-/* Port A Input Pins Address */
-#define PINA                            _SFR_IO8(0x00)
-
-  /* PINA */
-
-#define PINA0                           0
-#define PINA1                           1
-#define PINA2                           2
-#define PINA3                           3
-#define PINA4                           4
-#define PINA5                           5
-#define PINA6                           6
-#define PINA7                           7
-
-/* Port A Data Direction Register */
-#define DDRA                            _SFR_IO8(0x01)
-
-  /* DDRA */
-
-#define DDA0                            0
-#define DDA1                            1
-#define DDA2                            2
-#define DDA3                            3
-#define DDA4                            4
-#define DDA5                            5
-#define DDA6                            6
-#define DDA7                            7
-
-/* Port A Data Register */
-#define PORTA                           _SFR_IO8(0x02)
-
-  /* PORTA */
-
-#define PORTA0                          0
-#define PA0                             0
-#define PORTA1                          1
-#define PA1                             1
-#define PORTA2                          2
-#define PA2                             2
-#define PORTA3                          3
-#define PA3                             3
-#define PORTA4                          4
-#define PA4                             4
-#define PORTA5                          5
-#define PA5                             5
-#define PORTA6                          6
-#define PA6                             6
-#define PORTA7                          7
-#define PA7                             7
-
-/* Port B Input Pins Address */
-#define PINB                            _SFR_IO8(0x03)
-
-  /* PINB */
-
-#define PINB0                           0
-#define PINB1                           1
-#define PINB2                           2
-#define PINB3                           3
-#define PINB4                           4
-#define PINB5                           5
-#define PINB6                           6
-#define PINB7                           7
-
-/* Port B Data Direction Register */
-#define DDRB                            _SFR_IO8(0x04)
-
-  /* DDRB */
-
-#define DDB0                            0
-#define DDB1                            1
-#define DDB2                            2
-#define DDB3                            3
-#define DDB4                            4
-#define DDB5                            5
-#define DDB6                            6
-#define DDB7                            7
-
-/* Port B Data Register */
-#define PORTB                           _SFR_IO8(0x05)
-
-  /* PORTB */
-
-#define PORTB0                          0
-#define PB0                             0
-#define PORTB1                          1
-#define PB1                             1
-#define PORTB2                          2
-#define PB2                             2
-#define PORTB3                          3
-#define PB3                             3
-#define PORTB4                          4
-#define PB4                             4
-#define PORTB5                          5
-#define PB5                             5
-#define PORTB6                          6
-#define PB6                             6
-#define PORTB7                          7
-#define PB7                             7
-
-/* Port C Input Pins Address */
-#define PINC                            _SFR_IO8(0x06)
-
-  /* PINC */
-
-#define PINC0                           0
-#define PINC1                           1
-#define PINC2                           2
-#define PINC3                           3
-#define PINC4                           4
-#define PINC5                           5
-#define PINC6                           6
-#define PINC7                           7
-
-/* Port C Data Direction Register */
-#define DDRC                            _SFR_IO8(0x07)
-
-  /* DDRC */
-
-#define DDC0                            0
-#define DDC1                            1
-#define DDC2                            2
-#define DDC3                            3
-#define DDC4                            4
-#define DDC5                            5
-#define DDC6                            6
-#define DDC7                            7
-
-/* Port C Data Register */
-#define PORTC                           _SFR_IO8(0x08)
-
-  /* PORTC */
-
-#define PORTC0                          0
-#define PC0                             0
-#define PORTC1                          1
-#define PC1                             1
-#define PORTC2                          2
-#define PC2                             2
-#define PORTC3                          3
-#define PC3                             3
-#define PORTC4                          4
-#define PC4                             4
-#define PORTC5                          5
-#define PC5                             5
-#define PORTC6                          6
-#define PC6                             6
-#define PORTC7                          7
-#define PC7                             7
-
-/* Port D Input Pins Address */
-#define PIND                            _SFR_IO8(0x09)
-
-  /* PIND */
-
-#define PIND0                           0
-#define PIND1                           1
-#define PIND2                           2
-#define PIND3                           3
-#define PIND4                           4
-#define PIND5                           5
-#define PIND6                           6
-#define PIND7                           7
-
-/* Port D Data Direction Register */
-#define DDRD                            _SFR_IO8(0x0A)
-
-  /* DDRD */
-
-#define DDD0                            0
-#define DDD1                            1
-#define DDD2                            2
-#define DDD3                            3
-#define DDD4                            4
-#define DDD5                            5
-#define DDD6                            6
-#define DDD7                            7
-
-/* Port D Data Register */
-#define PORTD                           _SFR_IO8(0x0B)
-
-  /* PORTD */
-
-#define PORTD0                          0
-#define PD0                             0
-#define PORTD1                          1
-#define PD1                             1
-#define PORTD2                          2
-#define PD2                             2
-#define PORTD3                          3
-#define PD3                             3
-#define PORTD4                          4
-#define PD4                             4
-#define PORTD5                          5
-#define PD5                             5
-#define PORTD6                          6
-#define PD6                             6
-#define PORTD7                          7
-#define PD7                             7
-
-/* Port E Input Pins Address */
-#define PINE                            _SFR_IO8(0x0C)
-
-  /* PINE */
-
-#define PINE0                           0
-#define PINE1                           1
-#define PINE2                           2
-#define PINE3                           3
-#define PINE4                           4
-#define PINE5                           5
-#define PINE6                           6
-#define PINE7                           7
-
-/* Port E Data Direction Register */
-#define DDRE                            _SFR_IO8(0x0D)
-
-  /* DDRE */
-
-#define DDE0                            0
-#define DDE1                            1
-#define DDE2                            2
-#define DDE3                            3
-#define DDE4                            4
-#define DDE5                            5
-#define DDE6                            6
-#define DDE7                            7
-
-/* Port E Data Register */
-#define PORTE                           _SFR_IO8(0x0E)
-
-  /* PORTE */
-
-#define PORTE0                          0
-#define PE0                             0
-#define PORTE1                          1
-#define PE1                             1
-#define PORTE2                          2
-#define PE2                             2
-#define PORTE3                          3
-#define PE3                             3
-#define PORTE4                          4
-#define PE4                             4
-#define PORTE5                          5
-#define PE5                             5
-#define PORTE6                          6
-#define PE6                             6
-#define PORTE7                          7
-#define PE7                             7
-
-/* Port F Input Pins Address */
-#define PINF                            _SFR_IO8(0x0F)
-
-  /* PINF */
-
-#define PINF0                           0
-#define PINF1                           1
-#define PINF2                           2
-#define PINF3                           3
-#define PINF4                           4
-#define PINF5                           5
-#define PINF6                           6
-#define PINF7                           7
-
-/* Port F Data Direction Register */
-#define DDRF                            _SFR_IO8(0x10)
-
-  /* DDRF */
-
-#define DDF0                            0
-#define DDF1                            1
-#define DDF2                            2
-#define DDF3                            3
-#define DDF4                            4
-#define DDF5                            5
-#define DDF6                            6
-#define DDF7                            7
-
-/* Port F Data Register */
-#define PORTF                           _SFR_IO8(0x11)
-
-  /* PORTF */
-
-#define PORTF0                          0
-#define PF0                             0
-#define PORTF1                          1
-#define PF1                             1
-#define PORTF2                          2
-#define PF2                             2
-#define PORTF3                          3
-#define PF3                             3
-#define PORTF4                          4
-#define PF4                             4
-#define PORTF5                          5
-#define PF5                             5
-#define PORTF6                          6
-#define PF6                             6
-#define PORTF7                          7
-#define PF7                             7
-
-/* Port G Input Pins Address */
-#define PING                            _SFR_IO8(0x12)
-
-  /* PING */
-
-#define PING0                           0
-#define PING1                           1
-#define PING2                           2
-#define PING3                           3
-#define PING4                           4
-#define PING5                           5
-
-/* Port G Data Direction Register */
-#define DDRG                            _SFR_IO8(0x13)
-
-  /* DDRG */
-
-#define DDG0                            0
-#define DDG1                            1
-#define DDG2                            2
-#define DDG3                            3
-#define DDG4                            4
-#define DDG5                            5
-
-/* Port G Data Register */
-#define PORTG                           _SFR_IO8(0x14)
-
-  /* PORTG */
-
-#define PORTG0                          0
-#define PG0                             0
-#define PORTG1                          1
-#define PG1                             1
-#define PORTG2                          2
-#define PG2                             2
-#define PORTG3                          3
-#define PG3                             3
-#define PORTG4                          4
-#define PG4                             4
-#define PORTG5                          5
-#define PG5                             5
-
-/* Timer/Counter0 Interrupt Flag Register */
-#define TIFR0                           _SFR_IO8(0x15)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR0 {
-        unsigned int tov0 : 1;	/* Timer/Counter0 Overflow Flag */
-        unsigned int ocf0a : 1;	/* Timer/Counter0 Output Compare A Match Flag */
-        unsigned int ocf0b : 1;	/* Timer/Counter0 Output Compare B Match Flag */
-        unsigned int : 5;
-};
-
-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR0 */
-
-#define TOV0                            0
-#define OCF0A                           1
-#define OCF0B                           2
-
-/* Timer/Counter1 Interrupt Flag Register */
-#define TIFR1                           _SFR_IO8(0x16)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR1 {
-        unsigned int tov1 : 1;	/* Timer/Counter1 Overflow Flag */
-        unsigned int ocf1a : 1;	/* Timer/Counter1 Output Compare A Match Flag */
-        unsigned int ocf1b : 1;	/* Timer/Counter1 Output Compare B Match Flag */
-        unsigned int ocf1c : 1;	/* Timer/Counter1 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf1 : 1;	/* Timer/Counter1 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR1 */
-
-#define TOV1                            0
-#define OCF1A                           1
-#define OCF1B                           2
-#define OCF1C                           3
-#define ICF1                            5
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR2                           _SFR_IO8(0x17)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR2 {
-        unsigned int tov2 : 1;	/* Timer/Counter2 Overflow Flag */
-        unsigned int ocf2a : 1;	/* Output Compare Flag 2 A */
-        unsigned int ocf2b : 1;	/* Output Compare Flag 2 B */
-        unsigned int : 5;
-};
-
-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR2 */
-
-#define TOV2                            0
-#define OCF2A                           1
-#define OCF2B                           2
-
-/* Timer/Counter3 Interrupt Flag Register */
-#define TIFR3                           _SFR_IO8(0x18)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR3 {
-        unsigned int tov3 : 1;	/* Timer/Counter3 Overflow Flag */
-        unsigned int ocf3a : 1;	/* Timer/Counter3 Output Compare A Match Flag */
-        unsigned int ocf3b : 1;	/* Timer/Counter3 Output Compare B Match Flag */
-        unsigned int ocf3c : 1;	/* Timer/Counter3 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf3 : 1;	/* Timer/Counter3 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR3 */
-
-#define TOV3                            0
-#define OCF3A                           1
-#define OCF3B                           2
-#define OCF3C                           3
-#define ICF3                            5
-
-/* Timer/Counter4 Interrupt Flag Register */
-#define TIFR4                           _SFR_IO8(0x19)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR4 {
-        unsigned int tov4 : 1;	/* Timer/Counter4 Overflow Flag */
-        unsigned int ocf4a : 1;	/* Timer/Counter4 Output Compare A Match Flag */
-        unsigned int ocf4b : 1;	/* Timer/Counter4 Output Compare B Match Flag */
-        unsigned int ocf4c : 1;	/* Timer/Counter4 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf4 : 1;	/* Timer/Counter4 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR4 */
-
-#define TOV4                            0
-#define OCF4A                           1
-#define OCF4B                           2
-#define OCF4C                           3
-#define ICF4                            5
-
-/* Timer/Counter5 Interrupt Flag Register */
-#define TIFR5                           _SFR_IO8(0x1A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIFR5 {
-        unsigned int tov5 : 1;	/* Timer/Counter5 Overflow Flag */
-        unsigned int ocf5a : 1;	/* Timer/Counter5 Output Compare A Match Flag */
-        unsigned int ocf5b : 1;	/* Timer/Counter5 Output Compare B Match Flag */
-        unsigned int ocf5c : 1;	/* Timer/Counter5 Output Compare C Match Flag */
-        unsigned int : 1;
-        unsigned int icf5 : 1;	/* Timer/Counter5 Input Capture Flag */
-        unsigned int : 2;
-};
-
-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIFR5 */
-
-#define TOV5                            0
-#define OCF5A                           1
-#define OCF5B                           2
-#define OCF5C                           3
-#define ICF5                            5
-
-/* Pin Change Interrupt Flag Register */
-#define PCIFR                           _SFR_IO8(0x1B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCIFR {
-        unsigned int pcif : 3;	/* Pin Change Interrupt Flag 2 */
-        unsigned int : 5;
-};
-
-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCIFR */
-
-#define PCIF0                           0
-#define PCIF1                           1
-#define PCIF2                           2
-
-/* External Interrupt Flag Register */
-#define EIFR                            _SFR_IO8(0x1C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIFR {
-        unsigned int intf : 8;	/* External Interrupt Flag */
-};
-
-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIFR */
-
-#define INTF0                           0
-#define INTF1                           1
-#define INTF2                           2
-#define INTF3                           3
-#define INTF4                           4
-#define INTF5                           5
-#define INTF6                           6
-#define INTF7                           7
-
-/* External Interrupt Mask Register */
-#define EIMSK                           _SFR_IO8(0x1D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EIMSK {
-        unsigned int intm : 8;	/* External Interrupt Request Enable */
-};
-
-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EIMSK */
-
-#define INT0                            0
-#define INT1                            1
-#define INT2                            2
-#define INT3                            3
-#define INT4                            4
-#define INT5                            5
-#define INT6                            6
-#define INT7                            7
-
-/* General Purpose IO Register 0 */
-#define GPIOR0                          _SFR_IO8(0x1E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR0 {
-        unsigned int gpior0 : 8;	/* General Purpose I/O Register 0 Value */
-};
-
-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR0 */
-
-#define GPIOR00                         0
-#define GPIOR01                         1
-#define GPIOR02                         2
-#define GPIOR03                         3
-#define GPIOR04                         4
-#define GPIOR05                         5
-#define GPIOR06                         6
-#define GPIOR07                         7
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-/* EEPROM Control Register */
-#define EECR                            _SFR_IO8(0x1F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EECR {
-        unsigned int eere : 1;	/* EEPROM Read Enable */
-        unsigned int eepe : 1;	/* EEPROM Programming Enable */
-        unsigned int eempe : 1;	/* EEPROM Master Write Enable */
-        unsigned int eerie : 1;	/* EEPROM Ready Interrupt Enable */
-        unsigned int eepm : 2;	/* EEPROM Programming Mode */
-        unsigned int : 2;
-};
-
-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EECR */
-
-#define EERE                            0
-#define EEPE                            1
-#define EEMPE                           2
-#define EERIE                           3
-#define EEPM0                           4
-#define EEPM1                           5
-
-/* EEPROM Data Register */
-#define EEDR                            _SFR_IO8(0x20)
-
-  /* EEDR */
-
-#define EEDR0                           0
-#define EEDR1                           1
-#define EEDR2                           2
-#define EEDR3                           3
-#define EEDR4                           4
-#define EEDR5                           5
-#define EEDR6                           6
-#define EEDR7                           7
-
-/* EEPROM Address Register  Bytes */
-#define EEAR                            _SFR_IO16(0x21)
-#define EEARL                           _SFR_IO8(0x21)
-#define EEARH                           _SFR_IO8(0x22)
-
-/* General Timer/Counter Control Register */
-#define GTCCR                           _SFR_IO8(0x23)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GTCCR {
-        unsigned int psrsync : 1;	/* Prescaler Reset for Synchronous Timer/Counters */
-        unsigned int psrasy : 1;	/* Prescaler Reset Timer/Counter2 */
-        unsigned int : 5;
-        unsigned int tsm : 1;	/* Timer/Counter Synchronization Mode */
-};
-
-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GTCCR */
-
-#define PSRSYNC                         0
-#define PSR10                           0
-#define PSRASY                          1
-#define PSR2                            1
-#define TSM                             7
-
-/* Timer/Counter0 Control Register A */
-#define TCCR0A                          _SFR_IO8(0x24)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0A {
-        unsigned int wgm0 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com0b : 2;	/* Compare Match Output B Mode */
-        unsigned int com0a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0A */
-
-#define WGM00                           0
-#define WGM01                           1
-#define COM0B0                          4
-#define COM0B1                          5
-#define COM0A0                          6
-#define COM0A1                          7
-
-/* Timer/Counter0 Control Register B */
-#define TCCR0B                          _SFR_IO8(0x25)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR0B {
-        unsigned int cs0 : 3;	/* Clock Select */
-        unsigned int wgm02 : 1;	/*  */
-        unsigned int : 2;
-        unsigned int foc0b : 1;	/* Force Output Compare B */
-        unsigned int foc0a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR0B */
-
-#define CS00                            0
-#define CS01                            1
-#define CS02                            2
-#define WGM02                           3
-#define FOC0B                           6
-#define FOC0A                           7
-
-/* Timer/Counter0 Register */
-#define TCNT0                           _SFR_IO8(0x26)
-
-  /* TCNT0 */
-
-#define TCNT0_0                         0
-#define TCNT0_1                         1
-#define TCNT0_2                         2
-#define TCNT0_3                         3
-#define TCNT0_4                         4
-#define TCNT0_5                         5
-#define TCNT0_6                         6
-#define TCNT0_7                         7
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0A                           _SFR_IO8(0x27)
-
-  /* OCR0A */
-
-#define OCR0A_0                         0
-#define OCR0A_1                         1
-#define OCR0A_2                         2
-#define OCR0A_3                         3
-#define OCR0A_4                         4
-#define OCR0A_5                         5
-#define OCR0A_6                         6
-#define OCR0A_7                         7
-
-/* Timer/Counter0 Output Compare Register B */
-#define OCR0B                           _SFR_IO8(0x28)
-
-  /* OCR0B */
-
-#define OCR0B_0                         0
-#define OCR0B_1                         1
-#define OCR0B_2                         2
-#define OCR0B_3                         3
-#define OCR0B_4                         4
-#define OCR0B_5                         5
-#define OCR0B_6                         6
-#define OCR0B_7                         7
-
-/* General Purpose IO Register 1 */
-#define GPIOR1                          _SFR_IO8(0x2A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR1 {
-        unsigned int gpior1 : 8;	/* General Purpose I/O Register 1 Value */
-};
-
-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR1 */
-
-#define GPIOR10                         0
-#define GPIOR11                         1
-#define GPIOR12                         2
-#define GPIOR13                         3
-#define GPIOR14                         4
-#define GPIOR15                         5
-#define GPIOR16                         6
-#define GPIOR17                         7
-
-/* General Purpose I/O Register 2 */
-#define GPIOR2                          _SFR_IO8(0x2B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_GPIOR2 {
-        unsigned int gpior2 : 8;	/* General Purpose I/O Register 2 Value */
-};
-
-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* GPIOR2 */
-
-#define GPIOR20                         0
-#define GPIOR21                         1
-#define GPIOR22                         2
-#define GPIOR23                         3
-#define GPIOR24                         4
-#define GPIOR25                         5
-#define GPIOR26                         6
-#define GPIOR27                         7
-
-/* SPI Control Register */
-#define SPCR                            _SFR_IO8(0x2C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPCR {
-        unsigned int spr : 2;	/* SPI Clock Rate Select 1 and 0 */
-        unsigned int cpha : 1;	/* Clock Phase */
-        unsigned int cpol : 1;	/* Clock polarity */
-        unsigned int mstr : 1;	/* Master/Slave Select */
-        unsigned int dord : 1;	/* Data Order */
-        unsigned int spe : 1;	/* SPI Enable */
-        unsigned int spie : 1;	/* SPI Interrupt Enable */
-};
-
-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPCR */
-
-#define SPR0                            0
-#define SPR1                            1
-#define CPHA                            2
-#define CPOL                            3
-#define MSTR                            4
-#define DORD                            5
-#define SPE                             6
-#define SPIE                            7
-
-/* SPI Status Register */
-#define SPSR                            _SFR_IO8(0x2D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPSR {
-        unsigned int spi2x : 1;	/* Double SPI Speed Bit */
-        unsigned int : 5;
-        unsigned int wcol : 1;	/* Write Collision Flag */
-        unsigned int spif : 1;	/* SPI Interrupt Flag */
-};
-
-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPSR */
-
-#define SPI2X                           0
-#define WCOL                            6
-#define SPIF                            7
-
-/* SPI Data Register */
-#define SPDR                            _SFR_IO8(0x2E)
-
-  /* SPDR */
-
-#define SPDR0                           0
-#define SPDR1                           1
-#define SPDR2                           2
-#define SPDR3                           3
-#define SPDR4                           4
-#define SPDR5                           5
-#define SPDR6                           6
-#define SPDR7                           7
-
-/* Analog Comparator Control And Status Register */
-#define ACSR                            _SFR_IO8(0x30)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ACSR {
-        unsigned int acis : 2;	/* Analog Comparator Interrupt Mode Select */
-        unsigned int acic : 1;	/* Analog Comparator Input Capture Enable */
-        unsigned int acie : 1;	/* Analog Comparator Interrupt Enable */
-        unsigned int aci : 1;	/* Analog Comparator Interrupt Flag */
-        unsigned int aco : 1;	/* Analog Compare Output */
-        unsigned int acbg : 1;	/* Analog Comparator Bandgap Select */
-        unsigned int acd : 1;	/* Analog Comparator Disable */
-};
-
-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ACSR */
-
-#define ACIS0                           0
-#define ACIS1                           1
-#define ACIC                            2
-#define ACIE                            3
-#define ACI                             4
-#define ACO                             5
-#define ACBG                            6
-#define ACD                             7
-
-/* On-Chip Debug Register */
-#define OCDR                            _SFR_IO8(0x31)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OCDR {
-        unsigned int ocdr : 8;	/* On-Chip Debug Register Data */
-};
-
-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OCDR */
-
-#define OCDR0                           0
-#define OCDR1                           1
-#define OCDR2                           2
-#define OCDR3                           3
-#define OCDR4                           4
-#define OCDR5                           5
-#define OCDR6                           6
-#define OCDR7                           7
-#define IDRD                            7
-
-/* Sleep Mode Control Register */
-#define SMCR                            _SFR_IO8(0x33)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SMCR {
-        unsigned int se : 1;	/* Sleep Enable */
-        unsigned int sm : 3;	/* Sleep Mode Select bits */
-        unsigned int : 4;
-};
-
-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SMCR */
-
-#define SE                              0
-#define SM0                             1
-#define SM1                             2
-#define SM2                             3
-
-/* MCU Status Register */
-#define MCUSR                           _SFR_IO8(0x34)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUSR {
-        unsigned int porf : 1;	/* Power-on Reset Flag */
-        unsigned int extrf : 1;	/* External Reset Flag */
-        unsigned int borf : 1;	/* Brown-out Reset Flag */
-        unsigned int wdrf : 1;	/* Watchdog Reset Flag */
-        unsigned int jtrf : 1;	/* JTAG Reset Flag */
-        unsigned int : 3;
-};
-
-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUSR */
-
-#define PORF                            0
-#define EXTRF                           1
-#define BORF                            2
-#define WDRF                            3
-#define JTRF                            4
-
-/* MCU Control Register */
-#define MCUCR                           _SFR_IO8(0x35)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MCUCR {
-        unsigned int ivce : 1;	/* Interrupt Vector Change Enable */
-        unsigned int ivsel : 1;	/* Interrupt Vector Select */
-        unsigned int : 2;
-        unsigned int pud : 1;	/* Pull-up Disable */
-        unsigned int : 2;
-        unsigned int jtd : 1;	/* JTAG Interface Disable */
-};
-
-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* MCUCR */
-
-#define IVCE                            0
-#define IVSEL                           1
-#define PUD                             4
-#define JTD                             7
-
-/* Store Program Memory Control Register */
-#define SPMCSR                          _SFR_IO8(0x37)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SPMCSR {
-        unsigned int spmen : 1;	/* Store Program Memory Enable */
-        unsigned int pgers : 1;	/* Page Erase */
-        unsigned int pgwrt : 1;	/* Page Write */
-        unsigned int blbset : 1;	/* Boot Lock Bit Set */
-        unsigned int rwwsre : 1;	/* Read While Write Section Read Enable */
-        unsigned int sigrd : 1;	/* Signature Row Read */
-        unsigned int rwwsb : 1;	/* Read While Write Section Busy */
-        unsigned int spmie : 1;	/* SPM Interrupt Enable */
-};
-
-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SPMCSR */
-
-#define SPMEN                           0
-#define PGERS                           1
-#define PGWRT                           2
-#define BLBSET                          3
-#define RWWSRE                          4
-#define SIGRD                           5
-#define RWWSB                           6
-#define SPMIE                           7
-
-/* Extended Z-pointer Register for ELPM/SPM */
-#define RAMPZ                           _SFR_IO8(0x3B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RAMPZ {
-        unsigned int rampz : 2;	/* Extended Z-Pointer Value */
-        unsigned int : 6;
-};
-
-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ)
-
-#endif /* __ASSEMBLER__ */
-
-  /* RAMPZ */
-
-#define RAMPZ0                          0
-#define RAMPZ1                          1
-
-/* Stack Pointer */
-#define SP                              _SFR_IO16(0x3D)
-#define SPL                             _SFR_IO8(0x3D)
-#define SPH                             _SFR_IO8(0x3E)
-
-/* Status Register */
-#define SREG                            _SFR_IO8(0x3F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SREG {
-        unsigned int c : 1;	/* Carry Flag */
-        unsigned int z : 1;	/* Zero Flag */
-        unsigned int n : 1;	/* Negative Flag */
-        unsigned int v : 1;	/* Two's Complement Overflow Flag */
-        unsigned int s : 1;	/* Sign Bit */
-        unsigned int h : 1;	/* Half Carry Flag */
-        unsigned int t : 1;	/* Bit Copy Storage */
-        unsigned int i : 1;	/* Global Interrupt Enable */
-};
-
-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SREG */
-
-#define SREG_C                          0
-#define SREG_Z                          1
-#define SREG_N                          2
-#define SREG_V                          3
-#define SREG_S                          4
-#define SREG_H                          5
-#define SREG_T                          6
-#define SREG_I                          7
-
-/* Watchdog Timer Control Register */
-#define WDTCSR                          _SFR_MEM8(0x60)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_WDTCSR {
-        unsigned int wdp : 3;	/* Watchdog Timer Prescaler bits */
-        unsigned int wde : 1;	/* Watch Dog Enable */
-        unsigned int wdce : 1;	/* Watchdog Change Enable */
-        unsigned int : 1;
-        unsigned int wdie : 1;	/* Watchdog Timeout Interrupt Enable */
-        unsigned int wdif : 1;	/* Watchdog Timeout Interrupt Flag */
-};
-
-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* WDTCSR */
-
-#define WDP0                            0
-#define WDP1                            1
-#define WDP2                            2
-#define WDE                             3
-#define WDCE                            4
-#define WDP3                            5
-#define WDIE                            6
-#define WDIF                            7
-
-/* Clock Prescale Register */
-#define CLKPR                           _SFR_MEM8(0x61)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CLKPR {
-        unsigned int clkps : 4;	/* Clock Prescaler Select Bits */
-        unsigned int : 3;
-        unsigned int clkpce : 1;	/* Clock Prescaler Change Enable */
-};
-
-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CLKPR */
-
-#define CLKPS0                          0
-#define CLKPS1                          1
-#define CLKPS2                          2
-#define CLKPS3                          3
-#define CLKPCE                          7
-
-/* Power Reduction Register 2 */
-#define PRR2                            _SFR_MEM8(0x63)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR2 {
-        unsigned int prram : 4;	/* Power Reduction SRAM 3 */
-        unsigned int : 4;
-};
-
-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR2 */
-
-#define PRRAM0                          0
-#define PRRAM1                          1
-#define PRRAM2                          2
-#define PRRAM3                          3
-
-/* Power Reduction Register0 */
-#define PRR0                            _SFR_MEM8(0x64)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR0 {
-        unsigned int pradc : 1;	/* Power Reduction ADC */
-        unsigned int prusart0 : 1;	/* Power Reduction USART */
-        unsigned int prspi : 1;	/* Power Reduction Serial Peripheral Interface */
-        unsigned int prtim1 : 1;	/* Power Reduction Timer/Counter1 */
-        unsigned int prpga : 1;	/* Power Reduction PGA */
-        unsigned int prtim0 : 1;	/* Power Reduction Timer/Counter0 */
-        unsigned int prtim2 : 1;	/* Power Reduction Timer/Counter2 */
-        unsigned int prtwi : 1;	/* Power Reduction TWI */
-};
-
-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR0 */
-
-#define PRADC                           0
-#define PRUSART0                        1
-#define PRSPI                           2
-#define PRTIM1                          3
-#define PRPGA                           4
-#define PRTIM0                          5
-#define PRTIM2                          6
-#define PRTWI                           7
-
-/* Power Reduction Register 1 */
-#define PRR1                            _SFR_MEM8(0x65)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PRR1 {
-        unsigned int prusart : 3;	/* Reserved */
-        unsigned int prtim3 : 1;	/* Power Reduction Timer/Counter3 */
-        unsigned int prtim4 : 1;	/* Power Reduction Timer/Counter4 */
-        unsigned int prtim5 : 1;	/* Power Reduction Timer/Counter5 */
-        unsigned int prtrx24 : 1;	/* Power Reduction Transceiver */
-        unsigned int : 1;
-};
-
-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PRR1 */
-
-#define PRUSART1                        0
-#define PRUSART2                        1
-#define PRUSART3                        2
-#define PRTIM3                          3
-#define PRTIM4                          4
-#define PRTIM5                          5
-#define PRTRX24                         6
-
-/* Oscillator Calibration Value */
-#define OSCCAL                          _SFR_MEM8(0x66)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_OSCCAL {
-        unsigned int cal : 8;	/* Oscillator Calibration Tuning Value */
-};
-
-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* OSCCAL */
-
-#define CAL0                            0
-#define CAL1                            1
-#define CAL2                            2
-#define CAL3                            3
-#define CAL4                            4
-#define CAL5                            5
-#define CAL6                            6
-#define CAL7                            7
-
-/* Reference Voltage Calibration Register */
-#define BGCR                            _SFR_MEM8(0x67)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BGCR {
-        unsigned int bgcal : 3;	/* Coarse Calibration Bits */
-        unsigned int bgcal_fine : 4;	/* Fine Calibration Bits */
-        unsigned int : 1;
-};
-
-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* BGCR */
-
-#define BGCAL0                          0
-#define BGCAL1                          1
-#define BGCAL2                          2
-#define BGCAL_FINE0                     3
-#define BGCAL_FINE1                     4
-#define BGCAL_FINE2                     5
-#define BGCAL_FINE3                     6
-
-/* Pin Change Interrupt Control Register */
-#define PCICR                           _SFR_MEM8(0x68)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCICR {
-        unsigned int pcie : 3;	/* Pin Change Interrupt Enable 2 */
-        unsigned int : 5;
-};
-
-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCICR */
-
-#define PCIE0                           0
-#define PCIE1                           1
-#define PCIE2                           2
-
-/* External Interrupt Control Register A */
-#define EICRA                           _SFR_MEM8(0x69)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRA {
-        unsigned int isc0 : 2;	/* External Interrupt 0 Sense Control Bit */
-        unsigned int isc1 : 2;	/* External Interrupt 1 Sense Control Bit */
-        unsigned int isc2 : 2;	/* External Interrupt 2 Sense Control Bit */
-        unsigned int isc3 : 2;	/* External Interrupt 3 Sense Control Bit */
-};
-
-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRA */
-
-#define ISC00                           0
-#define ISC01                           1
-#define ISC10                           2
-#define ISC11                           3
-#define ISC20                           4
-#define ISC21                           5
-#define ISC30                           6
-#define ISC31                           7
-
-/* External Interrupt Control Register B */
-#define EICRB                           _SFR_MEM8(0x6A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_EICRB {
-        unsigned int isc4 : 2;	/* External Interrupt 4 Sense Control Bit */
-        unsigned int isc5 : 2;	/* External Interrupt 5 Sense Control Bit */
-        unsigned int isc6 : 2;	/* External Interrupt 6 Sense Control Bit */
-        unsigned int isc7 : 2;	/* External Interrupt 7 Sense Control Bit */
-};
-
-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* EICRB */
-
-#define ISC40                           0
-#define ISC41                           1
-#define ISC50                           2
-#define ISC51                           3
-#define ISC60                           4
-#define ISC61                           5
-#define ISC70                           6
-#define ISC71                           7
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0                          _SFR_MEM8(0x6B)
-
-  /* PCMSK0 */
-
-#define PCINT0                          0
-#define PCINT1                          1
-#define PCINT2                          2
-#define PCINT3                          3
-#define PCINT4                          4
-#define PCINT5                          5
-#define PCINT6                          6
-#define PCINT7                          7
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1                          _SFR_MEM8(0x6C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK1 {
-        unsigned int pcint : 2;	/* Pin Change Enable Mask */
-        unsigned int pcint1 : 6;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK1 */
-
-#define PCINT8                          0
-#define PCINT9                          1
-#define PCINT10                         2
-#define PCINT11                         3
-#define PCINT12                         4
-#define PCINT13                         5
-#define PCINT14                         6
-#define PCINT15                         7
-
-/* Pin Change Mask Register 2 */
-#define PCMSK2                          _SFR_MEM8(0x6D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PCMSK2 {
-        unsigned int pcint1 : 4;	/* Pin Change Enable Mask */
-        unsigned int pcint2 : 4;	/* Pin Change Enable Mask */
-};
-
-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PCMSK2 */
-
-#define PCINT16                         0
-#define PCINT17                         1
-#define PCINT18                         2
-#define PCINT19                         3
-#define PCINT20                         4
-#define PCINT21                         5
-#define PCINT22                         6
-#define PCINT23                         7
-
-/* Timer/Counter0 Interrupt Mask Register */
-#define TIMSK0                          _SFR_MEM8(0x6E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK0 {
-        unsigned int toie0 : 1;	/* Timer/Counter0 Overflow Interrupt Enable */
-        unsigned int ocie0a : 1;	/* Timer/Counter0 Output Compare Match A Interrupt Enable */
-        unsigned int ocie0b : 1;	/* Timer/Counter0 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK0 */
-
-#define TOIE0                           0
-#define OCIE0A                          1
-#define OCIE0B                          2
-
-/* Timer/Counter1 Interrupt Mask Register */
-#define TIMSK1                          _SFR_MEM8(0x6F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK1 {
-        unsigned int toie1 : 1;	/* Timer/Counter1 Overflow Interrupt Enable */
-        unsigned int ocie1a : 1;	/* Timer/Counter1 Output Compare A Match Interrupt Enable */
-        unsigned int ocie1b : 1;	/* Timer/Counter1 Output Compare B Match Interrupt Enable */
-        unsigned int ocie1c : 1;	/* Timer/Counter1 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie1 : 1;	/* Timer/Counter1 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK1 */
-
-#define TOIE1                           0
-#define OCIE1A                          1
-#define OCIE1B                          2
-#define OCIE1C                          3
-#define ICIE1                           5
-
-/* Timer/Counter Interrupt Mask register */
-#define TIMSK2                          _SFR_MEM8(0x70)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK2 {
-        unsigned int toie2 : 1;	/* Timer/Counter2 Overflow Interrupt Enable */
-        unsigned int ocie2a : 1;	/* Timer/Counter2 Output Compare Match A Interrupt Enable */
-        unsigned int ocie2b : 1;	/* Timer/Counter2 Output Compare Match B Interrupt Enable */
-        unsigned int : 5;
-};
-
-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK2 */
-
-#define TOIE2                           0
-#define TOIE2A                          0
-#define OCIE2A                          1
-#define OCIE2B                          2
-
-/* Timer/Counter3 Interrupt Mask Register */
-#define TIMSK3                          _SFR_MEM8(0x71)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK3 {
-        unsigned int toie3 : 1;	/* Timer/Counter3 Overflow Interrupt Enable */
-        unsigned int ocie3a : 1;	/* Timer/Counter3 Output Compare A Match Interrupt Enable */
-        unsigned int ocie3b : 1;	/* Timer/Counter3 Output Compare B Match Interrupt Enable */
-        unsigned int ocie3c : 1;	/* Timer/Counter3 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie3 : 1;	/* Timer/Counter3 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK3 */
-
-#define TOIE3                           0
-#define OCIE3A                          1
-#define OCIE3B                          2
-#define OCIE3C                          3
-#define ICIE3                           5
-
-/* Timer/Counter4 Interrupt Mask Register */
-#define TIMSK4                          _SFR_MEM8(0x72)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK4 {
-        unsigned int toie4 : 1;	/* Timer/Counter4 Overflow Interrupt Enable */
-        unsigned int ocie4a : 1;	/* Timer/Counter4 Output Compare A Match Interrupt Enable */
-        unsigned int ocie4b : 1;	/* Timer/Counter4 Output Compare B Match Interrupt Enable */
-        unsigned int ocie4c : 1;	/* Timer/Counter4 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie4 : 1;	/* Timer/Counter4 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK4 */
-
-#define TOIE4                           0
-#define OCIE4A                          1
-#define OCIE4B                          2
-#define OCIE4C                          3
-#define ICIE4                           5
-
-/* Timer/Counter5 Interrupt Mask Register */
-#define TIMSK5                          _SFR_MEM8(0x73)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TIMSK5 {
-        unsigned int toie5 : 1;	/* Timer/Counter5 Overflow Interrupt Enable */
-        unsigned int ocie5a : 1;	/* Timer/Counter5 Output Compare A Match Interrupt Enable */
-        unsigned int ocie5b : 1;	/* Timer/Counter5 Output Compare B Match Interrupt Enable */
-        unsigned int ocie5c : 1;	/* Timer/Counter5 Output Compare C Match Interrupt Enable */
-        unsigned int : 1;
-        unsigned int icie5 : 1;	/* Timer/Counter5 Input Capture Interrupt Enable */
-        unsigned int : 2;
-};
-
-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TIMSK5 */
-
-#define TOIE5                           0
-#define OCIE5A                          1
-#define OCIE5B                          2
-#define OCIE5C                          3
-#define ICIE5                           5
-
-/* Flash Extended-Mode Control-Register */
-#define NEMCR                           _SFR_MEM8(0x75)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_NEMCR {
-        unsigned int : 4;
-        unsigned int aeam : 2;	/* Address for Extended Address Mode of Extra Rows */
-        unsigned int eneam : 1;	/* Enable Extended Address Mode for Extra Rows */
-        unsigned int : 1;
-};
-
-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* NEMCR */
-
-#define AEAM0                           4
-#define AEAM1                           5
-#define ENEAM                           6
-
-/* The ADC Control and Status Register C */
-#define ADCSRC                          _SFR_MEM8(0x77)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRC {
-        unsigned int adsut : 5;	/* ADC Start-up Time */
-        unsigned int res0 : 1;	/* Reserved */
-        unsigned int adtht : 2;	/* ADC Track-and-Hold Time */
-};
-
-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRC */
-
-#define ADSUT0                          0
-#define ADSUT1                          1
-#define ADSUT2                          2
-#define ADSUT3                          3
-#define ADSUT4                          4
-#define ADTHT0                          6
-#define ADTHT1                          7
-
-/* ADC Data Register  Bytes */
-#ifndef __ASSEMBLER__
-#define ADC                             _SFR_MEM16(0x78)
-#define ADCL                            _SFR_MEM8(0x78)
-#define ADCH                            _SFR_MEM8(0x79)
-#endif /* __ASSEMBLER__ */
-#define ADCW                            _SFR_MEM16(0x78)
-#define ADCWL                           _SFR_MEM8(0x78)
-#define ADCWH                           _SFR_MEM8(0x79)
-
-/* The ADC Control and Status Register A */
-#define ADCSRA                          _SFR_MEM8(0x7A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRA {
-        unsigned int adps : 3;	/* ADC  Prescaler Select Bits */
-        unsigned int adie : 1;	/* ADC Interrupt Enable */
-        unsigned int adif : 1;	/* ADC Interrupt Flag */
-        unsigned int adate : 1;	/* ADC Auto Trigger Enable */
-        unsigned int adsc : 1;	/* ADC Start Conversion */
-        unsigned int aden : 1;	/* ADC Enable */
-};
-
-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRA */
-
-#define ADPS0                           0
-#define ADPS1                           1
-#define ADPS2                           2
-#define ADIE                            3
-#define ADIF                            4
-#define ADATE                           5
-#define ADSC                            6
-#define ADEN                            7
-
-/* ADC Control and Status Register B */
-#define ADCSRB                          _SFR_MEM8(0x7B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADCSRB {
-        unsigned int adts : 3;	/* ADC Auto Trigger Source */
-        unsigned int mux5 : 1;	/* Analog Channel and Gain Selection Bits */
-        unsigned int acch : 1;	/* Analog Channel Change */
-        unsigned int refok : 1;	/* Reference Voltage OK */
-        unsigned int acme : 1;	/* Analog Comparator Multiplexer Enable */
-        unsigned int avddok : 1;	/* AVDD Supply Voltage OK */
-};
-
-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADCSRB */
-
-#define ADTS0                           0
-#define ADTS1                           1
-#define ADTS2                           2
-#define MUX5                            3
-#define ACCH                            4
-#define REFOK                           5
-#define ACME                            6
-#define AVDDOK                          7
-
-/* The ADC Multiplexer Selection Register */
-#define ADMUX                           _SFR_MEM8(0x7C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ADMUX {
-        unsigned int mux : 5;	/* Analog Channel and Gain Selection Bits */
-        unsigned int adlar : 1;	/* ADC Left Adjust Result */
-        unsigned int refs : 2;	/* Reference Selection Bits */
-};
-
-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ADMUX */
-
-#define MUX0                            0
-#define MUX1                            1
-#define MUX2                            2
-#define MUX3                            3
-#define MUX4                            4
-#define ADLAR                           5
-#define REFS0                           6
-#define REFS1                           7
-
-/* Digital Input Disable Register 2 */
-#define DIDR2                           _SFR_MEM8(0x7D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR2 {
-        unsigned int adc8d : 1;	/* Reserved Bits */
-        unsigned int adc9d : 1;	/* Reserved Bits */
-        unsigned int adc10d : 1;	/* Reserved Bits */
-        unsigned int adc11d : 1;	/* Reserved Bits */
-        unsigned int adc12d : 1;	/* Reserved Bits */
-        unsigned int adc13d : 1;	/* Reserved Bits */
-        unsigned int adc14d : 1;	/* Reserved Bits */
-        unsigned int adc15d : 1;	/* Reserved Bits */
-};
-
-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR2 */
-
-#define ADC8D                           0
-#define ADC9D                           1
-#define ADC10D                          2
-#define ADC11D                          3
-#define ADC12D                          4
-#define ADC13D                          5
-#define ADC14D                          6
-#define ADC15D                          7
-
-/* Digital Input Disable Register 0 */
-#define DIDR0                           _SFR_MEM8(0x7E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR0 {
-        unsigned int adc0d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc1d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc2d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc3d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc4d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc5d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc6d : 1;	/* Disable ADC7:0 Digital Input */
-        unsigned int adc7d : 1;	/* Disable ADC7:0 Digital Input */
-};
-
-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR0 */
-
-#define ADC0D                           0
-#define ADC1D                           1
-#define ADC2D                           2
-#define ADC3D                           3
-#define ADC4D                           4
-#define ADC5D                           5
-#define ADC6D                           6
-#define ADC7D                           7
-
-/* Digital Input Disable Register 1 */
-#define DIDR1                           _SFR_MEM8(0x7F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DIDR1 {
-        unsigned int ain0d : 1;	/* AIN0 Digital Input Disable */
-        unsigned int ain1d : 1;	/* AIN1 Digital Input Disable */
-        unsigned int : 6;
-};
-
-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DIDR1 */
-
-#define AIN0D                           0
-#define AIN1D                           1
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A                          _SFR_MEM8(0x80)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1A {
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int com1c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com1b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com1a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1A */
-
-#define WGM10                           0
-#define WGM11                           1
-#define COM1C0                          2
-#define COM1C1                          3
-#define COM1B0                          4
-#define COM1B1                          5
-#define COM1A0                          6
-#define COM1A1                          7
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B                          _SFR_MEM8(0x81)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1B {
-        unsigned int cs1 : 3;	/* Clock Select */
-        unsigned int wgm1 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices1 : 1;	/* Input Capture 1 Edge Select */
-        unsigned int icnc1 : 1;	/* Input Capture 1 Noise Canceller */
-};
-
-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1B */
-
-#define CS10                            0
-#define CS11                            1
-#define CS12                            2
-#define WGM12                           3
-#define WGM13                           4
-#define ICES1                           6
-#define ICNC1                           7
-
-/* Timer/Counter1 Control Register C */
-#define TCCR1C                          _SFR_MEM8(0x82)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR1C {
-        unsigned int : 5;
-        unsigned int foc1c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc1b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc1a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR1C */
-
-#define FOC1C                           5
-#define FOC1B                           6
-#define FOC1A                           7
-
-/* Timer/Counter1  Bytes */
-#define TCNT1                           _SFR_MEM16(0x84)
-#define TCNT1L                          _SFR_MEM8(0x84)
-#define TCNT1H                          _SFR_MEM8(0x85)
-
-/* Timer/Counter1 Input Capture Register  Bytes */
-#define ICR1                            _SFR_MEM16(0x86)
-#define ICR1L                           _SFR_MEM8(0x86)
-#define ICR1H                           _SFR_MEM8(0x87)
-
-/* Timer/Counter1 Output Compare Register A  Bytes */
-#define OCR1A                           _SFR_MEM16(0x88)
-#define OCR1AL                          _SFR_MEM8(0x88)
-#define OCR1AH                          _SFR_MEM8(0x89)
-
-/* Timer/Counter1 Output Compare Register B  Bytes */
-#define OCR1B                           _SFR_MEM16(0x8A)
-#define OCR1BL                          _SFR_MEM8(0x8A)
-#define OCR1BH                          _SFR_MEM8(0x8B)
-
-/* Timer/Counter1 Output Compare Register C  Bytes */
-#define OCR1C                           _SFR_MEM16(0x8C)
-#define OCR1CL                          _SFR_MEM8(0x8C)
-#define OCR1CH                          _SFR_MEM8(0x8D)
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A                          _SFR_MEM8(0x90)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3A {
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int com3c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com3b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com3a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3A */
-
-#define WGM30                           0
-#define WGM31                           1
-#define COM3C0                          2
-#define COM3C1                          3
-#define COM3B0                          4
-#define COM3B1                          5
-#define COM3A0                          6
-#define COM3A1                          7
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B                          _SFR_MEM8(0x91)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3B {
-        unsigned int cs3 : 3;	/* Clock Select */
-        unsigned int wgm3 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices3 : 1;	/* Input Capture 3 Edge Select */
-        unsigned int icnc3 : 1;	/* Input Capture 3 Noise Canceller */
-};
-
-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3B */
-
-#define CS30                            0
-#define CS31                            1
-#define CS32                            2
-#define WGM32                           3
-#define WGM33                           4
-#define ICES3                           6
-#define ICNC3                           7
-
-/* Timer/Counter3 Control Register C */
-#define TCCR3C                          _SFR_MEM8(0x92)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR3C {
-        unsigned int : 5;
-        unsigned int foc3c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc3b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc3a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR3C */
-
-#define FOC3C                           5
-#define FOC3B                           6
-#define FOC3A                           7
-
-/* Timer/Counter3  Bytes */
-#define TCNT3                           _SFR_MEM16(0x94)
-#define TCNT3L                          _SFR_MEM8(0x94)
-#define TCNT3H                          _SFR_MEM8(0x95)
-
-/* Timer/Counter3 Input Capture Register  Bytes */
-#define ICR3                            _SFR_MEM16(0x96)
-#define ICR3L                           _SFR_MEM8(0x96)
-#define ICR3H                           _SFR_MEM8(0x97)
-
-/* Timer/Counter3 Output Compare Register A  Bytes */
-#define OCR3A                           _SFR_MEM16(0x98)
-#define OCR3AL                          _SFR_MEM8(0x98)
-#define OCR3AH                          _SFR_MEM8(0x99)
-
-/* Timer/Counter3 Output Compare Register B  Bytes */
-#define OCR3B                           _SFR_MEM16(0x9A)
-#define OCR3BL                          _SFR_MEM8(0x9A)
-#define OCR3BH                          _SFR_MEM8(0x9B)
-
-/* Timer/Counter3 Output Compare Register C  Bytes */
-#define OCR3C                           _SFR_MEM16(0x9C)
-#define OCR3CL                          _SFR_MEM8(0x9C)
-#define OCR3CH                          _SFR_MEM8(0x9D)
-
-/* Timer/Counter4 Control Register A */
-#define TCCR4A                          _SFR_MEM8(0xA0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4A {
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int com4c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com4b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com4a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4A */
-
-#define WGM40                           0
-#define WGM41                           1
-#define COM4C0                          2
-#define COM4C1                          3
-#define COM4B0                          4
-#define COM4B1                          5
-#define COM4A0                          6
-#define COM4A1                          7
-
-/* Timer/Counter4 Control Register B */
-#define TCCR4B                          _SFR_MEM8(0xA1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4B {
-        unsigned int cs4 : 3;	/* Clock Select */
-        unsigned int wgm4 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices4 : 1;	/* Input Capture 4 Edge Select */
-        unsigned int icnc4 : 1;	/* Input Capture 4 Noise Canceller */
-};
-
-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4B */
-
-#define CS40                            0
-#define CS41                            1
-#define CS42                            2
-#define WGM42                           3
-#define WGM43                           4
-#define ICES4                           6
-#define ICNC4                           7
-
-/* Timer/Counter4 Control Register C */
-#define TCCR4C                          _SFR_MEM8(0xA2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR4C {
-        unsigned int : 5;
-        unsigned int foc4c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc4b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc4a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR4C */
-
-#define FOC4C                           5
-#define FOC4B                           6
-#define FOC4A                           7
-
-/* Timer/Counter4  Bytes */
-#define TCNT4                           _SFR_MEM16(0xA4)
-#define TCNT4L                          _SFR_MEM8(0xA4)
-#define TCNT4H                          _SFR_MEM8(0xA5)
-
-/* Timer/Counter4 Input Capture Register  Bytes */
-#define ICR4                            _SFR_MEM16(0xA6)
-#define ICR4L                           _SFR_MEM8(0xA6)
-#define ICR4H                           _SFR_MEM8(0xA7)
-
-/* Timer/Counter4 Output Compare Register A  Bytes */
-#define OCR4A                           _SFR_MEM16(0xA8)
-#define OCR4AL                          _SFR_MEM8(0xA8)
-#define OCR4AH                          _SFR_MEM8(0xA9)
-
-/* Timer/Counter4 Output Compare Register B  Bytes */
-#define OCR4B                           _SFR_MEM16(0xAA)
-#define OCR4BL                          _SFR_MEM8(0xAA)
-#define OCR4BH                          _SFR_MEM8(0xAB)
-
-/* Timer/Counter4 Output Compare Register C  Bytes */
-#define OCR4C                           _SFR_MEM16(0xAC)
-#define OCR4CL                          _SFR_MEM8(0xAC)
-#define OCR4CH                          _SFR_MEM8(0xAD)
-
-/* Timer/Counter2 Control Register A */
-#define TCCR2A                          _SFR_MEM8(0xB0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2A {
-        unsigned int wgm2 : 2;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int com2b : 2;	/* Compare Match Output B Mode */
-        unsigned int com2a : 2;	/* Compare Match Output A Mode */
-};
-
-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2A */
-
-#define WGM20                           0
-#define WGM21                           1
-#define COM2B0                          4
-#define COM2B1                          5
-#define COM2A0                          6
-#define COM2A1                          7
-
-/* Timer/Counter2 Control Register B */
-#define TCCR2B                          _SFR_MEM8(0xB1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR2B {
-        unsigned int cs2 : 3;	/* Clock Select */
-        unsigned int wgm22 : 1;	/* Waveform Generation Mode */
-        unsigned int : 2;
-        unsigned int foc2b : 1;	/* Force Output Compare B */
-        unsigned int foc2a : 1;	/* Force Output Compare A */
-};
-
-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR2B */
-
-#define CS20                            0
-#define CS21                            1
-#define CS22                            2
-#define WGM22                           3
-#define FOC2B                           6
-#define FOC2A                           7
-
-/* Timer/Counter2 */
-#define TCNT2                           _SFR_MEM8(0xB2)
-
-  /* TCNT2 */
-
-#define TCNT20                          0
-#define TCNT21                          1
-#define TCNT22                          2
-#define TCNT23                          3
-#define TCNT24                          4
-#define TCNT25                          5
-#define TCNT26                          6
-#define TCNT27                          7
-
-/* Timer/Counter2 Output Compare Register A */
-#define OCR2A                           _SFR_MEM8(0xB3)
-
-  /* OCR2A */
-
-#define OCR2A0                          0
-#define OCR2A1                          1
-#define OCR2A2                          2
-#define OCR2A3                          3
-#define OCR2A4                          4
-#define OCR2A5                          5
-#define OCR2A6                          6
-#define OCR2A7                          7
-
-/* Timer/Counter2 Output Compare Register B */
-#define OCR2B                           _SFR_MEM8(0xB4)
-
-  /* OCR2B */
-
-#define OCR2B0                          0
-#define OCR2B1                          1
-#define OCR2B2                          2
-#define OCR2B3                          3
-#define OCR2B4                          4
-#define OCR2B5                          5
-#define OCR2B6                          6
-#define OCR2B7                          7
-
-/* Asynchronous Status Register */
-#define ASSR                            _SFR_MEM8(0xB6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ASSR {
-        unsigned int tcr2bub : 1;	/* Timer/Counter2 Control Register B Update Busy */
-        unsigned int tcr2aub : 1;	/* Timer/Counter2 Control Register A Update Busy */
-        unsigned int ocr2bub : 1;	/* Timer/Counter2 Output Compare Register B Update Busy */
-        unsigned int ocr2aub : 1;	/* Timer/Counter2 Output Compare Register A Update Busy */
-        unsigned int tcn2ub : 1;	/* Timer/Counter2 Update Busy */
-        unsigned int as2 : 1;	/* Timer/Counter2 Asynchronous Mode */
-        unsigned int exclk : 1;	/* Enable External Clock Input */
-        unsigned int exclkamr : 1;	/* Enable External Clock Input for AMR */
-};
-
-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* ASSR */
-
-#define TCR2BUB                         0
-#define TCR2AUB                         1
-#define OCR2BUB                         2
-#define OCR2AUB                         3
-#define TCN2UB                          4
-#define AS2                             5
-#define EXCLK                           6
-#define EXCLKAMR                        7
-
-/* TWI Bit Rate Register */
-#define TWBR                            _SFR_MEM8(0xB8)
-
-  /* TWBR */
-
-#define TWBR0                           0
-#define TWBR1                           1
-#define TWBR2                           2
-#define TWBR3                           3
-#define TWBR4                           4
-#define TWBR5                           5
-#define TWBR6                           6
-#define TWBR7                           7
-
-/* TWI Status Register */
-#define TWSR                            _SFR_MEM8(0xB9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWSR {
-        unsigned int twps : 2;	/* TWI Prescaler Bits */
-        unsigned int : 1;
-        unsigned int tws : 5;	/* TWI Status */
-};
-
-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWSR */
-
-#define TWPS0                           0
-#define TWPS1                           1
-#define TWS3                            3
-#define TWS4                            4
-#define TWS5                            5
-#define TWS6                            6
-#define TWS7                            7
-
-/* TWI (Slave) Address Register */
-#define TWAR                            _SFR_MEM8(0xBA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAR {
-        unsigned int twgce : 1;	/* TWI General Call Recognition Enable Bit */
-        unsigned int twa : 7;	/* TWI (Slave) Address */
-};
-
-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAR */
-
-#define TWGCE                           0
-#define TWA0                            1
-#define TWA1                            2
-#define TWA2                            3
-#define TWA3                            4
-#define TWA4                            5
-#define TWA5                            6
-#define TWA6                            7
-
-/* TWI Data Register */
-#define TWDR                            _SFR_MEM8(0xBB)
-
-  /* TWDR */
-
-#define TWD0                            0
-#define TWD1                            1
-#define TWD2                            2
-#define TWD3                            3
-#define TWD4                            4
-#define TWD5                            5
-#define TWD6                            6
-#define TWD7                            7
-
-/* TWI Control Register */
-#define TWCR                            _SFR_MEM8(0xBC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWCR {
-        unsigned int twie : 1;	/* TWI Interrupt Enable */
-        unsigned int : 1;
-        unsigned int twen : 1;	/* TWI Enable Bit */
-        unsigned int twwc : 1;	/* TWI Write Collision Flag */
-        unsigned int twsto : 1;	/* TWI STOP Condition Bit */
-        unsigned int twsta : 1;	/* TWI START Condition Bit */
-        unsigned int twea : 1;	/* TWI Enable Acknowledge Bit */
-        unsigned int twint : 1;	/* TWI Interrupt Flag */
-};
-
-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWCR */
-
-#define TWIE                            0
-#define TWEN                            2
-#define TWWC                            3
-#define TWSTO                           4
-#define TWSTA                           5
-#define TWEA                            6
-#define TWINT                           7
-
-/* TWI (Slave) Address Mask Register */
-#define TWAMR                           _SFR_MEM8(0xBD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TWAMR {
-        unsigned int : 1;
-        unsigned int twam : 7;	/* TWI Address Mask */
-};
-
-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TWAMR */
-
-#define TWAM0                           1
-#define TWAMR0                          1
-#define TWAM1                           2
-#define TWAMR1                          2
-#define TWAM2                           3
-#define TWAMR2                          3
-#define TWAM3                           4
-#define TWAMR3                          4
-#define TWAM4                           5
-#define TWAMR4                          5
-#define TWAM5                           6
-#define TWAMR5                          6
-#define TWAM6                           7
-#define TWAMR6                          7
-
-/* USART0 Control and Status Register A */
-#define UCSR0A                          _SFR_MEM8(0xC0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0A {
-        unsigned int mpcm0 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x0 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe0 : 1;	/* USART Parity Error */
-        unsigned int dor0 : 1;	/* Data OverRun */
-        unsigned int fe0 : 1;	/* Frame Error */
-        unsigned int udre0 : 1;	/* USART Data Register Empty */
-        unsigned int txc0 : 1;	/* USART Transmit Complete */
-        unsigned int rxc0 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0A */
-
-#define MPCM0                           0
-#define U2X0                            1
-#define UPE0                            2
-#define DOR0                            3
-#define FE0                             4
-#define UDRE0                           5
-#define TXC0                            6
-#define RXC0                            7
-
-/* USART0 Control and Status Register B */
-#define UCSR0B                          _SFR_MEM8(0xC1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0B {
-        unsigned int txb80 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb80 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz02 : 1;	/* Character Size */
-        unsigned int txen0 : 1;	/* Transmitter Enable */
-        unsigned int rxen0 : 1;	/* Receiver Enable */
-        unsigned int udrie0 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie0 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie0 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0B */
-
-#define TXB80                           0
-#define RXB80                           1
-#define UCSZ02                          2
-#define TXEN0                           3
-#define RXEN0                           4
-#define UDRIE0                          5
-#define TXCIE0                          6
-#define RXCIE0                          7
-
-/* USART0 Control and Status Register C */
-#define UCSR0C                          _SFR_MEM8(0xC2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR0C {
-        unsigned int ucpol0 : 1;	/* Clock Polarity */
-        unsigned int ucsz0 : 2;	/* Character Size */
-        unsigned int ucpha0 : 1;	/* Clock Phase */
-        unsigned int udord0 : 1;	/* Data Order */
-        unsigned int usbs0 : 1;	/* Stop Bit Select */
-        unsigned int upm0 : 2;	/* Parity Mode */
-        unsigned int umsel0 : 2;	/* USART Mode Select */
-};
-
-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR0C */
-
-#define UCPOL0                          0
-#define UCPHA0                          1
-#define UCPHA0                          1
-#define UCSZ00                          1
-#define UDORD0                          2
-#define UDORD0                          2
-#define UCSZ01                          2
-#define USBS0                           3
-#define UPM00                           4
-#define UPM01                           5
-#define UMSEL00                         6
-#define UMSEL0                          6
-#define UMSEL01                         7
-#define UMSEL1                          7
-
-/* USART0 Baud Rate Register  Bytes */
-#define UBRR0                           _SFR_MEM16(0xC4)
-#define UBRR0L                          _SFR_MEM8(0xC4)
-#define UBRR0H                          _SFR_MEM8(0xC5)
-
-/* USART0 I/O Data Register */
-#define UDR0                            _SFR_MEM8(0xC6)
-
-  /* UDR0 */
-
-#define UDR00                           0
-#define UDR01                           1
-#define UDR02                           2
-#define UDR03                           3
-#define UDR04                           4
-#define UDR05                           5
-#define UDR06                           6
-#define UDR07                           7
-
-/* USART1 Control and Status Register A */
-#define UCSR1A                          _SFR_MEM8(0xC8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1A {
-        unsigned int mpcm1 : 1;	/* Multi-processor Communication Mode */
-        unsigned int u2x1 : 1;	/* Double the USART Transmission Speed */
-        unsigned int upe1 : 1;	/* USART Parity Error */
-        unsigned int dor1 : 1;	/* Data OverRun */
-        unsigned int fe1 : 1;	/* Frame Error */
-        unsigned int udre1 : 1;	/* USART Data Register Empty */
-        unsigned int txc1 : 1;	/* USART Transmit Complete */
-        unsigned int rxc1 : 1;	/* USART Receive Complete */
-};
-
-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1A */
-
-#define MPCM1                           0
-#define U2X1                            1
-#define UPE1                            2
-#define DOR1                            3
-#define FE1                             4
-#define UDRE1                           5
-#define TXC1                            6
-#define RXC1                            7
-
-/* USART1 Control and Status Register B */
-#define UCSR1B                          _SFR_MEM8(0xC9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1B {
-        unsigned int txb81 : 1;	/* Transmit Data Bit 8 */
-        unsigned int rxb81 : 1;	/* Receive Data Bit 8 */
-        unsigned int ucsz12 : 1;	/* Character Size */
-        unsigned int txen1 : 1;	/* Transmitter Enable */
-        unsigned int rxen1 : 1;	/* Receiver Enable */
-        unsigned int udrie1 : 1;	/* USART Data Register Empty Interrupt Enable */
-        unsigned int txcie1 : 1;	/* TX Complete Interrupt Enable */
-        unsigned int rxcie1 : 1;	/* RX Complete Interrupt Enable */
-};
-
-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1B */
-
-#define TXB81                           0
-#define RXB81                           1
-#define UCSZ12                          2
-#define TXEN1                           3
-#define RXEN1                           4
-#define UDRIE1                          5
-#define TXCIE1                          6
-#define RXCIE1                          7
-
-/* USART1 Control and Status Register C */
-#define UCSR1C                          _SFR_MEM8(0xCA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_UCSR1C {
-        unsigned int ucpol1 : 1;	/* Clock Polarity */
-        unsigned int ucsz1 : 2;	/* Character Size */
-        unsigned int ucpha1 : 1;	/* Clock Phase */
-        unsigned int udord1 : 1;	/* Data Order */
-        unsigned int usbs1 : 1;	/* Stop Bit Select */
-        unsigned int upm1 : 2;	/* Parity Mode */
-        unsigned int umsel1 : 2;	/* USART Mode Select */
-};
-
-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* UCSR1C */
-
-#define UCPOL1                          0
-#define UCPHA1                          1
-#define UCPHA1                          1
-#define UCSZ10                          1
-#define UDORD1                          2
-#define UDORD1                          2
-#define UCSZ11                          2
-#define USBS1                           3
-#define UPM10                           4
-#define UPM11                           5
-#define UMSEL10                         6
-#define UMSEL11                         7
-
-/* USART1 Baud Rate Register  Bytes */
-#define UBRR1                           _SFR_MEM16(0xCC)
-#define UBRR1L                          _SFR_MEM8(0xCC)
-#define UBRR1H                          _SFR_MEM8(0xCD)
-
-/* USART1 I/O Data Register */
-#define UDR1                            _SFR_MEM8(0xCE)
-
-  /* UDR1 */
-
-#define UDR10                           0
-#define UDR11                           1
-#define UDR12                           2
-#define UDR13                           3
-#define UDR14                           4
-#define UDR15                           5
-#define UDR16                           6
-#define UDR17                           7
-
-/* Symbol Counter Control Register 0 */
-#define SCCR0                           _SFR_MEM8(0xDC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR0 {
-        unsigned int sccmp : 3;	/* Symbol Counter Compare Unit 3 Mode select */
-        unsigned int sctse : 1;	/* Symbol Counter Automatic Timestamping enable */
-        unsigned int sccksel : 1;	/* Symbol Counter Clock Source select */
-        unsigned int scen : 1;	/* Symbol Counter enable */
-        unsigned int scmbts : 1;	/* Manual Beacon Timestamp */
-        unsigned int scres : 1;	/* Symbol Counter Synchronization */
-};
-
-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR0 */
-
-#define SCCMP1                          0
-#define SCCMP2                          1
-#define SCCMP3                          2
-#define SCTSE                           3
-#define SCCKSEL                         4
-#define SCEN                            5
-#define SCMBTS                          6
-#define SCRES                           7
-
-/* Symbol Counter Control Register 1 */
-#define SCCR1                           _SFR_MEM8(0xDD)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCR1 {
-        unsigned int scenbo : 1;	/* Backoff Slot Counter enable */
-        unsigned int : 7;
-};
-
-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCR1 */
-
-#define SCENBO                          0
-
-/* Symbol Counter Status Register */
-#define SCSR                            _SFR_MEM8(0xDE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCSR {
-        unsigned int scbsy : 1;	/* Symbol Counter busy */
-        unsigned int : 7;
-};
-
-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCSR */
-
-#define SCBSY                           0
-
-/* Symbol Counter Interrupt Mask Register */
-#define SCIRQM                          _SFR_MEM8(0xDF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQM {
-        unsigned int irqmcp : 3;	/* Symbol Counter Compare Match 3 IRQ enable */
-        unsigned int irqmof : 1;	/* Symbol Counter Overflow IRQ enable */
-        unsigned int irqmbo : 1;	/* Backoff Slot Counter IRQ enable */
-        unsigned int : 3;
-};
-
-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQM */
-
-#define IRQMCP1                         0
-#define IRQMCP2                         1
-#define IRQMCP3                         2
-#define IRQMOF                          3
-#define IRQMBO                          4
-
-/* Symbol Counter Interrupt Status Register */
-#define SCIRQS                          _SFR_MEM8(0xE0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCIRQS {
-        unsigned int irqscp : 3;	/* Compare Unit 3 Compare Match IRQ */
-        unsigned int irqsof : 1;	/* Symbol Counter Overflow IRQ */
-        unsigned int irqsbo : 1;	/* Backoff Slot Counter IRQ */
-        unsigned int : 3;
-};
-
-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCIRQS */
-
-#define IRQSCP1                         0
-#define IRQSCP2                         1
-#define IRQSCP3                         2
-#define IRQSOF                          3
-#define IRQSBO                          4
-
-/* Symbol Counter Register LL-Byte */
-#define SCCNTLL                         _SFR_MEM8(0xE1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLL {
-        unsigned int sccntll : 8;	/* Symbol Counter Register LL-Byte */
-};
-
-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLL */
-
-#define SCCNTLL0                        0
-#define SCCNTLL1                        1
-#define SCCNTLL2                        2
-#define SCCNTLL3                        3
-#define SCCNTLL4                        4
-#define SCCNTLL5                        5
-#define SCCNTLL6                        6
-#define SCCNTLL7                        7
-
-/* Symbol Counter Register LH-Byte */
-#define SCCNTLH                         _SFR_MEM8(0xE2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTLH {
-        unsigned int sccntlh : 8;	/* Symbol Counter Register LH-Byte */
-};
-
-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTLH */
-
-#define SCCNTLH0                        0
-#define SCCNTLH1                        1
-#define SCCNTLH2                        2
-#define SCCNTLH3                        3
-#define SCCNTLH4                        4
-#define SCCNTLH5                        5
-#define SCCNTLH6                        6
-#define SCCNTLH7                        7
-
-/* Symbol Counter Register HL-Byte */
-#define SCCNTHL                         _SFR_MEM8(0xE3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHL {
-        unsigned int sccnthl : 8;	/* Symbol Counter Register HL-Byte */
-};
-
-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHL */
-
-#define SCCNTHL0                        0
-#define SCCNTHL1                        1
-#define SCCNTHL2                        2
-#define SCCNTHL3                        3
-#define SCCNTHL4                        4
-#define SCCNTHL5                        5
-#define SCCNTHL6                        6
-#define SCCNTHL7                        7
-
-/* Symbol Counter Register HH-Byte */
-#define SCCNTHH                         _SFR_MEM8(0xE4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCCNTHH {
-        unsigned int sccnthh : 8;	/* Symbol Counter Register HH-Byte */
-};
-
-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCCNTHH */
-
-#define SCCNTHH0                        0
-#define SCCNTHH1                        1
-#define SCCNTHH2                        2
-#define SCCNTHH3                        3
-#define SCCNTHH4                        4
-#define SCCNTHH5                        5
-#define SCCNTHH6                        6
-#define SCCNTHH7                        7
-
-/* Symbol Counter Beacon Timestamp Register LL-Byte */
-#define SCBTSRLL                        _SFR_MEM8(0xE5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLL {
-        unsigned int scbtsrll : 8;	/* Symbol Counter Beacon Timestamp Register LL-Byte */
-};
-
-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLL */
-
-#define SCBTSRLL0                       0
-#define SCBTSRLL1                       1
-#define SCBTSRLL2                       2
-#define SCBTSRLL3                       3
-#define SCBTSRLL4                       4
-#define SCBTSRLL5                       5
-#define SCBTSRLL6                       6
-#define SCBTSRLL7                       7
-
-/* Symbol Counter Beacon Timestamp Register LH-Byte */
-#define SCBTSRLH                        _SFR_MEM8(0xE6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRLH {
-        unsigned int scbtsrlh : 8;	/* Symbol Counter Beacon Timestamp Register LH-Byte */
-};
-
-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRLH */
-
-#define SCBTSRLH0                       0
-#define SCBTSRLH1                       1
-#define SCBTSRLH2                       2
-#define SCBTSRLH3                       3
-#define SCBTSRLH4                       4
-#define SCBTSRLH5                       5
-#define SCBTSRLH6                       6
-#define SCBTSRLH7                       7
-
-/* Symbol Counter Beacon Timestamp Register HL-Byte */
-#define SCBTSRHL                        _SFR_MEM8(0xE7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHL {
-        unsigned int scbtsrhl : 8;	/* Symbol Counter Beacon Timestamp Register HL-Byte */
-};
-
-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHL */
-
-#define SCBTSRHL0                       0
-#define SCBTSRHL1                       1
-#define SCBTSRHL2                       2
-#define SCBTSRHL3                       3
-#define SCBTSRHL4                       4
-#define SCBTSRHL5                       5
-#define SCBTSRHL6                       6
-#define SCBTSRHL7                       7
-
-/* Symbol Counter Beacon Timestamp Register HH-Byte */
-#define SCBTSRHH                        _SFR_MEM8(0xE8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCBTSRHH {
-        unsigned int scbtsrhh : 8;	/* Symbol Counter Beacon Timestamp Register HH-Byte */
-};
-
-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCBTSRHH */
-
-#define SCBTSRHH0                       0
-#define SCBTSRHH1                       1
-#define SCBTSRHH2                       2
-#define SCBTSRHH3                       3
-#define SCBTSRHH4                       4
-#define SCBTSRHH5                       5
-#define SCBTSRHH6                       6
-#define SCBTSRHH7                       7
-
-/* Symbol Counter Frame Timestamp Register LL-Byte */
-#define SCTSRLL                         _SFR_MEM8(0xE9)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLL {
-        unsigned int sctsrll : 8;	/* Symbol Counter Frame Timestamp Register LL-Byte */
-};
-
-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLL */
-
-#define SCTSRLL0                        0
-#define SCTSRLL1                        1
-#define SCTSRLL2                        2
-#define SCTSRLL3                        3
-#define SCTSRLL4                        4
-#define SCTSRLL5                        5
-#define SCTSRLL6                        6
-#define SCTSRLL7                        7
-
-/* Symbol Counter Frame Timestamp Register LH-Byte */
-#define SCTSRLH                         _SFR_MEM8(0xEA)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRLH {
-        unsigned int sctsrlh : 8;	/* Symbol Counter Frame Timestamp Register LH-Byte */
-};
-
-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRLH */
-
-#define SCTSRLH0                        0
-#define SCTSRLH1                        1
-#define SCTSRLH2                        2
-#define SCTSRLH3                        3
-#define SCTSRLH4                        4
-#define SCTSRLH5                        5
-#define SCTSRLH6                        6
-#define SCTSRLH7                        7
-
-/* Symbol Counter Frame Timestamp Register HL-Byte */
-#define SCTSRHL                         _SFR_MEM8(0xEB)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHL {
-        unsigned int sctsrhl : 8;	/* Symbol Counter Frame Timestamp Register HL-Byte */
-};
-
-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHL */
-
-#define SCTSRHL0                        0
-#define SCTSRHL1                        1
-#define SCTSRHL2                        2
-#define SCTSRHL3                        3
-#define SCTSRHL4                        4
-#define SCTSRHL5                        5
-#define SCTSRHL6                        6
-#define SCTSRHL7                        7
-
-/* Symbol Counter Frame Timestamp Register HH-Byte */
-#define SCTSRHH                         _SFR_MEM8(0xEC)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCTSRHH {
-        unsigned int sctsrhh : 8;	/* Symbol Counter Frame Timestamp Register HH-Byte */
-};
-
-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCTSRHH */
-
-#define SCTSRHH0                        0
-#define SCTSRHH1                        1
-#define SCTSRHH2                        2
-#define SCTSRHH3                        3
-#define SCTSRHH4                        4
-#define SCTSRHH5                        5
-#define SCTSRHH6                        6
-#define SCTSRHH7                        7
-
-/* Symbol Counter Output Compare Register 3 LL-Byte */
-#define SCOCR3LL                        _SFR_MEM8(0xED)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LL {
-        unsigned int scocr3ll : 8;	/* Symbol Counter Output Compare Register 3 LL-Byte */
-};
-
-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LL */
-
-#define SCOCR3LL0                       0
-#define SCOCR3LL1                       1
-#define SCOCR3LL2                       2
-#define SCOCR3LL3                       3
-#define SCOCR3LL4                       4
-#define SCOCR3LL5                       5
-#define SCOCR3LL6                       6
-#define SCOCR3LL7                       7
-
-/* Symbol Counter Output Compare Register 3 LH-Byte */
-#define SCOCR3LH                        _SFR_MEM8(0xEE)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3LH {
-        unsigned int scocr3lh : 8;	/* Symbol Counter Output Compare Register 3 LH-Byte */
-};
-
-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3LH */
-
-#define SCOCR3LH0                       0
-#define SCOCR3LH1                       1
-#define SCOCR3LH2                       2
-#define SCOCR3LH3                       3
-#define SCOCR3LH4                       4
-#define SCOCR3LH5                       5
-#define SCOCR3LH6                       6
-#define SCOCR3LH7                       7
-
-/* Symbol Counter Output Compare Register 3 HL-Byte */
-#define SCOCR3HL                        _SFR_MEM8(0xEF)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HL {
-        unsigned int scocr3hl : 8;	/* Symbol Counter Output Compare Register 3 HL-Byte */
-};
-
-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HL */
-
-#define SCOCR3HL0                       0
-#define SCOCR3HL1                       1
-#define SCOCR3HL2                       2
-#define SCOCR3HL3                       3
-#define SCOCR3HL4                       4
-#define SCOCR3HL5                       5
-#define SCOCR3HL6                       6
-#define SCOCR3HL7                       7
-
-/* Symbol Counter Output Compare Register 3 HH-Byte */
-#define SCOCR3HH                        _SFR_MEM8(0xF0)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR3HH {
-        unsigned int scocr3hh : 8;	/* Symbol Counter Output Compare Register 3 HH-Byte */
-};
-
-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR3HH */
-
-#define SCOCR3HH0                       0
-#define SCOCR3HH1                       1
-#define SCOCR3HH2                       2
-#define SCOCR3HH3                       3
-#define SCOCR3HH4                       4
-#define SCOCR3HH5                       5
-#define SCOCR3HH6                       6
-#define SCOCR3HH7                       7
-
-/* Symbol Counter Output Compare Register 2 LL-Byte */
-#define SCOCR2LL                        _SFR_MEM8(0xF1)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LL {
-        unsigned int scocr2ll : 8;	/* Symbol Counter Output Compare Register 2 LL-Byte */
-};
-
-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LL */
-
-#define SCOCR2LL0                       0
-#define SCOCR2LL1                       1
-#define SCOCR2LL2                       2
-#define SCOCR2LL3                       3
-#define SCOCR2LL4                       4
-#define SCOCR2LL5                       5
-#define SCOCR2LL6                       6
-#define SCOCR2LL7                       7
-
-/* Symbol Counter Output Compare Register 2 LH-Byte */
-#define SCOCR2LH                        _SFR_MEM8(0xF2)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2LH {
-        unsigned int scocr2lh : 8;	/* Symbol Counter Output Compare Register 2 LH-Byte */
-};
-
-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2LH */
-
-#define SCOCR2LH0                       0
-#define SCOCR2LH1                       1
-#define SCOCR2LH2                       2
-#define SCOCR2LH3                       3
-#define SCOCR2LH4                       4
-#define SCOCR2LH5                       5
-#define SCOCR2LH6                       6
-#define SCOCR2LH7                       7
-
-/* Symbol Counter Output Compare Register 2 HL-Byte */
-#define SCOCR2HL                        _SFR_MEM8(0xF3)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HL {
-        unsigned int scocr2hl : 8;	/* Symbol Counter Output Compare Register 2 HL-Byte */
-};
-
-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HL */
-
-#define SCOCR2HL0                       0
-#define SCOCR2HL1                       1
-#define SCOCR2HL2                       2
-#define SCOCR2HL3                       3
-#define SCOCR2HL4                       4
-#define SCOCR2HL5                       5
-#define SCOCR2HL6                       6
-#define SCOCR2HL7                       7
-
-/* Symbol Counter Output Compare Register 2 HH-Byte */
-#define SCOCR2HH                        _SFR_MEM8(0xF4)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR2HH {
-        unsigned int scocr2hh : 8;	/* Symbol Counter Output Compare Register 2 HH-Byte */
-};
-
-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR2HH */
-
-#define SCOCR2HH0                       0
-#define SCOCR2HH1                       1
-#define SCOCR2HH2                       2
-#define SCOCR2HH3                       3
-#define SCOCR2HH4                       4
-#define SCOCR2HH5                       5
-#define SCOCR2HH6                       6
-#define SCOCR2HH7                       7
-
-/* Symbol Counter Output Compare Register 1 LL-Byte */
-#define SCOCR1LL                        _SFR_MEM8(0xF5)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LL {
-        unsigned int scocr1ll : 8;	/* Symbol Counter Output Compare Register 1 LL-Byte */
-};
-
-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LL */
-
-#define SCOCR1LL0                       0
-#define SCOCR1LL1                       1
-#define SCOCR1LL2                       2
-#define SCOCR1LL3                       3
-#define SCOCR1LL4                       4
-#define SCOCR1LL5                       5
-#define SCOCR1LL6                       6
-#define SCOCR1LL7                       7
-
-/* Symbol Counter Output Compare Register 1 LH-Byte */
-#define SCOCR1LH                        _SFR_MEM8(0xF6)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1LH {
-        unsigned int scocr1lh : 8;	/* Symbol Counter Output Compare Register 1 LH-Byte */
-};
-
-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1LH */
-
-#define SCOCR1LH0                       0
-#define SCOCR1LH1                       1
-#define SCOCR1LH2                       2
-#define SCOCR1LH3                       3
-#define SCOCR1LH4                       4
-#define SCOCR1LH5                       5
-#define SCOCR1LH6                       6
-#define SCOCR1LH7                       7
-
-/* Symbol Counter Output Compare Register 1 HL-Byte */
-#define SCOCR1HL                        _SFR_MEM8(0xF7)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HL {
-        unsigned int scocr1hl : 8;	/* Symbol Counter Output Compare Register 1 HL-Byte */
-};
-
-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HL */
-
-#define SCOCR1HL0                       0
-#define SCOCR1HL1                       1
-#define SCOCR1HL2                       2
-#define SCOCR1HL3                       3
-#define SCOCR1HL4                       4
-#define SCOCR1HL5                       5
-#define SCOCR1HL6                       6
-#define SCOCR1HL7                       7
-
-/* Symbol Counter Output Compare Register 1 HH-Byte */
-#define SCOCR1HH                        _SFR_MEM8(0xF8)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SCOCR1HH {
-        unsigned int scocr1hh : 8;	/* Symbol Counter Output Compare Register 1 HH-Byte */
-};
-
-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SCOCR1HH */
-
-#define SCOCR1HH0                       0
-#define SCOCR1HH1                       1
-#define SCOCR1HH2                       2
-#define SCOCR1HH3                       3
-#define SCOCR1HH4                       4
-#define SCOCR1HH5                       5
-#define SCOCR1HH6                       6
-#define SCOCR1HH7                       7
-
-/* Timer/Counter5 Control Register A */
-#define TCCR5A                          _SFR_MEM8(0x120)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5A {
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int com5c : 2;	/* Compare Output Mode for Channel C */
-        unsigned int com5b : 2;	/* Compare Output Mode for Channel B */
-        unsigned int com5a : 2;	/* Compare Output Mode for Channel A */
-};
-
-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5A */
-
-#define WGM50                           0
-#define WGM51                           1
-#define COM5C0                          2
-#define COM5C1                          3
-#define COM5B0                          4
-#define COM5B1                          5
-#define COM5A0                          6
-#define COM5A1                          7
-
-/* Timer/Counter5 Control Register B */
-#define TCCR5B                          _SFR_MEM8(0x121)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5B {
-        unsigned int cs5 : 3;	/* Clock Select */
-        unsigned int wgm5 : 2;	/* Waveform Generation Mode */
-        unsigned int : 1;
-        unsigned int ices5 : 1;	/* Input Capture 5 Edge Select */
-        unsigned int icnc5 : 1;	/* Input Capture 5 Noise Canceller */
-};
-
-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5B */
-
-#define CS50                            0
-#define CS51                            1
-#define CS52                            2
-#define WGM52                           3
-#define WGM53                           4
-#define ICES5                           6
-#define ICNC5                           7
-
-/* Timer/Counter5 Control Register C */
-#define TCCR5C                          _SFR_MEM8(0x122)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TCCR5C {
-        unsigned int : 5;
-        unsigned int foc5c : 1;	/* Force Output Compare for Channel C */
-        unsigned int foc5b : 1;	/* Force Output Compare for Channel B */
-        unsigned int foc5a : 1;	/* Force Output Compare for Channel A */
-};
-
-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TCCR5C */
-
-#define FOC5C                           5
-#define FOC5B                           6
-#define FOC5A                           7
-
-/* Timer/Counter5  Bytes */
-#define TCNT5                           _SFR_MEM16(0x124)
-#define TCNT5L                          _SFR_MEM8(0x124)
-#define TCNT5H                          _SFR_MEM8(0x125)
-
-/* Timer/Counter5 Input Capture Register  Bytes */
-#define ICR5                            _SFR_MEM16(0x126)
-#define ICR5L                           _SFR_MEM8(0x126)
-#define ICR5H                           _SFR_MEM8(0x127)
-
-/* Timer/Counter5 Output Compare Register A  Bytes */
-#define OCR5A                           _SFR_MEM16(0x128)
-#define OCR5AL                          _SFR_MEM8(0x128)
-#define OCR5AH                          _SFR_MEM8(0x129)
-
-/* Timer/Counter5 Output Compare Register B  Bytes */
-#define OCR5B                           _SFR_MEM16(0x12A)
-#define OCR5BL                          _SFR_MEM8(0x12A)
-#define OCR5BH                          _SFR_MEM8(0x12B)
-
-/* Timer/Counter5 Output Compare Register C  Bytes */
-#define OCR5C                           _SFR_MEM16(0x12C)
-#define OCR5CL                          _SFR_MEM8(0x12C)
-#define OCR5CH                          _SFR_MEM8(0x12D)
-
-/* Low Leakage Voltage Regulator Control Register */
-#define LLCR                            _SFR_MEM8(0x12F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLCR {
-        unsigned int llencal : 1;	/* Enable Automatic Calibration */
-        unsigned int llshort : 1;	/* Short Lower Calibration Circuit */
-        unsigned int lltco : 1;	/* Temperature Coefficient of Current Source */
-        unsigned int llcal : 1;	/* Calibration Active */
-        unsigned int llcomp : 1;	/* Comparator Output */
-        unsigned int lldone : 1;	/* Calibration Done */
-        unsigned int : 2;
-};
-
-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLCR */
-
-#define LLENCAL                         0
-#define LLSHORT                         1
-#define LLTCO                           2
-#define LLCAL                           3
-#define LLCOMP                          4
-#define LLDONE                          5
-
-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */
-#define LLDRL                           _SFR_MEM8(0x130)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRL {
-        unsigned int lldrl : 4;	/* Low-Byte Data Register Bits */
-        unsigned int : 4;
-};
-
-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRL */
-
-#define LLDRL0                          0
-#define LLDRL1                          1
-#define LLDRL2                          2
-#define LLDRL3                          3
-
-/* Low Leakage Voltage Regulator Data Register (High-Byte) */
-#define LLDRH                           _SFR_MEM8(0x131)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_LLDRH {
-        unsigned int lldrh : 5;	/* High-Byte Data Register Bits */
-        unsigned int : 3;
-};
-
-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* LLDRH */
-
-#define LLDRH0                          0
-#define LLDRH1                          1
-#define LLDRH2                          2
-#define LLDRH3                          3
-#define LLDRH4                          4
-
-/* Data Retention Configuration Register of SRAM 3 */
-#define DRTRAM3                         _SFR_MEM8(0x132)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM3 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM3 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 2 */
-#define DRTRAM2                         _SFR_MEM8(0x133)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM2 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM2 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 1 */
-#define DRTRAM1                         _SFR_MEM8(0x134)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM1 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM1 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Data Retention Configuration Register of SRAM 0 */
-#define DRTRAM0                         _SFR_MEM8(0x135)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DRTRAM0 {
-        unsigned int : 4;
-        unsigned int endrt : 1;	/* Enable SRAM Data Retention */
-        unsigned int drtswok : 1;	/* DRT Switch OK */
-        unsigned int : 2;
-};
-
-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DRTRAM0 */
-
-#define ENDRT                           4
-#define DRTSWOK                         5
-
-/* Port Driver Strength Register 0 */
-#define DPDS0                           _SFR_MEM8(0x136)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS0 {
-        unsigned int pbdrv : 2;	/* Driver Strength Port B */
-        unsigned int pddrv : 2;	/* Driver Strength Port D */
-        unsigned int pedrv : 2;	/* Driver Strength Port E */
-        unsigned int pfdrv : 2;	/* Driver Strength Port F */
-};
-
-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS0 */
-
-#define PBDRV0                          0
-#define PBDRV1                          1
-#define PDDRV0                          2
-#define PDDRV1                          3
-#define PEDRV0                          4
-#define PEDRV1                          5
-#define PFDRV0                          6
-#define PFDRV1                          7
-
-/* Port Driver Strength Register 1 */
-#define DPDS1                           _SFR_MEM8(0x137)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_DPDS1 {
-        unsigned int pgdrv : 2;	/* Driver Strength Port G */
-        unsigned int : 6;
-};
-
-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* DPDS1 */
-
-#define PGDRV0                          0
-#define PGDRV1                          1
-
-/* Transceiver Pin Register */
-#define TRXPR                           _SFR_MEM8(0x139)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRXPR {
-        unsigned int trxrst : 1;	/* Force Transceiver Reset */
-        unsigned int slptr : 1;	/* Multi-purpose Transceiver Control Bit */
-        unsigned int : 6;
-};
-
-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRXPR */
-
-#define TRXRST                          0
-#define SLPTR                           1
-
-/* AES Control Register */
-#define AES_CTRL                        _SFR_MEM8(0x13C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_CTRL {
-        unsigned int : 2;
-        unsigned int aes_im : 1;	/* AES Interrupt Enable */
-        unsigned int aes_dir : 1;	/* Set AES Operation Direction */
-        unsigned int : 1;
-        unsigned int aes_mode : 1;	/* Set AES Operation Mode */
-        unsigned int : 1;
-        unsigned int aes_request : 1;	/* Request AES Operation. */
-};
-
-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL)
-
-/* symbolic names */
-
-#define AES_DIR_ENC                     0
-#define AES_DIR_DEC                     1
-#define AES_MODE_ECB                    0
-#define AES_MODE_CBC                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_CTRL */
-
-#define AES_IM                          2
-#define AES_DIR                         3
-#define AES_MODE                        5
-#define AES_REQUEST                     7
-
-/* AES Status Register */
-#define AES_STATUS                      _SFR_MEM8(0x13D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATUS {
-        unsigned int aes_done : 1;	/* AES Operation Finished with Success */
-        unsigned int : 6;
-        unsigned int aes_er : 1;	/* AES Operation Finished with Error */
-};
-
-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATUS */
-
-#define AES_DONE                        0
-#define AES_ER                          7
-
-/* AES Plain and Cipher Text Buffer Register */
-#define AES_STATE                       _SFR_MEM8(0x13E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_STATE {
-        unsigned int aes_state : 8;	/* AES Plain and Cipher Text Buffer */
-};
-
-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_STATE */
-
-#define AES_STATE0                      0
-#define AES_STATE1                      1
-#define AES_STATE2                      2
-#define AES_STATE3                      3
-#define AES_STATE4                      4
-#define AES_STATE5                      5
-#define AES_STATE6                      6
-#define AES_STATE7                      7
-
-/* AES Encryption and Decryption Key Buffer Register */
-#define AES_KEY                         _SFR_MEM8(0x13F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_AES_KEY {
-        unsigned int aes_key : 8;	/* AES Encryption/Decryption Key Buffer */
-};
-
-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY)
-
-#endif /* __ASSEMBLER__ */
-
-  /* AES_KEY */
-
-#define AES_KEY0                        0
-#define AES_KEY1                        1
-#define AES_KEY2                        2
-#define AES_KEY3                        3
-#define AES_KEY4                        4
-#define AES_KEY5                        5
-#define AES_KEY6                        6
-#define AES_KEY7                        7
-
-/* Transceiver Status Register */
-#define TRX_STATUS                      _SFR_MEM8(0x141)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATUS {
-        unsigned int trx_status : 5;	/* Transceiver Main Status */
-        unsigned int tst_status : 1;	/* Test mode status */
-        unsigned int cca_status : 1;	/* CCA Status Result */
-        unsigned int cca_done : 1;	/* CCA Algorithm Status */
-};
-
-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS)
-
-/* symbolic names */
-
-#define P_ON                            0
-#define BUSY_RX                         1
-#define BUSY_TX                         2
-#define RX_ON                           6
-#define TRX_OFF                         8
-#define PLL_ON                          9
-#define SLEEP                           15
-#define BUSY_RX_AACK                    17
-#define BUSY_TX_ARET                    18
-#define RX_AACK_ON                      22
-#define TX_ARET_ON                      25
-#define STATE_TRANSITION_IN_PROGRESS    31
-#define TST_DISABLED                    0
-#define TST_ENABLED                     1
-#define CCA_BUSY                        0
-#define CCA_IDLE                        1
-#define CCA_NOT_FIN                     0
-#define CCA_FIN                         1
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATUS */
-
-#define TRX_STATUS0                     0
-#define TRX_STATUS1                     1
-#define TRX_STATUS2                     2
-#define TRX_STATUS3                     3
-#define TRX_STATUS4                     4
-#define TST_STATUS                      5
-#define CCA_STATUS                      6
-#define CCA_DONE                        7
-
-/* Transceiver State Control Register */
-#define TRX_STATE                       _SFR_MEM8(0x142)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_STATE {
-        unsigned int trx_cmd : 5;	/* State Control Command */
-        unsigned int trac_status : 3;	/* Transaction Status */
-};
-
-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE)
-
-/* symbolic names */
-
-#define CMD_NOP                         0
-#define CMD_TX_START                    2
-#define CMD_FORCE_TRX_OFF               3
-#define CMD_FORCE_PLL_ON                4
-#define CMD_RX_ON                       6
-#define CMD_TRX_OFF                     8
-#define CMD_PLL_ON                      9
-#define CMD_RX_AACK_ON                  22
-#define CMD_TX_ARET_ON                  25
-#define TRAC_SUCCESS                    0
-#define TRAC_SUCCESS_DATA_PENDING       1
-#define TRAC_SUCCESS_WAIT_FOR_ACK       2
-#define TRAC_CHANNEL_ACCESS_FAILURE     3
-#define TRAC_NO_ACK                     5
-#define TRAC_INVALID                    7
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_STATE */
-
-#define TRX_CMD0                        0
-#define TRX_CMD1                        1
-#define TRX_CMD2                        2
-#define TRX_CMD3                        3
-#define TRX_CMD4                        4
-#define TRAC_STATUS0                    5
-#define TRAC_STATUS1                    6
-#define TRAC_STATUS2                    7
-
-/* Reserved */
-#define TRX_CTRL_0                      _SFR_MEM8(0x143)
-
-/* Transceiver Control Register 1 */
-#define TRX_CTRL_1                      _SFR_MEM8(0x144)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_1 {
-        unsigned int : 5;
-        unsigned int tx_auto_crc_on : 1;	/* Enable Automatic CRC Calculation */
-        unsigned int irq_2_ext_en : 1;	/* Connect Frame Start IRQ to TC1 */
-        unsigned int pa_ext_en : 1;	/* External PA support enable */
-};
-
-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_1 */
-
-#define TX_AUTO_CRC_ON                  5
-#define IRQ_2_EXT_EN                    6
-#define PA_EXT_EN                       7
-
-/* Transceiver Transmit Power Control Register */
-#define PHY_TX_PWR                      _SFR_MEM8(0x145)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_TX_PWR {
-        unsigned int tx_pwr : 4;	/* Transmit Power Setting */
-        unsigned int pa_lt : 2;	/* Power Amplifier Lead Time */
-        unsigned int pa_buf_lt : 2;	/* Power Amplifier Buffer Lead Time */
-};
-
-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR)
-
-/* symbolic names */
-
-#define PA_LT_2US                       0
-#define PA_LT_4US                       1
-#define PA_LT_6US                       2
-#define PA_LT_8US                       3
-#define PA_BUF_LT_0US                   0
-#define PA_BUF_LT_2US                   1
-#define PA_BUF_LT_4US                   2
-#define PA_BUF_LT_6US                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_TX_PWR */
-
-#define TX_PWR0                         0
-#define TX_PWR1                         1
-#define TX_PWR2                         2
-#define TX_PWR3                         3
-#define PA_LT0                          4
-#define PA_LT1                          5
-#define PA_BUF_LT0                      6
-#define PA_BUF_LT1                      7
-
-/* Receiver Signal Strength Indicator Register */
-#define PHY_RSSI                        _SFR_MEM8(0x146)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_RSSI {
-        unsigned int rssi : 5;	/* Receiver Signal Strength Indicator */
-        unsigned int rnd_value : 2;	/* Random Value */
-        unsigned int rx_crc_valid : 1;	/* Received Frame CRC Status */
-};
-
-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI)
-
-/* symbolic names */
-
-#define RSSI_MIN                        0
-#define RSSI_MIN_PLUS_3dB               1
-#define RSSI_MAX                        28
-#define CRC_INVALID                     0
-#define CRC_VALID                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_RSSI */
-
-#define RSSI0                           0
-#define RSSI1                           1
-#define RSSI2                           2
-#define RSSI3                           3
-#define RSSI4                           4
-#define RND_VALUE0                      5
-#define RND_VALUE1                      6
-#define RX_CRC_VALID                    7
-
-/* Transceiver Energy Detection Level Register */
-#define PHY_ED_LEVEL                    _SFR_MEM8(0x147)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_ED_LEVEL {
-        unsigned int ed_level : 8;	/* Energy Detection Level */
-};
-
-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL)
-
-/* symbolic names */
-
-#define ED_MIN                          0
-#define ED_MIN_PLUS_1dB                 1
-#define ED_MAX                          84
-#define ED_RESET                        255
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_ED_LEVEL */
-
-#define ED_LEVEL0                       0
-#define ED_LEVEL1                       1
-#define ED_LEVEL2                       2
-#define ED_LEVEL3                       3
-#define ED_LEVEL4                       4
-#define ED_LEVEL5                       5
-#define ED_LEVEL6                       6
-#define ED_LEVEL7                       7
-
-/* Transceiver Clear Channel Assessment (CCA) Control Register */
-#define PHY_CC_CCA                      _SFR_MEM8(0x148)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PHY_CC_CCA {
-        unsigned int channel : 5;	/* RX/TX Channel Selection */
-        unsigned int cca_mode : 2;	/* Select CCA Measurement Mode */
-        unsigned int cca_request : 1;	/* Manual CCA Measurement Request */
-};
-
-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA)
-
-/* symbolic names */
-
-#define F_2405MHZ                       11
-#define F_2410MHZ                       12
-#define F_2415MHZ                       13
-#define F_2420MHZ                       14
-#define F_2425MHZ                       15
-#define F_2430MHZ                       16
-#define F_2435MHZ                       17
-#define F_2440MHZ                       18
-#define F_2445MHZ                       19
-#define F_2450MHZ                       20
-#define F_2455MHZ                       21
-#define F_2460MHZ                       22
-#define F_2465MHZ                       23
-#define F_2470MHZ                       24
-#define F_2475MHZ                       25
-#define F_2480MHZ                       26
-#define CCA_CS_OR_ED                    0
-#define CCA_ED                          1
-#define CCA_CS                          2
-#define CCA_CS_AND_ED                   3
-
-#endif /* __ASSEMBLER__ */
-
-  /* PHY_CC_CCA */
-
-#define CHANNEL0                        0
-#define CHANNEL1                        1
-#define CHANNEL2                        2
-#define CHANNEL3                        3
-#define CHANNEL4                        4
-#define CCA_MODE0                       5
-#define CCA_MODE1                       6
-#define CCA_REQUEST                     7
-
-/* Transceiver CCA Threshold Setting Register */
-#define CCA_THRES                       _SFR_MEM8(0x149)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CCA_THRES {
-        unsigned int cca_ed_thres : 4;	/* ED Threshold Level for CCA Measurement */
-        unsigned int cca_cs_thres : 4;	/* CS Threshold Level for CCA Measurement */
-};
-
-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CCA_THRES */
-
-#define CCA_ED_THRES0                   0
-#define CCA_ED_THRES1                   1
-#define CCA_ED_THRES2                   2
-#define CCA_ED_THRES3                   3
-#define CCA_CS_THRES0                   4
-#define CCA_CS_THRES1                   5
-#define CCA_CS_THRES2                   6
-#define CCA_CS_THRES3                   7
-
-/* Transceiver Receive Control Register */
-#define RX_CTRL                         _SFR_MEM8(0x14A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_CTRL {
-        unsigned int pdt_thres : 4;	/* Receiver Sensitivity Control */
-        unsigned int : 4;
-};
-
-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL)
-
-/* symbolic names */
-
-#define PDT_THRES_ANT_DIV_OFF           7
-#define PDT_THRES_ANT_DIV_ON            3
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_CTRL */
-
-#define PDT_THRES0                      0
-#define PDT_THRES1                      1
-#define PDT_THRES2                      2
-#define PDT_THRES3                      3
-
-/* Start of Frame Delimiter Value Register */
-#define SFD_VALUE                       _SFR_MEM8(0x14B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SFD_VALUE {
-        unsigned int sfd_value : 8;	/* Start of Frame Delimiter Value */
-};
-
-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE)
-
-/* symbolic names */
-
-#define IEEE_SFD                        167
-
-#endif /* __ASSEMBLER__ */
-
-  /* SFD_VALUE */
-
-#define SFD_VALUE0                      0
-#define SFD_VALUE1                      1
-#define SFD_VALUE2                      2
-#define SFD_VALUE3                      3
-#define SFD_VALUE4                      4
-#define SFD_VALUE5                      5
-#define SFD_VALUE6                      6
-#define SFD_VALUE7                      7
-
-/* Transceiver Control Register 2 */
-#define TRX_CTRL_2                      _SFR_MEM8(0x14C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TRX_CTRL_2 {
-        unsigned int oqpsk_data_rate : 2;	/* Data Rate Selection */
-        unsigned int : 5;
-        unsigned int rx_safe_mode : 1;	/* RX Safe Mode */
-};
-
-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2)
-
-/* symbolic names */
-
-#define RATE_250KB                      0
-#define RATE_500KB                      1
-#define RATE_1000KB                     2
-#define RATE_2000KB                     3
-
-#endif /* __ASSEMBLER__ */
-
-  /* TRX_CTRL_2 */
-
-#define OQPSK_DATA_RATE0                0
-#define OQPSK_DATA_RATE1                1
-#define RX_SAFE_MODE                    7
-
-/* Antenna Diversity Control Register */
-#define ANT_DIV                         _SFR_MEM8(0x14D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_ANT_DIV {
-        unsigned int ant_ctrl : 2;	/* Static Antenna Diversity Switch Control */
-        unsigned int ant_ext_sw_en : 1;	/* Enable External Antenna Switch Control */
-        unsigned int ant_div_en : 1;	/* Enable Antenna Diversity */
-        unsigned int : 3;
-        unsigned int ant_sel : 1;	/* Antenna Diversity Antenna Status */
-};
-
-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV)
-
-/* symbolic names */
-
-#define ANT_1                           1
-#define ANT_0                           2
-#define ANT_RESET                       3
-#define ANT_DIV_EXT_SW_DIS              0
-#define ANT_DIV_EXT_SW_EN               1
-#define ANTENNA_0                       0
-#define ANTENNA_1                       1
-
-#endif /* __ASSEMBLER__ */
-
-  /* ANT_DIV */
-
-#define ANT_CTRL0                       0
-#define ANT_CTRL1                       1
-#define ANT_EXT_SW_EN                   2
-#define ANT_DIV_EN                      3
-#define ANT_SEL                         7
-
-/* Transceiver Interrupt Enable Register */
-#define IRQ_MASK                        _SFR_MEM8(0x14E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_MASK {
-        unsigned int pll_lock_en : 1;	/* PLL Lock Interrupt Enable */
-        unsigned int pll_unlock_en : 1;	/* PLL Unlock Interrupt Enable */
-        unsigned int rx_start_en : 1;	/* RX_START Interrupt Enable */
-        unsigned int rx_end_en : 1;	/* RX_END Interrupt Enable */
-        unsigned int cca_ed_done_en : 1;	/* End of ED Measurement Interrupt Enable */
-        unsigned int ami_en : 1;	/* Address Match Interrupt Enable */
-        unsigned int tx_end_en : 1;	/* TX_END Interrupt Enable */
-        unsigned int awake_en : 1;	/* Awake Interrupt Enable */
-};
-
-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_MASK */
-
-#define PLL_LOCK_EN                     0
-#define PLL_UNLOCK_EN                   1
-#define RX_START_EN                     2
-#define RX_END_EN                       3
-#define CCA_ED_DONE_EN                  4
-#define AMI_EN                          5
-#define TX_END_EN                       6
-#define AWAKE_EN                        7
-
-/* Transceiver Interrupt Status Register */
-#define IRQ_STATUS                      _SFR_MEM8(0x14F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IRQ_STATUS {
-        unsigned int pll_lock : 1;	/* PLL Lock Interrupt Status */
-        unsigned int pll_unlock : 1;	/* PLL Unlock Interrupt Status */
-        unsigned int rx_start : 1;	/* RX_START Interrupt Status */
-        unsigned int rx_end : 1;	/* RX_END Interrupt Status */
-        unsigned int cca_ed_done : 1;	/* End of ED Measurement Interrupt Status */
-        unsigned int ami : 1;	/* Address Match Interrupt Status */
-        unsigned int tx_end : 1;	/* TX_END Interrupt Status */
-        unsigned int awake : 1;	/* Awake Interrupt Status */
-};
-
-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IRQ_STATUS */
-
-#define PLL_LOCK                        0
-#define PLL_UNLOCK                      1
-#define RX_START                        2
-#define RX_END                          3
-#define CCA_ED_DONE                     4
-#define AMI                             5
-#define TX_END                          6
-#define AWAKE                           7
-
-/* Voltage Regulator Control and Status Register */
-#define VREG_CTRL                       _SFR_MEM8(0x150)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VREG_CTRL {
-        unsigned int : 2;
-        unsigned int dvdd_ok : 1;	/* DVDD Supply Voltage Valid */
-        unsigned int dvreg_ext : 1;	/* Use External DVDD Regulator */
-        unsigned int : 2;
-        unsigned int avdd_ok : 1;	/* AVDD Supply Voltage Valid */
-        unsigned int avreg_ext : 1;	/* Use External AVDD Regulator */
-};
-
-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL)
-
-/* symbolic names */
-
-#define DVDD_INT                        0
-#define DVDD_EXT                        1
-#define AVDD_INT                        0
-#define AVDD_EXT                        1
-
-#endif /* __ASSEMBLER__ */
-
-  /* VREG_CTRL */
-
-#define DVDD_OK                         2
-#define DVREG_EXT                       3
-#define AVDD_OK                         6
-#define AVREG_EXT                       7
-
-/* Battery Monitor Control and Status Register */
-#define BATMON                          _SFR_MEM8(0x151)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_BATMON {
-        unsigned int batmon_vth : 4;	/* Battery Monitor Threshold Voltage */
-        unsigned int batmon_hr : 1;	/* Battery Monitor Voltage Range */
-        unsigned int batmon_ok : 1;	/* Battery Monitor Status */
-        unsigned int bat_low_en : 1;	/* Battery Monitor Interrupt Enable */
-        unsigned int bat_low : 1;	/* Battery Monitor Interrupt Status */
-};
-
-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON)
-
-/* symbolic names */
-
-#define BATMON_HR_DIS                   0
-#define BATMON_HR_EN                    1
-
-#endif /* __ASSEMBLER__ */
-
-  /* BATMON */
-
-#define BATMON_VTH0                     0
-#define BATMON_VTH1                     1
-#define BATMON_VTH2                     2
-#define BATMON_VTH3                     3
-#define BATMON_HR                       4
-#define BATMON_OK                       5
-#define BAT_LOW_EN                      6
-#define BAT_LOW                         7
-
-/* Crystal Oscillator Control Register */
-#define XOSC_CTRL                       _SFR_MEM8(0x152)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XOSC_CTRL {
-        unsigned int xtal_trim : 4;	/* Crystal Oscillator Load Capacitance Trimming */
-        unsigned int xtal_mode : 4;	/* Crystal Oscillator Operating Mode */
-};
-
-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL)
-
-/* symbolic names */
-
-#define XTAL_TRIM_MIN                   0
-#define XTAL_TRIM_MAX                   15
-
-#endif /* __ASSEMBLER__ */
-
-  /* XOSC_CTRL */
-
-#define XTAL_TRIM0                      0
-#define XTAL_TRIM1                      1
-#define XTAL_TRIM2                      2
-#define XTAL_TRIM3                      3
-#define XTAL_MODE0                      4
-#define XTAL_MODE1                      5
-#define XTAL_MODE2                      6
-#define XTAL_MODE3                      7
-
-/* Transceiver Receiver Sensitivity Control Register */
-#define RX_SYN                          _SFR_MEM8(0x155)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_RX_SYN {
-        unsigned int rx_pdt_level : 4;	/* Reduce Receiver Sensitivity */
-        unsigned int : 3;
-        unsigned int rx_pdt_dis : 1;	/* Prevent Frame Reception */
-};
-
-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN)
-
-/* symbolic names */
-
-#define RX_PDT_LEVEL_MIN                0
-#define RX_PDT_LEVEL_MAX                15
-
-#endif /* __ASSEMBLER__ */
-
-  /* RX_SYN */
-
-#define RX_PDT_LEVEL0                   0
-#define RX_PDT_LEVEL1                   1
-#define RX_PDT_LEVEL2                   2
-#define RX_PDT_LEVEL3                   3
-#define RX_PDT_DIS                      7
-
-/* Transceiver Acknowledgment Frame Control Register 1 */
-#define XAH_CTRL_1                      _SFR_MEM8(0x157)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_1 {
-        unsigned int : 1;
-        unsigned int aack_prom_mode : 1;	/* Enable Promiscuous Mode */
-        unsigned int aack_ack_time : 1;	/* Reduce Acknowledgment Time */
-        unsigned int : 1;
-        unsigned int aack_upld_res_ft : 1;	/* Process Reserved Frames */
-        unsigned int aack_fltr_res_ft : 1;	/* Filter Reserved Frames */
-        unsigned int : 2;
-};
-
-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1)
-
-/* symbolic names */
-
-#define AACK_ACK_TIME_12_SYM            0
-#define AACK_ACK_TIME_2_SYM             1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_1 */
-
-#define AACK_PROM_MODE                  1
-#define AACK_ACK_TIME                   2
-#define AACK_UPLD_RES_FT                4
-#define AACK_FLTR_RES_FT                5
-
-/* Transceiver Filter Tuning Control Register */
-#define FTN_CTRL                        _SFR_MEM8(0x158)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_FTN_CTRL {
-        unsigned int : 7;
-        unsigned int ftn_start : 1;	/* Start Calibration Loop of Filter Tuning Network */
-};
-
-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL)
-
-#endif /* __ASSEMBLER__ */
-
-  /* FTN_CTRL */
-
-#define FTN_START                       7
-
-/* Transceiver Center Frequency Calibration Control Register */
-#define PLL_CF                          _SFR_MEM8(0x15A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_CF {
-        unsigned int : 7;
-        unsigned int pll_cf_start : 1;	/* Start Center Frequency Calibration */
-};
-
-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_CF */
-
-#define PLL_CF_START                    7
-
-/* Transceiver Delay Cell Calibration Control Register */
-#define PLL_DCU                         _SFR_MEM8(0x15B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PLL_DCU {
-        unsigned int : 7;
-        unsigned int pll_dcu_start : 1;	/* Start Delay Cell Calibration */
-};
-
-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PLL_DCU */
-
-#define PLL_DCU_START                   7
-
-/* Device Identification Register (Part Number) */
-#define PART_NUM                        _SFR_MEM8(0x15C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PART_NUM {
-        unsigned int part_num : 8;	/* Part Number */
-};
-
-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM)
-
-/* symbolic names */
-
-#define P_ATmega128RFA1                 131
-
-#endif /* __ASSEMBLER__ */
-
-  /* PART_NUM */
-
-#define PART_NUM0                       0
-#define PART_NUM1                       1
-#define PART_NUM2                       2
-#define PART_NUM3                       3
-#define PART_NUM4                       4
-#define PART_NUM5                       5
-#define PART_NUM6                       6
-#define PART_NUM7                       7
-
-/* Device Identification Register (Version Number) */
-#define VERSION_NUM                     _SFR_MEM8(0x15D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_VERSION_NUM {
-        unsigned int version_num : 8;	/* Version Number */
-};
-
-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM)
-
-/* symbolic names */
-
-#define REV_A                           2
-#define REV_B                           3
-
-#endif /* __ASSEMBLER__ */
-
-  /* VERSION_NUM */
-
-#define VERSION_NUM0                    0
-#define VERSION_NUM1                    1
-#define VERSION_NUM2                    2
-#define VERSION_NUM3                    3
-#define VERSION_NUM4                    4
-#define VERSION_NUM5                    5
-#define VERSION_NUM6                    6
-#define VERSION_NUM7                    7
-
-/* Device Identification Register (Manufacture ID Low Byte) */
-#define MAN_ID_0                        _SFR_MEM8(0x15E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_0 {
-        unsigned int man_id_0 : 8;	/* Manufacturer ID (Low Byte) */
-};
-
-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_0                    31
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_0 */
-
-#define MAN_ID_00                       0
-#define MAN_ID_01                       1
-#define MAN_ID_02                       2
-#define MAN_ID_03                       3
-#define MAN_ID_04                       4
-#define MAN_ID_05                       5
-#define MAN_ID_06                       6
-#define MAN_ID_07                       7
-
-/* Device Identification Register (Manufacture ID High Byte) */
-#define MAN_ID_1                        _SFR_MEM8(0x15F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_MAN_ID_1 {
-        unsigned int man_id_1 : 8;	/* Manufacturer ID (High Byte) */
-};
-
-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1)
-
-/* symbolic names */
-
-#define ATMEL_BYTE_1                    0
-
-#endif /* __ASSEMBLER__ */
-
-  /* MAN_ID_1 */
-
-#define MAN_ID_10                       0
-#define MAN_ID_11                       1
-#define MAN_ID_12                       2
-#define MAN_ID_13                       3
-#define MAN_ID_14                       4
-#define MAN_ID_15                       5
-#define MAN_ID_16                       6
-#define MAN_ID_17                       7
-
-/* Transceiver MAC Short Address Register (Low Byte) */
-#define SHORT_ADDR_0                    _SFR_MEM8(0x160)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_0 {
-        unsigned int short_addr_0 : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_0 */
-
-#define SHORT_ADDR_00                   0
-#define SHORT_ADDR_01                   1
-#define SHORT_ADDR_02                   2
-#define SHORT_ADDR_03                   3
-#define SHORT_ADDR_04                   4
-#define SHORT_ADDR_05                   5
-#define SHORT_ADDR_06                   6
-#define SHORT_ADDR_07                   7
-
-/* Transceiver MAC Short Address Register (High Byte) */
-#define SHORT_ADDR_1                    _SFR_MEM8(0x161)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_SHORT_ADDR_1 {
-        unsigned int short_addr_1 : 8;	/* MAC Short Address */
-};
-
-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* SHORT_ADDR_1 */
-
-#define SHORT_ADDR_10                   0
-#define SHORT_ADDR_11                   1
-#define SHORT_ADDR_12                   2
-#define SHORT_ADDR_13                   3
-#define SHORT_ADDR_14                   4
-#define SHORT_ADDR_15                   5
-#define SHORT_ADDR_16                   6
-#define SHORT_ADDR_17                   7
-
-/* Transceiver Personal Area Network ID Register (Low Byte) */
-#define PAN_ID_0                        _SFR_MEM8(0x162)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_0 {
-        unsigned int pan_id_0 : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_0 */
-
-#define PAN_ID_00                       0
-#define PAN_ID_01                       1
-#define PAN_ID_02                       2
-#define PAN_ID_03                       3
-#define PAN_ID_04                       4
-#define PAN_ID_05                       5
-#define PAN_ID_06                       6
-#define PAN_ID_07                       7
-
-/* Transceiver Personal Area Network ID Register (High Byte) */
-#define PAN_ID_1                        _SFR_MEM8(0x163)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_PAN_ID_1 {
-        unsigned int pan_id_1 : 8;	/* MAC Personal Area Network ID */
-};
-
-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* PAN_ID_1 */
-
-#define PAN_ID_10                       0
-#define PAN_ID_11                       1
-#define PAN_ID_12                       2
-#define PAN_ID_13                       3
-#define PAN_ID_14                       4
-#define PAN_ID_15                       5
-#define PAN_ID_16                       6
-#define PAN_ID_17                       7
-
-/* Transceiver MAC IEEE Address Register 0 */
-#define IEEE_ADDR_0                     _SFR_MEM8(0x164)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_0 {
-        unsigned int ieee_addr_0 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_0 */
-
-#define IEEE_ADDR_00                    0
-#define IEEE_ADDR_01                    1
-#define IEEE_ADDR_02                    2
-#define IEEE_ADDR_03                    3
-#define IEEE_ADDR_04                    4
-#define IEEE_ADDR_05                    5
-#define IEEE_ADDR_06                    6
-#define IEEE_ADDR_07                    7
-
-/* Transceiver MAC IEEE Address Register 1 */
-#define IEEE_ADDR_1                     _SFR_MEM8(0x165)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_1 {
-        unsigned int ieee_addr_1 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_1 */
-
-#define IEEE_ADDR_10                    0
-#define IEEE_ADDR_11                    1
-#define IEEE_ADDR_12                    2
-#define IEEE_ADDR_13                    3
-#define IEEE_ADDR_14                    4
-#define IEEE_ADDR_15                    5
-#define IEEE_ADDR_16                    6
-#define IEEE_ADDR_17                    7
-
-/* Transceiver MAC IEEE Address Register 2 */
-#define IEEE_ADDR_2                     _SFR_MEM8(0x166)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_2 {
-        unsigned int ieee_addr_2 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_2 */
-
-#define IEEE_ADDR_20                    0
-#define IEEE_ADDR_21                    1
-#define IEEE_ADDR_22                    2
-#define IEEE_ADDR_23                    3
-#define IEEE_ADDR_24                    4
-#define IEEE_ADDR_25                    5
-#define IEEE_ADDR_26                    6
-#define IEEE_ADDR_27                    7
-
-/* Transceiver MAC IEEE Address Register 3 */
-#define IEEE_ADDR_3                     _SFR_MEM8(0x167)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_3 {
-        unsigned int ieee_addr_3 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_3 */
-
-#define IEEE_ADDR_30                    0
-#define IEEE_ADDR_31                    1
-#define IEEE_ADDR_32                    2
-#define IEEE_ADDR_33                    3
-#define IEEE_ADDR_34                    4
-#define IEEE_ADDR_35                    5
-#define IEEE_ADDR_36                    6
-#define IEEE_ADDR_37                    7
-
-/* Transceiver MAC IEEE Address Register 4 */
-#define IEEE_ADDR_4                     _SFR_MEM8(0x168)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_4 {
-        unsigned int ieee_addr_4 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_4 */
-
-#define IEEE_ADDR_40                    0
-#define IEEE_ADDR_41                    1
-#define IEEE_ADDR_42                    2
-#define IEEE_ADDR_43                    3
-#define IEEE_ADDR_44                    4
-#define IEEE_ADDR_45                    5
-#define IEEE_ADDR_46                    6
-#define IEEE_ADDR_47                    7
-
-/* Transceiver MAC IEEE Address Register 5 */
-#define IEEE_ADDR_5                     _SFR_MEM8(0x169)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_5 {
-        unsigned int ieee_addr_5 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_5 */
-
-#define IEEE_ADDR_50                    0
-#define IEEE_ADDR_51                    1
-#define IEEE_ADDR_52                    2
-#define IEEE_ADDR_53                    3
-#define IEEE_ADDR_54                    4
-#define IEEE_ADDR_55                    5
-#define IEEE_ADDR_56                    6
-#define IEEE_ADDR_57                    7
-
-/* Transceiver MAC IEEE Address Register 6 */
-#define IEEE_ADDR_6                     _SFR_MEM8(0x16A)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_6 {
-        unsigned int ieee_addr_6 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_6 */
-
-#define IEEE_ADDR_60                    0
-#define IEEE_ADDR_61                    1
-#define IEEE_ADDR_62                    2
-#define IEEE_ADDR_63                    3
-#define IEEE_ADDR_64                    4
-#define IEEE_ADDR_65                    5
-#define IEEE_ADDR_66                    6
-#define IEEE_ADDR_67                    7
-
-/* Transceiver MAC IEEE Address Register 7 */
-#define IEEE_ADDR_7                     _SFR_MEM8(0x16B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_IEEE_ADDR_7 {
-        unsigned int ieee_addr_7 : 8;	/* MAC IEEE Address */
-};
-
-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7)
-
-#endif /* __ASSEMBLER__ */
-
-  /* IEEE_ADDR_7 */
-
-#define IEEE_ADDR_70                    0
-#define IEEE_ADDR_71                    1
-#define IEEE_ADDR_72                    2
-#define IEEE_ADDR_73                    3
-#define IEEE_ADDR_74                    4
-#define IEEE_ADDR_75                    5
-#define IEEE_ADDR_76                    6
-#define IEEE_ADDR_77                    7
-
-/* Transceiver Extended Operating Mode Control Register */
-#define XAH_CTRL_0                      _SFR_MEM8(0x16C)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_XAH_CTRL_0 {
-        unsigned int slotted_operation : 1;	/* Set Slotted Acknowledgment */
-        unsigned int max_csma_retries : 3;	/* Maximum Number of CSMA-CA Procedure Repetition Attempts */
-        unsigned int max_frame_retries : 4;	/* Maximum Number of Frame Re-transmission Attempts */
-};
-
-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0)
-
-/* symbolic names */
-
-#define SLOTTED_OP_DIS                  0
-#define SLOTTED_OP_EN                   1
-
-#endif /* __ASSEMBLER__ */
-
-  /* XAH_CTRL_0 */
-
-#define SLOTTED_OPERATION               0
-#define MAX_CSMA_RETRIES0               1
-#define MAX_CSMA_RETRIES1               2
-#define MAX_CSMA_RETRIES2               3
-#define MAX_FRAME_RETRIES0              4
-#define MAX_FRAME_RETRIES1              5
-#define MAX_FRAME_RETRIES2              6
-#define MAX_FRAME_RETRIES3              7
-
-/* Transceiver CSMA-CA Random Number Generator Seed Register */
-#define CSMA_SEED_0                     _SFR_MEM8(0x16D)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_0 {
-        unsigned int csma_seed_0 : 8;	/* Seed Value for CSMA Random Number Generator */
-};
-
-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_0 */
-
-#define CSMA_SEED_00                    0
-#define CSMA_SEED_01                    1
-#define CSMA_SEED_02                    2
-#define CSMA_SEED_03                    3
-#define CSMA_SEED_04                    4
-#define CSMA_SEED_05                    5
-#define CSMA_SEED_06                    6
-#define CSMA_SEED_07                    7
-
-/* Transceiver Acknowledgment Frame Control Register 2 */
-#define CSMA_SEED_1                     _SFR_MEM8(0x16E)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_SEED_1 {
-        unsigned int csma_seed_1 : 3;	/* Seed Value for CSMA Random Number Generator */
-        unsigned int aack_i_am_coord : 1;	/* Set Personal Area Network Coordinator */
-        unsigned int aack_dis_ack : 1;	/* Disable Acknowledgment Frame Transmission */
-        unsigned int aack_set_pd : 1;	/* Set Frame Pending Sub-field */
-        unsigned int aack_fvn_mode : 2;	/* Acknowledgment Frame Filter Mode */
-};
-
-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_SEED_1 */
-
-#define CSMA_SEED_10                    0
-#define CSMA_SEED_11                    1
-#define CSMA_SEED_12                    2
-#define AACK_I_AM_COORD                 3
-#define AACK_DIS_ACK                    4
-#define AACK_SET_PD                     5
-#define AACK_FVN_MODE0                  6
-#define AACK_FVN_MODE1                  7
-
-/* Transceiver CSMA-CA Back-off Exponent Control Register */
-#define CSMA_BE                         _SFR_MEM8(0x16F)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_CSMA_BE {
-        unsigned int min_be : 4;	/* Minimum Back-off Exponent */
-        unsigned int max_be : 4;	/* Maximum Back-off Exponent */
-};
-
-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE)
-
-#endif /* __ASSEMBLER__ */
-
-  /* CSMA_BE */
-
-#define MIN_BE0                         0
-#define MIN_BE1                         1
-#define MIN_BE2                         2
-#define MIN_BE3                         3
-#define MAX_BE0                         4
-#define MAX_BE1                         5
-#define MAX_BE2                         6
-#define MAX_BE3                         7
-
-/* Transceiver Digital Test Control Register */
-#define TST_CTRL_DIGI                   _SFR_MEM8(0x176)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_CTRL_DIGI {
-        unsigned int tst_ctrl_dig : 4;	/* Digital Test Controller Register */
-        unsigned int : 4;
-};
-
-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_CTRL_DIGI */
-
-#define TST_CTRL_DIG0                   0
-#define TST_CTRL_DIG1                   1
-#define TST_CTRL_DIG2                   2
-#define TST_CTRL_DIG3                   3
-
-/* Transceiver Received Frame Length Register */
-#define TST_RX_LENGTH                   _SFR_MEM8(0x17B)
-
-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__))
-
-struct __reg_TST_RX_LENGTH {
-        unsigned int rx_length : 8;	/* Received Frame Length */
-};
-
-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH)
-
-#endif /* __ASSEMBLER__ */
-
-  /* TST_RX_LENGTH */
-
-#define RX_LENGTH0                      0
-#define RX_LENGTH1                      1
-#define RX_LENGTH2                      2
-#define RX_LENGTH3                      3
-#define RX_LENGTH4                      4
-#define RX_LENGTH5                      5
-#define RX_LENGTH6                      6
-#define RX_LENGTH7                      7
-
-/* Start of frame buffer */
-#define TRXFBST                         _SFR_MEM8(0x180)
-
-  /* TRXFBST */
-
-#define TRXFBST0                        0
-#define TRXFBST1                        1
-#define TRXFBST2                        2
-#define TRXFBST3                        3
-#define TRXFBST4                        4
-#define TRXFBST5                        5
-#define TRXFBST6                        6
-#define TRXFBST7                        7
-
-/* End of frame buffer */
-#define TRXFBEND                        _SFR_MEM8(0x1FF)
-
-  /* TRXFBEND */
-
-#define TRXFBEND0                       0
-#define TRXFBEND1                       1
-#define TRXFBEND2                       2
-#define TRXFBEND3                       3
-#define TRXFBEND4                       4
-#define TRXFBEND5                       5
-#define TRXFBEND6                       6
-#define TRXFBEND7                       7
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-
-#define _VECTORS_SIZE                  288
-
-/* External Interrupt Request 0 */
-#define INT0_vect                       _VECTOR(1)
-#define INT0_vect_num                   1
-
-/* External Interrupt Request 1 */
-#define INT1_vect                       _VECTOR(2)
-#define INT1_vect_num                   2
-
-/* External Interrupt Request 2 */
-#define INT2_vect                       _VECTOR(3)
-#define INT2_vect_num                   3
-
-/* External Interrupt Request 3 */
-#define INT3_vect                       _VECTOR(4)
-#define INT3_vect_num                   4
-
-/* External Interrupt Request 4 */
-#define INT4_vect                       _VECTOR(5)
-#define INT4_vect_num                   5
-
-/* External Interrupt Request 5 */
-#define INT5_vect                       _VECTOR(6)
-#define INT5_vect_num                   6
-
-/* External Interrupt Request 6 */
-#define INT6_vect                       _VECTOR(7)
-#define INT6_vect_num                   7
-
-/* External Interrupt Request 7 */
-#define INT7_vect                       _VECTOR(8)
-#define INT7_vect_num                   8
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect                     _VECTOR(9)
-#define PCINT0_vect_num                 9
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect                     _VECTOR(10)
-#define PCINT1_vect_num                 10
-
-/* Pin Change Interrupt Request 2 */
-#define PCINT2_vect                     _VECTOR(11)
-#define PCINT2_vect_num                 11
-
-/* Watchdog Time-out Interrupt */
-#define WDT_vect                        _VECTOR(12)
-#define WDT_vect_num                    12
-
-/* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPA_vect               _VECTOR(13)
-#define TIMER2_COMPA_vect_num           13
-
-/* Timer/Counter2 Compare Match B */
-#define TIMER2_COMPB_vect               _VECTOR(14)
-#define TIMER2_COMPB_vect_num           14
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect                 _VECTOR(15)
-#define TIMER2_OVF_vect_num             15
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect                _VECTOR(16)
-#define TIMER1_CAPT_vect_num            16
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect               _VECTOR(17)
-#define TIMER1_COMPA_vect_num           17
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect               _VECTOR(18)
-#define TIMER1_COMPB_vect_num           18
-
-/* Timer/Counter1 Compare Match C */
-#define TIMER1_COMPC_vect               _VECTOR(19)
-#define TIMER1_COMPC_vect_num           19
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect                 _VECTOR(20)
-#define TIMER1_OVF_vect_num             20
-
-/* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPA_vect               _VECTOR(21)
-#define TIMER0_COMPA_vect_num           21
-
-/* Timer/Counter0 Compare Match B */
-#define TIMER0_COMPB_vect               _VECTOR(22)
-#define TIMER0_COMPB_vect_num           22
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect                 _VECTOR(23)
-#define TIMER0_OVF_vect_num             23
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect                    _VECTOR(24)
-#define SPI_STC_vect_num                24
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect                  _VECTOR(25)
-#define USART0_RX_vect_num              25
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect                _VECTOR(26)
-#define USART0_UDRE_vect_num            26
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect                  _VECTOR(27)
-#define USART0_TX_vect_num              27
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect                _VECTOR(28)
-#define ANALOG_COMP_vect_num            28
-
-/* ADC Conversion Complete */
-#define ADC_vect                        _VECTOR(29)
-#define ADC_vect_num                    29
-
-/* EEPROM Ready */
-#define EE_READY_vect                   _VECTOR(30)
-#define EE_READY_vect_num               30
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect                _VECTOR(31)
-#define TIMER3_CAPT_vect_num            31
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect               _VECTOR(32)
-#define TIMER3_COMPA_vect_num           32
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect               _VECTOR(33)
-#define TIMER3_COMPB_vect_num           33
-
-/* Timer/Counter3 Compare Match C */
-#define TIMER3_COMPC_vect               _VECTOR(34)
-#define TIMER3_COMPC_vect_num           34
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect                 _VECTOR(35)
-#define TIMER3_OVF_vect_num             35
-
-/* USART1, Rx Complete */
-#define USART1_RX_vect                  _VECTOR(36)
-#define USART1_RX_vect_num              36
-
-/* USART1 Data register Empty */
-#define USART1_UDRE_vect                _VECTOR(37)
-#define USART1_UDRE_vect_num            37
-
-/* USART1, Tx Complete */
-#define USART1_TX_vect                  _VECTOR(38)
-#define USART1_TX_vect_num              38
-
-/* 2-wire Serial Interface */
-#define TWI_vect                        _VECTOR(39)
-#define TWI_vect_num                    39
-
-/* Store Program Memory Read */
-#define SPM_READY_vect                  _VECTOR(40)
-#define SPM_READY_vect_num              40
-
-/* Timer/Counter4 Capture Event */
-#define TIMER4_CAPT_vect                _VECTOR(41)
-#define TIMER4_CAPT_vect_num            41
-
-/* Timer/Counter4 Compare Match A */
-#define TIMER4_COMPA_vect               _VECTOR(42)
-#define TIMER4_COMPA_vect_num           42
-
-/* Timer/Counter4 Compare Match B */
-#define TIMER4_COMPB_vect               _VECTOR(43)
-#define TIMER4_COMPB_vect_num           43
-
-/* Timer/Counter4 Compare Match C */
-#define TIMER4_COMPC_vect               _VECTOR(44)
-#define TIMER4_COMPC_vect_num           44
-
-/* Timer/Counter4 Overflow */
-#define TIMER4_OVF_vect                 _VECTOR(45)
-#define TIMER4_OVF_vect_num             45
-
-/* Timer/Counter5 Capture Event */
-#define TIMER5_CAPT_vect                _VECTOR(46)
-#define TIMER5_CAPT_vect_num            46
-
-/* Timer/Counter5 Compare Match A */
-#define TIMER5_COMPA_vect               _VECTOR(47)
-#define TIMER5_COMPA_vect_num           47
-
-/* Timer/Counter5 Compare Match B */
-#define TIMER5_COMPB_vect               _VECTOR(48)
-#define TIMER5_COMPB_vect_num           48
-
-/* Timer/Counter5 Compare Match C */
-#define TIMER5_COMPC_vect               _VECTOR(49)
-#define TIMER5_COMPC_vect_num           49
-
-/* Timer/Counter5 Overflow */
-#define TIMER5_OVF_vect                 _VECTOR(50)
-#define TIMER5_OVF_vect_num             50
-
-/* USART2, Rx Complete */
-#define USART2_RX_vect                  _VECTOR(51)
-#define USART2_RX_vect_num              51
-
-/* USART2 Data register Empty */
-#define USART2_UDRE_vect                _VECTOR(52)
-#define USART2_UDRE_vect_num            52
-
-/* USART2, Tx Complete */
-#define USART2_TX_vect                  _VECTOR(53)
-#define USART2_TX_vect_num              53
-
-/* USART3, Rx Complete */
-#define USART3_RX_vect                  _VECTOR(54)
-#define USART3_RX_vect_num              54
-
-/* USART3 Data register Empty */
-#define USART3_UDRE_vect                _VECTOR(55)
-#define USART3_UDRE_vect_num            55
-
-/* USART3, Tx Complete */
-#define USART3_TX_vect                  _VECTOR(56)
-#define USART3_TX_vect_num              56
-
-/* TRX24 - PLL lock interrupt */
-#define TRX24_PLL_LOCK_vect             _VECTOR(57)
-#define TRX24_PLL_LOCK_vect_num         57
-
-/* TRX24 - PLL unlock interrupt */
-#define TRX24_PLL_UNLOCK_vect           _VECTOR(58)
-#define TRX24_PLL_UNLOCK_vect_num       58
-
-/* TRX24 - Receive start interrupt */
-#define TRX24_RX_START_vect             _VECTOR(59)
-#define TRX24_RX_START_vect_num         59
-
-/* TRX24 - RX_END interrupt */
-#define TRX24_RX_END_vect               _VECTOR(60)
-#define TRX24_RX_END_vect_num           60
-
-/* TRX24 - CCA/ED done interrupt */
-#define TRX24_CCA_ED_DONE_vect          _VECTOR(61)
-#define TRX24_CCA_ED_DONE_vect_num      61
-
-/* TRX24 - XAH - AMI */
-#define TRX24_XAH_AMI_vect              _VECTOR(62)
-#define TRX24_XAH_AMI_vect_num          62
-
-/* TRX24 - TX_END interrupt */
-#define TRX24_TX_END_vect               _VECTOR(63)
-#define TRX24_TX_END_vect_num           63
-
-/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */
-#define TRX24_AWAKE_vect                _VECTOR(64)
-#define TRX24_AWAKE_vect_num            64
-
-/* Symbol counter - compare match 1 interrupt */
-#define SCNT_CMP1_vect                  _VECTOR(65)
-#define SCNT_CMP1_vect_num              65
-
-/* Symbol counter - compare match 2 interrupt */
-#define SCNT_CMP2_vect                  _VECTOR(66)
-#define SCNT_CMP2_vect_num              66
-
-/* Symbol counter - compare match 3 interrupt */
-#define SCNT_CMP3_vect                  _VECTOR(67)
-#define SCNT_CMP3_vect_num              67
-
-/* Symbol counter - overflow interrupt */
-#define SCNT_OVFL_vect                  _VECTOR(68)
-#define SCNT_OVFL_vect_num              68
-
-/* Symbol counter - backoff interrupt */
-#define SCNT_BACKOFF_vect               _VECTOR(69)
-#define SCNT_BACKOFF_vect_num           69
-
-/* AES engine ready interrupt */
-#define AES_READY_vect                  _VECTOR(70)
-#define AES_READY_vect_num              70
-
-/* Battery monitor indicates supply voltage below threshold */
-#define BAT_LOW_vect                    _VECTOR(71)
-#define BAT_LOW_vect_num                71
-
-
-/* memory parameters */
-
-#define SPM_PAGESIZE                    (256)
-#define RAMSTART                        (0x200)
-#define RAMSIZE                         (0x4000)
-#define RAMEND                          (0x41FF)
-#define XRAMSTART                       (0x0000)
-#define XRAMSIZE                        (0x0000)
-#define XRAMEND                         RAMEND
-#define E2END                           (0xFFF)
-#define E2PAGESIZE                      (0x08)
-#define FLASHEND                        (0x1ffff)
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* LFUSE Byte */
-#define FUSE_CKSEL0     ~_BV(0) /* Select Clock Source */
-#define FUSE_CKSEL1     ~_BV(1) /* Select Clock Source */
-#define FUSE_CKSEL2     ~_BV(2) /* Select Clock Source */
-#define FUSE_CKSEL3     ~_BV(3) /* Select Clock Source */
-#define FUSE_SUT0       ~_BV(4) /* Select start-up time */
-#define FUSE_SUT1       ~_BV(5) /* Select start-up time */
-#define FUSE_CKOUT      ~_BV(6) /* Clock output */
-#define FUSE_CKDIV8     ~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* HFUSE Byte */
-#define FUSE_BOOTRST    ~_BV(0) /* Select Reset Vector */
-#define FUSE_BOOTSZ0    ~_BV(1) /* Select Boot Size */
-#define FUSE_BOOTSZ1    ~_BV(2) /* Select Boot Size */
-#define FUSE_EESAVE     ~_BV(3) /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON      ~_BV(4) /* Watchdog timer always on */
-#define FUSE_SPIEN      ~_BV(5) /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN     ~_BV(6) /* Enable JTAG */
-#define FUSE_OCDEN      ~_BV(7) /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* EFUSE Byte */
-#define FUSE_BODLEVEL0  ~_BV(0) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  ~_BV(1) /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  ~_BV(2) /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-
-/* Lock Bits */
-
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-#define __LOCK_BITS_EXIST
-
-
-/* Signature */
-
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0xA7
-#define SIGNATURE_2 0x01
-
-#endif /* _AVR_IOM128RFA1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16.h b/cpukit/score/cpu/avr/avr/iom16.h
deleted file mode 100644
index 6d6e9e3..0000000
--- a/cpukit/score/cpu/avr/avr/iom16.h
+++ /dev/null
@@ -1,625 +0,0 @@
-/**
- * @file avr/iom16.h
- *
- * @brief Definitions for ATmega16
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2004 Eric B. Weddington
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM16_H_
-#define _AVR_IOM16_H_ 1
-
-/**
- *  @defgroup Avr_iom16 ATmega16 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom16.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Registers and associated bit numbers */
-
-#define TWBR    _SFR_IO8(0x00)
-
-#define TWSR    _SFR_IO8(0x01)
-#define TWPS0   0
-#define TWPS1   1
-#define TWS3    3
-#define TWS4    4
-#define TWS5    5
-#define TWS6    6
-#define TWS7    7
-
-#define TWAR    _SFR_IO8(0x02)
-#define TWGCE   0
-#define TWA0    1
-#define TWA1    2
-#define TWA2    3
-#define TWA3    4
-#define TWA4    5
-#define TWA5    6
-#define TWA6    7
-
-#define TWDR    _SFR_IO8(0x03)
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL    _SFR_IO8(0x04)
-#define ADCH    _SFR_IO8(0x05)
-
-#define ADCSRA  _SFR_IO8(0x06)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADMUX   _SFR_IO8(0x07)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-#define ACSR    _SFR_IO8(0x08)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define UBRRL   _SFR_IO8(0x09)
-
-#define UCSRB   _SFR_IO8(0x0A)
-#define TXB8    0
-#define RXB8    1
-#define UCSZ2   2
-#define TXEN    3
-#define RXEN    4
-#define UDRIE   5
-#define TXCIE   6
-#define RXCIE   7
-
-#define UCSRA   _SFR_IO8(0x0B)
-#define MPCM    0
-#define U2X     1
-#define PE      2
-#define DOR     3
-#define FE      4
-#define UDRE    5
-#define TXC     6
-#define RXC     7
-
-#define UDR     _SFR_IO8(0x0C)
-
-#define SPCR    _SFR_IO8(0x0D)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x0E)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0x0F)
-
-#define PIND    _SFR_IO8(0x10)
-#define PIND0   0
-#define PIND1   1
-#define PIND2   2
-#define PIND3   3
-#define PIND4   4
-#define PIND5   5
-#define PIND6   6
-#define PIND7   7
-
-#define DDRD    _SFR_IO8(0x11)
-#define DDD0    0
-#define DDD1    1
-#define DDD2    2
-#define DDD3    3
-#define DDD4    4
-#define DDD5    5
-#define DDD6    6
-#define DDD7    7
-
-#define PORTD   _SFR_IO8(0x12)
-#define PD0     0
-#define PD1     1
-#define PD2     2
-#define PD3     3
-#define PD4     4
-#define PD5     5
-#define PD6     6
-#define PD7     7
-
-#define PINC    _SFR_IO8(0x13)
-#define PINC0   0
-#define PINC1   1
-#define PINC2   2
-#define PINC3   3
-#define PINC4   4
-#define PINC5   5
-#define PINC6   6
-#define PINC7   7
-
-#define DDRC    _SFR_IO8(0x14)
-#define DDC0    0
-#define DDC1    1
-#define DDC2    2
-#define DDC3    3
-#define DDC4    4
-#define DDC5    5
-#define DDC6    6
-#define DDC7    7
-
-#define PORTC   _SFR_IO8(0x15)
-#define PC0     0
-#define PC1     1
-#define PC2     2
-#define PC3     3
-#define PC4     4
-#define PC5     5
-#define PC6     6
-#define PC7     7
-
-#define PINB    _SFR_IO8(0x16)
-#define PINB0   0
-#define PINB1   1
-#define PINB2   2
-#define PINB3   3
-#define PINB4   4
-#define PINB5   5
-#define PINB6   6
-#define PINB7   7
-
-#define DDRB    _SFR_IO8(0x17)
-#define DDB0    0
-#define DDB1    1
-#define DDB2    2
-#define DDB3    3
-#define DDB4    4
-#define DDB5    5
-#define DDB6    6
-#define DDB7    7
-
-#define PORTB   _SFR_IO8(0x18)
-#define PB0     0
-#define PB1     1
-#define PB2     2
-#define PB3     3
-#define PB4     4
-#define PB5     5
-#define PB6     6
-#define PB7     7
-
-#define PINA    _SFR_IO8(0x19)
-#define PINA0   0
-#define PINA1   1
-#define PINA2   2
-#define PINA3   3
-#define PINA4   4
-#define PINA5   5
-#define PINA6   6
-#define PINA7   7
-
-#define DDRA    _SFR_IO8(0x1A)
-#define DDA0    0
-#define DDA1    1
-#define DDA2    2
-#define DDA3    3
-#define DDA4    4
-#define DDA5    5
-#define DDA6    6
-#define DDA7    7
-
-#define PORTA   _SFR_IO8(0x1B)
-#define PA0     0
-#define PA1     1
-#define PA2     2
-#define PA3     3
-#define PA4     4
-#define PA5     5
-#define PA6     6
-#define PA7     7
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UCSRC   _SFR_IO8(0x20)
-#define UCPOL   0
-#define UCSZ0   1
-#define UCSZ1   2
-#define USBS    3
-#define UPM0    4
-#define UPM1    5
-#define UMSEL   6
-#define URSEL   7
-
-#define UBRRH   _SFR_IO8(0x20)
-#define URSEL   7
-
-#define WDTCR   _SFR_IO8(0x21)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDTOE   4
-
-#define ASSR    _SFR_IO8(0x22)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-
-#define OCR2    _SFR_IO8(0x23)
-
-#define TCNT2   _SFR_IO8(0x24)
-
-#define TCCR2   _SFR_IO8(0x25)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM20   4
-#define COM21   5
-#define WGM20   6
-#define FOC2    7
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_IO16(0x26)
-
-#define ICR1L   _SFR_IO8(0x26)
-#define ICR1H   _SFR_IO8(0x27)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_IO16(0x28)
-
-#define OCR1BL  _SFR_IO8(0x28)
-#define OCR1BH  _SFR_IO8(0x29)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_IO16(0x2A)
-
-#define OCR1AL  _SFR_IO8(0x2A)
-#define OCR1AH  _SFR_IO8(0x2B)
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_IO16(0x2C)
-
-#define TCNT1L  _SFR_IO8(0x2C)
-#define TCNT1H  _SFR_IO8(0x2D)
-
-#define TCCR1B  _SFR_IO8(0x2E)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1A  _SFR_IO8(0x2F)
-#define WGM10   0
-#define WGM11   1
-#define FOC1B   2
-#define FOC1A   3
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-/*
-   The ADHSM bit has been removed from all documentation,
-   as being not needed at all since the comparator has proven
-   to be fast enough even without feeding it more power.
-*/
-
-#define SFIOR   _SFR_IO8(0x30)
-#define PSR10   0
-#define PSR2    1
-#define PUD     2
-#define ACME    3
-#define ADTS0   5
-#define ADTS1   6
-#define ADTS2   7
-
-#define OSCCAL  _SFR_IO8(0x31)
-
-#define OCDR    _SFR_IO8(0x31)
-
-#define TCNT0   _SFR_IO8(0x32)
-
-#define TCCR0   _SFR_IO8(0x33)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM00   4
-#define COM01   5
-#define WGM00   6
-#define FOC0    7
-
-#define MCUCSR  _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-#define ISC2    6
-#define JTD     7
-
-#define MCUCR   _SFR_IO8(0x35)
-#define ISC00   0
-#define ISC01   1
-#define ISC10   2
-#define ISC11   3
-#define SM0     4
-#define SM1     5
-#define SE      6
-#define SM2     7
-
-#define TWCR    _SFR_IO8(0x36)
-#define TWIE    0
-#define TWEN    2
-#define TWWC    3
-#define TWSTO   4
-#define TWSTA   5
-#define TWEA    6
-#define TWINT   7
-
-#define SPMCR   _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-#define TIFR    _SFR_IO8(0x38)
-#define TOV0    0
-#define OCF0    1
-#define TOV1    2
-#define OCF1B   3
-#define OCF1A   4
-#define ICF1    5
-#define TOV2    6
-#define OCF2    7
-
-#define TIMSK   _SFR_IO8(0x39)
-#define TOIE0   0
-#define OCIE0   1
-#define TOIE1   2
-#define OCIE1B  3
-#define OCIE1A  4
-#define TICIE1  5
-#define TOIE2   6
-#define OCIE2   7
-
-#define GIFR    _SFR_IO8(0x3A)
-#define INTF2   5
-#define INTF0   6
-#define INTF1   7
-
-#define GICR    _SFR_IO8(0x3B)
-#define IVCE    0
-#define IVSEL   1
-#define INT2    5
-#define INT0    6
-#define INT1    7
-
-#define OCR0    _SFR_IO8(0x3C)
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector. */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* USART, Rx Complete */
-#define USART_RXC_vect			_VECTOR(11)
-#define SIG_USART_RECV			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* USART Data Register Empty */
-#define USART_UDRE_vect			_VECTOR(12)
-#define SIG_USART_DATA			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* USART, Tx Complete */
-#define USART_TXC_vect			_VECTOR(13)
-#define SIG_USART_TRANS			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* 2-wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(18)
-#define SIG_INTERRUPT2			_VECTOR(18)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(19)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(19)
-
-/* Store Program Memory Ready */
-#define SPM_RDY_vect			_VECTOR(20)
-#define SIG_SPM_READY			_VECTOR(20)
-
-#define _VECTORS_SIZE 84
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x45F
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_CKOPT       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x03
-
-/**@}*/
-#endif /* _AVR_IOM16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom161.h b/cpukit/score/cpu/avr/avr/iom161.h
deleted file mode 100644
index af7bebe..0000000
--- a/cpukit/score/cpu/avr/avr/iom161.h
+++ /dev/null
@@ -1,685 +0,0 @@
-/**
- * @file avr/iom161.h
- *
- * @brief Definitions for ATmega161
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2002, Marek Michalkiewicz
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM161_H_
-#define _AVR_IOM161_H_ 1
-
-/**
- *  @defgroup Avr_iom161 ATmega161 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom161.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-/* UART1 Baud Rate Register */
-#define UBRR1	_SFR_IO8(0x00)
-
-/* UART1 Control and Status Registers */
-#define UCSR1B	_SFR_IO8(0x01)
-#define UCSR1A	_SFR_IO8(0x02)
-
-/* UART1 I/O Data Register */
-#define UDR1	_SFR_IO8(0x03)
-
-/* 0x04 reserved */
-
-/* Input Pins, Port E */
-#define PINE	_SFR_IO8(0x05)
-
-/* Data Direction Register, Port E */
-#define DDRE	_SFR_IO8(0x06)
-
-/* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x07)
-
-/* Analog Comparator Control and Status Register */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART0 Baud Rate Register */
-#define UBRR0	_SFR_IO8(0x09)
-
-/* UART0 Control and Status Registers */
-#define UCSR0B	_SFR_IO8(0x0A)
-#define UCSR0A	_SFR_IO8(0x0B)
-
-/* UART0 I/O Data Register */
-#define UDR0	_SFR_IO8(0x0C)
-
-/* SPI Control Register */
-#define SPCR	_SFR_IO8(0x0D)
-
-/* SPI Status Register */
-#define SPSR	_SFR_IO8(0x0E)
-
-/* SPI I/O Data Register */
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Input Pins, Port D */
-#define PIND	_SFR_IO8(0x10)
-
-/* Data Direction Register, Port D */
-#define DDRD	_SFR_IO8(0x11)
-
-/* Data Register, Port D */
-#define PORTD	_SFR_IO8(0x12)
-
-/* Input Pins, Port C */
-#define PINC	_SFR_IO8(0x13)
-
-/* Data Direction Register, Port C */
-#define DDRC	_SFR_IO8(0x14)
-
-/* Data Register, Port C */
-#define PORTC	_SFR_IO8(0x15)
-
-/* Input Pins, Port B */
-#define PINB	_SFR_IO8(0x16)
-
-/* Data Direction Register, Port B */
-#define DDRB	_SFR_IO8(0x17)
-
-/* Data Register, Port B */
-#define PORTB	_SFR_IO8(0x18)
-
-/* Input Pins, Port A */
-#define PINA	_SFR_IO8(0x19)
-
-/* Data Direction Register, Port A */
-#define DDRA	_SFR_IO8(0x1A)
-
-/* Data Register, Port A */
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-/* UART Baud Register HIgh */
-#define UBRRH	_SFR_IO8(0x20)
-
-/* Watchdog Timer Control Register */
-#define WDTCR	_SFR_IO8(0x21)
-
-/* Timer/Counter2 Output Compare Register */
-#define OCR2	_SFR_IO8(0x22)
-
-/* Timer/Counter2 (8-bit) */
-#define TCNT2	_SFR_IO8(0x23)
-
-/* Timer/Counter1 Input Capture Register */
-#define ICR1	_SFR_IO16(0x24)
-#define ICR1L	_SFR_IO8(0x24)
-#define ICR1H	_SFR_IO8(0x25)
-
-/* ASynchronous mode Status Register */
-#define ASSR	_SFR_IO8(0x26)
-
-/* Timer/Counter2 Control Register */
-#define TCCR2	_SFR_IO8(0x27)
-
-/* Timer/Counter1 Output Compare RegisterB */
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-
-/* Timer/Counter1 Output Compare RegisterA */
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-
-/* Timer/Counter1 */
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-
-/* Timer/Counter1 Control Register B */
-#define TCCR1B	_SFR_IO8(0x2E)
-
-/* Timer/Counter1 Control Register A */
-#define TCCR1A	_SFR_IO8(0x2F)
-
-/* Special Function IO Register */
-#define SFIOR	_SFR_IO8(0x30)
-
-/* Timer/Counter0 Output Compare Register */
-#define OCR0	_SFR_IO8(0x31)
-
-/* Timer/Counter0 (8-bit) */
-#define TCNT0	_SFR_IO8(0x32)
-
-/* Timer/Counter0 Control Register */
-#define TCCR0	_SFR_IO8(0x33)
-
-/* MCU general Status Register */
-#define MCUSR	_SFR_IO8(0x34)
-
-/* MCU general Control Register */
-#define MCUCR	_SFR_IO8(0x35)
-
-/* Extended MCU general Control Register */
-#define EMCUCR	_SFR_IO8(0x36)
-
-/* Store Program Memory Control Register */
-#define SPMCR	_SFR_IO8(0x37)
-
-/* Timer/Counter Interrupt Flag Register */
-#define TIFR	_SFR_IO8(0x38)
-
-/* Timer/Counter Interrupt MaSK Register */
-#define TIMSK	_SFR_IO8(0x39)
-
-/* General Interrupt Flag Register */
-#define GIFR	_SFR_IO8(0x3A)
-
-/* General Interrupt MaSK register */
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(7)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				_VECTOR(12)
-
-/* UART0, Rx Complete */
-#define UART0_RX_vect			_VECTOR(13)
-#define SIG_UART0_RECV			_VECTOR(13)
-
-/* UART1, Rx Complete */
-#define UART1_RX_vect			_VECTOR(14)
-#define SIG_UART1_RECV			_VECTOR(14)
-
-/* UART0 Data Register Empty */
-#define UART0_UDRE_vect			_VECTOR(15)
-#define SIG_UART0_DATA			_VECTOR(15)
-
-/* UART1 Data Register Empty */
-#define UART1_UDRE_vect			_VECTOR(16)
-#define SIG_UART1_DATA			_VECTOR(16)
-
-/* UART0, Tx Complete */
-#define UART0_TX_vect			_VECTOR(17)
-#define SIG_UART0_TRANS			_VECTOR(17)
-
-/* UART1, Tx Complete */
-#define UART1_TX_vect			_VECTOR(18)
-#define SIG_UART1_TRANS			_VECTOR(18)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(19)
-#define SIG_EEPROM_READY		_VECTOR(19)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(20)
-#define SIG_COMPARATOR			_VECTOR(20)
-
-#define _VECTORS_SIZE 84
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-#define INT2	5
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-#define INTF2	5
-
-/* TIMSK */
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B	5
-#define TOIE2	4
-#define TICIE1	3
-#define OCIE2	2
-#define TOIE0	1
-#define OCIE0	0
-
-/* TIFR */
-#define TOV1	7
-#define	OCF1A	6
-#define	OCF1B	5
-#define TOV2	4
-#define ICF1	3
-#define OCF2	2
-#define TOV0	1
-#define OCF0	0
-
-/* MCUCR */
-#define SRE	7
-#define SRW10	6
-#define SE	5
-#define SM1	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* EMCUCR */
-#define SM0	7
-#define SRL2	6
-#define SRL1	5
-#define SRL0	4
-#define SRW01	3
-#define SRW00	2
-#define SRW11	1
-#define ISC2	0
-
-/* SPMCR */
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* SFIOR */
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-#define FOC0	7
-#define PWM0	6
-#define COM01	5
-#define COM00	4
-#define CTC0	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define PWM2	6
-#define COM21	5
-#define COM20	4
-#define CTC2	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define PWM11	1
-#define PWM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = TXD1 / AIN1
-   PB2 = RXD1 / AIN0
-   PB1 = OC2 / T1
-   PB0 = OC0 / T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = RD#
-   PD6 = WR#
-   PD5 = TOSC2 / OC1A
-   PD4 = TOSC1
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD0
-   PD0 = RXD0
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/*
-   PE2 = ALE
-   PE1 = OC1B
-   PE0 = ICP / INT2
- */
-
-/* PORTE */
-#define PE2	2
-#define PE1	1
-#define PE0	0
-
-/* DDRE */
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-/* PINE */
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSR0A, UCSR1A */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-#define U2X	1
-#define MPCM	0
-
-/* UCSR0B, UCSR1B */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define CHR9	2
-#define RXB8	1
-#define TXB8	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* EEPROM Control Register */
-#define    EERIE        3
-#define    EEMWE        2
-#define    EEWE         1
-#define    EERE         0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x45F
-#define XRAMEND		0xFFFF
-#define E2END		0x1FF
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 1
-
-/* Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_SUT         (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BOOTRST     (unsigned char)~_BV(6)
-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x01
-
-
-/**@}*/
-#endif /* _AVR_IOM161_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom162.h b/cpukit/score/cpu/avr/avr/iom162.h
deleted file mode 100644
index d10a59a..0000000
--- a/cpukit/score/cpu/avr/avr/iom162.h
+++ /dev/null
@@ -1,964 +0,0 @@
-/**
- * @file iom162.h
- *
- * @brief Definitions for ATmega162
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- * Copyright (c) 2002, Nils Kristian Strom <nilsst at omegav.ntnu.no>
- * All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM162_H_
-#define _AVR_IOM162_H_ 1
-
-/**
- *  @defgroup Avr_iom162 ATmega162 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom162.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* Memory mapped I/O registers */
-
-/* Timer/Counter3 Control Register A */
-#define TCCR3A	_SFR_MEM8(0x8B)
-
-/* Timer/Counter3 Control Register B */
-#define TCCR3B	_SFR_MEM8(0x8A)
-
-/* Timer/Counter3 - Counter Register */
-#define TCNT3H	_SFR_MEM8(0x89)
-#define TCNT3L	_SFR_MEM8(0x88)
-#define TCNT3	_SFR_MEM16(0x88)
-
-/* Timer/Counter3 - Output Compare Register A */
-#define OCR3AH	_SFR_MEM8(0x87)
-#define OCR3AL	_SFR_MEM8(0x86)
-#define OCR3A	_SFR_MEM16(0x86)
-
-/* Timer/Counter3 - Output Compare Register B */
-#define OCR3BH	_SFR_MEM8(0x85)
-#define OCR3BL	_SFR_MEM8(0x84)
-#define OCR3B	_SFR_MEM16(0x84)
-
-/* Timer/Counter3 - Input Capture Register */
-#define ICR3H	_SFR_MEM8(0x81)
-#define ICR3L	_SFR_MEM8(0x80)
-#define ICR3	_SFR_MEM16(0x80)
-
-/* Extended Timer/Counter Interrupt Mask */
-#define ETIMSK	_SFR_MEM8(0x7D)
-
-/* Extended Timer/Counter Interrupt Flag Register */
-#define ETIFR	_SFR_MEM8(0x7C)
-
-/* Pin Change Mask Register 1 */
-#define PCMSK1	_SFR_MEM8(0x6C)
-
-/* Pin Change Mask Register 0 */
-#define PCMSK0	_SFR_MEM8(0x6B)
-
-/* Clock PRescale */
-#define CLKPR	_SFR_MEM8(0x61)
-
-
-/* Standard I/O registers */
-
-/* 0x3F SREG */
-/* 0x3D..0x3E SP */
-#define	UBRR1H  _SFR_IO8(0x3C)  /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */
-#define UCSR1C  _SFR_IO8(0x3C)  /* USART 1 Control and Status Register, Shared with UBRR1H */
-#define GICR    _SFR_IO8(0x3B)	/* General Interrupt Control Register */
-#define GIFR	_SFR_IO8(0x3A)	/* General Interrupt Flag Register */
-#define TIMSK	_SFR_IO8(0x39)	/* Timer Interrupt Mask */
-#define TIFR	_SFR_IO8(0x38)	/* Timer Interrupt Flag Register */
-#define SPMCR	_SFR_IO8(0x37)	/* Store Program Memory Control Register */
-#define EMCUCR	_SFR_IO8(0x36)	/* Extended MCU Control Register */
-#define MCUCR	_SFR_IO8(0x35)	/* MCU Control Register */
-#define MCUCSR	_SFR_IO8(0x34)	/* MCU Control and Status Register */
-#define TCCR0	_SFR_IO8(0x33)	/* Timer/Counter 0 Control Register */
-#define TCNT0	_SFR_IO8(0x32)	/* TImer/Counter 0 */
-#define OCR0	_SFR_IO8(0x31)	/* Output Compare Register 0 */
-#define SFIOR	_SFR_IO8(0x30)	/* Special Function I/O Register */
-#define TCCR1A	_SFR_IO8(0x2F)	/* Timer/Counter 1 Control Register A */
-#define TCCR1B	_SFR_IO8(0x2E)	/* Timer/Counter 1 Control Register A */
-#define TCNT1H	_SFR_IO8(0x2D)	/* Timer/Counter 1 High Byte */
-#define TCNT1L	_SFR_IO8(0x2C)	/* Timer/Counter 1 Low Byte */
-#define TCNT1	_SFR_IO16(0x2C)	/* Timer/Counter 1 */
-#define OCR1AH	_SFR_IO8(0x2B)	/* Timer/Counter 1 Output Compare Register A High Byte */
-#define OCR1AL	_SFR_IO8(0x2A)  /* Timer/Counter 1 Output Compare Register A Low Byte */
-#define OCR1A	_SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */
-#define OCR1BH	_SFR_IO8(0x29)	/* Timer/Counter 1 Output Compare Register B High Byte */
-#define OCR1BL	_SFR_IO8(0x28)	/* Timer/Counter 1 Output Compare Register B Low Byte */
-#define OCR1B	_SFR_IO16(0x28)	/* Timer/Counter 1 Output Compare Register B */
-#define TCCR2	_SFR_IO8(0x27)	/* Timer/Counter 2 Control Register */
-#define ASSR	_SFR_IO8(0x26)	/* Asynchronous Status Register */
-#define ICR1H	_SFR_IO8(0x25)	/* Input Capture Register 1 High Byte */
-#define ICR1L	_SFR_IO8(0x24)	/* Input Capture Register 1 Low Byte */
-#define ICR1	_SFR_IO16(0x24)	/* Input Capture Register 1 */
-#define TCNT2	_SFR_IO8(0x23)	/* Timer/Counter 2 */
-#define OCR2	_SFR_IO8(0x22)	/* Timer/Counter 2 Output Compare Register */
-#define WDTCR	_SFR_IO8(0x21)	/* Watchdow Timer Control Register */
-#define UBRR0H	_SFR_IO8(0x20)	/* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */
-#define UCSR0C	_SFR_IO8(0x20)	/* USART 0 Control and Status Register C, Shared with UBRR0H */
-#define EEARH	_SFR_IO8(0x1F)  /* EEPROM Address Register High Byte */
-#define EEARL	_SFR_IO8(0x1E)  /* EEPROM Address Register Low Byte */
-#define EEAR	_SFR_IO16(0x1E) /* EEPROM Address Register */
-#define EEDR	_SFR_IO8(0x1D)  /* EEPROM Data Register */
-#define EECR	_SFR_IO8(0x1C)  /* EEPROM Control Register */
-#define PORTA	_SFR_IO8(0x1B)	/* Port A */
-#define DDRA	_SFR_IO8(0x1A)	/* Port A Data Direction Register */
-#define PINA	_SFR_IO8(0x19)	/* Port A Pin Register */
-#define PORTB	_SFR_IO8(0x18)	/* Port B */
-#define DDRB	_SFR_IO8(0x17)	/* Port B Data Direction Register */
-#define PINB	_SFR_IO8(0x16)	/* Port B Pin Register */
-#define PORTC	_SFR_IO8(0x15)	/* Port C */
-#define DDRC	_SFR_IO8(0x14)	/* Port C Data Direction Register */
-#define PINC	_SFR_IO8(0x13)	/* Port C Pin Register */
-#define PORTD	_SFR_IO8(0x12)	/* Port D */
-#define DDRD	_SFR_IO8(0x11)	/* Port D Data Direction Register */
-#define PIND	_SFR_IO8(0x10)	/* Port D Pin Register */
-#define SPDR	_SFR_IO8(0x0F)  /* SPI Data Register */
-#define SPSR	_SFR_IO8(0x0E)	/* SPI Status Register */
-#define SPCR	_SFR_IO8(0x0D)	/* SPI Control Register */
-#define UDR0	_SFR_IO8(0x0C)	/* USART 0 Data Register */
-#define UCSR0A	_SFR_IO8(0x0B)	/* USART 0 Control and Status Register A */
-#define UCSR0B	_SFR_IO8(0x0A)	/* USART 0 Control and Status Register B */
-#define UBRR0L	_SFR_IO8(0x09)	/* USART 0 Baud-Rate Register Low Byte */
-#define ACSR	_SFR_IO8(0x08)	/* Analog Comparator Status Register */
-#define PORTE	_SFR_IO8(0x07)	/* Port E */
-#define DDRE	_SFR_IO8(0x06)	/* Port E Data Direction Register */
-#define PINE	_SFR_IO8(0x05)	/* Port E Pin Register */
-#define OSCCAL	_SFR_IO8(0x04) 	/* Oscillator Calibration, Shared with OCDR */
-#define OCDR	_SFR_IO8(0x04) 	/* On-Chip Debug Register, Shared with OSCCAL */
-#define UDR1	_SFR_IO8(0x03)	/* USART 1 Data Register */
-#define UCSR1A	_SFR_IO8(0x02)	/* USART 1 Control and Status Register A */
-#define UCSR1B	_SFR_IO8(0x01)	/* USART 1 Control and Status Register B */
-#define	UBRR1L  _SFR_IO8(0x00)  /* USART 0 Baud Rate Register High Byte */
-
-
-/* Interrupt vectors (byte addresses) */
-
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt Request 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* External Interrupt Request 2 */
-#define INT2_vect			_VECTOR(3)
-#define SIG_INTERRUPT2			_VECTOR(3)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(4)
-#define SIG_PIN_CHANGE0			_VECTOR(4)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(5)
-#define SIG_PIN_CHANGE1			_VECTOR(5)
-
-/* Timer/Counter3 Capture Event */
-#define TIMER3_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE3		_VECTOR(6)
-
-/* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE3A		_VECTOR(7)
-
-/* Timer/Counter3 Compare Match B */
-#define TIMER3_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE3B		_VECTOR(8)
-
-/* Timer/Counter3 Overflow */
-#define TIMER3_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW3			_VECTOR(9)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(10)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW2			_VECTOR(11)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(12)
-#define SIG_INPUT_CAPTURE1		_VECTOR(12)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(13)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(13)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(14)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(14)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(15)
-#define SIG_OVERFLOW1			_VECTOR(15)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(16)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(16)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(17)
-#define SIG_OVERFLOW0			_VECTOR(17)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(18)
-#define SIG_SPI				_VECTOR(18)
-
-/* USART0, Rx Complete */
-#define USART0_RXC_vect			_VECTOR(19)
-#define SIG_USART0_RECV			_VECTOR(19)
-
-/* USART1, Rx Complete */
-#define USART1_RXC_vect			_VECTOR(20)
-#define SIG_USART1_RECV			_VECTOR(20)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(21)
-#define SIG_USART0_DATA			_VECTOR(21)
-
-/* USART1, Data register Empty */
-#define USART1_UDRE_vect		_VECTOR(22)
-#define SIG_USART1_DATA			_VECTOR(22)
-
-/* USART0, Tx Complete */
-#define USART0_TXC_vect			_VECTOR(23)
-#define SIG_USART0_TRANS		_VECTOR(23)
-
-/* USART1, Tx Complete */
-#define USART1_TXC_vect			_VECTOR(24)
-#define SIG_USART1_TRANS		_VECTOR(24)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(25)
-#define SIG_EEPROM_READY		_VECTOR(25)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(26)
-#define SIG_COMPARATOR			_VECTOR(26)
-
-/* Store Program Memory Read */
-#define SPM_RDY_vect			_VECTOR(27)
-#define SIG_SPM_READY			_VECTOR(27)
-
-#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */
-
-
-
-
-
-/* TCCR3B bit definitions, memory mapped I/O */
-
-#define ICNC3	7
-#define ICES3	6
-#define WGM33	4
-#define WGM32	3
-#define CS32	2
-#define CS31	1
-#define CS30	0
-
-
-
-/* TCCR3A bit definitions, memory mapped I/O */
-
-#define COM3A1	7
-#define COM3A0	6
-#define COM3B1	5
-#define COM3B0	4
-#define FOC3A	3
-#define FOC3B	2
-#define WGM31	1
-#define WGM30	0
-
-
-
-/* ETIMSK bit definitions, memory mapped I/O */
-
-#define TICIE3		5
-#define OCIE3A		4
-#define OCIE3B		3
-#define TOIE3		2
-
-
-
-/* ETIFR bit definitions, memory mapped I/O */
-
-#define ICF3		5
-#define OCF3A		4
-#define OCF3B		3
-#define TOV3		2
-
-
-
-/* PCMSK1 bit definitions, memory mapped I/O */
-#define PCINT15	7
-#define PCINT14	6
-#define PCINT13	5
-#define PCINT12	4
-#define PCINT11	3
-#define PCINT10	2
-#define PCINT9	1
-#define PCINT8	0
-
-
-
-/* PCMSK0 bit definitions, memory mapped I/O */
-
-#define PCINT7	7
-#define PCINT6	6
-#define PCINT5	5
-#define PCINT4	4
-#define PCINT3	3
-#define PCINT2	2
-#define PCINT1	1
-#define PCINT0	0
-
-
-
-/* CLKPR bit definitions, memory mapped I/O */
-
-#define CLKPCE	7
-#define CLKPS3	3
-#define CLKPS2	2
-#define CLKPS1	1
-#define CLKPS0	0
-
-
-
-/* SPH bit definitions */
-
-#define SP15	15
-#define SP14	14
-#define SP13	13
-#define SP12	12
-#define SP11	11
-#define SP10	10
-#define SP9	9
-#define SP8	8
-
-
-
-/* SPL bit definitions */
-
-#define SP7	7
-#define SP6	6
-#define SP5	5
-#define SP4	4
-#define SP3	3
-#define SP2	2
-#define SP1	1
-#define SP0	0
-
-
-
-/* UBRR1H bit definitions */
-
-#define URSEL1	7
-#define UBRR111	3
-#define UBRR110	2
-#define UBRR19	1
-#define UBRR18	0
-
-
-
-/* UCSR1C bit definitions */
-
-#define URSEL1	7
-#define UMSEL1	6
-#define UPM11	5
-#define UPM10	4
-#define USBS1	3
-#define UCSZ11	2
-#define UCSZ10	1
-#define UCPOL1	0
-
-
-
-/* GICR bit definitions */
-
-#define INT1	7
-#define INT0	6
-#define INT2	5
-#define PCIE1	4
-#define PCIE0	3
-#define IVSEL	1
-#define IVCE	0
-
-
-
-/* GIFR bit definitions */
-
-#define INTF1	7
-#define INTF0	6
-#define INTF2	5
-#define PCIF1	4
-#define PCIF0	3
-
-
-
-/* TIMSK bit definitions */
-
-#define TOIE1	7
-#define OCIE1A	6
-#define OCIE1B  5
-#define OCIE2	4
-#define TICIE1	3
-#define TOIE2	2
-#define TOIE0	1
-#define OCIE0	0
-
-
-
-/* TIFR bit definitions */
-
-#define TOV1	7
-#define OCF1A	6
-#define OCF1B	5
-#define OCF2	4
-#define ICF1	3
-#define TOV2	2
-#define TOV0	1
-#define OCF0	0
-
-
-
-/* SPMCR bit definitions */
-
-#define SPMIE	7
-#define RWWSB	6
-#define RWWSRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-
-
-/* EMCUCR bit definitions */
-
-#define SM0	7
-#define SRL2	6
-#define SRL1	5
-#define SRL0	4
-#define SRW01	3
-#define SRW00	2
-#define SRW11	1
-#define ISC2	0
-
-
-
-/* MCUCR bit definitions */
-
-#define SRE	7
-#define SRW10	6
-#define SE	5
-#define SM1	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-
-
-/* MCUCSR bit definitions */
-
-#define JTD	7
-#define SM2	5
-#define JTRF	4
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-
-
-/* TCCR0 bit definitions */
-
-#define FOC0	7
-#define WGM00	6
-#define COM01	5
-#define COM00	4
-#define WGM01	3
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-
-
-/* SFIOR bit definitions */
-
-#define TSM	7
-#define XMBK	6
-#define XMM2	5
-#define XMM1	4
-#define XMM0	3
-#define PUD	2
-#define PSR2	1
-#define PSR310	0
-
-
-
-/* TCCR1A bit definitions */
-
-#define COM1A1  7
-#define COM1A0  6
-#define COM1B1  5
-#define COM1B0  4
-#define FOC1A   3
-#define FOC1B   2
-#define WGM11   1
-#define WGM10   0
-
-
-
-
-/* TCCR1B bit definitions */
-
-#define ICNC1	7		/* Input Capture Noise Canceler */
-#define ICES1	6		/* Input Capture Edge Select */
-#define WGM13	4		/* Waveform Generation Mode 3 */
-#define WGM12	3		/* Waveform Generation Mode 2 */
-#define CS12	2		/* Clock Select 2 */
-#define CS11	1		/* Clock Select 1 */
-#define CS10	0		/* Clock Select 0 */
-
-
-
-/* TCCR2 bit definitions */
-
-#define FOC2	7
-#define WGM20	6
-#define COM21	5
-#define COM20	4
-#define WGM21	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-
-
-/* ASSR bit definitions */
-
-#define AS2	3
-#define TCN2UB  2
-#define TCON2UB	2   /* Kept for backwards compatibility. */
-#define OCR2UB	1
-#define TCR2UB	0
-
-
-
-/* WDTCR bit definitions */
-
-#define WDCE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-
-
-/* UBRR0H bif definitions */
-
-#define URSEL0	7
-#define UBRR011	3
-#define UBRR010	2
-#define UBRR09	1
-#define UBRR08	0
-
-
-
-/* UCSR0C bit definitions */
-
-#define URSEL0	7
-#define UMSEL0	6
-#define UPM01	5
-#define UPM00	4
-#define USBS0	3
-#define UCSZ01	2
-#define UCSZ00	1
-#define UCPOL0	0
-
-
-
-/* EEARH bit definitions */
-
-#define EEAR8	0
-
-
-
-/* EECR bit definitions */
-
-#define EERIE	3
-#define EEMWE	2
-#define EEWE	1
-#define EERE	0
-
-
-
-/* PORTA bit definitions */
-
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-
-
-/* DDRA bit definitions */
-
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-
-
-/* PINA bit definitions */
-
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-
-/* PORTB bit definitions */
-
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-
-
-/* DDRB bit definitions */
-
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-
-
-/* PINB bit definitions */
-
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-
-
-/* PORTC bit definitions */
-
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-
-
-/* DDRC bit definitions */
-
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-
-
-/* PINC bit definitions */
-
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-
-
-/* PORTD bit definitions */
-
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-
-
-/* DDRD bit definitions */
-
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-
-
-/* PIND bit definitions */
-
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-
-
-/* SPSR bit definitions */
-
-#define SPIF	7
-#define WCOL	6
-#define SPI2X	0
-
-
-
-/* SPCR bit definitions */
-
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-
-
-/* UCSR0A bit definitions */
-
-#define RXC0	7
-#define TXC0	6
-#define UDRE0	5
-#define FE0	4
-#define DOR0	3
-#define UPE0	2
-#define U2X0	1
-#define MPCM0	0
-
-
-
-/* UCSR0B bit definitions */
-
-#define RXCIE0	7
-#define TXCIE0	6
-#define UDRIE0	5
-#define RXEN0	4
-#define	TXEN0	3
-#define UCSZ02 	2
-#define RXB80	1
-#define TXB80	0
-
-
-
-/* ACSR bit definitions */
-
-#define ACD	7
-#define ACBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-
-
-/* PORTE bit definitions */
-
-#define PE2	2
-#define PE1	1
-#define PE0	0
-
-
-
-/* DDRE bit definitions */
-
-#define DDE2	2
-#define DDE1	1
-#define DDE0	0
-
-
-
-/* PINE bit definitions */
-
-#define PINE2	2
-#define PINE1	1
-#define PINE0	0
-
-
-
-/* UCSR1A bit definitions */
-
-#define RXC1	7
-#define TXC1	6
-#define UDRE1	5
-#define FE1	4
-#define DOR1	3
-#define UPE1    2
-#define U2X1	1
-#define MPCM1	0
-
-
-
-/* UCSR1B bit definitions */
-
-#define RXCIE1	7
-#define TXCIE1	6
-#define UDRIE1	5
-#define RXEN1	4
-#define TXEN1	3
-#define UCSZ12	2
-#define RXB81	1
-#define TXB81	0
-
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x4FF
-#define XRAMEND		0xFFFF
-#define E2END		0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define FUSE_M161C       (unsigned char)~_BV(4)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x04
-
-
-/**@}*/
-#endif  /* _AVR_IOM162_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom163.h b/cpukit/score/cpu/avr/avr/iom163.h
deleted file mode 100644
index 2dabcd8..0000000
--- a/cpukit/score/cpu/avr/avr/iom163.h
+++ /dev/null
@@ -1,651 +0,0 @@
-/**
- * @file avr/iom163.h
- *
- * @brief Definitions for ATmega163
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *   Copyright (c) 2007 Anatoly Sokolov
- *   All rights reserved.
- *
- *   Redistribution and use in source and binary forms, with or without
- *   modification, are permitted provided that the following conditions are met:
- *
- *  * Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *  * Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- *
- *  * Neither the name of the copyright holders nor the names of
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM163_H_
-#define _AVR_IOM163_H_ 1
-
-/**
- *  @defgroup Avr_iom163 ATmega163 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom163.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-/* I/O registers */
-
-#define TWBR	_SFR_IO8(0x00)
-#define TWSR	_SFR_IO8(0x01)
-#define TWAR	_SFR_IO8(0x02)
-#define TWDR	_SFR_IO8(0x03)
-
-/* ADC */
-#ifndef __ASSEMBLER__
-#define ADC 	_SFR_IO16(0x04)
-#endif
-#define ADCW	_SFR_IO16(0x04)
-#define ADCL	_SFR_IO8(0x04)
-#define ADCH	_SFR_IO8(0x05)
-#define ADCSR	_SFR_IO8(0x06)
-#define ADMUX	_SFR_IO8(0x07)
-
-/* analog comparator */
-#define ACSR	_SFR_IO8(0x08)
-
-/* UART */
-#define UBRR	_SFR_IO8(0x09)
-#define UCSRB	_SFR_IO8(0x0A)
-#define UCSRA	_SFR_IO8(0x0B)
-#define UDR	_SFR_IO8(0x0C)
-
-/* SPI */
-#define SPCR	_SFR_IO8(0x0D)
-#define SPSR	_SFR_IO8(0x0E)
-#define SPDR	_SFR_IO8(0x0F)
-
-/* Port D */
-#define PIND	_SFR_IO8(0x10)
-#define DDRD	_SFR_IO8(0x11)
-#define PORTD	_SFR_IO8(0x12)
-
-/* Port C */
-#define PINC	_SFR_IO8(0x13)
-#define DDRC	_SFR_IO8(0x14)
-#define PORTC	_SFR_IO8(0x15)
-
-/* Port B */
-#define PINB	_SFR_IO8(0x16)
-#define DDRB	_SFR_IO8(0x17)
-#define PORTB	_SFR_IO8(0x18)
-
-/* Port A */
-#define PINA	_SFR_IO8(0x19)
-#define DDRA	_SFR_IO8(0x1A)
-#define PORTA	_SFR_IO8(0x1B)
-
-/* EEPROM Control Register */
-#define EECR	_SFR_IO8(0x1C)
-
-/* EEPROM Data Register */
-#define EEDR	_SFR_IO8(0x1D)
-
-/* EEPROM Address Register */
-#define EEAR	_SFR_IO16(0x1E)
-#define EEARL	_SFR_IO8(0x1E)
-#define EEARH	_SFR_IO8(0x1F)
-
-#define UBRRHI	_SFR_IO8(0x20)
-
-#define WDTCR	_SFR_IO8(0x21)
-
-#define ASSR	_SFR_IO8(0x22)
-
-/* Timer 2 */
-#define OCR2	_SFR_IO8(0x23)
-#define TCNT2	_SFR_IO8(0x24)
-#define TCCR2	_SFR_IO8(0x25)
-
-/* Timer 1 */
-#define ICR1	_SFR_IO16(0x26)
-#define ICR1L	_SFR_IO8(0x26)
-#define ICR1H	_SFR_IO8(0x27)
-#define OCR1B	_SFR_IO16(0x28)
-#define OCR1BL	_SFR_IO8(0x28)
-#define OCR1BH	_SFR_IO8(0x29)
-#define OCR1A	_SFR_IO16(0x2A)
-#define OCR1AL	_SFR_IO8(0x2A)
-#define OCR1AH	_SFR_IO8(0x2B)
-#define TCNT1	_SFR_IO16(0x2C)
-#define TCNT1L	_SFR_IO8(0x2C)
-#define TCNT1H	_SFR_IO8(0x2D)
-#define TCCR1B	_SFR_IO8(0x2E)
-#define TCCR1A	_SFR_IO8(0x2F)
-
-#define SFIOR	_SFR_IO8(0x30)
-
-#define OSCCAL	_SFR_IO8(0x31)
-
-/* Timer 0 */
-#define TCNT0	_SFR_IO8(0x32)
-#define TCCR0	_SFR_IO8(0x33)
-
-#define MCUSR	_SFR_IO8(0x34)
-#define MCUCR	_SFR_IO8(0x35)
-
-#define TWCR	_SFR_IO8(0x36)
-
-#define SPMCR	_SFR_IO8(0x37)
-
-#define TIFR	_SFR_IO8(0x38)
-#define TIMSK	_SFR_IO8(0x39)
-
-#define GIFR	_SFR_IO8(0x3A)
-#define GIMSK	_SFR_IO8(0x3B)
-
-/* 0x3C reserved */
-
-/* 0x3D..0x3E SP */
-
-/* 0x3F SREG */
-
-/* Interrupt vectors */
-
-/* External Interrupt 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* External Interrupt 1 */
-#define INT1_vect			_VECTOR(2)
-#define SIG_INTERRUPT1			_VECTOR(2)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(3)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(3)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(4)
-#define SIG_OVERFLOW2			_VECTOR(4)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(5)
-#define SIG_INPUT_CAPTURE1		_VECTOR(5)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(6)
-#define SIG_OUTPUT_COMPARE1A		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1B		_VECTOR(7)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(8)
-#define SIG_OVERFLOW1			_VECTOR(8)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW0			_VECTOR(9)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(10)
-#define SIG_SPI				_VECTOR(10)
-
-/* UART, RX Complete */
-#define UART_RX_vect			_VECTOR(11)
-#define SIG_UART_RECV			_VECTOR(11)
-
-/* UART Data Register Empty */
-#define UART_UDRE_vect			_VECTOR(12)
-#define SIG_UART_DATA			_VECTOR(12)
-
-/* UART, TX Complete */
-#define UART_TX_vect			_VECTOR(13)
-#define SIG_UART_TRANS			_VECTOR(13)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(14)
-#define SIG_ADC				_VECTOR(14)
-
-/* EEPROM Ready */
-#define EE_RDY_vect			_VECTOR(15)
-#define SIG_EEPROM_READY		_VECTOR(15)
-
-/* Analog Comparator */
-#define ANA_COMP_vect			_VECTOR(16)
-#define SIG_COMPARATOR			_VECTOR(16)
-
-/* 2-Wire Serial Interface */
-#define TWI_vect			_VECTOR(17)
-#define SIG_2WIRE_SERIAL		_VECTOR(17)
-
-#define _VECTORS_SIZE 72
-
-/* Bit numbers */
-
-/* GIMSK */
-#define INT1	7
-#define INT0	6
-/* bit 5 reserved, undefined */
-/* bits 4-0 reserved */
-
-/* GIFR */
-#define INTF1	7
-#define INTF0	6
-/* bits 5-0 reserved */
-
-/* TIMSK */
-#define OCIE2	7
-#define TOIE2	6
-#define TICIE1	5
-#define OCIE1A	4
-#define OCIE1B	3
-#define TOIE1	2
-/* bit 1 reserved */
-#define TOIE0	0
-
-/* TIFR */
-#define OCF2	7
-#define TOV2	6
-#define ICF1	5
-#define OCF1A	4
-#define OCF1B	3
-#define TOV1	2
-/* bit 1 reserved, undefined */
-#define TOV0	0
-
-/* SPMCR */
-/* bit 7 reserved */
-#define ASB	6
-/* bit 5 reserved */
-#define ASRE	4
-#define BLBSET	3
-#define PGWRT	2
-#define PGERS	1
-#define SPMEN	0
-
-/* TWCR */
-#define TWINT	7
-#define TWEA	6
-#define TWSTA	5
-#define TWSTO	4
-#define TWWC	3
-#define TWEN	2
-/* bit 1 reserved */
-#define TWIE	0
-
-/* TWAR */
-#define TWGCE	0
-
-/* TWSR */
-#define    TWS7         7
-#define    TWS6         6
-#define    TWS5         5
-#define    TWS4         4
-#define    TWS3         3
-/* bits 2-0 reserved */
-
-/* MCUCR */
-/* bit 7 reserved */
-#define SE	6
-#define SM1	5
-#define SM0	4
-#define ISC11	3
-#define ISC10	2
-#define ISC01	1
-#define ISC00	0
-
-/* MCUSR */
-/* bits 7-4 reserved */
-#define WDRF	3
-#define BORF	2
-#define EXTRF	1
-#define PORF	0
-
-/* SFIOR */
-/* bits 7-4 reserved */
-#define ACME	3
-#define PUD	2
-#define PSR2	1
-#define PSR10	0
-
-/* TCCR0 */
-/* bits 7-3 reserved */
-#define CS02	2
-#define CS01	1
-#define CS00	0
-
-/* TCCR2 */
-#define FOC2	7
-#define PWM2	6
-#define COM21	5
-#define COM20	4
-#define CTC2	3
-#define CS22	2
-#define CS21	1
-#define CS20	0
-
-/* ASSR */
-/* bits 7-4 reserved */
-#define AS2	3
-#define TCN2UB	2
-#define OCR2UB	1
-#define TCR2UB	0
-
-/* TCCR1A */
-#define COM1A1	7
-#define COM1A0	6
-#define COM1B1	5
-#define COM1B0	4
-#define FOC1A	3
-#define FOC1B	2
-#define PWM11	1
-#define PWM10	0
-
-/* TCCR1B */
-#define ICNC1	7
-#define ICES1	6
-/* bits 5-4 reserved */
-#define CTC1	3
-#define CS12	2
-#define CS11	1
-#define CS10	0
-
-/* WDTCR */
-/* bits 7-5 reserved */
-#define WDTOE	4
-#define WDE	3
-#define WDP2	2
-#define WDP1	1
-#define WDP0	0
-
-/* PA7-PA0 = ADC7-ADC0 */
-/* PORTA */
-#define PA7	7
-#define PA6	6
-#define PA5	5
-#define PA4	4
-#define PA3	3
-#define PA2	2
-#define PA1	1
-#define PA0	0
-
-/* DDRA */
-#define DDA7	7
-#define DDA6	6
-#define DDA5	5
-#define DDA4	4
-#define DDA3	3
-#define DDA2	2
-#define DDA1	1
-#define DDA0	0
-
-/* PINA */
-#define PINA7	7
-#define PINA6	6
-#define PINA5	5
-#define PINA4	4
-#define PINA3	3
-#define PINA2	2
-#define PINA1	1
-#define PINA0	0
-
-/*
-   PB7 = SCK
-   PB6 = MISO
-   PB5 = MOSI
-   PB4 = SS#
-   PB3 = AIN1
-   PB2 = AIN0
-   PB1 = T1
-   PB0 = T0
- */
-
-/* PORTB */
-#define PB7	7
-#define PB6	6
-#define PB5	5
-#define PB4	4
-#define PB3	3
-#define PB2	2
-#define PB1	1
-#define PB0	0
-
-/* DDRB */
-#define DDB7	7
-#define DDB6	6
-#define DDB5	5
-#define DDB4	4
-#define DDB3	3
-#define DDB2	2
-#define DDB1	1
-#define DDB0	0
-
-/* PINB */
-#define PINB7	7
-#define PINB6	6
-#define PINB5	5
-#define PINB4	4
-#define PINB3	3
-#define PINB2	2
-#define PINB1	1
-#define PINB0	0
-
-/*
-   PC7 = TOSC2
-   PC6 = TOSC1
-   PC1 = SDA
-   PC0 = SCL
- */
-/* PORTC */
-#define PC7	 7
-#define PC6	 6
-#define PC5	 5
-#define PC4	 4
-#define PC3	 3
-#define PC2	 2
-#define PC1	 1
-#define PC0	 0
-
-/* DDRC */
-#define DDC7	7
-#define DDC6	6
-#define DDC5	5
-#define DDC4	4
-#define DDC3	3
-#define DDC2	2
-#define DDC1	1
-#define DDC0	0
-
-/* PINC */
-#define PINC7	7
-#define PINC6	6
-#define PINC5	5
-#define PINC4	4
-#define PINC3	3
-#define PINC2	2
-#define PINC1	1
-#define PINC0	0
-
-/*
-   PD7 = OC2
-   PD6 = ICP
-   PD5 = OC1A
-   PD4 = OC1B
-   PD3 = INT1
-   PD2 = INT0
-   PD1 = TXD
-   PD0 = RXD
- */
-
-/* PORTD */
-#define PD7	 7
-#define PD6	 6
-#define PD5	 5
-#define PD4	 4
-#define PD3	 3
-#define PD2	 2
-#define PD1	 1
-#define PD0	 0
-
-/* DDRD */
-#define DDD7	7
-#define DDD6	6
-#define DDD5	5
-#define DDD4	4
-#define DDD3	3
-#define DDD2	2
-#define DDD1	1
-#define DDD0	0
-
-/* PIND */
-#define PIND7	7
-#define PIND6	6
-#define PIND5	5
-#define PIND4	4
-#define PIND3	3
-#define PIND2	2
-#define PIND1	1
-#define PIND0	0
-
-/* SPSR */
-#define SPIF	7
-#define WCOL	6
-/* bits 5-1 reserved */
-#define SPI2X	0
-
-/* SPCR */
-#define SPIE	7
-#define SPE	6
-#define DORD	5
-#define MSTR	4
-#define CPOL	3
-#define CPHA	2
-#define SPR1	1
-#define SPR0	0
-
-/* UCSRA */
-#define RXC	7
-#define TXC	6
-#define UDRE	5
-#define FE	4
-#define DOR	3
-/* bit 2 reserved */
-#define U2X	1
-#define MPCM	0
-
-/* UCSRB */
-#define RXCIE	7
-#define TXCIE	6
-#define UDRIE	5
-#define RXEN	4
-#define	TXEN	3
-#define CHR9	2
-#define RXB8	1
-#define TXB8	0
-
-/* ACSR */
-#define ACD	7
-#define AINBG	6
-#define ACO	5
-#define ACI	4
-#define ACIE	3
-#define ACIC	2
-#define ACIS1	1
-#define ACIS0	0
-
-/* ADCSR */
-#define ADEN	7
-#define ADSC	6
-#define ADFR	5
-#define ADIF	4
-#define ADIE	3
-#define ADPS2	2
-#define ADPS1	1
-#define ADPS0	0
-
-/* ADMUX */
-#define REFS1	7
-#define REFS0	6
-#define ADLAR	5
-#define MUX4	4
-#define MUX3	3
-#define MUX2	2
-#define MUX1	1
-#define MUX0	0
-
-/* EEPROM Control Register */
-#define EERIE   3
-#define EEMWE   2
-#define EEWE    1
-#define EERE    0
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND		0x45F
-#define XRAMEND		RAMEND
-#define E2END		0x1FF
-#define E2PAGESIZE  0
-#define FLASHEND	0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 2
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_BODEN       (unsigned char)~_BV(6)
-#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define HFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x02
-
-
-/**@}*/
-#endif /* _AVR_IOM163_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom164.h b/cpukit/score/cpu/avr/avr/iom164.h
deleted file mode 100644
index 160663d..0000000
--- a/cpukit/score/cpu/avr/avr/iom164.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega164
- */
-
-/* Copyright (c) 2005, 2006 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom164.h - definitions for ATmega164 */
-
-
-#ifndef _AVR_IOM164_H_
-#define _AVR_IOM164_H_ 1
-
-#include <avr/iomxx4.h>
-
-/**
- * @defgroup AvrDef_iom164 ATmega164 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x04FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature (ATmega164P) */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x0A 
-
-/** @} */
-
-#endif /* _AVR_IOM164_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom165.h b/cpukit/score/cpu/avr/avr/iom165.h
deleted file mode 100644
index 72cbc39..0000000
--- a/cpukit/score/cpu/avr/avr/iom165.h
+++ /dev/null
@@ -1,836 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for ATmega165
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom165.h - definitions for ATmega165 */
-
-#ifndef _AVR_IOM165_H_
-#define _AVR_IOM165_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom165.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/**
- * @defgroup AvrDef_iom165 ATmega165 Definitions
- *
- * @ingroup avr
- *
- */
-/**@{**/
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   6
-#define PCIF1   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   6
-#define PCIE1   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-/* Combine PCMSK0 and PCMSK1 */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSRA   _SFR_MEM8(0xC0)
-#define MPCM    0
-#define U2X     1
-#define UPE     2
-#define DOR     3
-#define FE      4
-#define UDRE    5
-#define TXC     6
-#define RXC     7
-
-#define UCSRB   _SFR_MEM8(0XC1)
-#define TXB8    0
-#define RXB8    1
-#define UCSZ2   2
-#define TXEN    3
-#define RXEN    4
-#define UDRIE   5
-#define TXCIE   6
-#define RXCIE   7
-
-#define UCSRC   _SFR_MEM8(0xC2)
-#define UCPOL   0
-#define UCSZ0   1
-#define UCSZ1   2
-#define USBS    3
-#define UPM0    4
-#define UPM1    5
-#define UMSEL   6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRRL and UBRRH */
-#define UBRR    _SFR_MEM16(0xC4)
-
-#define UBRRL   _SFR_MEM8(0xC4)
-#define UBRRH   _SFR_MEM8(0xC5)
-
-#define UDR     _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define USART_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-#define _VECTORS_SIZE 88
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x4FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x07
-
-/** @} */
-
-#endif /* _AVR_IOM165_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom165p.h b/cpukit/score/cpu/avr/avr/iom165p.h
deleted file mode 100644
index 90daff5..0000000
--- a/cpukit/score/cpu/avr/avr/iom165p.h
+++ /dev/null
@@ -1,821 +0,0 @@
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   Copyright (c) 2006 Anatoly Sokolov <aesok at post.ru>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom165p.h - definitions for ATmega165P */
-
-#ifndef _AVR_IOM165P_H_
-#define _AVR_IOM165P_H_ 1
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom165p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-/* Registers and associated bit numbers */
-
-#define PINA    _SFR_IO8(0x00)
-#define PINA7   7
-#define PINA6   6
-#define PINA5   5
-#define PINA4   4
-#define PINA3   3
-#define PINA2   2
-#define PINA1   1
-#define PINA0   0
-
-#define DDRA    _SFR_IO8(0x01)
-#define DDA7    7
-#define DDA6    6
-#define DDA5    5
-#define DDA4    4
-#define DDA3    3
-#define DDA2    2
-#define DDA1    1
-#define DDA0    0
-
-#define PORTA   _SFR_IO8(0x02)
-#define PA7     7
-#define PA6     6
-#define PA5     5
-#define PA4     4
-#define PA3     3
-#define PA2     2
-#define PA1     1
-#define PA0     0
-
-#define PINB    _SFR_IO8(0x03)
-#define PINB7   7
-#define PINB6   6
-#define PINB5   5
-#define PINB4   4
-#define PINB3   3
-#define PINB2   2
-#define PINB1   1
-#define PINB0   0
-
-#define DDRB    _SFR_IO8(0x04)
-#define DDB7    7
-#define DDB6    6
-#define DDB5    5
-#define DDB4    4
-#define DDB3    3
-#define DDB2    2
-#define DDB1    1
-#define DDB0    0
-
-#define PORTB   _SFR_IO8(0x05)
-#define PB7     7
-#define PB6     6
-#define PB5     5
-#define PB4     4
-#define PB3     3
-#define PB2     2
-#define PB1     1
-#define PB0     0
-
-#define PINC    _SFR_IO8(0x06)
-#define PINC7   7
-#define PINC6   6
-#define PINC5   5
-#define PINC4   4
-#define PINC3   3
-#define PINC2   2
-#define PINC1   1
-#define PINC0   0
-
-#define DDRC    _SFR_IO8(0x07)
-#define DDC7    7
-#define DDC6    6
-#define DDC5    5
-#define DDC4    4
-#define DDC3    3
-#define DDC2    2
-#define DDC1    1
-#define DDC0    0
-
-#define PORTC   _SFR_IO8(0x08)
-#define PC7     7
-#define PC6     6
-#define PC5     5
-#define PC4     4
-#define PC3     3
-#define PC2     2
-#define PC1     1
-#define PC0     0
-
-#define PIND    _SFR_IO8(0x09)
-#define PIND7   7
-#define PIND6   6
-#define PIND5   5
-#define PIND4   4
-#define PIND3   3
-#define PIND2   2
-#define PIND1   1
-#define PIND0   0
-
-#define DDRD    _SFR_IO8(0x0A)
-#define DDD7    7
-#define DDD6    6
-#define DDD5    5
-#define DDD4    4
-#define DDD3    3
-#define DDD2    2
-#define DDD1    1
-#define DDD0    0
-
-#define PORTD   _SFR_IO8(0x0B)
-#define PD7     7
-#define PD6     6
-#define PD5     5
-#define PD4     4
-#define PD3     3
-#define PD2     2
-#define PD1     1
-#define PD0     0
-
-#define PINE    _SFR_IO8(0x0C)
-#define PINE7   7
-#define PINE6   6
-#define PINE5   5
-#define PINE4   4
-#define PINE3   3
-#define PINE2   2
-#define PINE1   1
-#define PINE0   0
-
-#define DDRE    _SFR_IO8(0x0D)
-#define DDE7    7
-#define DDE6    6
-#define DDE5    5
-#define DDE4    4
-#define DDE3    3
-#define DDE2    2
-#define DDE1    1
-#define DDE0    0
-
-#define PORTE   _SFR_IO8(0x0E)
-#define PE7     7
-#define PE6     6
-#define PE5     5
-#define PE4     4
-#define PE3     3
-#define PE2     2
-#define PE1     1
-#define PE0     0
-
-#define PINF    _SFR_IO8(0x0F)
-#define PINF7   7
-#define PINF6   6
-#define PINF5   5
-#define PINF4   4
-#define PINF3   3
-#define PINF2   2
-#define PINF1   1
-#define PINF0   0
-
-#define DDRF    _SFR_IO8(0x10)
-#define DDF7    7
-#define DDF6    6
-#define DDF5    5
-#define DDF4    4
-#define DDF3    3
-#define DDF2    2
-#define DDF1    1
-#define DDF0    0
-
-#define PORTF   _SFR_IO8(0x11)
-#define PF7     7
-#define PF6     6
-#define PF5     5
-#define PF4     4
-#define PF3     3
-#define PF2     2
-#define PF1     1
-#define PF0     0
-
-#define PING    _SFR_IO8(0x12)
-#define PING5   5
-#define PING4   4
-#define PING3   3
-#define PING2   2
-#define PING1   1
-#define PING0   0
-
-#define DDRG    _SFR_IO8(0x13)
-#define DDG4    4
-#define DDG3    3
-#define DDG2    2
-#define DDG1    1
-#define DDG0    0
-
-#define PORTG   _SFR_IO8(0x14)
-#define PG4     4
-#define PG3     3
-#define PG2     2
-#define PG1     1
-#define PG0     0
-
-#define TIFR0   _SFR_IO8(0x15)
-#define TOV0    0
-#define OCF0A   1
-
-#define TIFR1   _SFR_IO8(0x16)
-#define TOV1    0
-#define OCF1A   1
-#define OCF1B   2
-#define ICF1    5
-
-#define TIFR2   _SFR_IO8(0x17)
-#define TOV2    0
-#define OCF2A   1
-
-/* Reserved [0x18..0x1B] */
-
-#define EIFR   _SFR_IO8(0x1C)
-#define INTF0   0
-#define PCIF0   6
-#define PCIF1   7
-
-#define EIMSK   _SFR_IO8(0x1D)
-#define INT0    0
-#define PCIE0   6
-#define PCIE1   7
-
-#define GPIOR0  _SFR_IO8(0x1E)
-
-#define EECR    _SFR_IO8(0x1F)
-#define EERE    0
-#define EEWE    1
-#define EEMWE   2
-#define EERIE   3
-
-#define EEDR    _SFR_IO8(0X20)
-
-/* Combine EEARL and EEARH */
-#define EEAR    _SFR_IO16(0x21)
-#define EEARL   _SFR_IO8(0x21)
-#define EEARH   _SFR_IO8(0X22)
-
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
-#define __EEPROM_REG_LOCATIONS__ 1F2021
-
-#define GTCCR   _SFR_IO8(0x23)
-#define PSR10   0
-#define PSR2    1
-#define TSM     7
-
-#define TCCR0A  _SFR_IO8(0x24)
-#define CS00    0
-#define CS01    1
-#define CS02    2
-#define WGM01   3
-#define COM0A0  4
-#define COM0A1  5
-#define WGM00   6
-#define FOC0A   7
-
-/* Reserved [0x25] */
-
-#define TCNT0   _SFR_IO8(0X26)
-
-#define OCR0A   _SFR_IO8(0X27)
-
-/* Reserved [0x28..0x29] */
-
-#define GPIOR1  _SFR_IO8(0x2A)
-
-#define GPIOR2  _SFR_IO8(0x2B)
-
-#define SPCR    _SFR_IO8(0x2C)
-#define SPR0    0
-#define SPR1    1
-#define CPHA    2
-#define CPOL    3
-#define MSTR    4
-#define DORD    5
-#define SPE     6
-#define SPIE    7
-
-#define SPSR    _SFR_IO8(0x2D)
-#define SPI2X   0
-#define WCOL    6
-#define SPIF    7
-
-#define SPDR    _SFR_IO8(0X2E)
-
-/* Reserved [0x2F] */
-
-#define ACSR    _SFR_IO8(0x30)
-#define ACIS0   0
-#define ACIS1   1
-#define ACIC    2
-#define ACIE    3
-#define ACI     4
-#define ACO     5
-#define ACBG    6
-#define ACD     7
-
-#define OCDR    _SFR_IO8(0x31)
-#define OCDR0   0
-#define OCDR1   1
-#define OCDR2   2
-#define OCDR3   3
-#define OCDR4   4
-#define OCDR5   5
-#define OCDR6   6
-#define OCD     7   // The datasheet defines this but IMO it should be OCDR7.
-#define OCDR7   7
-#define IDRD    7
-
-/* Reserved [0x32] */
-
-#define SMCR    _SFR_IO8(0x33)
-#define SE      0
-#define SM0     1
-#define SM1     2
-#define SM2     3
-
-#define MCUSR   _SFR_IO8(0x34)
-#define PORF    0
-#define EXTRF   1
-#define BORF    2
-#define WDRF    3
-#define JTRF    4
-
-#define MCUCR   _SFR_IO8(0X35)
-#define IVCE    0
-#define IVSEL   1
-#define PUD     4
-#define JTD     7
-
-/* Reserved [0x36] */
-
-#define SPMCSR  _SFR_IO8(0x37)
-#define SPMEN   0
-#define PGERS   1
-#define PGWRT   2
-#define BLBSET  3
-#define RWWSRE  4
-#define RWWSB   6
-#define SPMIE   7
-
-/* Reserved [0x38..0x3C] */
-
-/* SP [0x3D..0x3E] */
-/* SREG [0x3F] */
-
-#define WDTCR   _SFR_MEM8(0x60)
-#define WDP0    0
-#define WDP1    1
-#define WDP2    2
-#define WDE     3
-#define WDCE    4
-
-#define CLKPR   _SFR_MEM8(0x61)
-#define CLKPS0  0
-#define CLKPS1  1
-#define CLKPS2  2
-#define CLKPS3  3
-#define CLKPCE  7
-
-/* Reserved [0x62..0x63] */
-
-#define PRR     _SFR_MEM8(0x64)
-#define PRADC       0
-#define PRUSART0    1
-#define PRSPI       2
-#define PRTIM1      3
-
-/* Reserved [0x65] */
-
-#define OSCCAL  _SFR_MEM8(0x66)
-
-/* Reserved [0x67..0x68] */
-
-#define EICRA   _SFR_MEM8(0x69)
-#define ISC00   0
-#define ISC01   1
-
-/* Reserved [0x6A] */
-
-/* Combine PCMSK0 and PCMSK1 */
-#define PCMSK   _SFR_MEM16(0x6B)
-
-#define PCMSK0  _SFR_MEM8(0x6B)
-#define PCINT0  0
-#define PCINT1  1
-#define PCINT2  2
-#define PCINT3  3
-#define PCINT4  4
-#define PCINT5  5
-#define PCINT6  6
-#define PCINT7  7
-
-#define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT8  0
-#define PCINT9  1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-/* Reserved [0x6D] */
-
-#define TIMSK0  _SFR_MEM8(0x6E)
-#define TOIE0   0
-#define OCIE0A  1
-
-#define TIMSK1  _SFR_MEM8(0x6F)
-#define TOIE1   0
-#define OCIE1A  1
-#define OCIE1B  2
-#define ICIE1   5
-
-#define TIMSK2  _SFR_MEM8(0x70)
-#define TOIE2   0
-#define OCIE2A  1
-
-/* Reserved [0x71..0x77] */
-
-/* Combine ADCL and ADCH */
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-#define ADCL    _SFR_MEM8(0x78)
-#define ADCH    _SFR_MEM8(0x79)
-
-#define ADCSRA  _SFR_MEM8(0x7A)
-#define ADPS0   0
-#define ADPS1   1
-#define ADPS2   2
-#define ADIE    3
-#define ADIF    4
-#define ADATE   5
-#define ADSC    6
-#define ADEN    7
-
-#define ADCSRB  _SFR_MEM8(0x7B)
-#define ADTS0   0
-#define ADTS1   1
-#define ADTS2   2
-#define ACME    6
-
-#define ADMUX   _SFR_MEM8(0x7C)
-#define MUX0    0
-#define MUX1    1
-#define MUX2    2
-#define MUX3    3
-#define MUX4    4
-#define ADLAR   5
-#define REFS0   6
-#define REFS1   7
-
-/* Reserved [0x7D] */
-
-#define DIDR0   _SFR_MEM8(0x7E)
-#define ADC0D   0
-#define ADC1D   1
-#define ADC2D   2
-#define ADC3D   3
-#define ADC4D   4
-#define ADC5D   5
-#define ADC6D   6
-#define ADC7D   7
-
-#define DIDR1   _SFR_MEM8(0x7F)
-#define AIN0D   0
-#define AIN1D   1
-
-#define TCCR1A  _SFR_MEM8(0X80)
-#define WGM10   0
-#define WGM11   1
-#define COM1B0  4
-#define COM1B1  5
-#define COM1A0  6
-#define COM1A1  7
-
-#define TCCR1B  _SFR_MEM8(0X81)
-#define CS10    0
-#define CS11    1
-#define CS12    2
-#define WGM12   3
-#define WGM13   4
-#define ICES1   6
-#define ICNC1   7
-
-#define TCCR1C  _SFR_MEM8(0x82)
-#define FOC1B   6
-#define FOC1A   7
-
-/* Reserved [0x83] */
-
-/* Combine TCNT1L and TCNT1H */
-#define TCNT1   _SFR_MEM16(0x84)
-
-#define TCNT1L  _SFR_MEM8(0x84)
-#define TCNT1H  _SFR_MEM8(0x85)
-
-/* Combine ICR1L and ICR1H */
-#define ICR1    _SFR_MEM16(0x86)
-
-#define ICR1L   _SFR_MEM8(0x86)
-#define ICR1H   _SFR_MEM8(0x87)
-
-/* Combine OCR1AL and OCR1AH */
-#define OCR1A   _SFR_MEM16(0x88)
-
-#define OCR1AL  _SFR_MEM8(0x88)
-#define OCR1AH  _SFR_MEM8(0x89)
-
-/* Combine OCR1BL and OCR1BH */
-#define OCR1B   _SFR_MEM16(0x8A)
-
-#define OCR1BL  _SFR_MEM8(0x8A)
-#define OCR1BH  _SFR_MEM8(0x8B)
-
-/* Reserved [0x8C..0xAF] */
-
-#define TCCR2A  _SFR_MEM8(0xB0)
-#define CS20    0
-#define CS21    1
-#define CS22    2
-#define WGM21   3
-#define COM2A0  4
-#define COM2A1  5
-#define WGM20   6
-#define FOC2A   7
-
-/* Reserved [0xB1] */
-
-#define TCNT2   _SFR_MEM8(0xB2)
-
-#define OCR2A   _SFR_MEM8(0xB3)
-
-/* Reserved [0xB4..0xB5] */
-
-#define ASSR    _SFR_MEM8(0xB6)
-#define TCR2UB  0
-#define OCR2UB  1
-#define TCN2UB  2
-#define AS2     3
-#define EXCLK   4
-
-/* Reserved [0xB7] */
-
-#define USICR   _SFR_MEM8(0xB8)
-#define USITC   0
-#define USICLK  1
-#define USICS0  2
-#define USICS1  3
-#define USIWM0  4
-#define USIWM1  5
-#define USIOIE  6
-#define USISIE  7
-
-#define USISR   _SFR_MEM8(0xB9)
-#define USICNT0 0
-#define USICNT1 1
-#define USICNT2 2
-#define USICNT3 3
-#define USIDC   4
-#define USIPF   5
-#define USIOIF  6
-#define USISIF  7
-
-#define USIDR   _SFR_MEM8(0xBA)
-
-/* Reserved [0xBB..0xBF] */
-
-#define UCSR0A  _SFR_MEM8(0xC0)
-#define MPCM0   0
-#define U2X0    1
-#define UPE0    2
-#define DOR0    3
-#define FE0     4
-#define UDRE0   5
-#define TXC0    6
-#define RXC0    7
-
-#define UCSR0B  _SFR_MEM8(0XC1)
-#define TXB80   0
-#define RXB80   1
-#define UCSZ02  2
-#define TXEN0   3
-#define RXEN0   4
-#define UDRIE0  5
-#define TXCIE0  6
-#define RXCIE0  7
-
-#define UCSR0C  _SFR_MEM8(0xC2)
-#define UCPOL0  0
-#define UCSZ00  1
-#define UCSZ01  2
-#define USBS0   3
-#define UPM00   4
-#define UPM01   5
-#define UMSEL0  6
-
-/* Reserved [0xC3] */
-
-/* Combine UBRRL and UBRRH */
-#define UBRR0   _SFR_MEM16(0xC4)
-
-#define UBRR0L  _SFR_MEM8(0xC4)
-#define UBRR0H  _SFR_MEM8(0xC5)
-
-#define UDR0    _SFR_MEM8(0XC6)
-
-/* Reserved [0xC7..0xFF] */
-
-
-/* Interrupt vectors */
-/* Vector 0 is the reset vector */
-/* External Interrupt Request 0 */
-#define INT0_vect			_VECTOR(1)
-#define SIG_INTERRUPT0			_VECTOR(1)
-
-/* Pin Change Interrupt Request 0 */
-#define PCINT0_vect			_VECTOR(2)
-#define SIG_PIN_CHANGE0			_VECTOR(2)
-
-/* Pin Change Interrupt Request 1 */
-#define PCINT1_vect			_VECTOR(3)
-#define SIG_PIN_CHANGE1			_VECTOR(3)
-
-/* Timer/Counter2 Compare Match */
-#define TIMER2_COMP_vect		_VECTOR(4)
-#define SIG_OUTPUT_COMPARE2		_VECTOR(4)
-
-/* Timer/Counter2 Overflow */
-#define TIMER2_OVF_vect			_VECTOR(5)
-#define SIG_OVERFLOW2			_VECTOR(5)
-
-/* Timer/Counter1 Capture Event */
-#define TIMER1_CAPT_vect		_VECTOR(6)
-#define SIG_INPUT_CAPTURE1		_VECTOR(6)
-
-/* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPA_vect		_VECTOR(7)
-#define SIG_OUTPUT_COMPARE1A	_VECTOR(7)
-
-/* Timer/Counter Compare Match B */
-#define TIMER1_COMPB_vect		_VECTOR(8)
-#define SIG_OUTPUT_COMPARE1B	_VECTOR(8)
-
-/* Timer/Counter1 Overflow */
-#define TIMER1_OVF_vect			_VECTOR(9)
-#define SIG_OVERFLOW1			_VECTOR(9)
-
-/* Timer/Counter0 Compare Match */
-#define TIMER0_COMP_vect		_VECTOR(10)
-#define SIG_OUTPUT_COMPARE0		_VECTOR(10)
-
-/* Timer/Counter0 Overflow */
-#define TIMER0_OVF_vect			_VECTOR(11)
-#define SIG_OVERFLOW0			_VECTOR(11)
-
-/* SPI Serial Transfer Complete */
-#define SPI_STC_vect			_VECTOR(12)
-#define SIG_SPI				    _VECTOR(12)
-
-/* USART0, Rx Complete */
-#define USART0_RX_vect			_VECTOR(13)
-#define USART_RX_vect			_VECTOR(13)  /* Alias */
-#define SIG_UART_RECV			_VECTOR(13)
-
-/* USART0 Data register Empty */
-#define USART0_UDRE_vect		_VECTOR(14)
-#define USART_UDRE_vect		    _VECTOR(14)  /* Alias */
-#define SIG_UART_DATA			_VECTOR(14)
-
-/* USART0, Tx Complete */
-#define USART0_TX_vect			_VECTOR(15)
-#define USART_TX_vect			_VECTOR(15)  /* Alias */
-#define SIG_UART_TRANS			_VECTOR(15)
-
-/* USI Start Condition */
-#define USI_START_vect			_VECTOR(16)
-#define SIG_USI_START			_VECTOR(16)
-
-/* USI Overflow */
-#define USI_OVERFLOW_vect		_VECTOR(17)
-#define SIG_USI_OVERFLOW		_VECTOR(17)
-
-/* Analog Comparator */
-#define ANALOG_COMP_vect		_VECTOR(18)
-#define SIG_COMPARATOR			_VECTOR(18)
-
-/* ADC Conversion Complete */
-#define ADC_vect			_VECTOR(19)
-#define SIG_ADC				_VECTOR(19)
-
-/* EEPROM Ready */
-#define EE_READY_vect			_VECTOR(20)
-#define SIG_EEPROM_READY		_VECTOR(20)
-
-/* Store Program Memory Read */
-#define SPM_READY_vect			_VECTOR(21)
-#define SIG_SPM_READY			_VECTOR(21)
-
-#define _VECTORS_SIZE 88
-
-
-/* Constants */
-#define SPM_PAGESIZE    128
-#define RAMEND          0x4FF
-#define XRAMEND         RAMEND
-#define E2END           0x1FF
-#define E2PAGESIZE      4
-#define FLASHEND        0x3FFF
-
-
-/* Fuses */
-
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0      (unsigned char)~_BV(0)
-#define FUSE_CKSEL1      (unsigned char)~_BV(1)
-#define FUSE_CKSEL2      (unsigned char)~_BV(2)
-#define FUSE_CKSEL3      (unsigned char)~_BV(3)
-#define FUSE_SUT0        (unsigned char)~_BV(4)
-#define FUSE_SUT1        (unsigned char)~_BV(5)
-#define FUSE_CKOUT       (unsigned char)~_BV(6)
-#define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST     (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
-#define FUSE_EESAVE      (unsigned char)~_BV(3)
-#define FUSE_WDTON       (unsigned char)~_BV(4)
-#define FUSE_SPIEN       (unsigned char)~_BV(5)
-#define FUSE_JTAGEN      (unsigned char)~_BV(6)
-#define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
-#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
-#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x07
-
-
-#endif /* _AVR_IOM165P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168.h b/cpukit/score/cpu/avr/avr/iom168.h
deleted file mode 100644
index 7f1dee2..0000000
--- a/cpukit/score/cpu/avr/avr/iom168.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
- * @file
- *
- * @brief Definitions for iom168
- */
-
-/*
- *  Copyright (c) 2004, Theodore A. Roth
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _AVR_IOM168_H_
-#define _AVR_IOM168_H_ 1
-
-/**
- *  @defgroup Avr_iom168 iom168 Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-#include <avr/iomx8.h>
-
-/* Constants */
-#define SPM_PAGESIZE 128
-#define RAMEND      0x4FF
-#define XRAMEND     RAMEND
-#define E2END       0x1FF
-#define E2PAGESIZE  4
-#define FLASHEND    0x3FFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define FUSE_EESAVE    (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON     (unsigned char)~_BV(4)  /* Watchdog Timer Always On */
-#define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
-#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x94
-#define SIGNATURE_2 0x06
-
-/**@}*/
-#endif /* _AVR_IOM168_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168p.h b/cpukit/score/cpu/avr/avr/iom168p.h
deleted file mode 100644
index 987d489..0000000
--- a/cpukit/score/cpu/avr/avr/iom168p.h
+++ /dev/null
@@ -1,885 +0,0 @@
-/**
- * @file avr/iom168p.h
- *
- * @brief Definitions for ATmega168P
- *
- * This file should only be included from <avr/io.h>, never directly.
- */
-
-/*
- *  Copyright (c) 2007 Atmel Corporation
- *  All rights reserved.
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in
- *   the documentation and/or other materials provided with the
- *   distribution.
- *
- * * Neither the name of the copyright holders nor the names of
- *   contributors may be used to endorse or promote products derived
- *   from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom168p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif
-
-
-#ifndef _AVR_IOM168P_H_
-#define _AVR_IOM168P_H_ 1
-
-/**
- *  @defgroup Avr_iom168p ATmega168P Definitions
- *
- *  @ingroup avr
- */
-/**@{*/
-
-/* Registers and associated bit numbers */
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-
-#define EEPROM_REG_LOCATIONS 1F2021
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SELFPRGEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define RWWSB 6
-#define SPMIE 7
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1BL0 0
-#define OCR1BL1 1
-#define OCR1BL2 2
-#define OCR1BL3 3
-#define OCR1BL4 4
-#define OCR1BL5 5
-#define OCR1BL6 6
-#define OCR1BL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1BH0 0
-#define OCR1BH1 1
-#define OCR1BH2 2
-#define OCR1BH3 3
-#define OCR1BH4 4
-#define OCR1BH5 5
-#define OCR1BH6 6
-#define OCR1BH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 0
-#define TWAM1 1
-#define TWAM2 2
-#define TWAM3 3
-#define TWAM4 4
-#define TWAM5 5
-#define TWAM6 6
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define