[PATCH 2/6] Remove H8300 port

Gedare Bloom gedare at rtems.org
Mon Jan 4 02:03:55 UTC 2016


Instead of deleting the cpu supplement from the doc, it may be worth
it to leave a stub that indicates when support was removed?

On Sun, Jan 3, 2016 at 4:27 PM, Joel Sherrill <joel at rtems.org> wrote:
> From: Joel Sherrill <joel.sherrill at oarcorp.com>
>
> updates #2452.
> ---
>  c/ACKNOWLEDGEMENTS                                 |    9 +-
>  c/TOOL_TARGETS                                     |    3 -
>  c/src/aclocal/check-networking.m4                  |    2 +-
>  c/src/aclocal/rtems-cpu-subdirs.m4                 |    1 -
>  c/src/lib/libbsp/h8300/Makefile.am                 |    7 -
>  c/src/lib/libbsp/h8300/acinclude.m4                |    8 -
>  c/src/lib/libbsp/h8300/configure.ac                |   19 -
>  cpukit/aclocal/check-networking.m4                 |    2 +-
>  cpukit/configure.ac                                |    4 -
>  cpukit/librpc/src/xdr/xdr_float.c                  |    1 -
>  cpukit/score/cpu/Makefile.am                       |    1 -
>  cpukit/score/cpu/h8300/Makefile.am                 |   19 -
>  cpukit/score/cpu/h8300/README                      |   27 -
>  cpukit/score/cpu/h8300/cpu.c                       |  134 ---
>  cpukit/score/cpu/h8300/cpu_asm.S                   |  221 ----
>  .../score/cpu/h8300/h8300-exception-frame-print.c  |   24 -
>  cpukit/score/cpu/h8300/preinstall.am               |   45 -
>  cpukit/score/cpu/h8300/rtems/asm.h                 |  118 --
>  cpukit/score/cpu/h8300/rtems/score/cpu.h           | 1176 --------------------
>  cpukit/score/cpu/h8300/rtems/score/cpuatomic.h     |   14 -
>  cpukit/score/cpu/h8300/rtems/score/h8300.h         |   44 -
>  cpukit/score/cpu/h8300/rtems/score/types.h         |   47 -
>  doc/cpu_supplement/Makefile.am                     |    6 -
>  doc/cpu_supplement/cpu_supplement.texi             |    2 -
>  doc/cpu_supplement/h8300.t                         |   11 -
>  testsuites/libtests/configure.ac                   |    3 -
>  testsuites/psxtests/psx04/task3.c                  |    2 +-
>  27 files changed, 5 insertions(+), 1945 deletions(-)
>  delete mode 100644 c/src/lib/libbsp/h8300/Makefile.am
>  delete mode 100644 c/src/lib/libbsp/h8300/acinclude.m4
>  delete mode 100644 c/src/lib/libbsp/h8300/configure.ac
>  delete mode 100644 cpukit/score/cpu/h8300/Makefile.am
>  delete mode 100644 cpukit/score/cpu/h8300/README
>  delete mode 100644 cpukit/score/cpu/h8300/cpu.c
>  delete mode 100644 cpukit/score/cpu/h8300/cpu_asm.S
>  delete mode 100644 cpukit/score/cpu/h8300/h8300-exception-frame-print.c
>  delete mode 100644 cpukit/score/cpu/h8300/preinstall.am
>  delete mode 100644 cpukit/score/cpu/h8300/rtems/asm.h
>  delete mode 100644 cpukit/score/cpu/h8300/rtems/score/cpu.h
>  delete mode 100644 cpukit/score/cpu/h8300/rtems/score/cpuatomic.h
>  delete mode 100644 cpukit/score/cpu/h8300/rtems/score/h8300.h
>  delete mode 100644 cpukit/score/cpu/h8300/rtems/score/types.h
>  delete mode 100644 doc/cpu_supplement/h8300.t
>
> diff --git a/c/ACKNOWLEDGEMENTS b/c/ACKNOWLEDGEMENTS
> index 76956fd..25d4a0b 100644
> --- a/c/ACKNOWLEDGEMENTS
> +++ b/c/ACKNOWLEDGEMENTS
> @@ -150,9 +150,8 @@ The following persons/organizations have made contributions:
>    it easier to support external interrupt controllers.
>
>  + Joel Sherrill <joel at OARcorp.com> for the BSPs that work with
> -  numerous simulators including psim, c4xsim, h8sim, armulator,
> -  sim68000, and simcpu32.  Most of these BSPs work with instruction
> -  set simulators in gdb.
> +  numerous simulators. Many work with instruction set simulators
> +  in gdb.
>
>  + Darlene Stewart <Darlene.Stewart at nrc.ca> and Charles Gauthier
>    <Charles.Gauthier at nrc.ca> of the Institute for Information Technology
> @@ -165,10 +164,6 @@ The following persons/organizations have made contributions:
>    Technology for the National Research Council of Canada
>    submitted the RTEMS Cache Manager.
>
> -+ Philip Quaife <philip at qs.co.nz> of Q Solutions ported
> -  RTEMS to the Hitachi H8300H.  This effort was sponsored by
> -  Comnet Technologies Ltd.
> -
>  + Joel Sherrill <joel at OARcorp.com> and Jennifer Averett <jennifer at OARcorp.com>
>    for the Texas Instruments C3x/C4x port and c4xsim BSP that works
>    with the C3x/C4X instruction set simulator in gdb.
> diff --git a/c/TOOL_TARGETS b/c/TOOL_TARGETS
> index 4811277..3b22d81 100644
> --- a/c/TOOL_TARGETS
> +++ b/c/TOOL_TARGETS
> @@ -7,9 +7,6 @@ arm:
>  c4x:
>          c4x-rtems               COFF           Requires patches
>
> -h8300:
> -        h8300-rtems             COFF
> -
>  i386:
>         i386-rtems              ELF
>
> diff --git a/c/src/aclocal/check-networking.m4 b/c/src/aclocal/check-networking.m4
> index 53d2d36..69265ac 100644
> --- a/c/src/aclocal/check-networking.m4
> +++ b/c/src/aclocal/check-networking.m4
> @@ -8,7 +8,7 @@ AC_CACHE_CHECK([whether BSP supports networking],
>    [dnl
>      case "$RTEMS_CPU" in
>      # do not have address space to hold BSD TCP/IP stack
> -    avr*|h8300*|m32c*)
> +    avr*|m32c*)
>        rtems_cv_HAS_NETWORKING="no"
>        ;;
>      *)
> diff --git a/c/src/aclocal/rtems-cpu-subdirs.m4 b/c/src/aclocal/rtems-cpu-subdirs.m4
> index 3cb28b1..5f10bda 100644
> --- a/c/src/aclocal/rtems-cpu-subdirs.m4
> +++ b/c/src/aclocal/rtems-cpu-subdirs.m4
> @@ -14,7 +14,6 @@ _RTEMS_CPU_SUBDIR([arm],[$1]);;
>  _RTEMS_CPU_SUBDIR([bfin],[$1]);;
>  _RTEMS_CPU_SUBDIR([epiphany],[$1]);;
>  _RTEMS_CPU_SUBDIR([avr],[$1]);;
> -_RTEMS_CPU_SUBDIR([h8300],[$1]);;
>  _RTEMS_CPU_SUBDIR([i386],[$1]);;
>  _RTEMS_CPU_SUBDIR([lm32],[$1]);;
>  _RTEMS_CPU_SUBDIR([m32c],[$1]);;
> diff --git a/c/src/lib/libbsp/h8300/Makefile.am b/c/src/lib/libbsp/h8300/Makefile.am
> deleted file mode 100644
> index 140d76e..0000000
> --- a/c/src/lib/libbsp/h8300/Makefile.am
> +++ /dev/null
> @@ -1,7 +0,0 @@
> -ACLOCAL_AMFLAGS = -I ../../../aclocal
> -
> -# Descend into the @RTEMS_BSP_FAMILY@ directory
> -SUBDIRS = @RTEMS_BSP_FAMILY@
> -
> -include $(top_srcdir)/../../../automake/subdirs.am
> -include $(top_srcdir)/../../../automake/local.am
> diff --git a/c/src/lib/libbsp/h8300/acinclude.m4 b/c/src/lib/libbsp/h8300/acinclude.m4
> deleted file mode 100644
> index 296a6f7..0000000
> --- a/c/src/lib/libbsp/h8300/acinclude.m4
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -# RTEMS_CHECK_BSPDIR(RTEMS_BSP_FAMILY)
> -AC_DEFUN([RTEMS_CHECK_BSPDIR],
> -[
> -  case "$1" in
> -  *)
> -    AC_MSG_ERROR([Invalid BSP]);;
> -  esac
> -])
> diff --git a/c/src/lib/libbsp/h8300/configure.ac b/c/src/lib/libbsp/h8300/configure.ac
> deleted file mode 100644
> index e885460..0000000
> --- a/c/src/lib/libbsp/h8300/configure.ac
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -## Process this file with autoconf to produce a configure script.
> -
> -AC_PREREQ([2.69])
> -AC_INIT([rtems-c-src-lib-libbsp-h8300],[_RTEMS_VERSION],[https://devel.rtems.org/newticket])
> -AC_CONFIG_SRCDIR([Makefile.am])
> -RTEMS_TOP(../../../../..)
> -
> -RTEMS_CANONICAL_TARGET_CPU
> -AM_INIT_AUTOMAKE([no-define foreign 1.12.2])
> -AM_MAINTAINER_MODE
> -
> -RTEMS_ENV_RTEMSBSP
> -
> -RTEMS_PROJECT_ROOT
> -RTEMS_CHECK_BSPDIR([$RTEMS_BSP_FAMILY])
> -
> -# Explicitly list all Makefiles here
> -AC_CONFIG_FILES([Makefile])
> -AC_OUTPUT
> diff --git a/cpukit/aclocal/check-networking.m4 b/cpukit/aclocal/check-networking.m4
> index 06c94c0..50982f3 100644
> --- a/cpukit/aclocal/check-networking.m4
> +++ b/cpukit/aclocal/check-networking.m4
> @@ -9,7 +9,7 @@ AC_CACHE_CHECK([whether CPU supports networking],
>    [dnl
>      case "$host" in
>      # do not have address space to hold BSD TCP/IP stack
> -    avr*|h8300*|m32c*)
> +    avr*|m32c*)
>        rtems_cv_HAS_NETWORKING="no"
>        ;;
>      *-*-rtems*)
> diff --git a/cpukit/configure.ac b/cpukit/configure.ac
> index 8436c91..c5bbee8 100644
> --- a/cpukit/configure.ac
> +++ b/cpukit/configure.ac
> @@ -393,9 +393,6 @@ case $RTEMS_CPU in
>    # bfin has an issue to resolve with libdl. See ticket #2252
>    bfin)
>     HAVE_LIBDL=no ;;
> -  # h8300 has an issue to resolve with libdl. See ticket #2284
> -  h8300)
> -   HAVE_LIBDL=no ;;
>    # lm32 has an issue to resolve with libdl. See ticket #2283
>    lm32)
>     HAVE_LIBDL=no ;;
> @@ -457,7 +454,6 @@ score/cpu/arm/Makefile
>  score/cpu/bfin/Makefile
>  score/cpu/avr/Makefile
>  score/cpu/epiphany/Makefile
> -score/cpu/h8300/Makefile
>  score/cpu/i386/Makefile
>  score/cpu/lm32/Makefile
>  score/cpu/m68k/Makefile
> diff --git a/cpukit/librpc/src/xdr/xdr_float.c b/cpukit/librpc/src/xdr/xdr_float.c
> index 5d6b4ea..74d0bbc 100644
> --- a/cpukit/librpc/src/xdr/xdr_float.c
> +++ b/cpukit/librpc/src/xdr/xdr_float.c
> @@ -62,7 +62,6 @@ static char *rcsid = "$FreeBSD: src/lib/libc/xdr/xdr_float.c,v 1.7 1999/08/28 00
>      defined(_AM29K) || \
>      defined(__arm__) || \
>      defined(__epiphany__) ||  defined(__EPIPHANY__) || \
> -    defined(__H8300__) || defined(__h8300__) || \
>      defined(__hppa__) || \
>      defined(__i386__) || \
>      defined(__lm32__) || \
> diff --git a/cpukit/score/cpu/Makefile.am b/cpukit/score/cpu/Makefile.am
> index 4438e3f..a973a82 100644
> --- a/cpukit/score/cpu/Makefile.am
> +++ b/cpukit/score/cpu/Makefile.am
> @@ -5,7 +5,6 @@ DIST_SUBDIRS += arm
>  DIST_SUBDIRS += avr
>  DIST_SUBDIRS += bfin
>  DIST_SUBDIRS += epiphany
> -DIST_SUBDIRS += h8300
>  DIST_SUBDIRS += i386
>  DIST_SUBDIRS += lm32
>  DIST_SUBDIRS += m32c
> diff --git a/cpukit/score/cpu/h8300/Makefile.am b/cpukit/score/cpu/h8300/Makefile.am
> deleted file mode 100644
> index 6a80409..0000000
> --- a/cpukit/score/cpu/h8300/Makefile.am
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -include $(top_srcdir)/automake/compile.am
> -
> -include_rtemsdir = $(includedir)/rtems
> -include_rtems_HEADERS = rtems/asm.h
> -
> -include_rtems_scoredir = $(includedir)/rtems/score
> -include_rtems_score_HEADERS = rtems/score/cpu.h
> -include_rtems_score_HEADERS += rtems/score/h8300.h
> -include_rtems_score_HEADERS += rtems/score/types.h
> -include_rtems_score_HEADERS += rtems/score/cpuatomic.h
> -
> -noinst_LIBRARIES = libscorecpu.a
> -libscorecpu_a_SOURCES = cpu.c cpu_asm.S
> -libscorecpu_a_SOURCES += ../no_cpu/cpucounterread.c
> -libscorecpu_a_SOURCES += h8300-exception-frame-print.c
> -libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
> -
> -include $(srcdir)/preinstall.am
> -include $(top_srcdir)/automake/local.am
> diff --git a/cpukit/score/cpu/h8300/README b/cpukit/score/cpu/h8300/README
> deleted file mode 100644
> index 1fed837..0000000
> --- a/cpukit/score/cpu/h8300/README
> +++ /dev/null
> @@ -1,27 +0,0 @@
> -
> -This port was done by Philip Quaife <philip at qs.co.nz> of Q Solutions
> -using RTEMS 3.5.1 under DOS and Hiview.   Philip used an H8300H
> -to develop and test this port.
> -
> -It was updated to 4.5 and merged into the main development trunk
> -by Joel Sherrill <joel at OARcorp.com>.  As part of the merger, the
> -port was made to conditionally compile for the H8, H8300H, and H8300S
> -series.
> -
> -The status of each CPU subfamily is as follows.
> -
> -H8  - Although RTEMS compiles with for these CPUs, it does not
> -      truly support them.  All code that will not work on these
> -      CPUs is conditionally disabled.  These CPUs have a 16-bit
> -      address space.  Thus although a port is technically
> -      feasible, some work will to be performed on RTEMS to
> -      further minimize its footprint and address pointer
> -      manipulation issues.
> -
> -H8H - Port was developed on this class of H8 so there should be
> -      no problems.
> -
> -H8S - Port should work on this class of H8 but it is untested.
> -
> ---joel
> -28 June 2000
> diff --git a/cpukit/score/cpu/h8300/cpu.c b/cpukit/score/cpu/h8300/cpu.c
> deleted file mode 100644
> index 36c41a2..0000000
> --- a/cpukit/score/cpu/h8300/cpu.c
> +++ /dev/null
> @@ -1,134 +0,0 @@
> -/**
> - *  @file
> - *
> - *  @brief H8300 CPU Dependent Source
> - */
> -
> -/*
> - *  COPYRIGHT (c) 1989-1999.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifdef HAVE_CONFIG_H
> -#include "config.h"
> -#endif
> -
> -#include <rtems/system.h>
> -#include <rtems/score/isr.h>
> -#include <rtems/score/wkspace.h>
> -
> -/*  _CPU_Initialize
> - *
> - *  This routine performs processor dependent initialization.
> - *
> - *  INPUT PARAMETERS: NONE
> - */
> -
> -
> -void _CPU_Initialize(void)
> -{
> -  /*
> -   *  If there is not an easy way to initialize the FP context
> -   *  during Context_Initialize, then it is usually easier to
> -   *  save an "uninitialized" FP context here and copy it to
> -   *  the task's during Context_Initialize.
> -   */
> -
> -  /* FP context initialization support goes here */
> -}
> -
> -uint32_t   _CPU_ISR_Get_level( void )
> -{
> -  unsigned int _ccr;
> -
> -#if defined(__H8300__)
> -#warning "How do we get ccr on base CPU models"
> -#else
> -  __asm__ volatile ( "stc ccr, %0" : "=m" (_ccr) : );
> -#endif
> -
> -  if ( _ccr & 0x80 )
> -    return 1;
> -  return 0;
> -}
> -
> -/*
> - *  _CPU_ISR_install_raw_handler
> - */
> -
> -void _CPU_ISR_install_raw_handler(
> -  uint32_t    vector,
> -  proc_ptr    new_handler,
> -  proc_ptr   *old_handler
> -)
> -{
> -  /*
> -   *  This is where we install the interrupt handler into the "raw" interrupt
> -   *  table used by the CPU to dispatch interrupt handlers.
> -   *  Use Debug level IRQ Handlers
> -   */
> -  H8BD_Install_IRQ(vector,new_handler,old_handler);
> -}
> -
> -void _CPU_ISR_install_vector(
> -  uint32_t    vector,
> -  proc_ptr    new_handler,
> -  proc_ptr   *old_handler
> -)
> -{
> -   *old_handler = _ISR_Vector_table[ vector ];
> -
> -   /*
> -    *  If the interrupt vector table is a table of pointer to isr entry
> -    *  points, then we need to install the appropriate RTEMS interrupt
> -    *  handler for this vector number.
> -    */
> -
> -   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
> -
> -   /*
> -    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
> -    *  be used by the _ISR_Handler so the user gets control.
> -    */
> -
> -    _ISR_Vector_table[ vector ] = new_handler;
> -}
> -
> -/*
> - *  _CPU_Install_interrupt_stack
> - */
> -
> -void _CPU_Install_interrupt_stack( void )
> -{
> -}
> -
> -/*
> - *  _CPU_Thread_Idle_body
> - *
> - *  NOTES:
> - *
> - *  1. This is the same as the regular CPU independent algorithm.
> - *
> - *  2. If you implement this using a "halt", "idle", or "shutdown"
> - *     instruction, then don't forget to put it in an infinite loop.
> - *
> - *  3. Be warned. Some processors with onboard DMA have been known
> - *     to stop the DMA if the CPU were put in IDLE mode.  This might
> - *     also be a problem with other on-chip peripherals.  So use this
> - *     hook with caution.
> - */
> -
> -#if 0
> -void *_CPU_Thread_Idle_body( uintptr_t ignored )
> -{
> -
> -  for( ; ; )
> -    IDLE_Monitor();
> -       /* __asm__ ("   sleep   \n"); */
> -    /* insert your "halt" instruction here */ ;
> -}
> -#endif
> diff --git a/cpukit/score/cpu/h8300/cpu_asm.S b/cpukit/score/cpu/h8300/cpu_asm.S
> deleted file mode 100644
> index e0fdf0a..0000000
> --- a/cpukit/score/cpu/h8300/cpu_asm.S
> +++ /dev/null
> @@ -1,221 +0,0 @@
> -/*
> - * Hitachi H8 Score CPU functions
> - *   Copyright Comnet Technologies Ltd 1999
> - *
> - *  Based on example code and other ports with this copyright:
> - *
> - *  COPYRIGHT (c) 1989-1999.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifdef HAVE_CONFIG_H
> -#include "config.h"
> -#endif
> -
> -#include <rtems/asm.h>
> -#include <rtems/score/percpu.h>
> -
> -;.equ  RUNCONTEXT_ARG,  er0
> -;.equ  HEIRCONTEXT_ARG, er1
> -
> -/*
> - *  Make sure we tell the assembler what type of CPU model we are
> - *  being compiled for.
> - */
> -
> -#if defined(__H8300H__)
> -        .h8300h
> -#endif
> -#if defined(__H8300S__)
> -        .h8300s
> -#endif
> -#if defined(__H8300SX__)
> -        .h8300sx
> -#endif
> -        .text
> -
> -       .text
> -/*
> -       GCC Compiled with optimisations and Wimplicit decs to ensure
> -    that stack from doesn't change
> -
> -       Supposedly R2 and R3 do not need to be saved but who knows
> -
> -       Arg1 = er0      (not on stack)
> -       Arg2 = er1      (not on stack)
> -*/
> -
> -       .align 2
> -
> -       .global SYM(_CPU_Context_switch)
> -
> -SYM(_CPU_Context_switch):
> -       /* Save Context */
> -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
> -       stc.w   ccr,@(0:16,er0)
> -       mov.l   er7,@(2:16,er0)
> -       mov.l   er6,@(6:16,er0)
> -       mov.l   er5,@(10:16,er0)
> -       mov.l   er4,@(14:16,er0)
> -       mov.l   er3,@(18:16,er0)
> -       mov.l   er2,@(22:16,er0)
> -
> -       /* Install New context */
> -
> -restore:
> -       mov.l   @(22:16,er1),er2
> -       mov.l   @(18:16,er1),er3
> -       mov.l   @(14:16,er1),er4
> -       mov.l   @(10:16,er1),er5
> -       mov.l   @(6:16,er1),er6
> -       mov.l   @(2:16,er1),er7
> -       ldc.w   @(0:16,er1),ccr
> -#endif
> -
> -       rts
> -
> -       .align 2
> -
> -       .global SYM(_CPU_Context_restore)
> -
> -SYM(_CPU_Context_restore):
> -
> -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
> -       mov.l   er0,er1
> -       jmp             @restore:24
> -#endif
> -
> -
> -
> -/*
> -       VHandler for Vectored Interrupts
> -
> -       All IRQ's are vectored to routine _ISR_#vector_number
> -       This routine stacks er0 and loads er0 with vector number
> -       before transferring to here
> -
> -*/
> -       .align 2
> -       .global SYM(_ISR_Handler)
> -       .extern SYM(_Vector_table)
> -
> -
> -SYM(_ISR_Handler):
> -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
> -       mov.l   er1, at -er7
> -       mov.l   er2, at -er7
> -       mov.l   er3, at -er7
> -       mov.l   er4, at -er7
> -       mov.l   er5, at -er7
> -       mov.l   er6, at -er7
> -
> -/*  Set IRQ Stack */
> -       orc             #0xc0,ccr
> -       mov.l   er7,er6         ; save stack pointer
> -       mov.l   @ISR_NEST_LEVEL,er1
> -       bne             nested
> -       mov.l   @INTERRUPT_STACK_HIGH,er7
> -
> -nested:
> -       mov.l   er6, at -er7       ; save sp so pop regardless of nest level
> -
> -;; Inc  system counters
> -       mov.l   @ISR_NEST_LEVEL,er1
> -       inc.l   #1,er1
> -       mov.l   er1, at ISR_NEST_LEVEL
> -       mov.l   @THREAD_DISPATCH_DISABLE_LEVEL,er1
> -       inc.l   #1,er1
> -       mov.l   er1, at THREAD_DISPATCH_DISABLE_LEVEL
> -
> -/* Vector to ISR */
> -
> -       mov             er0,er2 ; copy vector
> -       shll.l  er2
> -       shll.l  er2             ; vector = vector * 4 (sizeof(int))
> -       mov.l   @(SYM(_ISR_Vector_table), er2),er1
> -       jsr             @er1    ; er0 = arg1 =vector
> -
> -       orc             #0xc0,ccr
> -       mov.l   @ISR_NEST_LEVEL,er1
> -       dec.l   #1,er1
> -       mov.l   er1, at ISR_NEST_LEVEL
> -       mov.l   @THREAD_DISPATCH_DISABLE_LEVEL,er1
> -       dec.l   #1,er1
> -       mov.l   er1, at THREAD_DISPATCH_DISABLE_LEVEL
> -       bne     exit
> -
> -       mov.l   @DISPATCH_NEEDED,er1
> -       beq     exit            ; If no then exit
> -
> -       /* Context switch here through ISR_Dispatch */
> -bframe:
> -       orc     #0xc0,ccr
> -/*     Pop Stack       */
> -       mov     @er7+,er6
> -       mov     er6,er7
> -
> -       /* Set up IRQ stack frame and dispatch to _ISR_Dispatch */
> -
> -       mov.l   #0xc0000000,er2         /* Disable IRQ */
> -       or.l    #SYM(_ISR_Dispatch),er2
> -       mov.l   er2, at -er7
> -       rte
> -
> -/*     Inner IRQ Return, pop flags and return */
> -exit:
> -/*     Pop Stack       */
> -       orc             #0x80,ccr
> -       mov             @er7+,er6
> -       mov             er6,er7
> -       mov             @er7+,er6
> -       mov             @er7+,er5
> -       mov             @er7+,er4
> -       mov             @er7+,er3
> -       mov             @er7+,er2
> -       mov             @er7+,er1
> -       mov             @er7+,er0
> -#endif
> -       rte
> -
> -/*
> -       Called from ISR_Handler as a way of ending IRQ
> -       but allowing dispatch to another task.
> -       Must use RTE as CCR is still on stack but IRQ has been serviced.
> -       CCR and PC occupy same word so rte can be used.
> -       now using task stack
> -*/
> -
> -       .align 2
> -       .global SYM(_ISR_Dispatch)
> -
> -SYM(_ISR_Dispatch):
> -
> -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
> -       jsr             @SYM(_Thread_Dispatch)
> -       mov             @er7+,er6
> -       mov             @er7+,er5
> -       mov             @er7+,er4
> -       mov             @er7+,er3
> -       mov             @er7+,er2
> -       mov             @er7+,er1
> -       mov             @er7+,er0
> -#endif
> -       rte
> -
> -
> -       .align 2
> -       .global SYM(_CPU_Context_save_fp)
> -
> -SYM(_CPU_Context_save_fp):
> -       rts
> -
> -
> -       .align 2
> -       .global SYM(_CPU_Context_restore_fp)
> -
> -SYM(_CPU_Context_restore_fp):
> -       rts
> diff --git a/cpukit/score/cpu/h8300/h8300-exception-frame-print.c b/cpukit/score/cpu/h8300/h8300-exception-frame-print.c
> deleted file mode 100644
> index 71e7e1c..0000000
> --- a/cpukit/score/cpu/h8300/h8300-exception-frame-print.c
> +++ /dev/null
> @@ -1,24 +0,0 @@
> -/*
> - * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
> - *
> - *  embedded brains GmbH
> - *  Obere Lagerstr. 30
> - *  82178 Puchheim
> - *  Germany
> - *  <rtems at embedded-brains.de>
> - *
> - * The license and distribution terms for this file may be
> - * found in the file LICENSE in this distribution or at
> - * http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifdef HAVE_CONFIG_H
> -  #include "config.h"
> -#endif
> -
> -#include <rtems/score/cpu.h>
> -
> -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
> -{
> -  /* TODO */
> -}
> diff --git a/cpukit/score/cpu/h8300/preinstall.am b/cpukit/score/cpu/h8300/preinstall.am
> deleted file mode 100644
> index f3c1681..0000000
> --- a/cpukit/score/cpu/h8300/preinstall.am
> +++ /dev/null
> @@ -1,45 +0,0 @@
> -## Automatically generated by ampolish3 - Do not edit
> -
> -if AMPOLISH3
> -$(srcdir)/preinstall.am: Makefile.am
> -       $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
> -endif
> -
> -PREINSTALL_DIRS =
> -DISTCLEANFILES = $(PREINSTALL_DIRS)
> -
> -all-am: $(PREINSTALL_FILES)
> -
> -PREINSTALL_FILES =
> -CLEANFILES = $(PREINSTALL_FILES)
> -
> -$(PROJECT_INCLUDE)/rtems/$(dirstamp):
> -       @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
> -       @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> -
> -$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
> -       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
> -
> -$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
> -       @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/score
> -       @: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -
> -$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
> -
> -$(PROJECT_INCLUDE)/rtems/score/h8300.h: rtems/score/h8300.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/h8300.h
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/h8300.h
> -
> -$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
> -
> -$(PROJECT_INCLUDE)/rtems/score/cpuatomic.h: rtems/score/cpuatomic.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
> -       $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
> -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpuatomic.h
> -
> diff --git a/cpukit/score/cpu/h8300/rtems/asm.h b/cpukit/score/cpu/h8300/rtems/asm.h
> deleted file mode 100644
> index 6c1a643..0000000
> --- a/cpukit/score/cpu/h8300/rtems/asm.h
> +++ /dev/null
> @@ -1,118 +0,0 @@
> -/**
> - * @file
> - *
> - * @brief Address the Problems Caused by Incompatible Flavor of
> - * Assemblers and Toolsets
> - *
> - * This include file attempts to address the problems
> - * caused by incompatible flavors of assemblers and
> - * toolsets.  It primarily addresses variations in the
> - * use of leading underscores on symbols and the requirement
> - * that register names be preceded by a %.
> - *
> - * NOTE: The spacing in the use of these macros
> - *       is critical to them working as advertised.
> - */
> -
> -/*
> - *  COPYRIGHT:
> - *
> - *  This file is based on similar code found in newlib available
> - *  from ftp.cygnus.com.  The file which was used had no copyright
> - *  notice.  This file is freely distributable as long as the source
> - *  of the file is noted.  This file is:
> - *
> - *
> - *  COPYRIGHT (c) 1989-1999.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifndef _RTEMS_ASM_H
> -#define _RTEMS_ASM_H
> -
> -/*
> - *  Indicate we are in an assembly file and get the basic CPU definitions.
> - */
> -
> -#include <rtems/score/h8300.h>
> -
> -/*
> - *  Recent versions of GNU cpp define variables which indicate the
> - *  need for underscores and percents.  If not using GNU cpp or
> - *  the version does not support this, then you will obviously
> - *  have to define these as appropriate.
> - */
> -
> -#ifndef __USER_LABEL_PREFIX__
> -#define __USER_LABEL_PREFIX__ _
> -#endif
> -
> -#ifndef __REGISTER_PREFIX__
> -#define __REGISTER_PREFIX__
> -#endif
> -
> -#include <rtems/concat.h>
> -
> -/* Use the right prefix for global labels.  */
> -
> -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
> -
> -/* Use the right prefix for registers.  */
> -
> -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
> -
> -/*
> - *  define macros for all of the registers on this CPU
> - *
> - *  EXAMPLE:     #define d0 REG (d0)
> - */
> -#define        r0      REG(r0)
> -#define r1     REG(r1)
> -#define r2     REG(r2)
> -#define r3     REG(r3)
> -#define r4     REG(r4)
> -#define r5     REG(r5)
> -#define r6     REG(r6)
> -#define r7     REG(r7)
> -
> -#define        er0     REG(er0)
> -#define er1    REG(er1)
> -#define er2    REG(er2)
> -#define er3    REG(er3)
> -#define er4    REG(er4)
> -#define er5    REG(er5)
> -#define er6    REG(er6)
> -#define er7    REG(er7)
> -
> -#define sp     REG(sp)
> -
> -/*
> - *  Define macros to handle section beginning and ends.
> - */
> -
> -
> -#define BEGIN_CODE_DCL .text
> -#define END_CODE_DCL
> -#define BEGIN_DATA_DCL .data
> -#define END_DATA_DCL
> -#define BEGIN_CODE __asm__ ( ".text
> -#define END_CODE ");
> -#define BEGIN_DATA
> -#define END_DATA
> -#define BEGIN_BSS
> -#define END_BSS
> -#define END
> -
> -/*
> - *  Following must be tailor for a particular flavor of the C compiler.
> - *  They may need to put underscores in front of the symbols.
> - */
> -
> -#define PUBLIC(sym) .globl SYM (sym)
> -#define EXTERN(sym) .globl SYM (sym)
> -
> -#endif
> diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h
> deleted file mode 100644
> index 8b34bb4..0000000
> --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h
> +++ /dev/null
> @@ -1,1176 +0,0 @@
> -/**
> - * @file
> - *
> - * @brief Hitachi H8300 CPU Department Source
> - *
> - * This include file contains information pertaining to the H8300
> - *  processor.
> - */
> -
> -/*
> - *  COPYRIGHT (c) 1989-2006.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifndef _RTEMS_SCORE_CPU_H
> -#define _RTEMS_SCORE_CPU_H
> -
> -#ifdef __cplusplus
> -extern "C" {
> -#endif
> -
> -#include <rtems/score/types.h>
> -#include <rtems/score/h8300.h>
> -#ifndef ASM
> -  #include <rtems/bspIo.h>
> -#endif
> -
> -/* conditional compilation parameters */
> -
> -/*
> - *  Should the calls to _Thread_Enable_dispatch be inlined?
> - *
> - *  If TRUE, then they are inlined.
> - *  If FALSE, then a subroutine call is made.
> - *
> - *  Basically this is an example of the classic trade-off of size
> - *  versus speed.  Inlining the call (TRUE) typically increases the
> - *  size of RTEMS while speeding up the enabling of dispatching.
> - *  [NOTE: In general, the _Thread_Dispatch_disable_level will
> - *  only be 0 or 1 unless you are in an interrupt handler and that
> - *  interrupt handler invokes the executive.]  When not inlined
> - *  something calls _Thread_Enable_dispatch which in turns calls
> - *  _Thread_Dispatch.  If the enable dispatch is inlined, then
> - *  one subroutine call is avoided entirely.]
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_INLINE_ENABLE_DISPATCH       FALSE
> -
> -/*
> - *  Should this target use 16 or 32 bit object Ids?
> - *
> - */
> -#define RTEMS_USE_16_BIT_OBJECT
> -
> -/*
> - *  Does RTEMS manage a dedicated interrupt stack in software?
> - *
> - *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
> - *  If FALSE, nothing is done.
> - *
> - *  If the CPU supports a dedicated interrupt stack in hardware,
> - *  then it is generally the responsibility of the BSP to allocate it
> - *  and set it up.
> - *
> - *  If the CPU does not support a dedicated interrupt stack, then
> - *  the porter has two options: (1) execute interrupts on the
> - *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
> - *  interrupt stack.
> - *
> - *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
> - *
> - *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
> - *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
> - *  possible that both are FALSE for a particular CPU.  Although it
> - *  is unclear what that would imply about the interrupt processing
> - *  procedure on that CPU.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
> -
> -/*
> - *  Does the CPU follow the simple vectored interrupt model?
> - *
> - *  If TRUE, then RTEMS allocates the vector table it internally manages.
> - *  If FALSE, then the BSP is assumed to allocate and manage the vector
> - *  table
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX document implementation including references if appropriate
> - */
> -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
> -
> -/*
> - *  Does this CPU have hardware support for a dedicated interrupt stack?
> - *
> - *  If TRUE, then it must be installed during initialization.
> - *  If FALSE, then no installation is performed.
> - *
> - *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
> - *
> - *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
> - *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
> - *  possible that both are FALSE for a particular CPU.  Although it
> - *  is unclear what that would imply about the interrupt processing
> - *  procedure on that CPU.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
> -
> -/*
> - *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
> - *
> - *  If TRUE, then the memory is allocated during initialization.
> - *  If FALSE, then the memory is allocated during initialization.
> - *
> - *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
> -
> -/*
> - *  Does the CPU have hardware floating point?
> - *
> - *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
> - *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
> - *
> - *  If there is a FP coprocessor such as the i387 or mc68881, then
> - *  the answer is TRUE.
> - *
> - *  The macro name "H8300_HAS_FPU" should be made CPU specific.
> - *  It indicates whether or not this CPU model has FP support.  For
> - *  example, it would be possible to have an i386_nofp CPU model
> - *  which set this to false to indicate that you have an i386 without
> - *  an i387 and wish to leave floating point support out of RTEMS.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_HARDWARE_FP     FALSE
> -
> -/*
> - *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
> - *
> - *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
> - *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
> - *
> - *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_ALL_TASKS_ARE_FP     FALSE
> -
> -/*
> - *  Should the IDLE task have a floating point context?
> - *
> - *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
> - *  and it has a floating point context which is switched in and out.
> - *  If FALSE, then the IDLE task does not have a floating point context.
> - *
> - *  Setting this to TRUE negatively impacts the time required to preempt
> - *  the IDLE task from an interrupt because the floating point context
> - *  must be saved as part of the preemption.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_IDLE_TASK_IS_FP      FALSE
> -
> -/*
> - *  Should the saving of the floating point registers be deferred
> - *  until a context switch is made to another different floating point
> - *  task?
> - *
> - *  If TRUE, then the floating point context will not be stored until
> - *  necessary.  It will remain in the floating point registers and not
> - *  disturned until another floating point task is switched to.
> - *
> - *  If FALSE, then the floating point context is saved when a floating
> - *  point task is switched out and restored when the next floating point
> - *  task is restored.  The state of the floating point registers between
> - *  those two operations is not specified.
> - *
> - *  If the floating point context does NOT have to be saved as part of
> - *  interrupt dispatching, then it should be safe to set this to TRUE.
> - *
> - *  Setting this flag to TRUE results in using a different algorithm
> - *  for deciding when to save and restore the floating point context.
> - *  The deferred FP switch algorithm minimizes the number of times
> - *  the FP context is saved and restored.  The FP context is not saved
> - *  until a context switch is made to another, different FP task.
> - *  Thus in a system with only one FP task, the FP context will never
> - *  be saved or restored.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
> -
> -/*
> - *  Does this port provide a CPU dependent IDLE task implementation?
> - *
> - *  If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
> - *  must be provided and is the default IDLE thread body instead of
> - *  _Internal_threads_Idle_thread_body.
> - *
> - *  If FALSE, then use the generic IDLE thread body if the BSP does
> - *  not provide one.
> - *
> - *  This is intended to allow for supporting processors which have
> - *  a low power or idle mode.  When the IDLE thread is executed, then
> - *  the CPU can be powered down.
> - *
> - *  The order of precedence for selecting the IDLE thread body is:
> - *
> - *    1.  BSP provided
> - *    2.  CPU dependent (if provided)
> - *    3.  generic (if no BSP and no CPU dependent)
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - *  The port initially called a BSP dependent routine called
> - *  IDLE_Monitor.  The idle task body can be overridden by
> - *  the BSP in newer versions of RTEMS.
> - */
> -
> -#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
> -
> -/*
> - *  Does the stack grow up (toward higher addresses) or down
> - *  (toward lower addresses)?
> - *
> - *  If TRUE, then the grows upward.
> - *  If FALSE, then the grows toward smaller addresses.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_STACK_GROWS_UP               FALSE
> -
> -/*
> - *  The following is the variable attribute used to force alignment
> - *  of critical RTEMS structures.  On some processors it may make
> - *  sense to have these aligned on tighter boundaries than
> - *  the minimum requirements of the compiler in order to have as
> - *  much of the critical data area as possible in a cache line.
> - *
> - *  The placement of this macro in the declaration of the variables
> - *  is based on the syntactically requirements of the GNU C
> - *  "__attribute__" extension.  For example with GNU C, use
> - *  the following to force a structures to a 32 byte boundary.
> - *
> - *      __attribute__ ((aligned (32)))
> - *
> - *  NOTE:  Currently only the Priority Bit Map table uses this feature.
> - *         To benefit from using this, the data must be heavily
> - *         used so it will stay in the cache and used frequently enough
> - *         in the executive to justify turning this on.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_STRUCTURE_ALIGNMENT
> -
> -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
> -
> -/*
> - *  Define what is required to specify how the network to host conversion
> - *  routines are handled.
> - */
> -
> -#define CPU_BIG_ENDIAN                           TRUE
> -#define CPU_LITTLE_ENDIAN                        FALSE
> -
> -/*
> - *  The following defines the number of bits actually used in the
> - *  interrupt field of the task mode.  How those bits map to the
> - *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_MODES_INTERRUPT_MASK   0x00000001
> -
> -#define CPU_PER_CPU_CONTROL_SIZE 0
> -
> -/*
> - *  Processor defined structures required for cpukit/score.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -/* may need to put some structures here.  */
> -
> -/*
> - * Contexts
> - *
> - *  Generally there are 2 types of context to save.
> - *     1. Interrupt registers to save
> - *     2. Task level registers to save
> - *
> - *  This means we have the following 3 context items:
> - *     1. task level context stuff::  Context_Control
> - *     2. floating point task stuff:: Context_Control_fp
> - *     3. special interrupt level context :: Context_Control_interrupt
> - *
> - *  On some processors, it is cost-effective to save only the callee
> - *  preserved registers during a task context switch.  This means
> - *  that the ISR code needs to save those registers which do not
> - *  persist across function calls.  It is not mandatory to make this
> - *  distinctions between the caller/callee saves registers for the
> - *  purpose of minimizing context saved during task switch and on interrupts.
> - *  If the cost of saving extra registers is minimal, simplicity is the
> - *  choice.  Save the same context on interrupt entry as for tasks in
> - *  this case.
> - *
> - *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
> - *  care should be used in designing the context area.
> - *
> - *  On some CPUs with hardware floating point support, the Context_Control_fp
> - *  structure will not be used or it simply consist of an array of a
> - *  fixed number of bytes.   This is done when the floating point context
> - *  is dumped by a "FP save context" type instruction and the format
> - *  is not really defined by the CPU.  In this case, there is no need
> - *  to figure out the exact format -- only the size.  Of course, although
> - *  this is enough information for RTEMS, it is probably not enough for
> - *  a debugger such as gdb.  But that is another problem.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#ifndef ASM
> -
> -typedef struct {
> -  /* There is no CPU specific per-CPU state */
> -} CPU_Per_CPU_control;
> -
> -#define nogap __attribute__ ((packed))
> -
> -typedef struct {
> -    uint16_t    ccr nogap;
> -    void       *er7 nogap;
> -    void       *er6 nogap;
> -    uint32_t    er5 nogap;
> -    uint32_t   er4 nogap;
> -    uint32_t    er3 nogap;
> -    uint32_t   er2 nogap;
> -    uint32_t    er1 nogap;
> -    uint32_t   er0 nogap;
> -    uint32_t    xxx nogap;
> -} Context_Control;
> -
> -#define _CPU_Context_Get_SP( _context ) \
> -  (_context)->er7
> -
> -typedef struct {
> -    double      some_float_register[2];
> -} Context_Control_fp;
> -
> -typedef struct {
> -    uint32_t   special_interrupt_register;
> -} CPU_Interrupt_frame;
> -
> -/*
> - *  This variable is optional.  It is used on CPUs on which it is difficult
> - *  to generate an "uninitialized" FP context.  It is filled in by
> - *  _CPU_Initialize and copied into the task's FP context area during
> - *  _CPU_Context_Initialize.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
> -
> -/*
> - *  Nothing prevents the porter from declaring more CPU specific variables.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -/* XXX: if needed, put more variables here */
> -
> -/*
> - *  The size of the floating point context area.  On some CPUs this
> - *  will not be a "sizeof" because the format of the floating point
> - *  area is not defined -- only the size is.  This is usually on
> - *  CPUs with a "floating point save context" instruction.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
> -
> -#endif /* ASM */
> -
> -/*
> - *  Amount of extra stack (above minimum stack size) required by
> - *  system initialization thread.  Remember that in a multiprocessor
> - *  system the system intialization thread becomes the MP server thread.
> - *
> - *  H8300 Specific Information:
> - *
> - *  It is highly unlikely the H8300 will get used in a multiprocessor system.
> - */
> -
> -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
> -
> -/*
> - *  This defines the number of entries in the ISR_Vector_table managed
> - *  by RTEMS.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
> -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
> -
> -/*
> - *  This is defined if the port has a special way to report the ISR nesting
> - *  level.  Most ports maintain the variable _ISR_Nest_level.
> - */
> -
> -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
> -
> -/*
> - *  Should be large enough to run all RTEMS tests.  This ensures
> - *  that a "reasonable" small application should not have any problems.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_STACK_MINIMUM_SIZE          (1536)
> -
> -#if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__)
> -  #define CPU_SIZEOF_POINTER 4
> -#else
> -  #define CPU_SIZEOF_POINTER 2
> -#endif
> -
> -/*
> - *  CPU's worst alignment requirement for data types on a byte boundary.  This
> - *  alignment does not take into account the requirements for the stack.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_ALIGNMENT              8
> -
> -/*
> - *  This number corresponds to the byte alignment requirement for the
> - *  heap handler.  This alignment requirement may be stricter than that
> - *  for the data types alignment specified by CPU_ALIGNMENT.  It is
> - *  common for the heap to follow the same alignment requirement as
> - *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
> - *  then this should be set to CPU_ALIGNMENT.
> - *
> - *  NOTE:  This does not have to be a power of 2.  It does have to
> - *         be greater or equal to than CPU_ALIGNMENT.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
> -
> -/*
> - *  This number corresponds to the byte alignment requirement for memory
> - *  buffers allocated by the partition manager.  This alignment requirement
> - *  may be stricter than that for the data types alignment specified by
> - *  CPU_ALIGNMENT.  It is common for the partition to follow the same
> - *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
> - *  enough for the partition, then this should be set to CPU_ALIGNMENT.
> - *
> - *  NOTE:  This does not have to be a power of 2.  It does have to
> - *         be greater or equal to than CPU_ALIGNMENT.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
> -
> -/*
> - *  This number corresponds to the byte alignment requirement for the
> - *  stack.  This alignment requirement may be stricter than that for the
> - *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
> - *  is strict enough for the stack, then this should be set to 0.
> - *
> - *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_STACK_ALIGNMENT        2
> -
> -/*
> - *  ISR handler macros
> - */
> -
> -/*
> - *  Support routine to initialize the RTEMS vector table after it is allocated.
> - */
> -
> -#define _CPU_Initialize_vectors()
> -
> -/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
> -   Note requires ISR_Level be uint16_t or assembler croaks.
> -*/
> -
> -#if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 )
> -
> -
> -/*
> - *  Disable all interrupts for an RTEMS critical section.  The previous
> - *  level is returned in _level.
> - */
> -
> -#define _CPU_ISR_Disable( _isr_cookie ) \
> -  do { \
> -    __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" :  : "r" (_isr_cookie) ); \
> -  } while (0)
> -
> -
> -/*
> - *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
> - *  This indicates the end of an RTEMS critical section.  The parameter
> - *  _level is not modified.
> - */
> -
> -
> -#define _CPU_ISR_Enable( _isr_cookie )  \
> -  do { \
> -    __asm__ volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr" :  : "r" (_isr_cookie) ); \
> -  } while (0)
> -
> -
> -/*
> - *  This temporarily restores the interrupt to _level before immediately
> - *  disabling them again.  This is used to divide long RTEMS critical
> - *  sections into two or more parts.  The parameter _level is not
> - * modified.
> - */
> -
> -
> -#define _CPU_ISR_Flash( _isr_cookie ) \
> -  do { \
> -    __asm__ volatile( "mov.w %0, at -er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" :  : "r" (_isr_cookie) ); \
> -  } while (0)
> -
> -/* end of ISR handler macros */
> -
> -#else /* modern gcc version */
> -
> -/*
> - *  Disable all interrupts for an RTEMS critical section.  The previous
> - *  level is returned in _level.
> - *
> - *  H8300 Specific Information:
> - *
> - *  TODO: As of 8 October 2014, this method is not implemented for the SX.
> - */
> -
> -#if defined(__H8300H__) || defined(__H8300S__)
> -#define _CPU_ISR_Disable( _isr_cookie ) \
> -  do { \
> -    unsigned char __ccr; \
> -    __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \
> -             : "=m" (__ccr) /* : "0" (__ccr) */ ); \
> -    (_isr_cookie) = __ccr; \
> -  } while (0)
> -#else
> -#define _CPU_ISR_Disable( _isr_cookie ) \
> -  do { \
> -    (_isr_cookie) = 0; \
> -  } while (0)
> -#endif
> -
> -
> -/*
> - *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
> - *  This indicates the end of an RTEMS critical section.  The parameter
> - *  _level is not modified.
> - *
> - *  H8300 Specific Information:
> - *
> - *  TODO: As of 8 October 2014, this method is not implemented for the SX.
> - */
> -
> -#if defined(__H8300H__) || defined(__H8300S__)
> -#define _CPU_ISR_Enable( _isr_cookie )  \
> -  do { \
> -    unsigned char __ccr = (unsigned char) (_isr_cookie); \
> -    __asm__ volatile( "ldc %0, ccr" :  : "m" (__ccr) ); \
> -  } while (0)
> -#else
> -#define _CPU_ISR_Enable( _isr_cookie ) \
> -  do { \
> -    (_isr_cookie) = (_isr_cookie); \
> -  } while (0)
> -#endif
> -
> -/*
> - *  This temporarily restores the interrupt to _level before immediately
> - *  disabling them again.  This is used to divide long RTEMS critical
> - *  sections into two or more parts.  The parameter _level is not
> - *  modified.
> - *
> - *  H8300 Specific Information:
> - *
> - *  TODO: As of 8 October 2014, this method is not implemented for the SX.
> - */
> -
> -#if defined(__H8300H__) || defined(__H8300S__)
> -#define _CPU_ISR_Flash( _isr_cookie ) \
> -  do { \
> -    unsigned char __ccr = (unsigned char) (_isr_cookie); \
> -    __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " :  : "m" (__ccr) ); \
> -  } while (0)
> -#else
> -#define _CPU_ISR_Flash( _isr_cookie ) \
> -  do { \
> -    _CPU_ISR_Enable( _isr_cookie ); \
> -    _CPU_ISR_Disable( _isr_cookie ); \
> -  } while (0)
> -#endif
> -
> -#endif /* end of old gcc */
> -
> -
> -/*
> - *  Map interrupt level in task mode onto the hardware that the CPU
> - *  actually provides.  Currently, interrupt levels which do not
> - *  map onto the CPU in a generic fashion are undefined.  Someday,
> - *  it would be nice if these were "mapped" by the application
> - *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
> - *  8 - 255 would be available for bsp/application specific meaning.
> - *  This could be used to manage a programmable interrupt controller
> - *  via the rtems_task_mode directive.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define _CPU_ISR_Set_level( _new_level ) \
> -  { \
> -    if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \
> -    else              __asm__ volatile ( "andc #0x7f,ccr\n" ); \
> -  }
> -
> -#ifndef ASM
> -
> -uint32_t   _CPU_ISR_Get_level( void );
> -
> -/* end of ISR handler macros */
> -
> -/* Context handler macros */
> -
> -/*
> - *  Initialize the context to a state suitable for starting a
> - *  task after a context restore operation.  Generally, this
> - *  involves:
> - *
> - *     - setting a starting address
> - *     - preparing the stack
> - *     - preparing the stack and frame pointers
> - *     - setting the proper interrupt level in the context
> - *     - initializing the floating point context
> - *
> - *  This routine generally does not set any unnecessary register
> - *  in the context.  The state of the "general data" registers is
> - *  undefined at task start time.
> - *
> - *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
> - *        point thread.  This is typically only used on CPUs where the
> - *        FPU may be easily disabled by software such as on the SPARC
> - *        where the PSR contains an enable FPU bit.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -
> -#define CPU_CCR_INTERRUPTS_ON  0x80
> -#define CPU_CCR_INTERRUPTS_OFF 0x00
> -
> -#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
> -                                   _isr, _entry_point, _is_fp, _tls_area ) \
> -  /* Locate Me */ \
> -  do { \
> -    uintptr_t   _stack; \
> -    \
> -    if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \
> -    else          (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \
> -    \
> -    (void) _is_fp; /* to eliminate set but not used warning */ \
> -    _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \
> -    *((proc_ptr *)(_stack)) = (_entry_point); \
> -     (_the_context)->er7     = (void *) _stack; \
> -     (_the_context)->er6     = (void *) _stack; \
> -     (_the_context)->er5     = 0; \
> -     (_the_context)->er4     = 1; \
> -     (_the_context)->er3     = 2; \
> -  } while (0)
> -
> -
> -/*
> - *  This routine is responsible for somehow restarting the currently
> - *  executing task.  If you are lucky, then all that is necessary
> - *  is restoring the context.  Otherwise, there will need to be
> - *  a special assembly routine which does something special in this
> - *  case.  Context_Restore should work most of the time.  It will
> - *  not work if restarting self conflicts with the stack frame
> - *  assumptions of restoring a context.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define _CPU_Context_Restart_self( _the_context ) \
> -   _CPU_Context_restore( (_the_context) );
> -
> -/*
> - *  The purpose of this macro is to allow the initial pointer into
> - *  a floating point context area (used to save the floating point
> - *  context) to be at an arbitrary place in the floating point
> - *  context area.
> - *
> - *  This is necessary because some FP units are designed to have
> - *  their context saved as a stack which grows into lower addresses.
> - *  Other FP units can be saved by simply moving registers into offsets
> - *  from the base of the context area.  Finally some FP units provide
> - *  a "dump context" instruction which could fill in from high to low
> - *  or low to high based on the whim of the CPU designers.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define _CPU_Context_Fp_start( _base, _offset ) \
> -   ( (void *) (_base) + (_offset) )
> -
> -/*
> - *  This routine initializes the FP context area passed to it to.
> - *  There are a few standard ways in which to initialize the
> - *  floating point context.  The code included for this macro assumes
> - *  that this is a CPU in which a "initial" FP context was saved into
> - *  _CPU_Null_fp_context and it simply copies it to the destination
> - *  context passed to it.
> - *
> - *  Other models include (1) not doing anything, and (2) putting
> - *  a "null FP status word" in the correct place in the FP context.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define _CPU_Context_Initialize_fp( _destination ) \
> -  { \
> -   *(*(_destination)) = _CPU_Null_fp_context; \
> -  }
> -
> -/* end of Context handler macros */
> -
> -/* Fatal Error manager macros */
> -
> -/*
> - *  This routine copies _error into a known place -- typically a stack
> - *  location or a register, optionally disables interrupts, and
> - *  halts/stops the CPU.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define _CPU_Fatal_halt( _source, _error ) \
> -       printk("Fatal Error %d.%d Halted\n",_source, _error); \
> -       for(;;)
> -
> -
> -/* end of Fatal Error manager macros */
> -
> -/* Bitfield handler macros */
> -
> -/*
> - *  This routine sets _output to the bit number of the first bit
> - *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
> - *  This type may be either 16 or 32 bits wide although only the 16
> - *  least significant bits will be used.
> - *
> - *  There are a number of variables in using a "find first bit" type
> - *  instruction.
> - *
> - *    (1) What happens when run on a value of zero?
> - *    (2) Bits may be numbered from MSB to LSB or vice-versa.
> - *    (3) The numbering may be zero or one based.
> - *    (4) The "find first bit" instruction may search from MSB or LSB.
> - *
> - *  RTEMS guarantees that (1) will never happen so it is not a concern.
> - *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
> - *  _CPU_Priority_bits_index().  These three form a set of routines
> - *  which must logically operate together.  Bits in the _value are
> - *  set and cleared based on masks built by _CPU_Priority_mask().
> - *  The basic major and minor values calculated by _Priority_Major()
> - *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
> - *  to properly range between the values returned by the "find first bit"
> - *  instruction.  This makes it possible for _Priority_Get_highest() to
> - *  calculate the major and directly index into the minor table.
> - *  This mapping is necessary to ensure that 0 (a high priority major/minor)
> - *  is the first bit found.
> - *
> - *  This entire "find first bit" and mapping process depends heavily
> - *  on the manner in which a priority is broken into a major and minor
> - *  components with the major being the 4 MSB of a priority and minor
> - *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
> - *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
> - *  to the lowest priority.
> - *
> - *  If your CPU does not have a "find first bit" instruction, then
> - *  there are ways to make do without it.  Here are a handful of ways
> - *  to implement this in software:
> - *
> - *    - a series of 16 bit test instructions
> - *    - a "binary search using if's"
> - *    - _number = 0
> - *      if _value > 0x00ff
> - *        _value >>=8
> - *        _number = 8;
> - *
> - *      if _value > 0x0000f
> - *        _value >=8
> - *        _number += 4
> - *
> - *      _number += bit_set_table[ _value ]
> - *
> - *    where bit_set_table[ 16 ] has values which indicate the first
> - *      bit set
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
> -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
> -
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> -
> -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
> -  { \
> -    (_output) = 0;   /* do something to prevent warnings */ \
> -  }
> -
> -#endif
> -
> -/* end of Bitfield handler macros */
> -
> -/*
> - *  This routine builds the mask which corresponds to the bit fields
> - *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
> - *  for that routine.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> -
> -#define _CPU_Priority_Mask( _bit_number ) \
> -  ( 1 << (_bit_number) )
> -
> -#endif
> -
> -/*
> - *  This routine translates the bit numbers returned by
> - *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
> - *  a major or minor component of a priority.  See the discussion
> - *  for that routine.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
> -
> -#define _CPU_Priority_bits_index( _priority ) \
> -  (_priority)
> -
> -#endif
> -
> -/* end of Priority handler macros */
> -
> -/* functions */
> -
> -/*
> - *  _CPU_Initialize
> - *
> - *  This routine performs CPU dependent initialization.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Initialize(void);
> -
> -/*
> - *  _CPU_ISR_install_raw_handler
> - *
> - *  This routine installs a "raw" interrupt handler directly into the
> - *  processor's vector table.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_ISR_install_raw_handler(
> -  uint32_t    vector,
> -  proc_ptr    new_handler,
> -  proc_ptr   *old_handler
> -);
> -
> -/*
> - *  _CPU_ISR_install_vector
> - *
> - *  This routine installs an interrupt vector.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_ISR_install_vector(
> -  uint32_t    vector,
> -  proc_ptr    new_handler,
> -  proc_ptr   *old_handler
> -);
> -
> -/*
> - *  _CPU_Install_interrupt_stack
> - *
> - *  This routine installs the hardware interrupt stack pointer.
> - *
> - *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
> - *         is TRUE.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Install_interrupt_stack( void );
> -
> -/*
> - *  _CPU_Internal_threads_Idle_thread_body
> - *
> - *  This routine is the CPU dependent IDLE thread body.
> - *
> - *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
> - *         is TRUE.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void *_CPU_Thread_Idle_body( uint32_t );
> -
> -/*
> - *  _CPU_Context_switch
> - *
> - *  This routine switches from the run context to the heir context.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Context_switch(
> -  Context_Control  *run,
> -  Context_Control  *heir
> -);
> -
> -/*
> - *  _CPU_Context_restore
> - *
> - *  This routine is generallu used only to restart self in an
> - *  efficient manner.  It may simply be a label in _CPU_Context_switch.
> - *
> - *  NOTE: May be unnecessary to reload some registers.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Context_restore(
> -  Context_Control *new_context
> -) RTEMS_NO_RETURN;
> -
> -/*
> - *  _CPU_Context_save_fp
> - *
> - *  This routine saves the floating point context passed to it.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Context_save_fp(
> -  Context_Control_fp **fp_context_ptr
> -);
> -
> -/*
> - *  _CPU_Context_restore_fp
> - *
> - *  This routine restores the floating point context passed to it.
> - *
> - *  H8300 Specific Information:
> - *
> - *  XXX
> - */
> -
> -void _CPU_Context_restore_fp(
> -  Context_Control_fp **fp_context_ptr
> -);
> -
> -static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
> -{
> -  /* TODO */
> -}
> -
> -static inline void _CPU_Context_validate( uintptr_t pattern )
> -{
> -  while (1) {
> -    /* TODO */
> -  }
> -}
> -
> -/* FIXME */
> -typedef CPU_Interrupt_frame CPU_Exception_frame;
> -
> -void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
> -
> -/*  The following routine swaps the endian format of an unsigned int.
> - *  It must be static because it is referenced indirectly.
> - *
> - *  This version will work on any processor, but if there is a better
> - *  way for your CPU PLEASE use it.  The most common way to do this is to:
> - *
> - *     swap least significant two bytes with 16-bit rotate
> - *     swap upper and lower 16-bits
> - *     swap most significant two bytes with 16-bit rotate
> - *
> - *  Some CPUs have special instructions which swap a 32-bit quantity in
> - *  a single instruction (e.g. i486).  It is probably best to avoid
> - *  an "endian swapping control bit" in the CPU.  One good reason is
> - *  that interrupts would probably have to be disabled to ensure that
> - *  an interrupt does not try to access the same "chunk" with the wrong
> - *  endian.  Another good reason is that on some CPUs, the endian bit
> - *  endianness for ALL fetches -- both code and data -- so the code
> - *  will be fetched incorrectly.
> - *
> - *  H8300 Specific Information:
> - *
> - *  This is the generic implementation.
> - */
> -
> -static inline uint32_t   CPU_swap_u32(
> -  uint32_t   value
> -)
> -{
> -  uint32_t   byte1, byte2, byte3, byte4, swapped;
> -
> -  byte4 = (value >> 24) & 0xff;
> -  byte3 = (value >> 16) & 0xff;
> -  byte2 = (value >> 8)  & 0xff;
> -  byte1 =  value        & 0xff;
> -
> -  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
> -  return( swapped );
> -}
> -
> -#define CPU_swap_u16( value ) \
> -  (((value&0xff) << 8) | ((value >> 8)&0xff))
> -
> -typedef uint32_t CPU_Counter_ticks;
> -
> -CPU_Counter_ticks _CPU_Counter_read( void );
> -
> -static inline CPU_Counter_ticks _CPU_Counter_difference(
> -  CPU_Counter_ticks second,
> -  CPU_Counter_ticks first
> -)
> -{
> -  return second - first;
> -}
> -
> -/* to be provided by the BSP */
> -extern void H8BD_Install_IRQ(
> -  uint32_t     vector,
> -  proc_ptr     new_handler,
> -  proc_ptr     *old_handler );
> -
> -#endif /* ASM */
> -
> -#ifdef __cplusplus
> -}
> -#endif
> -
> -#endif
> diff --git a/cpukit/score/cpu/h8300/rtems/score/cpuatomic.h b/cpukit/score/cpu/h8300/rtems/score/cpuatomic.h
> deleted file mode 100644
> index 598ee76..0000000
> --- a/cpukit/score/cpu/h8300/rtems/score/cpuatomic.h
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -/*
> - * COPYRIGHT (c) 2012-2013 Deng Hengyi.
> - *
> - * The license and distribution terms for this file may be
> - * found in the file LICENSE in this distribution or at
> - * http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifndef _RTEMS_SCORE_ATOMIC_CPU_H
> -#define _RTEMS_SCORE_ATOMIC_CPU_H
> -
> -#include <rtems/score/cpustdatomic.h>
> -
> -#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */
> diff --git a/cpukit/score/cpu/h8300/rtems/score/h8300.h b/cpukit/score/cpu/h8300/rtems/score/h8300.h
> deleted file mode 100644
> index e30343c..0000000
> --- a/cpukit/score/cpu/h8300/rtems/score/h8300.h
> +++ /dev/null
> @@ -1,44 +0,0 @@
> -/**
> - * @file
> - *
> - * @brief Information Required to Build RTEMS for a Particular Member
> - * of the Hitachi H8/300 Family
> - *
> - * This file contains information pertaining to the Hitachi H8/300
> - * processor family.
> - */
> -
> -/*
> - *  COPYRIGHT (c) 1989-1999.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifndef _RTEMS_SCORE_H8300_H
> -#define _RTEMS_SCORE_H8300_H
> -
> -#ifdef __cplusplus
> -extern "C" {
> -#endif
> -
> -/*
> - *  This file contains the information required to build
> - *  RTEMS for a particular member of the "h8300"
> - *  family when executing in protected mode.  It does
> - *  this by setting variables to indicate which implementation
> - *  dependent features are present in a particular member
> - *  of the family.
> - */
> -
> -#define CPU_NAME  "Hitachi H8300"
> -#define CPU_MODEL_NAME  "h8300"
> -#define H8300_HAS_FPU     0
> -
> -#ifdef __cplusplus
> -}
> -#endif
> -
> -#endif
> diff --git a/cpukit/score/cpu/h8300/rtems/score/types.h b/cpukit/score/cpu/h8300/rtems/score/types.h
> deleted file mode 100644
> index 7fcac8b..0000000
> --- a/cpukit/score/cpu/h8300/rtems/score/types.h
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -/**
> - * @file
> - *
> - * @brief Hitachi H8300 CPU Type Definitions
> - *
> - * This include file contains type definitions pertaining to the Hitachi
> - * h8300 processor family.
> - */
> -
> -/*
> - *  COPYRIGHT (c) 1989-1999.
> - *  On-Line Applications Research Corporation (OAR).
> - *
> - *  The license and distribution terms for this file may be
> - *  found in the file LICENSE in this distribution or at
> - *  http://www.rtems.org/license/LICENSE.
> - */
> -
> -#ifndef _RTEMS_SCORE_TYPES_H
> -#define _RTEMS_SCORE_TYPES_H
> -
> -#include <rtems/score/basedefs.h>
> -
> -#ifndef ASM
> -
> -#ifdef __cplusplus
> -extern "C" {
> -#endif
> -
> -/*
> - *  This section defines the basic types for this processor.
> - */
> -
> -/** Type that can store a 32-bit integer or a pointer. */
> -typedef unsigned long CPU_Uint32ptr;
> -
> -typedef uint16_t     Priority_bit_map_Word;
> -typedef void h8300_isr;
> -typedef void ( *h8300_isr_entry )( void );
> -
> -#ifdef __cplusplus
> -}
> -#endif
> -
> -#endif  /* !ASM */
> -
> -#endif
> diff --git a/doc/cpu_supplement/Makefile.am b/doc/cpu_supplement/Makefile.am
> index f27cc6a..4d8ac98 100644
> --- a/doc/cpu_supplement/Makefile.am
> +++ b/doc/cpu_supplement/Makefile.am
> @@ -16,7 +16,6 @@ GENERATED_FILES += arm.texi
>  GENERATED_FILES += avr.texi
>  GENERATED_FILES += bfin.texi
>  GENERATED_FILES += epiphany.texi
> -GENERATED_FILES += h8300.texi
>  GENERATED_FILES += i386.texi
>  GENERATED_FILES += lm32.texi
>  GENERATED_FILES += m32c.texi
> @@ -67,11 +66,6 @@ epiphany.texi: epiphany.t
>             -u "Top" \
>             -n "" < $< > $@
>
> -h8300.texi: h8300.t
> -       $(BMENU2) -p "" \
> -           -u "Top" \
> -           -n "" < $< > $@
> -
>  i386.texi: i386.t
>         $(BMENU2) -p "" \
>             -u "Top" \
> diff --git a/doc/cpu_supplement/cpu_supplement.texi b/doc/cpu_supplement/cpu_supplement.texi
> index 2fcdfa0..52c1a6f 100644
> --- a/doc/cpu_supplement/cpu_supplement.texi
> +++ b/doc/cpu_supplement/cpu_supplement.texi
> @@ -66,7 +66,6 @@
>  * Atmel AVR Specific Information::
>  * Blackfin Specific Information::
>  * Epiphany Specific Information::
> -* Renesas H8/300 Specific Information::
>  * Intel/AMD x86 Specific Information::
>  * Lattice Mico32 Specific Information::
>  * Renesas M32C Specific Information::
> @@ -90,7 +89,6 @@
>  @include avr.texi
>  @include bfin.texi
>  @include epiphany.texi
> - at include h8300.texi
>  @include i386.texi
>  @include lm32.texi
>  @include m32c.texi
> diff --git a/doc/cpu_supplement/h8300.t b/doc/cpu_supplement/h8300.t
> deleted file mode 100644
> index 8c50ffb..0000000
> --- a/doc/cpu_supplement/h8300.t
> +++ /dev/null
> @@ -1,11 +0,0 @@
> - at c Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
> -
> - at chapter Renesas H8/300 Specific Information
> -
> - at section Symmetric Multiprocessing
> -
> -SMP is not supported.
> -
> - at section Thread-Local Storage
> -
> -Thread-local storage is not implemented.
> diff --git a/testsuites/libtests/configure.ac b/testsuites/libtests/configure.ac
> index 4941c51..5ac2dfd 100644
> --- a/testsuites/libtests/configure.ac
> +++ b/testsuites/libtests/configure.ac
> @@ -53,9 +53,6 @@ case $RTEMS_CPU in
>    # bfin has an issue to resolve with libdl. See ticket #2252
>    bfin)
>     HAVE_LIBDL=no ;;
> -  # h8300 has an issue to resolve with libdl. See ticket #2284
> -  h8300)
> -   HAVE_LIBDL=no ;;
>    # lm32 has an issue to resolve with libdl. See ticket #2283
>    lm32)
>     HAVE_LIBDL=no ;;
> diff --git a/testsuites/psxtests/psx04/task3.c b/testsuites/psxtests/psx04/task3.c
> index 71ac39f..5d4172c 100644
> --- a/testsuites/psxtests/psx04/task3.c
> +++ b/testsuites/psxtests/psx04/task3.c
> @@ -29,7 +29,7 @@ void *Task_3(
>    unsigned int  remaining;
>    int           status;
>    int           sig;
> -  volatile union sigval  value; /* should be removed once the H8300 target is fixed */
> +  volatile union sigval  value;
>    sigset_t      mask;
>    siginfo_t     info;
>
> --
> 1.7.1
>
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