Progress notes on hacking on RPi2 with new firmware

Pavel Pisa ppisa4lists at
Sun Jul 3 07:20:42 UTC 2016

Hello everybody,

I have managed HYP boot to run on RPi2 even when application
is loaded by U-boot. Code is functional on RPi1 in SVC
boot mode and U-boot load with cache enabled and should
work even with direct boots from (hopefully) all versions
of firmware. Graphic works on RPi1 and on RPi2 under QEMU
but on real board there is no screen output on RPi2
U-boot loaded application even that mailbox operations
report correct values for modes, memory size and initialization
result. May be cache/setup problems? May be U-boot misconfiguring
something. Anyway, even when graphic console is requested
and HDMI not detected serial output is selected.
Default is serial port anyway.

I have started on cache manager extensions and corrections.
The RPi boot and cache manager work is available from GitHub
for testing

I consider at least patches listed at the end of this e-mail
as mainline quality material. Comments review welcome.
I expect to send them as e-mail series this evening.
Current version includes proposal for new cave manager
operations but no real cache manager correction for ARM
BSPs where it is missing. Proposed new operations

+ * @brief Returns the maximal cache line size of all cache kinds in bytes.
+ *
+ * Returns computed or obtained maximal cache line size of all
+ * all caches in the system.
+ *
+ * @retval 0 No cache is present
+ * @retval positive The maximal cache line size in bytes.
+ */
+size_t rtems_cache_get_maximal_line_size( void );

+ * @brief Ensure necessary synchronization required after code changes
+ *
+ * When code is loaded or modified then many Harvard cache equipped
+ * systems require synchronization of main memory and or updated
+ * code in data cache to ensure visibility of change in all
+ * connected CPUs instruction memory view. This operation
+ * should be used by run time loader for example.
+ *
+ * @param[in] addr The start address of the area to invalidate.
+ * @param[in] size The size in bytes of the area to invalidate.
+ */
+void rtems_cache_instruction_sync_after_code_change(
+  const void * code_addr,
+  size_t n_bytes

They are implemented naive way for now but should be clean
interface to build on in future.

Cache manager is compiled only for initial set of RAM BSPs
still which means that it is missing for most of the targets.

I plan to take some journey to refres the body and mind
from Monday evening until next Sunday without net access.
I would be happy if patches at least up to

  arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.

could be pushed to mainline to correct RPi2 situation.

Best wishes,


commit 28e36bba4ad343877aeac1fa0de9d0471c1c505c
Author: Pavel Pisa <pisa at>
Date:   Fri Jul 1 00:05:33 2016 +0200

    arm/score and shared: define ARM hypervisor mode and alternate vector table base access.
    The main reason for inclusion of minimum hypervisor related defines
    is that current ARM boards firmware and loaders (U-boot for example)
    start loaded operating system kernel in HYP mode to allow it take
    control of virtualization (Linux/KVM for example).

commit e6dc617b27bc2ddd67f4eff9b0eb6a43438fcca8
Author: Pavel Pisa <pisa at>
Date:   Sat Jul 2 17:02:57 2016 +0200

    bsps/arm: Support recent bootloaders starting kernel in HYP mode
    When HYP mode is detected at startup then setup HYP mode
    vectors table (for future extensions) clean exceptions
    switching to HYP mode and switch CPU to ARM SVC mode.
    BSPs which want to use this support need to include next option
    in their
      RTEMS_BSPOPTS_HELP([BSP_START_IN_HYP_SUPPORT], [Support start of BSP in ARM HYP mode])
    and need to include next lines in corresponding
      libbsp_a_SOURCES += ../shared/startup/bsp-start-in-hyp-support.S

commit 7428e3300dcbf83567335c8e1dbd56a54e3c34b1
Author: Pavel Pisa <pisa at>
Date:   Sat Jul 2 13:15:02 2016 +0200

    arm/raspberrypi: Enable HYP to SVC switch for this BSP.
    This support is required when newer firmware is used on
    Raspberry Pi 2 boards.

commit 1f89edd41f84d14cafc1ddeda6f815ba20298197
Author: Pavel Pisa <pisa at>
Date:   Sat Jul 2 14:33:11 2016 +0200

    score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib.
    Some/many Cortex-A cores have data cache line length 64 bytes and maximum
    value has to be used for system structures alignment.

commit 2422dce40537b97f471625a680344281737c6bcb
Author: Pavel Pisa <pisa at>
Date:   Sat Jul 2 18:52:44 2016 +0200

    arm/raspberrypi: update VideoCore cache flush workaround to work on RPi2.
    The arm_cp15_data_cache_clean_and_invalidate leads to hang on RPi2,
    clean by individual lines works on RPi1 and RPi2.

commit 7b3598068405e45452958e7c91db500c9de23768
Author: Pavel Pisa <pisa at>
Date:   Sun Jul 3 00:19:38 2016 +0200

    rtems+bsps/cache: Define cache manager operations for code synchronization and maximal alignment.
    There is need for unambiguous named and defined cache function
    which should be called when code is updated, loaded
    or is self-modifying.
    There should be function to obtain maximal cache line length
    as well. This function can and should be used for allocations
    which can be used for data and or code and ensures that
    there are no partial cache lines overlaps on start and
    end of allocated region.

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