[PATCH 00/10] HYP mode boot and cache manager updates for ARM and RaspberryPi specially.
pisa at cmp.felk.cvut.cz
Mon Jul 4 20:17:54 UTC 2016
Hello Alan and Rohini Kulkarni,
On Monday 04 of July 2016 18:47:09 Alan Cudmore wrote:
> Hi Pavel,
> I can confirm that your rtems-rpi-devel branch from your github account
> works on the Raspberry Pi A+, Raspberry Pi Zero, and Raspberry Pi 2 with
> the latest firmware.
> I did notice that the Dhrystone benchmark runs 3 times faster on the Pi 1
> than the Pi 2, but that could be the cache configuration.
Is this problem of the new firmware only?
If answer is yes, then it can be problem with providing
permission to control cache from SVC mode. Then some
register setup before switching from HYP mode could be required.
If it is not related to new hardware then I think that
there is no change in caching attributes introduced
by all my changes and experience of Rohini Kulkarni working
on RPi2 SMP project in frame of GSoC 2015 could help.
Code is on GitHub,
which is not merged to RTEMS mainline yet.
There are some changes to change cache configuration.
I have tried some changes in bsp_start_hook_1
+ uint32_t ctrl;
+ /* turn mmu off first in case it's on */
+ ctrl = arm_cp15_start_setup_mmu_and_cache(
+ ARM_CP15_CTRL_M | ARM_CP15_CTRL_A, /* clear - mmu off */
+ ctrl |= ARM_CP15_CTRL_Z;
+ (uint32_t *) bsp_translation_table_base,
to ensure that ARM_CP15_CTRL_Z is set for branch predictor.
But I have tried some modifications in BSP and I have observed
no changes. RPi1 seems to run about 4 times faster in my case.
So it is probable that at cache is not enabled. May be only L2???
There can be mitchmatch between configured MMU table format/bit use
and the way bits are filled. I have not time to recheck that
yet but RPi2 code matches Cyclone Cortex-A9 BSP in CPU setup
so it should be OK if there is not some Broadcom specific control
More information about the devel