[3/6] add ti cpsw driver file part 2

yao0718 29171383 at qq.com
Tue Jul 5 07:28:48 UTC 2016


+
+#define CPSW_DUMP_QUEUE(sc, q) do {				\
+	IF_DEBUG(sc) {						\
+		cpsw_dump_queue(sc, q);				\
+	}							\
+} while (0)
+
+static void
+cpsw_init_slots(struct cpsw_softc *sc)
+{
+	struct cpsw_slot *slot;
+	int i;
+
+	STAILQ_INIT(&sc->avail);
+
+	/* Put the slot descriptors onto the global avail list. */
+	for (i = 0; i < sizeof(sc->_slots) / sizeof(sc->_slots[0]); i++) {
+		slot = &sc->_slots[i];
+		slot->bd_offset = cpsw_cpdma_bd_offset(i);
+		STAILQ_INSERT_TAIL(&sc->avail, slot, next);
+	}
+}
+
+static int
+cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested)
+{
+	const int max_slots = sizeof(sc->_slots) / sizeof(sc->_slots[0]);
+	struct cpsw_slot *slot;
+	int i;
+
+	if (requested < 0)
+		requested = max_slots;
+
+	for (i = 0; i < requested; ++i) {
+		slot = STAILQ_FIRST(&sc->avail);
+		if (slot == NULL)
+			return (0);
+		if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) {
+			device_printf(sc->dev, "failed to create dmamap\n");
+			return (ENOMEM);
+		}
+		slot->resemble = malloc(CPSW_RESEMBLE_BUFFER_LEN+(CPSW_RESEMBLE_BUFFER_ALIGN-1), M_DEVBUF, M_NOWAIT | M_ZERO);
+		if (slot->resemble == NULL) {
+			device_printf(sc->dev, "failed to create resemble buffer\n");
+			return (ENOMEM);
+		}
+        slot->align_res = ((uint32_t)(slot->resemble) +CPSW_RESEMBLE_BUFFER_ALIGN-1)&(~(CPSW_RESEMBLE_BUFFER_ALIGN-1)); 
+		STAILQ_REMOVE_HEAD(&sc->avail, next);
+		STAILQ_INSERT_TAIL(&queue->avail, slot, next);
+		++queue->avail_queue_len;
+		++queue->queue_slots;
+	}
+	return (0);
+}
+
+static void
+cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
+{
+	int error;
+
+	if (slot->dmamap) {
+		if (slot->mbuf)
+			bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
+		error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap);
+		KASSERT(error == 0, ("Mapping still active"));
+		slot->dmamap = NULL;
+	}
+	if (slot->mbuf) {
+		m_freem(slot->mbuf);
+		slot->mbuf = NULL;
+	}
+	if (slot->resemble){
+         free(slot->resemble, M_DEVBUF);
+		 slot->resemble = NULL;
+         slot->align_res = NULL;
+	}
+}
+
+static void
+cpsw_reset(struct cpsw_softc *sc)
+{
+	int i;
+
+	callout_stop(&sc->watchdog.callout);
+
+	/* Reset RMII/RGMII wrapper. */
+	cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
+		;
+
+	/* Disable TX and RX interrupts for all cores. */
+	for (i = 0; i < 3; ++i) {
+		cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
+		cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
+	}
+
+	/* Reset CPSW subsystem. */
+	cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
+		;
+
+	/* Reset Sliver port 1 and 2 */
+	for (i = 0; i < 2; i++) {
+		/* Reset */
+		cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
+		while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
+			;
+	}
+
+	/* Reset DMA controller. */
+	cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
+	while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
+		;
+
+	/* Disable TX & RX DMA */
+	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
+	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
+
+	/* Clear all queues. */
+	for (i = 0; i < 8; i++) {
+		cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
+		cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
+	}
+
+	/* Clear all interrupt Masks */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
+	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
+}
+
+static void
+cpsw_init(struct cpsw_softc *sc)
+{
+	struct cpsw_slot *slot;
+	uint32_t reg;
+
+	/* Clear ALE */
+	cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL);
+
+	/* Enable ALE */
+	reg = CPSW_ALE_CTL_ENABLE;
+	if (sc->dualemac)
+		reg |= (CPSW_ALE_CTL_VLAN_AWARE);
+	cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);
+
+	/* Set Host Port Mapping. */
+	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
+	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
+
+	/* Initialize ALE: set host port to forwarding(3). */
+	cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 3);
+
+	cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
+
+	/* Enable statistics for ports 0, 1 and 2 */
+	cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
+
+	/* Experiment:  Turn off flow control */
+	/* This seems to fix the watchdog resets that have plagued
+	   earlier versions of this driver; I'm not yet sure if there
+	   are negative effects yet. */
+	cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
+	/* Make IP hdr aligned with 4 */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
+
+	/* Initialize RX Buffer Descriptors */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
+
+	/* Enable TX & RX DMA */
+	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
+	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
+
+	/* Enable Interrupts for core 0 */
+	cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
+	cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
+	cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
+
+	/* Enable host Error Interrupt */
+	cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
+
+	/* Enable interrupts for RX Channel 0 */
+	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 1);
+
+	/* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
+	/* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
+	cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff);
+
+	/* Select MII in GMII_SEL, Internal Delay mode */
+#ifndef __rtems__
+	ti_scm_reg_write_4(0x650, 0);
+#else
+	cm_write(CONTROL_MOD_BASE+CPSW_GMII_SEL,
+			GMIISEL_GMII2_SEL(RGMII_MODE)|GMIISEL_GMII1_SEL(RGMII_MODE)|0x30);
+#endif	
+
+	/* Initialize active queues. */
+	slot = STAILQ_FIRST(&sc->tx.active);
+	if (slot != NULL)
+		cpsw_write_hdp_slot(sc, &sc->tx, slot);
+	slot = STAILQ_FIRST(&sc->rx.active);
+	if (slot != NULL)
+		cpsw_write_hdp_slot(sc, &sc->rx, slot);
+	cpsw_rx_enqueue(sc);
+
+	/* Activate network interface. */
+	sc->rx.running = 1;
+	sc->tx.running = 1;
+	sc->watchdog.timer = 0;
+	callout_init(&sc->watchdog.callout, 0);
+	callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc);
+}
+
+/*
+ *
+ * Device Probe, Attach, Detach.
+ *
+ */
+
+static int
+cpsw_probe(device_t dev)
+{
+#ifndef __rtems__
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "ti,cpsw"))
+		return (ENXIO);
+#endif
+	device_set_desc(dev, "3-port Switch Ethernet Subsystem");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+cpsw_intr_attach(struct cpsw_softc *sc)
+{
+
+	/* Note: We don't use sc->irq_res[2] (TX interrupt) */
+	if (bus_setup_intr(sc->dev, sc->irq_res[1],
+	    INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_rx_thresh,
+	    sc, &sc->ih_cookie[0]) != 0) {
+		return (-1);
+	}
+	if (bus_setup_intr(sc->dev, sc->irq_res[2],
+	    INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_rx,
+	    sc, &sc->ih_cookie[1]) != 0) {
+		return (-1);
+	}
+	if (bus_setup_intr(sc->dev, sc->irq_res[4],
+	    INTR_TYPE_NET | INTR_MPSAFE, NULL, cpsw_intr_misc,
+	    sc, &sc->ih_cookie[3]) != 0) {
+		return (-1);
+	}
+
+	return (0);
+}
+
+static void
+cpsw_intr_detach(struct cpsw_softc *sc)
+{
+	int i;
+
+	for (i = 0; i < CPSW_INTR_COUNT; i++) {
+		if (sc->ih_cookie[i]) {
+			bus_teardown_intr(sc->dev, sc->irq_res[i],
+			    sc->ih_cookie[i]);
+		}
+	}
+}
+#ifndef __rtems__
+static int
+cpsw_get_fdt_data(struct cpsw_softc *sc, int port)
+{
+	char *name;
+	int len, phy, vlan;
+	pcell_t phy_id[3], vlan_id;
+	phandle_t child;
+	unsigned long mdio_child_addr;
+
+	/* Find any slave with phy_id */
+	phy = -1;
+	vlan = -1;
+	for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) {
+		if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0)
+			continue;
+		if (sscanf(name, "slave@%x", &mdio_child_addr) != 1) {
+			free(name, M_OFWPROP);
+			continue;
+		}
+		free(name, M_OFWPROP);
+		if (mdio_child_addr != slave_mdio_addr[port])
+			continue;
+
+		len = OF_getproplen(child, "phy_id");
+		if (len / sizeof(pcell_t) == 2) {
+			/* Get phy address from fdt */
+			if (OF_getencprop(child, "phy_id", phy_id, len) > 0)
+				phy = phy_id[1];
+		}
+
+		len = OF_getproplen(child, "dual_emac_res_vlan");
+		if (len / sizeof(pcell_t) == 1) {
+			/* Get phy address from fdt */
+			if (OF_getencprop(child, "dual_emac_res_vlan",
+			    &vlan_id, len) > 0) {
+				vlan = vlan_id;
+			}
+		}
+
+		break;
+	}
+	if (phy == -1)
+		return (ENXIO);
+	sc->port[port].phy = phy;
+	sc->port[port].vlan = vlan;
+
+	return (0);
+}
+#endif
+
+static int
+cpsw_attach(device_t dev)
+{
+	bus_dma_segment_t segs[1];
+	int error, i, nsegs;
+	struct cpsw_softc *sc;
+	uint32_t reg;
+
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+    getbinuptime(&sc->attach_uptime);
+
+#ifndef __rtems__
+	sc->node = ofw_bus_get_node(dev);
+	
+
+	if (OF_getencprop(sc->node, "active_slave", &sc->active_slave,
+	    sizeof(sc->active_slave)) <= 0) {
+		sc->active_slave = 0;
+	}
+	if (sc->active_slave > 1)
+		sc->active_slave = 1;
+
+	if (OF_hasprop(sc->node, "dual_emac"))
+		sc->dualemac = 1;
+
+	for (i = 0; i < CPSW_PORTS; i++) {
+		if (!sc->dualemac && i != sc->active_slave)
+			continue;
+		if (cpsw_get_fdt_data(sc, i) != 0) {
+			device_printf(dev,
+			    "failed to get PHY address from FDT\n");
+			return (ENXIO);
+		}
+	}
+#else
+	sc->debug = 0;
+    sc->active_slave = 0;
+    sc->dualemac = 1;
+    sc->port[0].phy = 4;
+	sc->port[0].vlan = 2;
+	sc->port[1].phy = 6;
+	sc->port[1].vlan = 3;
+#endif
+	/* Initialize mutexes */
+	mtx_init(&sc->tx.lock, device_get_nameunit(dev),
+	    "cpsw TX lock", MTX_DEF);
+	mtx_init(&sc->rx.lock, device_get_nameunit(dev),
+	    "cpsw RX lock", MTX_DEF);
+
+	/* Allocate IRQ resources */
+#ifndef __rtems__
+	error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
+	if (error) {
+		device_printf(dev, "could not allocate IRQ resources\n");
+		cpsw_detach(dev);
+		return (ENXIO);
+	}
+
+	sc->mem_rid = 0;
+	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 
+	    &sc->mem_rid, RF_ACTIVE);
+	if (sc->mem_res == NULL) {
+		device_printf(sc->dev, "failed to allocate memory resource\n");
+		cpsw_detach(dev);
+		return (ENXIO);
+	}
+#else
+	error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
+	if (error) {
+		device_printf(dev, "could not allocate resources\n");
+		cpsw_detach(dev);
+		return (ENXIO);
+	}
+#endif
+	reg = cpsw_read_4(sc, CPSW_SS_IDVER);
+	device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7),
+		reg & 0xFF, (reg >> 11) & 0x1F);
+
+#ifndef __rtems__
+	cpsw_add_sysctls(sc);
+#endif
+
+	/* Allocate a busdma tag and DMA safe memory for mbufs. */
+	error = bus_dma_tag_create(
+		bus_get_dma_tag(sc->dev),	/* parent */
+		1, 0,				/* alignment, boundary */
+		BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
+		BUS_SPACE_MAXADDR,		/* highaddr */
+		NULL, NULL,			/* filtfunc, filtfuncarg */
+		MCLBYTES, CPSW_TXFRAGS,		/* maxsize, nsegments */
+		MCLBYTES, 0,			/* maxsegsz, flags */
+		NULL, NULL,			/* lockfunc, lockfuncarg */
+		&sc->mbuf_dtag);		/* dmatag */
+	if (error) {
+		device_printf(dev, "bus_dma_tag_create failed\n");
+		cpsw_detach(dev);
+		return (error);
+	}
+
+	/* Allocate the null mbuf and pre-sync it. */
+	sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+	memset(sc->null_mbuf->m_data, 0, sc->null_mbuf->m_ext.ext_size);
+	bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap);
+	bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap,
+	    sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
+	bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap,
+	    BUS_DMASYNC_PREWRITE);
+	sc->null_mbuf_paddr = segs[0].ds_addr;
+
+	cpsw_init_slots(sc);
+
+	/* Allocate slots to TX and RX queues. */
+	STAILQ_INIT(&sc->rx.avail);
+	STAILQ_INIT(&sc->rx.active);
+	STAILQ_INIT(&sc->tx.avail);
+	STAILQ_INIT(&sc->tx.active);
+	// For now:  128 slots to TX, rest to RX.
+	// XXX TODO: start with 32/64 and grow dynamically based on demand.
+	if (cpsw_add_slots(sc, &sc->tx, 128) ||
+	    cpsw_add_slots(sc, &sc->rx, -1)) {
+		device_printf(dev, "failed to allocate dmamaps\n");
+		cpsw_detach(dev);
+		return (ENOMEM);
+	}
+	device_printf(dev, "Initial queue size TX=%d RX=%d\n",
+	    sc->tx.queue_slots, sc->rx.queue_slots);
+
+	sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0);
+	sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0);
+
+	if (cpsw_intr_attach(sc) == -1) {
+		device_printf(dev, "failed to setup interrupts\n");
+		cpsw_detach(dev);
+		return (ENXIO);
+	}
+
+	/* Reset the controller. */
+	cpsw_reset(sc);
+	cpsw_init(sc);
+
+	for (i = 0; i < CPSW_PORTS; i++) {
+		if (!sc->dualemac && i != sc->active_slave)
+			continue;
+		sc->port[i].dev = device_add_child(dev, "cpswp", i);
+		if (sc->port[i].dev == NULL) {
+			cpsw_detach(dev);
+			printf("attach child failure!\n");
+			return (ENXIO);
+		}
+	}
+	bus_generic_attach(dev);
+
+	return (0);
+}
+
+static int
+cpsw_detach(device_t dev)
+{
+	struct cpsw_softc *sc;
+	int error, i;
+
+	bus_generic_detach(dev);
+ 	sc = device_get_softc(dev);
+
+	for (i = 0; i < CPSW_PORTS; i++) {
+		if (sc->port[i].dev)
+			device_delete_child(dev, sc->port[i].dev);
+	}
+
+	if (device_is_attached(dev)) {
+		callout_stop(&sc->watchdog.callout);
+		callout_drain(&sc->watchdog.callout);
+	}
+
+	/* Stop and release all interrupts */
+	cpsw_intr_detach(sc);
+
+	/* Free dmamaps and mbufs */
+	for (i = 0; i < sizeof(sc->_slots) / sizeof(sc->_slots[0]); ++i)
+		cpsw_free_slot(sc, &sc->_slots[i]);
+
+	/* Free null mbuf. */
+	if (sc->null_mbuf_dmamap) {
+		bus_dmamap_unload(sc->mbuf_dtag, sc->null_mbuf_dmamap);
+		error = bus_dmamap_destroy(sc->mbuf_dtag, sc->null_mbuf_dmamap);
+		KASSERT(error == 0, ("Mapping still active"));
+		m_freem(sc->null_mbuf);
+	}
+
+	/* Free DMA tag */
+	if (sc->mbuf_dtag) {
+		error = bus_dma_tag_destroy(sc->mbuf_dtag);
+		KASSERT(error == 0, ("Unable to destroy DMA tag"));
+	}
+#ifndef __rtems__
+	/* Free IO memory handler */
+	if (sc->mem_res != NULL)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
+	bus_release_resources(dev, irq_res_spec, sc->irq_res);
+#else
+    /* Free IO memory handler */
+	bus_release_resources(dev, irq_res_spec, sc->irq_res);
+#endif
+	/* Destroy mutexes */
+	mtx_destroy(&sc->rx.lock);
+	mtx_destroy(&sc->tx.lock);
+
+	return (0);
+}
+#ifndef __rtems__
+static phandle_t
+cpsw_get_node(device_t bus, device_t dev)
+{
+
+	/* Share controller node with port device. */
+	return (ofw_bus_get_node(bus));
+}
+#endif
+static int
+cpswp_probe(device_t dev)
+{
+
+	if (device_get_unit(dev) > 1) {
+		device_printf(dev, "Only two ports are supported.\n");
+		return (ENXIO);
+	}
+	device_set_desc(dev, "Ethernet Switch Port");
+
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+cpswp_attach(device_t dev)
+{
+	int error;
+	struct ifnet *ifp;
+	struct cpswp_softc *sc;
+	uint32_t reg;
+	uint8_t mac_addr[ETHER_ADDR_LEN];
+	sc = device_get_softc(dev);
+	sc->dev = dev;
+	sc->pdev = device_get_parent(dev);
+	sc->swsc = device_get_softc(sc->pdev);
+	sc->unit = device_get_unit(dev);
+	sc->phy = sc->swsc->port[sc->unit].phy;
+	sc->vlan = sc->swsc->port[sc->unit].vlan;
+	if (sc->swsc->dualemac && sc->vlan == -1)
+		sc->vlan = sc->unit + 1;
+
+	if (sc->unit == 0) {
+		sc->physel = MDIOUSERPHYSEL0;
+		sc->phyaccess = MDIOUSERACCESS0;
+	} else {
+		sc->physel = MDIOUSERPHYSEL1;
+		sc->phyaccess = MDIOUSERACCESS1;
+	}
+
+	mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock",
+	    MTX_DEF);
+
+	/* Allocate network interface */
+	ifp = sc->ifp = if_alloc(IFT_ETHER);
+	if (ifp == NULL) {
+		cpswp_detach(dev);
+		printf("alloc if failure!\n");
+		return (ENXIO);
+	}
+
+	if_initname(ifp, device_get_name(sc->dev), sc->unit);
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
+	ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN?
+	ifp->if_capenable = ifp->if_capabilities;
+
+	ifp->if_init = cpswp_init;
+	ifp->if_start = cpswp_start;
+	ifp->if_ioctl = cpswp_ioctl;
+
+	ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots;
+	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
+	IFQ_SET_READY(&ifp->if_snd);
+
+	/* Get high part of MAC address from control module (mac_id[0|1]_hi) */
+#ifndef __rtems__
+	ti_scm_reg_read_4(0x634 + sc->unit * 8, &reg);
+#else
+    reg = cm_read(CONTROL_MOD_BASE+0x634 + sc->unit * 8);
+#endif
+	mac_addr[0] = reg & 0xFF;
+	mac_addr[1] = (reg >>  8) & 0xFF;
+	mac_addr[2] = (reg >> 16) & 0xFF;
+	mac_addr[3] = (reg >> 24) & 0xFF;
+
+	/* Get low part of MAC address from control module (mac_id[0|1]_lo) */
+#ifndef __rtems__
+	ti_scm_reg_read_4(0x630 + sc->unit * 8, &reg);
+#else
+    reg = cm_read(CONTROL_MOD_BASE+0x630+ sc->unit * 8);
+#endif
+	mac_addr[4] = reg & 0xFF;
+	mac_addr[5] = (reg >>  8) & 0xFF;
+   
+	error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd,
+	    cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0);
+	if (error) {
+		device_printf(dev, "attaching PHYs failed\n");
+		cpswp_detach(dev);
+		return (error);
+	}
+	sc->mii = device_get_softc(sc->miibus);
+
+	/* Select PHY and enable interrupts */
+	cpsw_write_4(sc->swsc, sc->physel,
+	    MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F));
+
+	ether_ifattach(sc->ifp, mac_addr);
+	callout_init(&sc->mii_callout, 0);
+
+	return (0);
+}
+
+static int
+cpswp_detach(device_t dev)
+{
+	struct cpswp_softc *sc;
+
+	sc = device_get_softc(dev);
+	CPSWP_DEBUGF(sc, (""));
+	if (device_is_attached(dev)) {
+		ether_ifdetach(sc->ifp);
+		CPSW_PORT_LOCK(sc);
+		cpswp_stop_locked(sc);
+		CPSW_PORT_UNLOCK(sc);
+		callout_drain(&sc->mii_callout);
+	}
+
+	bus_generic_detach(dev);
+
+	if_free(sc->ifp);
+	mtx_destroy(&sc->lock);
+
+	return (0);
+}





------------------ Original ------------------
From:  "yao0718";<29171383 at qq.com>;
Date:  Tue, Jul 5, 2016 03:17 PM
To:  "devel"<devel at rtems.org>; 

Subject:  Re:  [3/6] add ti cpsw driver file part 1



diff -ruN ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpsw.c ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpsw.c
--- ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpsw.c	1970-01-01 08:00:00.000000000 +0800
+++ ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpsw.c	2016-07-05 09:22:41.794327800 +0800
@@ -0,0 +1,2772 @@
+#include <machine/rtems-bsd-kernel-space.h>
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * TI Common Platform Ethernet Switch (CPSW) Driver
+ * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs.
+ *
+ * This controller is documented in the AM335x Technical Reference
+ * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM
+ * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
+ *
+ * It is basically a single Ethernet port (port 0) wired internally to
+ * a 3-port store-and-forward switch connected to two independent
+ * "sliver" controllers (port 1 and port 2).  You can operate the
+ * controller in a variety of different ways by suitably configuring
+ * the slivers and the Address Lookup Engine (ALE) that routes packets
+ * between the ports.
+ *
+ * This code was developed and tested on a BeagleBone with
+ * an AM335x SoC.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <rtems/bsd/sys/param.h>
+#include <sys/systm.h>
+#include <sys/endian.h>
+#include <sys/mbuf.h>
+#ifndef __rtems__
+#include <sys/lock.h>
+#else
+#include <rtems/bsd/sys/lock.h>
+#endif
+#include <sys/mutex.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/sysctl.h>
+
+#include <net/ethernet.h>
+#include <net/bpf.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+#include <net/if_vlan_var.h>
+
+#include <netinet/in_systm.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+
+#include <sys/sockio.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+#ifndef __rtems__
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#endif
+#include "if_cpswreg.h"
+#include "if_cpswvar.h"
+#ifndef __rtems__ 
+#include <arm/ti/ti_scm.h>
+#endif
+#include <rtems/bsd/local/miibus_if.h>
+#include <sys/malloc.h>
+
+/* Device probe/attach/detach. */
+static int cpsw_probe(device_t);
+static void cpsw_init_slots(struct cpsw_softc *);
+static int cpsw_attach(device_t);
+static void cpsw_free_slot(struct cpsw_softc *, struct cpsw_slot *);
+static int cpsw_detach(device_t);
+
+/* Device probe/attach/detach. */
+static int cpswp_probe(device_t);
+static int cpswp_attach(device_t);
+static int cpswp_detach(device_t);
+#ifndef __rtems__ 
+static phandle_t cpsw_get_node(device_t, device_t);
+#endif
+/* Device Init/shutdown. */
+static int cpsw_shutdown(device_t);
+static void cpswp_init(void *);
+static void cpswp_init_locked(void *);
+static void cpswp_stop_locked(struct cpswp_softc *);
+
+/* Device Suspend/Resume. */
+static int cpsw_suspend(device_t);
+static int cpsw_resume(device_t);
+
+/* Ioctl. */
+static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data);
+
+static int cpswp_miibus_readreg(device_t, int phy, int reg);
+static int cpswp_miibus_writereg(device_t, int phy, int reg, int value);
+static void cpswp_miibus_statchg(device_t);
+
+/* Send/Receive packets. */
+static void cpsw_intr_rx(void *arg);
+static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *);
+static void cpsw_rx_enqueue(struct cpsw_softc *);
+static void cpswp_start(struct ifnet *);
+static void cpswp_tx_enqueue(struct cpswp_softc *);
+static int cpsw_tx_dequeue(struct cpsw_softc *);
+
+/* Misc interrupts and watchdog. */
+static void cpsw_intr_rx_thresh(void *);
+static void cpsw_intr_misc(void *);
+static void cpswp_tick(void *);
+static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int cpswp_ifmedia_upd(struct ifnet *);
+static void cpsw_tx_watchdog(void *);
+
+/* ALE support */
+static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *);
+static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *);
+static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *);
+static void cpsw_ale_dump_table(struct cpsw_softc *);
+static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int);
+static int cpswp_ale_update_addresses(struct cpswp_softc *, int);
+
+/* Statistics and sysctls. */
+#ifndef __rtems__
+static void cpsw_add_sysctls(struct cpsw_softc *);
+static void cpsw_stats_collect(struct cpsw_softc *);
+static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS);
+#endif
+
+/*
+ * Arbitrary limit on number of segments in an mbuf to be transmitted.
+ * Packets with more segments than this will be defragmented before
+ * they are queued.
+ */
+#define	CPSW_TXFRAGS		8
+
+/* Shared resources. */
+static device_method_t cpsw_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		cpsw_probe),
+	DEVMETHOD(device_attach,	cpsw_attach),
+	DEVMETHOD(device_detach,	cpsw_detach),
+	DEVMETHOD(device_shutdown,	cpsw_shutdown),
+	DEVMETHOD(device_suspend,	cpsw_suspend),
+	DEVMETHOD(device_resume,	cpsw_resume),
+	/* OFW methods */
+#ifndef __rtems__
+	DEVMETHOD(ofw_bus_get_node,	cpsw_get_node),
+#endif	
+	DEVMETHOD_END
+};
+
+static driver_t cpsw_driver = {
+	"cpsw",
+	cpsw_methods,
+	sizeof(struct cpsw_softc),
+};
+
+static devclass_t cpsw_devclass;
+
+#ifndef __rtems__
+DRIVER_MODULE(cpsw, simplebus, cpsw_driver, cpsw_devclass, 0, 0);
+#else
+DRIVER_MODULE(cpsw, nexus, cpsw_driver, cpsw_devclass, 0, 0);
+#endif
+/* Port/Slave resources. */
+static device_method_t cpswp_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		cpswp_probe),
+	DEVMETHOD(device_attach,	cpswp_attach),
+	DEVMETHOD(device_detach,	cpswp_detach),
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	cpswp_miibus_readreg),
+	DEVMETHOD(miibus_writereg,	cpswp_miibus_writereg),
+	DEVMETHOD(miibus_statchg,	cpswp_miibus_statchg),
+	DEVMETHOD_END
+};
+
+static driver_t cpswp_driver = {
+	"cpswp",
+	cpswp_methods,
+	sizeof(struct cpswp_softc),
+};
+
+static devclass_t cpswp_devclass;
+
+DRIVER_MODULE(cpswp, cpsw, cpswp_driver, cpswp_devclass, 0, 0);
+DRIVER_MODULE(miibus, cpswp, miibus_driver, miibus_devclass, 0, 0);
+MODULE_DEPEND(cpsw, ether, 1, 1, 1);
+MODULE_DEPEND(cpswp, miibus, 1, 1, 1);
+
+static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 };
+
+static struct resource_spec irq_res_spec[] = {
+#ifdef __rtems__
+	{ SYS_RES_MEMORY, 0, RF_ACTIVE },
+#endif
+	{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
+	{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
+	{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE },
+	{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE },
+	{ -1, 0 }
+};
+
+/* Number of entries here must match size of stats
+ * array in struct cpswp_softc. */
+static struct cpsw_stat {
+	int	reg;
+	char *oid;
+} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = {
+	{0x00, "GoodRxFrames"},
+	{0x04, "BroadcastRxFrames"},
+	{0x08, "MulticastRxFrames"},
+	{0x0C, "PauseRxFrames"},
+	{0x10, "RxCrcErrors"},
+	{0x14, "RxAlignErrors"},
+	{0x18, "OversizeRxFrames"},
+	{0x1c, "RxJabbers"},
+	{0x20, "ShortRxFrames"},
+	{0x24, "RxFragments"},
+	{0x30, "RxOctets"},
+	{0x34, "GoodTxFrames"},
+	{0x38, "BroadcastTxFrames"},
+	{0x3c, "MulticastTxFrames"},
+	{0x40, "PauseTxFrames"},
+	{0x44, "DeferredTxFrames"},
+	{0x48, "CollisionsTxFrames"},
+	{0x4c, "SingleCollisionTxFrames"},
+	{0x50, "MultipleCollisionTxFrames"},
+	{0x54, "ExcessiveCollisions"},
+	{0x58, "LateCollisions"},
+	{0x5c, "TxUnderrun"},
+	{0x60, "CarrierSenseErrors"},
+	{0x64, "TxOctets"},
+	{0x68, "RxTx64OctetFrames"},
+	{0x6c, "RxTx65to127OctetFrames"},
+	{0x70, "RxTx128to255OctetFrames"},
+	{0x74, "RxTx256to511OctetFrames"},
+	{0x78, "RxTx512to1024OctetFrames"},
+	{0x7c, "RxTx1024upOctetFrames"},
+	{0x80, "NetOctets"},
+	{0x84, "RxStartOfFrameOverruns"},
+	{0x88, "RxMiddleOfFrameOverruns"},
+	{0x8c, "RxDmaOverruns"}
+};
+
+/*
+ * Basic debug support.
+ */
+
+#define	IF_DEBUG(_sc)		if ((_sc)->if_flags & IFF_DEBUG)
+
+static void
+cpsw_debugf_head(const char *funcname)
+{
+	int t = (int)(time_second % (24 * 60 * 60));
+
+	printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname);
+}
+
+#include <machine/stdarg.h>
+static void
+cpsw_debugf(const char *fmt, ...)
+{
+	va_list ap;
+
+	va_start(ap, fmt);
+	vprintf(fmt, ap);
+	va_end(ap);
+	printf("\n");
+
+}
+
+#define	CPSW_DEBUGF(_sc, a) do {					\
+	if (sc->debug) {						\
+		cpsw_debugf_head(__func__);				\
+		cpsw_debugf a;						\
+	}								\
+} while (0)
+
+#define	CPSWP_DEBUGF(_sc, a) do {					\
+	IF_DEBUG((_sc)) {						\
+		cpsw_debugf_head(__func__);				\
+		cpsw_debugf a;						\
+	}								\
+} while (0)
+
+
+/*
+ * Locking macros
+ */
+#define	CPSW_TX_LOCK(sc) do {						\
+		mtx_assert(&(sc)->rx.lock, MA_NOTOWNED);		\
+		mtx_lock(&(sc)->tx.lock);				\
+} while (0)
+
+#define	CPSW_TX_UNLOCK(sc)	mtx_unlock(&(sc)->tx.lock)
+#define	CPSW_TX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->tx.lock, MA_OWNED)
+
+#define	CPSW_RX_LOCK(sc) do {						\
+		mtx_assert(&(sc)->tx.lock, MA_NOTOWNED);		\
+		mtx_lock(&(sc)->rx.lock);				\
+} while (0)
+
+#define	CPSW_RX_UNLOCK(sc)		mtx_unlock(&(sc)->rx.lock)
+#define	CPSW_RX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->rx.lock, MA_OWNED)
+
+#define	CPSW_GLOBAL_LOCK(sc) do {					\
+		if ((mtx_owned(&(sc)->tx.lock) ? 1 : 0) !=		\
+		    (mtx_owned(&(sc)->rx.lock) ? 1 : 0)) {		\
+			panic("cpsw deadlock possibility detection!");	\
+		}							\
+		mtx_lock(&(sc)->tx.lock);				\
+		mtx_lock(&(sc)->rx.lock);				\
+} while (0)
+
+#define	CPSW_GLOBAL_UNLOCK(sc) do {					\
+		CPSW_RX_UNLOCK(sc);					\
+		CPSW_TX_UNLOCK(sc);					\
+} while (0)
+
+#define	CPSW_GLOBAL_LOCK_ASSERT(sc) do {				\
+		CPSW_TX_LOCK_ASSERT(sc);				\
+		CPSW_RX_LOCK_ASSERT(sc);				\
+} while (0)
+
+#define CPSW_PORT_LOCK(_sc) do {					\
+		mtx_assert(&(_sc)->lock, MA_NOTOWNED);			\
+		mtx_lock(&(_sc)->lock);					\
+} while (0)
+
+#define	CPSW_PORT_UNLOCK(_sc)	mtx_unlock(&(_sc)->lock)
+#define	CPSW_PORT_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->lock, MA_OWNED)
+
+/*
+ * Read/Write macros
+ */
+#define	cpsw_read_4(_sc, _reg)		bus_read_4((_sc)->irq_res[0], (_reg))
+#define	cpsw_write_4(_sc, _reg, _val)					\
+	bus_write_4((_sc)->irq_res[0], (_reg), (_val))
+
+#define BUS_SPACE_PHYSADDR(res, offs) \
+        ((u_int)(rman_get_start(res)+(offs)))
+#define CONTROL_MOD_BASE 0x44E10000
+#define CPSW_GMII_SEL			         (0x0650)
+/* GMII_SEL Register Field */
+#define GMIISEL_RMII2_IO_CLK_EN	             (1UL<<(7))
+#define GMIISEL_RMII1_IO_CLK_EN	             (1UL<<(6))
+#define GMIISEL_RGMII2_IDMODE	             (1UL<<(5))
+#define GMIISEL_RGMII1_IDMODE	             (1UL<<(4))
+#define GMIISEL_GMII2_SEL(val)	             ((0x3 & (val)) << 2)
+#define GMIISEL_GMII1_SEL(val)	             ((0x3 & (val)) << 0)
+#define GMII_MODE	                              0
+#define RMII_MODE	                              1
+#define RGMII_MODE	                          2
+
+
+#define cm_read(a)    (*(volatile uint32_t *)(a))
+#define cm_write(a,v) (*(volatile uint32_t *)(a) = (v))
+
+
+
+
+
+
+#define	cpsw_cpdma_bd_offset(i)	(CPSW_CPPI_RAM_OFFSET + ((i)*16))
+
+#define	cpsw_cpdma_bd_paddr(sc, slot)					\
+	BUS_SPACE_PHYSADDR(sc->irq_res[0], slot->bd_offset)
+#define	cpsw_cpdma_read_bd(sc, slot, val)				\
+	bus_read_region_4(sc->irq_res[0], slot->bd_offset, (uint32_t *) val, 4)
+#define	cpsw_cpdma_write_bd(sc, slot, val)				\
+	bus_write_region_4(sc->irq_res[0], slot->bd_offset, (uint32_t *) val, 4)
+#define	cpsw_cpdma_write_bd_next(sc, slot, next_slot)			\
+	cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
+#define	cpsw_cpdma_read_bd_flags(sc, slot)				\
+	bus_read_2(sc->irq_res[0], slot->bd_offset + 14)
+#define	cpsw_write_hdp_slot(sc, queue, slot)				\
+	cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
+#define	CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
+#define	cpsw_read_cp(sc, queue)						\
+	cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 
+#define	cpsw_write_cp(sc, queue, val)					\
+	cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
+#define	cpsw_write_cp_slot(sc, queue, slot)				\
+	cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
+
+#if 0
+/* XXX temporary function versions for debugging. */
+static void
+cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
+{
+	uint32_t reg = queue->hdp_offset;
+	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
+	CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
+	cpsw_write_4(sc, reg, v);
+}
+static void
+cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
+{
+	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
+	CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue)));
+	cpsw_write_cp(sc, queue, v);
+}
+#endif
+
+/*
+ * Expanded dump routines for verbose debugging.
+ */
+static void
+cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
+{
+	static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ",
+	    "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun",
+	    "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1",
+	    "Port0"};
+	struct cpsw_cpdma_bd bd;
+	const char *sep;
+	int i;
+
+	cpsw_cpdma_read_bd(sc, slot, &bd);
+	printf("BD Addr: 0x%08x   Next: 0x%08x\n", cpsw_cpdma_bd_paddr(sc, slot), bd.next);
+	printf("  BufPtr: 0x%08x   BufLen: 0x%08x\n", bd.bufptr, bd.buflen);
+	printf("  BufOff: 0x%08x   PktLen: 0x%08x\n", bd.bufoff, bd.pktlen);
+	printf("  Flags: ");
+	sep = "";
+	for (i = 0; i < 16; ++i) {
+		if (bd.flags & (1 << (15 - i))) {
+			printf("%s%s", sep, flags[i]);
+			sep = ",";
+		}
+	}
+	printf("\n");
+	if (slot->mbuf) {
+		printf("  Ether:  %14D\n",
+		    (char *)(slot->mbuf->m_data), " ");
+		printf("  Packet: %16D\n",
+		    (char *)(slot->mbuf->m_data) + 14, " ");
+	}
+}
+
+#define	CPSW_DUMP_SLOT(cs, slot) do {				\
+	IF_DEBUG(sc) {						\
+		cpsw_dump_slot(sc, slot);			\
+	}							\
+} while (0)
+
+static void
+cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
+{
+	struct cpsw_slot *slot;
+	int i = 0;
+	int others = 0;
+
+	STAILQ_FOREACH(slot, q, next) {
+		if (i > 4)
+			++others;
+		else
+			cpsw_dump_slot(sc, slot);
+		++i;
+	}
+	if (others)
+		printf(" ... and %d more.\n", others);
+	printf("\n");
+}





------------------ Original ------------------
From:  "yao0718";<29171383 at qq.com>;
Date:  Tue, Jul 5, 2016 03:15 PM
To:  "devel"<devel at rtems.org>; 

Subject:  Re: [2/6] add ti cpsw head file



diff -ruN ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswreg.h ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswreg.h
--- ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswreg.h	1970-01-01 08:00:00.000000000 +0800
+++ ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswreg.h	2016-03-18 11:38:45.324075400 +0800
@@ -0,0 +1,178 @@
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_IF_CPSWREG_H
+#define	_IF_CPSWREG_H
+
+#define	CPSW_SS_OFFSET			0x0000
+#define	CPSW_SS_IDVER			(CPSW_SS_OFFSET + 0x00)
+#define	CPSW_SS_SOFT_RESET		(CPSW_SS_OFFSET + 0x08)
+#define	CPSW_SS_STAT_PORT_EN		(CPSW_SS_OFFSET + 0x0C)
+#define	CPSW_SS_PTYPE			(CPSW_SS_OFFSET + 0x10)
+#define	CPSW_SS_FLOW_CONTROL		(CPSW_SS_OFFSET + 0x24)
+
+#define	CPSW_PORT_OFFSET		0x0100
+#define	CPSW_PORT_P_MAX_BLKS(p)		(CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
+#define	CPSW_PORT_P_BLK_CNT(p)		(CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
+#define	CPSW_PORT_P_VLAN(p)		(CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
+#define	CPSW_PORT_P_TX_PRI_MAP(p)	(CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100))
+#define	CPSW_PORT_P0_CPDMA_TX_PRI_MAP	(CPSW_PORT_OFFSET + 0x01C)
+#define	CPSW_PORT_P0_CPDMA_RX_CH_MAP	(CPSW_PORT_OFFSET + 0x020)
+#define	CPSW_PORT_P_SA_LO(p)		(CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100))
+#define	CPSW_PORT_P_SA_HI(p)		(CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100))
+
+#define	CPSW_CPDMA_OFFSET		0x0800
+#define	CPSW_CPDMA_TX_CONTROL		(CPSW_CPDMA_OFFSET + 0x04)
+#define	CPSW_CPDMA_TX_TEARDOWN		(CPSW_CPDMA_OFFSET + 0x08)
+#define	CPSW_CPDMA_RX_CONTROL		(CPSW_CPDMA_OFFSET + 0x14)
+#define	CPSW_CPDMA_RX_TEARDOWN		(CPSW_CPDMA_OFFSET + 0x18)
+#define	CPSW_CPDMA_SOFT_RESET		(CPSW_CPDMA_OFFSET + 0x1c)
+#define	CPSW_CPDMA_DMACONTROL		(CPSW_CPDMA_OFFSET + 0x20)
+#define	CPSW_CPDMA_DMASTATUS		(CPSW_CPDMA_OFFSET + 0x24)
+#define	CPSW_CPDMA_RX_BUFFER_OFFSET	(CPSW_CPDMA_OFFSET + 0x28)
+#define	CPSW_CPDMA_TX_INTSTAT_RAW	(CPSW_CPDMA_OFFSET + 0x80)
+#define	CPSW_CPDMA_TX_INTSTAT_MASKED	(CPSW_CPDMA_OFFSET + 0x84)
+#define	CPSW_CPDMA_TX_INTMASK_SET	(CPSW_CPDMA_OFFSET + 0x88)
+#define	CPSW_CPDMA_TX_INTMASK_CLEAR	(CPSW_CPDMA_OFFSET + 0x8C)
+#define	CPSW_CPDMA_CPDMA_EOI_VECTOR	(CPSW_CPDMA_OFFSET + 0x94)
+#define	CPSW_CPDMA_RX_INTSTAT_RAW	(CPSW_CPDMA_OFFSET + 0xA0)
+#define	CPSW_CPDMA_RX_INTSTAT_MASKED	(CPSW_CPDMA_OFFSET + 0xA4)
+#define	CPSW_CPDMA_RX_INTMASK_SET	(CPSW_CPDMA_OFFSET + 0xA8)
+#define	CPSW_CPDMA_RX_INTMASK_CLEAR	(CPSW_CPDMA_OFFSET + 0xAc)
+#define	CPSW_CPDMA_DMA_INTSTAT_RAW	(CPSW_CPDMA_OFFSET + 0xB0)
+#define	CPSW_CPDMA_DMA_INTSTAT_MASKED	(CPSW_CPDMA_OFFSET + 0xB4)
+#define	CPSW_CPDMA_DMA_INTMASK_SET	(CPSW_CPDMA_OFFSET + 0xB8)
+#define	CPSW_CPDMA_DMA_INTMASK_CLEAR	(CPSW_CPDMA_OFFSET + 0xBC)
+#define	CPSW_CPDMA_RX_FREEBUFFER(p)	(CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04))
+
+#define	CPSW_STATS_OFFSET		0x0900
+
+#define	CPSW_STATERAM_OFFSET		0x0A00
+#define	CPSW_CPDMA_TX_HDP(p)		(CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04))
+#define	CPSW_CPDMA_RX_HDP(p)		(CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04))
+#define	CPSW_CPDMA_TX_CP(p)		(CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04))
+#define	CPSW_CPDMA_RX_CP(p)		(CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04))
+
+#define	CPSW_CPTS_OFFSET		0x0C00
+
+#define	CPSW_ALE_OFFSET			0x0D00
+#define	CPSW_ALE_CONTROL		(CPSW_ALE_OFFSET + 0x08)
+#define	 CPSW_ALE_CTL_ENABLE		(1U << 31)
+#define	 CPSW_ALE_CTL_CLEAR_TBL		(1 << 30)
+#define	 CPSW_ALE_CTL_BYPASS		(1 << 4)
+#define	 CPSW_ALE_CTL_VLAN_AWARE	(1 << 2)
+#define	CPSW_ALE_TBLCTL			(CPSW_ALE_OFFSET + 0x20)
+#define	CPSW_ALE_TBLW2			(CPSW_ALE_OFFSET + 0x34)
+#define	CPSW_ALE_TBLW1			(CPSW_ALE_OFFSET + 0x38)
+#define	CPSW_ALE_TBLW0			(CPSW_ALE_OFFSET + 0x3C)
+#define	 ALE_MCAST(_a)			((_a[1] >> 8) & 1)
+#define	 ALE_MCAST_FWD			(3 << 30)
+#define	 ALE_PORTS(_a)			((_a[2] >> 2) & 7)
+#define	 ALE_TYPE(_a)			((_a[1] >> 28) & 3)
+#define	 ALE_TYPE_ADDR			1
+#define	 ALE_TYPE_VLAN			2
+#define	 ALE_TYPE_VLAN_ADDR		3
+#define	 ALE_VLAN(_a)			((_a[1] >> 16) & 0xfff)
+#define	 ALE_VLAN_REGFLOOD(_a)		((_a[0] >> 8) & 7)
+#define	 ALE_VLAN_UNREGFLOOD(_a)	((_a[0] >> 16) & 7)
+#define	 ALE_VLAN_UNTAG(_a)		((_a[0] >> 24) & 7)
+#define	 ALE_VLAN_MEMBERS(_a)		(_a[0] & 7)
+#define	CPSW_ALE_PORTCTL(p)		(CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04))
+
+/* SL1 is at 0x0D80, SL2 is at 0x0DC0 */
+#define	CPSW_SL_OFFSET			0x0D80
+#define	CPSW_SL_MACCONTROL(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x04)
+#define	 CPSW_SL_MACTL_IFCTL_B		(1 << 16)
+#define	 CPSW_SL_MACTL_IFCTL_A		(1 << 15)
+#define	 CPSW_SL_MACTL_GIG		(1 << 7)
+#define	 CPSW_SL_MACTL_GMII_ENABLE	(1 << 5)
+#define	 CPSW_SL_MACTL_FULLDUPLEX	(1 << 0)
+#define	CPSW_SL_MACSTATUS(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x08)
+#define	CPSW_SL_SOFT_RESET(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C)
+#define	CPSW_SL_RX_MAXLEN(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x10)
+#define	CPSW_SL_RX_PAUSE(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x18)
+#define	CPSW_SL_TX_PAUSE(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C)
+#define	CPSW_SL_RX_PRI_MAP(p)		(CPSW_SL_OFFSET + (0x40 * (p)) + 0x24)
+
+#define	MDIO_OFFSET			0x1000
+#define	MDIOCONTROL			(MDIO_OFFSET + 0x04)
+#define	 MDIOCTL_ENABLE			(1 << 30)
+#define	 MDIOCTL_FAULTENB		(1 << 18)
+#define	MDIOLINKINTRAW			(MDIO_OFFSET + 0x10)
+#define	MDIOLINKINTMASKED		(MDIO_OFFSET + 0x14)
+#define	MDIOUSERACCESS0			(MDIO_OFFSET + 0x80)
+#define	MDIOUSERPHYSEL0			(MDIO_OFFSET + 0x84)
+#define	MDIOUSERACCESS1			(MDIO_OFFSET + 0x88)
+#define	MDIOUSERPHYSEL1			(MDIO_OFFSET + 0x8C)
+#define	 MDIO_PHYSEL_LINKINTENB		(1 << 6)
+#define	 MDIO_PHYACCESS_GO		(1U << 31)
+#define	 MDIO_PHYACCESS_WRITE		(1 << 30)
+#define	 MDIO_PHYACCESS_ACK		(1 << 29)
+
+#define	CPSW_WR_OFFSET			0x1200
+#define	CPSW_WR_SOFT_RESET		(CPSW_WR_OFFSET + 0x04)
+#define	CPSW_WR_CONTROL			(CPSW_WR_OFFSET + 0x08)
+#define	CPSW_WR_INT_CONTROL		(CPSW_WR_OFFSET + 0x0c)
+#define	CPSW_WR_C_RX_THRESH_EN(p)	(CPSW_WR_OFFSET + (0x10 * (p)) + 0x10)
+#define	CPSW_WR_C_RX_EN(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x14)
+#define	CPSW_WR_C_TX_EN(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x18)
+#define	CPSW_WR_C_MISC_EN(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C)
+#define	CPSW_WR_C_RX_THRESH_STAT(p)	(CPSW_WR_OFFSET + (0x10 * (p)) + 0x40)
+#define	CPSW_WR_C_RX_STAT(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
+#define	CPSW_WR_C_TX_STAT(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
+#define	CPSW_WR_C_MISC_STAT(p)		(CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
+#define	 CPSW_WR_C_MISC_EVNT_PEND	(1 << 4)
+#define	 CPSW_WR_C_MISC_STAT_PEND	(1 << 3)
+#define	 CPSW_WR_C_MISC_HOST_PEND	(1 << 2)
+#define	 CPSW_WR_C_MISC_MDIOLINK	(1 << 1)
+#define	 CPSW_WR_C_MISC_MDIOUSER	(1 << 0)
+
+#define	CPSW_CPPI_RAM_OFFSET		0x2000
+#define	CPSW_CPPI_RAM_SIZE		0x2000
+
+#define	CPSW_MEMWINDOW_SIZE		0x4000
+
+#define	 CPDMA_BD_SOP			(1 << 15)
+#define	 CPDMA_BD_EOP			(1 << 14)
+#define	 CPDMA_BD_OWNER			(1 << 13)
+#define	 CPDMA_BD_EOQ			(1 << 12)
+#define	 CPDMA_BD_TDOWNCMPLT		(1 << 11)
+#define	 CPDMA_BD_PKT_ERR_MASK		(3 << 4)
+#define	 CPDMA_BD_TO_PORT		(1 << 4)
+#define	 CPDMA_BD_PORT_MASK		3
+
+struct cpsw_cpdma_bd {
+	volatile uint32_t next;
+	volatile uint32_t bufptr;
+	volatile uint16_t buflen;
+	volatile uint16_t bufoff;
+	volatile uint16_t pktlen;
+	volatile uint16_t flags;
+};
+
+#endif /*_IF_CPSWREG_H */


diff -ruN ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswvar.h ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswvar.h
--- ./rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswvar.h	1970-01-01 08:00:00.000000000 +0800
+++ ./am335x_bsp/rtems-libbsd/freebsd/sys/arm/ti/cpsw/if_cpswvar.h	2016-07-02 21:43:26.205209800 +0800
@@ -0,0 +1,147 @@
+/*-
+ * Copyright (c) 2012 Damjan Marion <dmarion at Freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_IF_CPSWVAR_H
+#define	_IF_CPSWVAR_H
+
+#define	CPSW_PORTS		2
+#define	CPSW_INTR_COUNT		4
+
+/* MII BUS  */
+#define	CPSW_MIIBUS_RETRIES	10
+#define	CPSW_MIIBUS_DELAY	2000
+
+#define	CPSW_MAX_ALE_ENTRIES	1024
+
+#define	CPSW_SYSCTL_COUNT	34
+
+#define CPSW_RESEMBLE_BUFFER_LEN  2048
+#define CPSW_RESEMBLE_BUFFER_ALIGN 4
+struct cpsw_slot {
+	uint32_t bd_offset;  /* Offset of corresponding BD within CPPI RAM. */
+	bus_dmamap_t dmamap;
+	struct mbuf *mbuf;
+/* yao0718 add  why cppi dma can not send when address misalign 32 bits*/
+    uint8_t  *resemble;
+	uint8_t  *align_res;
+	STAILQ_ENTRY(cpsw_slot) next;
+};
+STAILQ_HEAD(cpsw_slots, cpsw_slot);
+
+struct cpsw_queue {
+	struct mtx	lock;
+	int		running;
+	struct cpsw_slots active;
+	struct cpsw_slots avail;
+	uint32_t	queue_adds; /* total bufs added */
+	uint32_t	queue_removes; /* total bufs removed */
+	uint32_t	queue_removes_at_last_tick; /* Used by watchdog */
+	int		queue_slots;
+	int		active_queue_len;
+	int		max_active_queue_len;
+	int		avail_queue_len;
+	int		max_avail_queue_len;
+	int		longest_chain; /* Largest # segments in a single packet. */
+	int		hdp_offset;
+};
+
+struct cpsw_port {
+	device_t	dev;
+	int		phy;
+	int		vlan;
+};
+
+struct cpsw_softc {
+	device_t	dev;
+	int		active_slave;
+	int		debug;
+	int		dualemac;
+#ifndef __rtems__
+	phandle_t	node;
+#endif
+	struct bintime	attach_uptime; /* system uptime when attach happened. */
+	struct cpsw_port port[2];
+
+	/* RX and TX buffer tracking */
+	struct cpsw_queue rx, tx;
+
+	/* We expect 1 memory resource and 4 interrupts from the device tree. */
+	void		*ih_cookie[CPSW_INTR_COUNT];
+#ifndef __rtems__
+	int		mem_rid;
+	struct resource	*mem_res;
+	struct resource	*irq_res[CPSW_INTR_COUNT];
+#else
+    struct resource	*irq_res[1+CPSW_INTR_COUNT];
+#endif
+	/* An mbuf full of nulls for TX padding. */
+	bus_dmamap_t null_mbuf_dmamap;
+	struct mbuf *null_mbuf;
+	bus_addr_t null_mbuf_paddr;
+
+	bus_dma_tag_t	mbuf_dtag;
+
+	struct {
+		int resets;
+		int timer;
+		struct callout  callout;
+	} watchdog;
+
+	/* 64-bit versions of 32-bit hardware statistics counters */
+	uint64_t shadow_stats[CPSW_SYSCTL_COUNT];
+
+	/* CPPI STATERAM has 512 slots for building TX/RX queues. */
+	/* TODO: Size here supposedly varies with different versions
+	   of the controller.  Check DaVinci specs and find a good
+	   way to adjust this.  One option is to have a separate
+	   Device Tree parameter for number slots; another option
+	   is to calculate it from the memory size in the device tree. */
+	struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)];
+	struct cpsw_slots avail;
+};
+
+struct cpswp_softc {
+	device_t	dev;
+	device_t	miibus;
+	device_t	pdev;
+	int		media_status;
+	int		unit;
+	int		vlan;
+	struct bintime	init_uptime; /* system uptime when init happened. */
+	struct callout	mii_callout;
+	struct cpsw_softc *swsc;
+	struct ifnet	*ifp;
+	struct mii_data	*mii;
+	struct mtx	lock;
+	uint32_t	if_flags;
+	uint32_t	phy;
+	uint32_t	phyaccess;
+	uint32_t	physel;
+};
+
+#endif /*_IF_CPSWVAR_H */





------------------ Original ------------------
From:  "yao0718";<29171383 at qq.com>;
Date:  Tue, Jul 5, 2016 03:11 PM
To:  "devel"<devel at rtems.org>; 

Subject:  [0/6] ti cpsw driver port from freebsd for am335x 



I add cpsw driver from freebsd and modify some code for my board, my board is not beagleblack, so i am not sure it can work fine in BB board,to reduce phy find process, I  set phy address 4 and 6 for which phy address on my board,my board has two eth port ,I set dualmac when attach;
can somebody test it on beaglebone and merge to beaglebone  bsp?
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