[PATCH] rtems: ensure that rtems_cache_aligned_malloc do not align less than to CPU_CACHE_LINE_BYTES.

[Sebastian Huber]

On 29/06/16 13:14, Pavel Pisa wrote:
> Hello Sebastian,
>
> On Wednesday 29 of June 2016 07:28:46 Sebastian Huber wrote:
>> >Hallo Pavel,
>> >
>> >On 25/06/16 17:06, Pavel Pisa wrote:
>>> > >There are architectures (for example some/many ARM Cortex-A) which have
>>> > >different cache line sizes for data and instruction caches.
>>> > >CPU kit and even BSP can be build for group of CPUs which differs
>>> > >in cache line sizes as well and there are situations when maximum
>>> > >alignment is not reported by rtems_cache_get_data_line_size.
>>> > >
>>> > >Ensure, that allocated memory is aligned at least to CPU_CACHE_LINE_BYTES
>>> > >which is in pair with compile time data structures allocation.
>>> > >
>>> > >Signed-off-by: Pavel Pisa<pisa at cmp.felk.cvut.cz>
>>> > >---
>>> > >   cpukit/libcsupport/src/cachealignedalloc.c | 3 +++
>>> > >   1 file changed, 3 insertions(+)
>>> > >
>>> > >diff --git a/cpukit/libcsupport/src/cachealignedalloc.c
>>> > >b/cpukit/libcsupport/src/cachealignedalloc.c index a704859..bb93937
>>> > >100644
>>> > >--- a/cpukit/libcsupport/src/cachealignedalloc.c
>>> > >+++ b/cpukit/libcsupport/src/cachealignedalloc.c
>>> > >@@ -18,6 +18,9 @@ void *rtems_cache_aligned_malloc( size_t nbytes )
>>> > >     size_t line_size = rtems_cache_get_data_line_size();
>>> > >
>>> > >     if ( line_size > 0 ) {
>>> > >+    if ( line_size < CPU_CACHE_LINE_BYTES )
>>> > >+      line_size = CPU_CACHE_LINE_BYTES;
>>> > >+
>>> > >       /* Assume that the cache line size is a power of two */
>>> > >       size_t m = line_size - 1;
>> >
>> >so, in case rtems_cache_get_data_line_size() returns a non-zero value,
>> >then you assume that it lies to the user and fix it here in this place
>> >only?
>> >
>> >The purpose of CPU_CACHE_LINE_BYTES is to provide a worst-case cache
>> >line size at cpukit compile-time.
> I am sure that logic in the ARM case is fundamentally broken/missing
> for the most BSPs/architecture variants now and it needs to be corrected.
> The question is where/which way.

Your cache manager changes for ARM are fine, but we should not add 
workarounds for broken functions to cpukit. Instead these broken 
functions should be fixed.

In case we need the ability to do some run-time stuff in 
rtems_cache_get_data_line_size(), then we have to add this ability to 
the cache manager.

-- 
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
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