[PATCH] arm/raspberrypi: ensure that RTEMS application image can be started by U-boot.

[Chris Johns]

On 18/05/2016 10:15, Pavel Pisa wrote:
> From: Pavel Pisa <ppisa at pikron.com>
>
> The current versions of U-boot start kernel/RTEMS application image
> with instruction and data caches enabled and it sets exception
> base register to new address after its self-relocation.
>
>          ldr     r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
>          mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
>
> Included changes in bsp_start_hook_0 restore default state to
> allow RTEMS image to run after startup from newer U-boot version
> on Raspberry Pi.
>
> Signed-off-by: Pavel Pisa <ppisa at pikron.com>
> ---
>   .../libbsp/arm/raspberrypi/startup/bspstarthooks.c | 48 +++++++++++++++++++++-
>   1 file changed, 47 insertions(+), 1 deletion(-)
>
>   If there is no objection I commit the patch to mainline and it should be
>   considered for 4.11 as well. Generalization and use for all ARMv6+ targets
>   should be considered in the future as well. But to not block RPi
>   related GSoC projects I suggest to not start with generalization
>   at this moment because this problem is a blocker to development
>   without instant SD card manipulation.
>
> diff --git a/c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c
> b/c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c
> index 047c8ad..fbd13be 100644
> --- a/c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c
> +++ b/c/src/lib/libbsp/arm/raspberrypi/startup/bspstarthooks.c
> @@ -26,11 +26,57 @@
>   #include <bsp/start.h>
>   #include <bsp/raspberrypi.h>
>   #include <bsp/mm.h>
> +#include <libcpu/arm-cp15.h>
>
>   void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
>   {
> -}
> +  uint32_t sctlr_val;
> +  char s[32];
> +
> +  sctlr_val = arm_cp15_get_control();
> +
> +  /*
> +   * Current U-boot loader seems to start kernel image
> +   * with I and D caches on and MMU enabled.
> +   * If RTEMS application image finds that cache is on
> +   * during startup then disable caches.

Is the cache and MMU configured and enabled at a later stage in the 
initialisation? On my first read of this comment I was left wondering if 
caches can be disabled on these targets.

Chris

> +   */
> +  if (sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
> +    if (sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M)) {
> +      /*
> +       * If the data cache is on then ensure that it is clean
> +       * before switching off to be extra carefull.
> +       */
> +
> +      /* Flush Prefetch Buffer */
> +      asm volatile ("mcr p15, 0, %0, c7, c5,  4" :: "r" (0) : "memory");
> +
> +      /* Clean Entire Data Cache */
> +      asm volatile ("mcr p15, 0, %0, c7, c10,  0" :: "r" (0) : "memory");
> +    }
> +    sctlr_val &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A);
> +    arm_cp15_set_control(sctlr_val);
> +
> +    arm_cp15_tlb_invalidate();
>
> +    /* Flush Prefetch Buffer */
> +    asm volatile ("mcr p15, 0, %0, c7, c5,  4" :: "r" (0) : "memory");
> +
> +    /* Invalidate Entire Data Cache */
> +    asm volatile ("mcr p15, 0, %0, c7, c6,  0" :: "r" (0) : "memory");
> +    /* Invalidate Entire Instruction Cache */
> +    asm volatile ("mcr p15, 0, %0, c7, c5,  0" :: "r" (0) : "memory");
> +  }
> +
> +  /* Clear Translation Table Base Control Register */
> +  asm volatile ("mcr p15, 0, %0, c2, c0,  2" :: "r" (0) : "memory");
> +
> +  /* Clear Secure or Non-secure Vector Base Address Register */
> +  asm volatile ("mcr p15, 0, %0, c12, c0, 0" :: "r" (0) : "memory");
> +
> +  /* Clear Monitor Vector Base Address Register */
> +  asm volatile ("mcr p15, 0, %0, c12, c0, 1" :: "r" (0) : "memory");
> +}
>
>   void BSP_START_TEXT_SECTION bsp_start_hook_1(void)
>   {
>