[PATCH 30/32] score: Rename _ISR_Disable() and _ISR_Enable()
Sebastian Huber
sebastian.huber at embedded-brains.de
Wed May 18 09:20:49 UTC 2016
Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable()
into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant().
This is a preparation to remove the Giant lock.
Update #2555.
---
c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c | 4 +-
c/src/lib/libbsp/m68k/mvme167/network/network.c | 16 ++---
c/src/lib/libcpu/or1k/shared/cache/cache.c | 60 ++++++++---------
c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c | 4 +-
c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c | 4 +-
c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c | 12 ++--
c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c | 12 ++--
c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c | 8 +--
c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c | 8 +--
c/src/libchip/ide/ata.c | 8 +--
cpukit/rtems/include/rtems/rtems/intr.h | 4 +-
cpukit/rtems/src/intrbody.c | 4 +-
cpukit/score/cpu/arm/armv7m-isr-vector-install.c | 4 +-
.../score/cpu/nios2/nios2-mpu-disable-protected.c | 4 +-
cpukit/score/cpu/or1k/cpu.c | 4 +-
cpukit/score/include/rtems/score/assert.h | 13 +---
cpukit/score/include/rtems/score/cpustdatomic.h | 76 +++++++++++-----------
cpukit/score/include/rtems/score/isrlevel.h | 25 ++-----
cpukit/score/include/rtems/score/isrlock.h | 8 +--
cpukit/score/include/rtems/score/percpu.h | 8 +--
cpukit/score/include/rtems/score/threaddispatch.h | 8 +--
cpukit/score/include/rtems/score/threadimpl.h | 2 +-
cpukit/score/src/threaddispatch.c | 4 +-
cpukit/score/src/threaddispatchdisablelevel.c | 10 ---
testsuites/tmtests/tm26/task1.c | 4 +-
25 files changed, 139 insertions(+), 175 deletions(-)
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c b/c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c
index 8e6b63c..53f9087 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/alloc360.c
@@ -47,7 +47,7 @@ M360AllocateBufferDescriptors (int count)
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
/*
* Verify that the region exists.
@@ -74,7 +74,7 @@ M360AllocateBufferDescriptors (int count)
break;
}
}
- _ISR_Enable (level);
+ _ISR_Local_enable (level);
if (bdp == NULL)
rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);
return bdp;
diff --git a/c/src/lib/libbsp/m68k/mvme167/network/network.c b/c/src/lib/libbsp/m68k/mvme167/network/network.c
index ab4ccf4..2ab09da 100644
--- a/c/src/lib/libbsp/m68k/mvme167/network/network.c
+++ b/c/src/lib/libbsp/m68k/mvme167/network/network.c
@@ -568,7 +568,7 @@ static void uti596_addCmd(
pCmd->status = 0;
pCmd->next = I596_NULL;
- _ISR_Disable(level);
+ _ISR_Local_disable(level);
if (uti596_softc.pCmdHead == I596_NULL) {
uti596_softc.pCmdHead = uti596_softc.pCmdTail = uti596_softc.scb.pCmd = pCmd;
@@ -578,12 +578,12 @@ static void uti596_addCmd(
uti596_softc.scb.command = CUC_START;
uti596_issueCA ( &uti596_softc, UTI596_NO_WAIT );
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
else {
uti596_softc.pCmdTail->next = (i596_cmd *) word_swap ((unsigned long)pCmd);
uti596_softc.pCmdTail = pCmd;
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
#ifdef DBG_ADD_CMD
@@ -1272,11 +1272,11 @@ i596_rfd * uti596_dequeue(
ISR_Level level;
i596_rfd * pRfd;
- _ISR_Disable(level);
+ _ISR_Local_disable(level);
/* invalid address, or empty queue or emptied queue */
if( ppQ == NULL || *ppQ == NULL || *ppQ == I596_NULL) {
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
return I596_NULL;
}
@@ -1288,7 +1288,7 @@ i596_rfd * uti596_dequeue(
*ppQ = (i596_rfd *) word_swap ((unsigned long) pRfd->next);
pRfd->next = I596_NULL; /* unlink the rfd being returned */
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
return pRfd;
}
@@ -2083,9 +2083,9 @@ void uti596_txDaemon(
UTI_596_ASSERT(pRfd != I596_NULL, "Supplying NULL RFD\n")
- _ISR_Disable(level);
+ _ISR_Local_disable(level);
uti596_supplyFD ( pRfd ); /* Return RFD to RFA. */
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
pRfd = uti596_dequeue( (i596_rfd **)&sc->pInboundFrameQueue); /* grab next frame */
diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
index d17fec2..54728e1 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
@@ -20,11 +20,11 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
uint32_t sr;
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_data(void)
@@ -32,12 +32,12 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
uint32_t sr;
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_enable_instruction(void)
@@ -45,12 +45,12 @@ static inline void _CPU_OR1K_Cache_enable_instruction(void)
uint32_t sr;
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_disable_instruction(void)
@@ -58,96 +58,96 @@ static inline void _CPU_OR1K_Cache_disable_instruction(void)
uint32_t sr;
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
/* Implement RTEMS cache manager functions */
@@ -155,23 +155,23 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
void _CPU_cache_flush_1_data_line(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_flush(d_addr);
//asm volatile("l.csync");
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_invalidate(d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
void _CPU_cache_freeze_data(void)
@@ -187,11 +187,11 @@ void _CPU_cache_unfreeze_data(void)
void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
ISR_Level level;
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
_CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
}
void _CPU_cache_freeze_instruction(void)
diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
index 4e6202e..8b74a97 100644
--- a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
+++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c
@@ -57,7 +57,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
/*
@@ -85,7 +85,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
}
}
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
if (blockp == NULL)
rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
index 94fcaa6..4f6cb6d 100644
--- a/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
+++ b/c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
@@ -55,7 +55,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
- _ISR_Disable (level);
+ _ISR_Local_disable (level);
for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
/*
@@ -83,7 +83,7 @@ m8xx_dpram_allocate( unsigned int byte_count )
}
}
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
if (blockp == NULL)
rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
index 649c89d..99d9cc9 100644
--- a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c
@@ -111,14 +111,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return 0;
}
@@ -131,7 +131,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -147,13 +147,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -166,7 +166,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
index f753426..47bc859 100644
--- a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c
@@ -112,14 +112,14 @@ unsigned int sh_set_irq_priority(
/*
* Set the interrupt priority register
*/
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
temp16 = read16( prioreg);
temp16 &= ~( 15 << shiftcount);
temp16 |= prio << shiftcount;
write16( temp16, prioreg);
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return 0;
}
@@ -132,7 +132,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -148,13 +148,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -167,7 +167,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
diff --git a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
index f47e360..52a033b 100644
--- a/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c
@@ -56,7 +56,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -72,13 +72,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_enable( _Per_CPU_Get() );
@@ -90,7 +90,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
diff --git a/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c b/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
index cb93c5a..2ca8926 100644
--- a/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
+++ b/c/src/lib/libcpu/sh/shgdb/score/cpu_asm.c
@@ -33,7 +33,7 @@ void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_disable();
@@ -49,13 +49,13 @@ void __ISR_Handler( uint32_t vector)
_ISR_Nest_level++;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Thread_Dispatch_unnest( _Per_CPU_Get() );
@@ -68,7 +68,7 @@ void __ISR_Handler( uint32_t vector)
stack_ptr = _old_stack_ptr;
#endif
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
diff --git a/c/src/libchip/ide/ata.c b/c/src/libchip/ide/ata.c
index 2014f8e..31af5df 100644
--- a/c/src/libchip/ide/ata.c
+++ b/c/src/libchip/ide/ata.c
@@ -387,9 +387,9 @@ ata_process_request(rtems_device_minor_number ctrl_minor)
return;
/* get first request in the controller's queue */
- _ISR_Disable(level);
+ _ISR_Local_disable(level);
areq = (ata_req_t *)rtems_chain_first(&ata_ide_ctrls[ctrl_minor].reqs);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
#if 0
/* get ATA device identifier (0 or 1) */
@@ -831,9 +831,9 @@ ata_queue_task(rtems_task_argument arg)
rtems_ata_lock();
/* get current request to the controller */
- _ISR_Disable(level);
+ _ISR_Local_disable(level);
areq = (ata_req_t *)rtems_chain_first(&ata_ide_ctrls[ctrl_minor].reqs);
- _ISR_Enable(level);
+ _ISR_Local_enable(level);
switch(msg.type)
{
diff --git a/cpukit/rtems/include/rtems/rtems/intr.h b/cpukit/rtems/include/rtems/rtems/intr.h
index ebf7a58..4142230 100644
--- a/cpukit/rtems/include/rtems/rtems/intr.h
+++ b/cpukit/rtems/include/rtems/rtems/intr.h
@@ -100,7 +100,7 @@ rtems_status_code rtems_interrupt_catch(
* rtems_interrupt_local_disable() is available on all configurations.
*/
#define rtems_interrupt_disable( _isr_cookie ) \
- _ISR_Disable(_isr_cookie)
+ _ISR_Local_disable(_isr_cookie)
/**
* @brief Enable RTEMS Interrupt
@@ -111,7 +111,7 @@ rtems_status_code rtems_interrupt_catch(
* rtems_interrupt_local_enable() is available on all configurations.
*/
#define rtems_interrupt_enable( _isr_cookie ) \
- _ISR_Enable(_isr_cookie)
+ _ISR_Local_enable(_isr_cookie)
/**
* @brief Flash RTEMS Interrupt
diff --git a/cpukit/rtems/src/intrbody.c b/cpukit/rtems/src/intrbody.c
index a82dc10..abee60d 100644
--- a/cpukit/rtems/src/intrbody.c
+++ b/cpukit/rtems/src/intrbody.c
@@ -47,7 +47,7 @@ rtems_interrupt_level rtems_interrupt_disable( void )
{
rtems_interrupt_level previous_level;
- _ISR_Disable( previous_level );
+ _ISR_Local_disable( previous_level );
return previous_level;
}
@@ -56,7 +56,7 @@ void rtems_interrupt_enable(
rtems_interrupt_level previous_level
)
{
- _ISR_Enable( previous_level );
+ _ISR_Local_enable( previous_level );
}
void rtems_interrupt_flash(
diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
index ca3eeb3..cb3abc9 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
@@ -35,12 +35,12 @@ void _CPU_ISR_install_vector(
{
uint32_t level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
if ( old_handler != NULL ) {
*old_handler = _ARMV7M_Get_exception_handler( (int) vector );
}
_ARMV7M_Set_exception_handler( (int) vector, new_handler );
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
}
#endif /* ARM_MULTILIB_ARCH_V7M */
diff --git a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
index a8e39df..05602cd 100644
--- a/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
+++ b/cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
@@ -30,9 +30,9 @@ uint32_t _Nios2_MPU_Disable_protected( void )
ISR_Level level;
uint32_t config;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
config = _Nios2_MPU_Disable();
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return config;
}
diff --git a/cpukit/score/cpu/or1k/cpu.c b/cpukit/score/cpu/or1k/cpu.c
index 3cf6f6b..fe933f0 100644
--- a/cpukit/score/cpu/or1k/cpu.c
+++ b/cpukit/score/cpu/or1k/cpu.c
@@ -88,7 +88,7 @@ void _CPU_ISR_install_vector(
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
current_handler = table [vector];
@@ -102,7 +102,7 @@ void _CPU_ISR_install_vector(
table [vector] = new_handler;
}
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
}
void _CPU_Install_interrupt_stack( void )
diff --git a/cpukit/score/include/rtems/score/assert.h b/cpukit/score/include/rtems/score/assert.h
index 69736ae..c61c0a0 100644
--- a/cpukit/score/include/rtems/score/assert.h
+++ b/cpukit/score/include/rtems/score/assert.h
@@ -95,24 +95,13 @@ extern "C" {
* @brief Returns true if thread dispatching is allowed.
*
* Thread dispatching can be repressed via _Thread_Disable_dispatch() or
- * _ISR_Disable().
+ * _ISR_Local_disable().
*/
#if defined( RTEMS_DEBUG )
bool _Debug_Is_thread_dispatching_allowed( void );
#endif
/**
- * @brief Returns true if the current thread of execution owns the giant lock.
- */
-#if defined( RTEMS_DEBUG )
- #if defined( RTEMS_SMP )
- bool _Debug_Is_owner_of_giant( void );
- #else
- #define _Debug_Is_owner_of_giant() (true)
- #endif
-#endif
-
-/**
* @brief Returns true if the current thread of execution owns the allocator
* mutex.
*/
diff --git a/cpukit/score/include/rtems/score/cpustdatomic.h b/cpukit/score/include/rtems/score/cpustdatomic.h
index fb7ba2d..6c6db8d 100644
--- a/cpukit/score/include/rtems/score/cpustdatomic.h
+++ b/cpukit/score/include/rtems/score/cpustdatomic.h
@@ -277,10 +277,10 @@ static inline unsigned int _CPU_atomic_Fetch_add_uint( CPU_atomic_Uint *obj, uns
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val + arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -297,10 +297,10 @@ static inline unsigned long _CPU_atomic_Fetch_add_ulong( CPU_atomic_Ulong *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val + arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -317,10 +317,10 @@ static inline uintptr_t _CPU_atomic_Fetch_add_uintptr( CPU_atomic_Uintptr *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val + arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -337,10 +337,10 @@ static inline unsigned int _CPU_atomic_Fetch_sub_uint( CPU_atomic_Uint *obj, uns
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val - arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -357,10 +357,10 @@ static inline unsigned long _CPU_atomic_Fetch_sub_ulong( CPU_atomic_Ulong *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val - arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -377,10 +377,10 @@ static inline uintptr_t _CPU_atomic_Fetch_sub_uintptr( CPU_atomic_Uintptr *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val - arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -397,10 +397,10 @@ static inline unsigned int _CPU_atomic_Fetch_or_uint( CPU_atomic_Uint *obj, unsi
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val | arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -417,10 +417,10 @@ static inline unsigned long _CPU_atomic_Fetch_or_ulong( CPU_atomic_Ulong *obj, u
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val | arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -437,10 +437,10 @@ static inline uintptr_t _CPU_atomic_Fetch_or_uintptr( CPU_atomic_Uintptr *obj, u
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val | arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -457,10 +457,10 @@ static inline unsigned int _CPU_atomic_Fetch_and_uint( CPU_atomic_Uint *obj, uns
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val & arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -477,10 +477,10 @@ static inline unsigned long _CPU_atomic_Fetch_and_ulong( CPU_atomic_Ulong *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val & arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -497,10 +497,10 @@ static inline uintptr_t _CPU_atomic_Fetch_and_uintptr( CPU_atomic_Uintptr *obj,
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = val & arg;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -517,10 +517,10 @@ static inline unsigned int _CPU_atomic_Exchange_uint( CPU_atomic_Uint *obj, unsi
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = desired;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -537,10 +537,10 @@ static inline unsigned long _CPU_atomic_Exchange_ulong( CPU_atomic_Ulong *obj, u
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = desired;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -557,10 +557,10 @@ static inline uintptr_t _CPU_atomic_Exchange_uintptr( CPU_atomic_Uintptr *obj, u
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
val = *obj;
*obj = desired;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return val;
#endif
@@ -579,7 +579,7 @@ static inline bool _CPU_atomic_Compare_exchange_uint( CPU_atomic_Uint *obj, unsi
(void) succ;
(void) fail;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
actual = *obj;
success = ( actual == *expected );
if ( success ) {
@@ -587,7 +587,7 @@ static inline bool _CPU_atomic_Compare_exchange_uint( CPU_atomic_Uint *obj, unsi
} else {
*expected = actual;
}
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return success;
#endif
@@ -606,7 +606,7 @@ static inline bool _CPU_atomic_Compare_exchange_ulong( CPU_atomic_Ulong *obj, un
(void) succ;
(void) fail;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
actual = *obj;
success = ( actual == *expected );
if ( success ) {
@@ -614,7 +614,7 @@ static inline bool _CPU_atomic_Compare_exchange_ulong( CPU_atomic_Ulong *obj, un
} else {
*expected = actual;
}
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return success;
#endif
@@ -633,7 +633,7 @@ static inline bool _CPU_atomic_Compare_exchange_uintptr( CPU_atomic_Uintptr *obj
(void) succ;
(void) fail;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
actual = *obj;
success = ( actual == *expected );
if ( success ) {
@@ -641,7 +641,7 @@ static inline bool _CPU_atomic_Compare_exchange_uintptr( CPU_atomic_Uintptr *obj
} else {
*expected = actual;
}
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return success;
#endif
@@ -670,10 +670,10 @@ static inline bool _CPU_atomic_Flag_test_and_set( CPU_atomic_Flag *obj, CPU_atom
ISR_Level level;
(void) order;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
flag = *obj;
*obj = true;
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
return flag;
#endif
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h
index cf8712a..0eccd3a 100644
--- a/cpukit/score/include/rtems/score/isrlevel.h
+++ b/cpukit/score/include/rtems/score/isrlevel.h
@@ -55,10 +55,9 @@ typedef uint32_t ISR_Level;
* @param[out] _level The argument @a _level will contain the previous
* interrupt mask level.
*/
-#define _ISR_Disable( _level ) \
+#define _ISR_Local_disable( _level ) \
do { \
_CPU_ISR_Disable( _level ); \
- _Assert( _Debug_Is_owner_of_giant() ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
@@ -66,17 +65,16 @@ typedef uint32_t ISR_Level;
* @brief Enables interrupts on this processor.
*
* This macro restores the interrupt status on the processor with the
- * interrupt level value obtained by _ISR_Disable(). It is used at the end of
+ * interrupt level value obtained by _ISR_Local_disable(). It is used at the end of
* a critical section of code to enable interrupts so they can be processed
* again.
*
* @param[in] _level The interrupt level previously obtained by
- * _ISR_Disable().
+ * _ISR_Local_disable().
*/
-#define _ISR_Enable( _level ) \
+#define _ISR_Local_enable( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
- _Assert( _Debug_Is_owner_of_giant() ); \
_CPU_ISR_Enable( _level ); \
} while (0)
@@ -97,12 +95,11 @@ typedef uint32_t ISR_Level;
* properly protects itself.
*
* @param[in] _level The interrupt level previously obtained by
- * _ISR_Disable().
+ * _ISR_Local_disable().
*/
#define _ISR_Flash( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
- _Assert( _Debug_Is_owner_of_giant() ); \
_CPU_ISR_Flash( _level ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
@@ -136,18 +133,6 @@ typedef uint32_t ISR_Level;
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
-#define _ISR_Local_disable( _level ) \
- do { \
- _CPU_ISR_Disable( _level ); \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- } while (0)
-
-#define _ISR_Local_enable( _level ) \
- do { \
- RTEMS_COMPILER_MEMORY_BARRIER(); \
- _CPU_ISR_Enable( _level ); \
- } while (0)
-
/**@}*/
#ifdef __cplusplus
diff --git a/cpukit/score/include/rtems/score/isrlock.h b/cpukit/score/include/rtems/score/isrlock.h
index 2af75c9..3843fd6 100644
--- a/cpukit/score/include/rtems/score/isrlock.h
+++ b/cpukit/score/include/rtems/score/isrlock.h
@@ -203,7 +203,7 @@ typedef struct {
)
#else
#define _ISR_lock_ISR_disable_and_acquire( _lock, _context ) \
- _ISR_Disable( ( _context )->isr_level )
+ _ISR_Local_disable( ( _context )->isr_level )
#endif
/**
@@ -228,7 +228,7 @@ typedef struct {
)
#else
#define _ISR_lock_Release_and_ISR_enable( _lock, _context ) \
- _ISR_Enable( ( _context )->isr_level )
+ _ISR_Local_enable( ( _context )->isr_level )
#endif
/**
@@ -357,7 +357,7 @@ typedef struct {
#else
#define _ISR_lock_ISR_disable( _context ) \
do { \
- _ISR_Disable( ( _context )->isr_level ); \
+ _ISR_Local_disable( ( _context )->isr_level ); \
_ISR_lock_ISR_disable_profile( _context ) \
} while ( 0 )
#endif
@@ -377,7 +377,7 @@ typedef struct {
_ISR_Local_enable( ( _context )->Lock_context.isr_level )
#else
#define _ISR_lock_ISR_enable( _context ) \
- _ISR_Enable( ( _context )->isr_level )
+ _ISR_Local_enable( ( _context )->isr_level )
#endif
/** @} */
diff --git a/cpukit/score/include/rtems/score/percpu.h b/cpukit/score/include/rtems/score/percpu.h
index fa0c289..ea69cd6 100644
--- a/cpukit/score/include/rtems/score/percpu.h
+++ b/cpukit/score/include/rtems/score/percpu.h
@@ -499,7 +499,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
#else
#define _Per_CPU_ISR_disable_and_acquire( cpu, isr_cookie ) \
do { \
- _ISR_Disable( isr_cookie ); \
+ _ISR_Local_disable( isr_cookie ); \
(void) ( cpu ); \
} while ( 0 )
#endif
@@ -514,7 +514,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
#define _Per_CPU_Release_and_ISR_enable( cpu, isr_cookie ) \
do { \
(void) ( cpu ); \
- _ISR_Enable( isr_cookie ); \
+ _ISR_Local_enable( isr_cookie ); \
} while ( 0 )
#endif
@@ -530,7 +530,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
} while ( 0 )
#else
#define _Per_CPU_Acquire_all( isr_cookie ) \
- _ISR_Disable( isr_cookie )
+ _ISR_Local_disable( isr_cookie )
#endif
#if defined( RTEMS_SMP )
@@ -545,7 +545,7 @@ extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
} while ( 0 )
#else
#define _Per_CPU_Release_all( isr_cookie ) \
- _ISR_Enable( isr_cookie )
+ _ISR_Local_enable( isr_cookie )
#endif
/*
diff --git a/cpukit/score/include/rtems/score/threaddispatch.h b/cpukit/score/include/rtems/score/threaddispatch.h
index ac8855b..be3883f 100644
--- a/cpukit/score/include/rtems/score/threaddispatch.h
+++ b/cpukit/score/include/rtems/score/threaddispatch.h
@@ -152,7 +152,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
#if defined( RTEMS_PROFILING )
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
_Profiling_Thread_dispatch_disable( _Per_CPU_Get(), disable_level );
#endif
@@ -160,7 +160,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
_Thread_Dispatch_disable_level = disable_level;
#if defined( RTEMS_PROFILING )
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
#endif
return disable_level;
@@ -177,7 +177,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
#if defined( RTEMS_PROFILING )
ISR_Level level;
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
#endif
--disable_level;
@@ -185,7 +185,7 @@ RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization( void )
#if defined( RTEMS_PROFILING )
_Profiling_Thread_dispatch_enable( _Per_CPU_Get(), disable_level );
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
#endif
return disable_level;
diff --git a/cpukit/score/include/rtems/score/threadimpl.h b/cpukit/score/include/rtems/score/threadimpl.h
index 4a6a6bf..17d86d8 100644
--- a/cpukit/score/include/rtems/score/threadimpl.h
+++ b/cpukit/score/include/rtems/score/threadimpl.h
@@ -1181,7 +1181,7 @@ RTEMS_INLINE_ROUTINE void *_Thread_Lock_acquire(
_Thread_Lock_release( lock, lock_context );
}
#else
- _ISR_Disable( lock_context->isr_level );
+ _ISR_Local_disable( lock_context->isr_level );
return NULL;
#endif
diff --git a/cpukit/score/src/threaddispatch.c b/cpukit/score/src/threaddispatch.c
index 4d840bf..5a9c566 100644
--- a/cpukit/score/src/threaddispatch.c
+++ b/cpukit/score/src/threaddispatch.c
@@ -104,7 +104,7 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
* to this function.
*/
#if !defined( RTEMS_SMP )
- _ISR_Enable( level );
+ _ISR_Local_enable( level );
#endif
_User_extensions_Thread_switch( executing, heir );
@@ -122,7 +122,7 @@ void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level )
_Thread_Debug_set_real_processor( executing, cpu_self );
#if !defined( RTEMS_SMP )
- _ISR_Disable( level );
+ _ISR_Local_disable( level );
#endif
} while (
#if defined( RTEMS_SMP )
diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c
index 826d5b2..75b12bd 100644
--- a/cpukit/score/src/threaddispatchdisablelevel.c
+++ b/cpukit/score/src/threaddispatchdisablelevel.c
@@ -138,13 +138,3 @@ void _Giant_Release( Per_CPU_Control *cpu_self )
_Giant_Do_release( cpu_self );
_ISR_Local_enable( isr_level );
}
-
-#if defined( RTEMS_DEBUG )
-bool _Debug_Is_owner_of_giant( void )
-{
- Giant_Control *giant = &_Giant;
-
- return giant->owner_cpu == _Per_CPU_Get_snapshot()
- || !_System_state_Is_up( _System_state_Get() );
-}
-#endif
diff --git a/testsuites/tmtests/tm26/task1.c b/testsuites/tmtests/tm26/task1.c
index 8463cd3..84811b8 100644
--- a/testsuites/tmtests/tm26/task1.c
+++ b/testsuites/tmtests/tm26/task1.c
@@ -544,7 +544,7 @@ void complete_test( void )
*/
put_time(
- "rtems interrupt: _ISR_Disable",
+ "rtems interrupt: _ISR_Local_disable",
isr_disable_time,
1,
0,
@@ -560,7 +560,7 @@ void complete_test( void )
);
put_time(
- "rtems interrupt: _ISR_Enable",
+ "rtems interrupt: _ISR_Local_enable",
isr_enable_time,
1,
0,
--
1.8.4.5
More information about the devel
mailing list