[PATCH 25/26] score: Add _ISR_Is_enabled()
Sebastian Huber
sebastian.huber at embedded-brains.de
Tue Nov 15 13:51:57 UTC 2016
In contrast to _ISR_Get_level() the _ISR_Is_enabled() function evaluates
a level parameter and returns a boolean value.
Update #2811.
---
cpukit/score/cpu/arm/rtems/score/cpu.h | 11 +++++++++--
cpukit/score/cpu/bfin/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/epiphany/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/i386/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/lm32/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/m32c/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/m68k/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/mips/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/moxie/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/nios2/nios2-isr-get-level.c | 12 ++++++++++++
cpukit/score/cpu/nios2/rtems/score/cpu.h | 2 ++
cpukit/score/cpu/no_cpu/rtems/score/cpu.h | 14 ++++++++++++++
cpukit/score/cpu/or1k/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/powerpc/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/sh/rtems/score/cpu.h | 6 ++++++
cpukit/score/cpu/sparc/rtems/score/cpu.h | 8 ++++++++
cpukit/score/cpu/sparc64/rtems/score/cpu.h | 5 +++++
cpukit/score/cpu/v850/rtems/score/cpu.h | 6 ++++++
cpukit/score/include/rtems/score/isrlevel.h | 12 ++++++++++++
testsuites/sptests/sp37/init.c | 2 ++
20 files changed, 126 insertions(+), 2 deletions(-)
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h
index b1fabaf..6a57ac8 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -350,8 +350,6 @@ static inline uint32_t arm_interrupt_disable( void )
: [level] "=&r" (level)
: [basepri] "r" (basepri)
);
-#else
- level = 0;
#endif
return level;
@@ -416,6 +414,15 @@ static inline void arm_interrupt_flash( uint32_t level )
#define _CPU_ISR_Flash( _isr_cookie ) \
arm_interrupt_flash( _isr_cookie )
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+#if defined(ARM_MULTILIB_ARCH_V4)
+ return ( level & 0x80 ) == 0;
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+ return level > 0x80;
+#endif
+}
+
void _CPU_ISR_Set_level( uint32_t level );
uint32_t _CPU_ISR_Get_level( void );
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index d0c21cd..85dbf78 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -667,6 +667,11 @@ typedef struct {
: : "d"(_level) : "R0" ); \
}
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return level != 0;
+}
+
/**
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
diff --git a/cpukit/score/cpu/epiphany/rtems/score/cpu.h b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
index 9d11a3d..871f30e 100644
--- a/cpukit/score/cpu/epiphany/rtems/score/cpu.h
+++ b/cpukit/score/cpu/epiphany/rtems/score/cpu.h
@@ -525,6 +525,11 @@ static inline void epiphany_interrupt_enable(uint32_t level)
epiphany_interrupt_disable(); \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x2 ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 4dd98ae..f70e2c6 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -403,6 +403,11 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Set_level( _new_level ) i386_set_interrupt_level(_new_level)
#endif
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & EFLAGS_INTR_ENABLE ) != 0;
+}
+
uint32_t _CPU_ISR_Get_level( void );
/* Make sure interrupt stack has space for ISR
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index 1bba1e4..ed397dc 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -679,6 +679,11 @@ extern Context_Control_fp _CPU_Null_fp_context;
#define _CPU_ISR_Flash( _isr_cookie ) \
lm32_flash_interrupts( _isr_cookie );
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x0001 ) != 0;
+}
+
/**
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h b/cpukit/score/cpu/m32c/rtems/score/cpu.h
index 25953d7..e37cda9 100644
--- a/cpukit/score/cpu/m32c/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32c/rtems/score/cpu.h
@@ -669,6 +669,11 @@ typedef struct {
__asm__ volatile( "fclr I" ); \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x40 ) != 0;
+}
+
/**
* @ingroup CPUInterrupt
*
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index f8184dc..5936e15 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -399,6 +399,11 @@ extern void* _VBR;
#define _CPU_ISR_Flash( _level ) \
m68k_flash_interrupts( _level )
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & 0x0700 ) == 0;
+}
+
#define _CPU_ISR_Set_level( _newlevel ) \
m68k_set_interrupt_level( _newlevel )
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 4e1eba1..3fe0b8d 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -699,6 +699,11 @@ uint32_t mips_interrupt_mask( void );
_xlevel = _scratch2; \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & SR_INTERRUPT_ENABLE_BITS ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/moxie/rtems/score/cpu.h b/cpukit/score/cpu/moxie/rtems/score/cpu.h
index d38492a..fdefdcb 100644
--- a/cpukit/score/cpu/moxie/rtems/score/cpu.h
+++ b/cpukit/score/cpu/moxie/rtems/score/cpu.h
@@ -522,6 +522,11 @@ typedef struct {
_CPU_ISR_Disable( _isr_cookie ); \
} while (0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return true;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/nios2/nios2-isr-get-level.c b/cpukit/score/cpu/nios2/nios2-isr-get-level.c
index 498bc79..7c7f6a2 100644
--- a/cpukit/score/cpu/nios2/nios2-isr-get-level.c
+++ b/cpukit/score/cpu/nios2/nios2-isr-get-level.c
@@ -19,6 +19,18 @@
#include <rtems/score/interr.h>
#include <rtems/score/nios2-utility.h>
+bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ switch ( _Nios2_ISR_Get_status_mask() ) {
+ case NIOS2_ISR_STATUS_MASK_EIC_IL:
+ return ((status & NIOS2_STATUS_IL_MASK) >> NIOS2_STATUS_IL_OFFSET) == 0;
+ case NIOS2_ISR_STATUS_MASK_EIC_RSIE:
+ return (status & NIOS2_STATUS_RSIE) != 0;
+ default:
+ return (status & NIOS2_STATUS_PIE) != 0;
+ }
+}
+
uint32_t _CPU_ISR_Get_level( void )
{
uint32_t status = _Nios2_Get_ctlreg_status();
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h
index b1defd2..1e9b7b3 100644
--- a/cpukit/score/cpu/nios2/rtems/score/cpu.h
+++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h
@@ -241,6 +241,8 @@ typedef struct {
__builtin_wrctl( 0, _status ); \
} while ( 0 )
+bool _CPU_ISR_Is_enabled( uint32_t level );
+
/**
* @brief Sets the interrupt level for the executing thread.
*
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
index f1b431e..9af3571 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
@@ -791,6 +791,20 @@ extern Context_Control_fp _CPU_Null_fp_context;
}
/**
+ * @brief Returns true if interrupts are enabled in the specified ISR level,
+ * otherwise returns false.
+ *
+ * @param[in] level The ISR level.
+ *
+ * @retval true Interrupts are enabled in the ISR level.
+ * @retval false Otherwise.
+ */
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return false;
+}
+
+/**
* @ingroup CPUInterrupt
*
* This routine and @ref _CPU_ISR_Get_level
diff --git a/cpukit/score/cpu/or1k/rtems/score/cpu.h b/cpukit/score/cpu/or1k/rtems/score/cpu.h
index 6f0c9ad..58bc927 100644
--- a/cpukit/score/cpu/or1k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/or1k/rtems/score/cpu.h
@@ -528,6 +528,11 @@ static inline void or1k_interrupt_enable(uint32_t level)
_OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
} while(0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & CPU_OR1K_SPR_SR ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index 0c8abae..903bfa5 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -633,6 +633,11 @@ typedef struct {
#ifndef ASM
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & MSR_EE ) != 0;
+}
+
static inline uint32_t _CPU_ISR_Get_level( void )
{
register unsigned int msr;
diff --git a/cpukit/score/cpu/sh/rtems/score/cpu.h b/cpukit/score/cpu/sh/rtems/score/cpu.h
index 409b7a7..2b47bae 100644
--- a/cpukit/score/cpu/sh/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sh/rtems/score/cpu.h
@@ -491,6 +491,12 @@ void CPU_delay( uint32_t microseconds );
#define _CPU_ISR_Flash( _level) \
sh_flash_interrupts( _level)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ sh_get_interrupt_level( level );
+ return level == 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 27393b7..07601de 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -889,6 +889,14 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
+#define _CPU_ISR_Is_enabled( _isr_cookie ) \
+ sparc_interrupt_is_enabled( _isr_cookie )
+
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & SPARC_PSR_PIL_MASK ) == 0;
+}
+
/**
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
index 4e95784..11fbac4 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
@@ -754,6 +754,11 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
#define _CPU_ISR_Flash( _level ) \
sparc_flash_interrupts( _level )
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( psr & SPARC_PSTATE_IE_MASK ) != 0;
+}
+
/*
* Map interrupt level in task mode onto the hardware that the CPU
* actually provides. Currently, interrupt levels which do not
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h
index 47b9055..263c88d 100644
--- a/cpukit/score/cpu/v850/rtems/score/cpu.h
+++ b/cpukit/score/cpu/v850/rtems/score/cpu.h
@@ -627,6 +627,12 @@ typedef struct {
__asm__ __volatile__( "di" ); \
} while (0)
+RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
+{
+ return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
+ != V850_PSW_INTERRUPT_DISABLE;
+}
+
/**
* This routine and @ref _CPU_ISR_Get_level
* Map the interrupt level in task mode onto the hardware that the CPU
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h
index 2ad1740..abfb1b6 100644
--- a/cpukit/score/include/rtems/score/isrlevel.h
+++ b/cpukit/score/include/rtems/score/isrlevel.h
@@ -105,6 +105,18 @@ typedef uint32_t ISR_Level;
} while (0)
/**
+ * @brief Returns true if interrupts are enabled in the specified interrupt
+ * level, otherwise returns false.
+ *
+ * @param[in] _level The ISR level.
+ *
+ * @retval true Interrupts are enabled in the interrupt level.
+ * @retval false Otherwise.
+ */
+#define _ISR_Is_enabled( _level ) \
+ _CPU_ISR_Is_enabled( _level )
+
+/**
* @brief Return current interrupt level.
*
* This routine returns the current interrupt level.
diff --git a/testsuites/sptests/sp37/init.c b/testsuites/sptests/sp37/init.c
index e87ad9f..08d6285 100644
--- a/testsuites/sptests/sp37/init.c
+++ b/testsuites/sptests/sp37/init.c
@@ -339,10 +339,12 @@ void test_interrupt_inline(void)
rtems_interrupt_local_disable( level );
isr_level_1 = _ISR_Get_level();
rtems_test_assert( isr_level_1 != isr_level_0 );
+ rtems_test_assert( _ISR_Is_enabled( level ) );
rtems_interrupt_local_disable( level_1 );
isr_level_2 = _ISR_Get_level();
rtems_test_assert( isr_level_2 == isr_level_1 );
+ rtems_test_assert( !_ISR_Is_enabled( level_1 ) );
rtems_interrupt_local_enable( level_1 );
rtems_test_assert( _ISR_Get_level() == isr_level_1 );
--
1.8.4.5
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