Backport of ARM cache, RTL and TMS570 to RTEMS 4.11 Was: Simple question about RTL

[Pavel Pisa]

Hello Chris and Joel,

I would like to correct my mistake which breaks RTEMS 4.11 build for non-ARM
architectures, as fast as possible. Proposed solution on devel list.

[PATCH] libdl/rtl-obj.c: synchronize cache should not depend on CPU_CACHE_LINE_BYTES.

[PATCH] bsps/arm: do not introduce CPU_CACHE_LINE_BYTES in 4.11 and correct CPU_STRUCTURE_ALIGNMENT.

I have checked 4.11 build with patches for Raspberry Pi 2 and TMS570.
including RTL functionality on targets. I have tested 4.11 that it
works on TMS570 with lwIP in build without initialization when
loaded to SDRAM with external init and standalone RTEMS Flash version
which includes complete RTEMS driven initialization.

I have tested that i386 builds and checked to run ticker,
my dlopen and PCI i82557b/fxp1 betworking tests in QEMU.
i386 build has been done mainly to check that I have not
introduced problem to non-ARM architectures this time.

Do you agree with fixes?
What is your opinion for CPU_CACHE_LINE_BYTES in 4.11.
Do you agree/prefer that it should not be introduced back
(which I have done by mistake) and kept as 4.12 specific?

Best wishes,

               Pavel