Backport of ARM cache, RTL and TMS570 to RTEMS 4.11 Was: Simple question about RTL

[Pavel Pisa]

Hello Chris,

On Tuesday 04 of October 2016 23:10:20 Chris Johns wrote:
> On 04/10/2016 09:51, Pavel Pisa wrote:
> > Hello Chris and Joel,
> >
> > I would like to correct my mistake which breaks RTEMS 4.11 build for
> > non-ARM architectures, as fast as possible. Proposed solution on devel
> > list.
> >
> > [PATCH] libdl/rtl-obj.c: synchronize cache should not depend on
> > CPU_CACHE_LINE_BYTES.
> >
> > [PATCH] bsps/arm: do not introduce CPU_CACHE_LINE_BYTES in 4.11 and
> > correct CPU_STRUCTURE_ALIGNMENT.
> >
> > I have checked 4.11 build with patches for Raspberry Pi 2 and TMS570.
> > including RTL functionality on targets. I have tested 4.11 that it
> > works on TMS570 with lwIP in build without initialization when
> > loaded to SDRAM with external init and standalone RTEMS Flash version
> > which includes complete RTEMS driven initialization.
> >
> > I have tested that i386 builds and checked to run ticker,
> > my dlopen and PCI i82557b/fxp1 betworking tests in QEMU.
> > i386 build has been done mainly to check that I have not
> > introduced problem to non-ARM architectures this time.
>
> Great.
>
> > Do you agree with fixes?
>
> Yes.
>
> > What is your opinion for CPU_CACHE_LINE_BYTES in 4.11.
> > Do you agree/prefer that it should not be introduced back
> > (which I have done by mistake) and kept as 4.12 specific?
>
> I agree it should not be introduced back into 4.11.

OK, I have pushed changes to 4.11 and I have changed master
to use the same rtems_cache_get_maximal_line_size() in RTL
as is used 4.11 now to have support consistent between branches
and have chance to catch eventual problem even on master.

Best wishes,

              Pavel