Optimization issue in RISC-V BSP

[Denis Obrezkov]

2017-08-01 2:01 GMT+02:00 Hesham Almatary <heshamelmatary at gmail.com>:

> Hi Denis,
>
> If you're not using interrupts (i.e. only using dummy clock), then
> trap_entry at start.S shouldn't be executed after bootstrap. That's
> why I suggested you use dummy clock first to figure out if the problem
> is with the context switch code or not.
>
> I'm not getting the full context/details; did you try with dummy clock
> first (interrupts disabled) and it didn't work? If so, you can set a
> breakpoint at trap_entry to check it's not being executed.
>

I checked that trap_entry saves registers properly. And I am trying to
implement interrupt-driven clock driver.
With it, I can at least obtain some ticks.

As for now, I am getting an error on mret instruction, I will try to figure
out tomorrow, why it happens.
Also, in my debugger 'display /i $pc' suddenly started to work properly.
So, now I can debug a bit more efficient.
-- 
Regards, Denis Obrezkov
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