Optimization issue in RISC-V BSP

[Gedare Bloom]

On Wed, Aug 2, 2017 at 4:54 AM, Denis Obrezkov <denisobrezkov at gmail.com> wrote:
>> > + Special registers
>> Yes, this might be the issue, specifically if the port is using
>> interrupts. For example, mstatus/mcause/mepc might need to be saved
>> and/or reset.
>>
>> What I'm suspicious of is that the trap_entry code is the problem,
>> since it didn't have a chance to get executed/tested on my Spike
>> (dummy clock simulated) BSP/Spike, especially after updating the port
>> from 2015 to 2017 (RISC-V ABI has changed).
>>
>> >
>> > If it is not preserved across a subroutine call, then it does not have
>> > to be
>> > in the context switch but is in the ISR context.
>> >
>> > If it is preserved across subroutine calls, then it is in the context
>> > switch.
>> >
>> > Special registers have to be analyzed. Some may have a magic value
>> > across
>> > the entire system life. Others will require special handling.
>> >
>> > Every register needs to be logically places in a class for management
>> > purposes.
>> >
>> >
>> >> As for now, I am getting an error on mret instruction, I will try to
>> >> figure
>> >> out tomorrow, why it happens.
>> >> Also, in my debugger 'display /i $pc' suddenly started to work
>> >> properly.
>> >> So, now I can debug a bit more efficient.
>> >> --
>> >> Regards, Denis Obrezkov
>> >
>> >
>> >
>> > --
>> > Hesham
>> >
>> >
>>
>>
>>
>> --
>> Hesham
>
> Hello, interrupt-driven clock driver works to some extent!
>
> *** LOW MEMORY CLOCK TICK TEST ***
>
> TA1 - rtems_clock_get_tod - 09:00:00 12/31/1988
>
> TA2 - rtems_clock_get_tod - 09:00:00 12/31/1988
>
> TA3 - rtems_clock_get_tod - 09:00:00 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:04 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:09 12/31/1988
>
> TA2 - rtems_clock_get_tod - 09:00:10 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:14 12/31/1988
>
> TA3 - rtems_clock_get_tod - 09:00:15 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:19 12/31/1988
>
> TA2 - rtems_clock_get_tod - 09:00:20 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:24 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:29 12/31/1988
>
> TA3 - rtems_clock_get_tod - 09:00:30 12/31/1988
>
> TA2 - rtems_clock_get_tod - 09:00:30 12/31/1988
>
> TA1 - rtems_clock_get_tod - 09:00:34 12/31/1988
>
> *** END OF LOW MEMORY CLOCK TICK TEST ***
>
> Fatal Error 5.0 Halted
>
This appears to be basically correct. There is some roundoff error in
timing when you don't have a good timecounter implementation.

>
> I've started to save and restore mepc and mcause registers, though, they are
> handled differently in the
> provided example.
>
> Also, the optimized version doesn't work.
> --
> Regards, Denis Obrezkov
>
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