Common practice of interrupt implementation in RTEMS

[Denis Obrezkov]

Could someone expand it a bit.
For example, I can provide an interrupt table in my start.S file.
So, when interrupts occurs, pc counter is set to the appropriate address in
table entry.
And we have several RTEMS interrupt handlers. And RTEMS handlers table.
How do they relate to each other?


2017-06-30 20:48 GMT+02:00 Gedare Bloom <gedare at rtems.org>:

> https://docs.rtems.org/branches/master/cpu-supplement/port.html#
> interrupt-processing
>
> https://docs.rtems.org/branches/master/bsp-howto.
> html#set-vector-install-an-interrupt-vector
>
>
> On Fri, Jun 30, 2017 at 10:49 AM, Denis Obrezkov
> <denisobrezkov at gmail.com> wrote:
> > Hello all,
> > what is the common practice of interrupt implementation in RTEMS?
> > I wasn't able to find much information in RTEMS BSP manual.
> >
> > My platform RISC-V has vectored interrupts and exceptions.
> > A cause of an exception or of an interrupt is always available in
> 'mcause'
> > register.
> > But for interrupts an address of a handlers' table can also be
> dynamically
> > provided.
> > So, what should I do in order to implement interrupt handlers?
> > What is the consequence of steps when interrupt appears (save stack,
> make a
> > routine...)?
> > Also, what is a good example of a BSP which implements ISR in a proper
> way?
> >
> > --
> > Regards, Denis Obrezkov
> >
> > _______________________________________________
> > devel mailing list
> > devel at rtems.org
> > http://lists.rtems.org/mailman/listinfo/devel
>



-- 
Regards, Denis Obrezkov
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