RTEMS Tier Allocations.
chrisj at rtems.org
Sun Oct 22 00:17:57 UTC 2017
This post is the start of the process to formally define the tiers for RTEMS.
The RTEMS Tiers helps the project and you understand the current tested state of
RTEMS in an open and public manner. It is important we do this and we get valid
Up to this starting I have made a bit of guess at the structure and now is the
time to create the tiers based on real results. This is needed so we can move to
cutting a 5.1(?) release.
The tiers are defined here:
The current tier structure can be viewed here:
To be placed in a tier there needs to be test results posted to build at rtems.org.
The archive of recent test results can be viewed here:
I encourage everyone to run the tests and add `--mail` to the `rtems-test`
command line and post results. If you need a hand doing this or there are
problems please ask.
1. We need to examine the current failures, timeouts and invalid test results
and either fix or tag as expected failure.
2. Tier 4 architectures and BSP can be removed after the next release unless
someone steps up and we can move the BSP to tier 3.
3. We will not or should not be changing tiers once a release branch is made.
1. ARM (Cortex-A9, Cortex-A8)
2. Intel i386 (i686)
Empty (no posted test results, SPARC sim, ARM qemu anyone?)
More information about the devel