Status of smptests ...?
sebastian.huber at embedded-brains.de
Tue Dec 11 15:01:41 UTC 2018
On 11/12/2018 15:55, Jiri Gaisler wrote:
>> Even if the screen is a guide of what to expect in some cases.
>> How does the smp support in sis switch back and forth between the
>> cores? Per cycle, instruction, etc. Qemu switches per instruction
>> translation block as I recall.
> The scheduling slice is (dynamically) configurable in number of clock
> cycles. I currently have it set to 50 but the smp tests works also at
> 1000. The scheduling overhead is ~ 10% at 50 cycles, so the slowdown is
> acceptable even for non-smp loads. My plan is to simulate each cpu
> instance in a separate host thread, and synchronize them on events in
> the event queue. Not quite sure how well that will work though ...:-)
How do you synchronize the simulated memory accesses across the threads?
The big advantage of SIS compared to Qemu for example is that the
simulated execution is very predictable and stable across different
simulation runs. It would be nice if this would be also the case for the
SMP support even if this costs performance. So for example just use a
single thread and switch to an other processor every X instructions.
Sebastian Huber, embedded brains GmbH
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