RISC-V Update (2)

Sebastian Huber sebastian.huber at embedded-brains.de
Wed Jul 25 10:21:12 UTC 2018


Hello,

I checked in a couple of patches today aiming to improve the RISC-V 
support. The Platform-Level Interrupt Controller (PLIC) and 
inter-processor interrupts are now supported. To run the BSP on Qemu 
some patches are necessary:

https://github.com/riscv/riscv-qemu/pull/155

There is a general Qemu/GDB issue:

https://github.com/riscv/riscv-qemu/issues/156

The SMP tests on Qemu seem to work like on ARM for example. My next step 
is to run tests on a FPGA board which runs a two hart RISC-V SoC.

https://lists.rtems.org/pipermail/build/2018-July/000771.html

There is an open tool chain issue:

https://sourceware.org/bugzilla/show_bug.cgi?id=23451

-- 
Sebastian Huber, embedded brains GmbH

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E-Mail  : sebastian.huber at embedded-brains.de
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