RISC-V tool chain

[Hesham Almatary]

On Mon, May 28, 2018 at 6:23 AM, Sebastian Huber
<sebastian.huber at embedded-brains.de> wrote:
> Hello,
>
> we currently have a riscv32-rtems* and riscv64-rtems* tool chain. However,
> the RISC-V GCC is a bi-arch compiler, e.g. we have
>
> riscv32-rtems5-gcc --print-multi-lib
> .;
> rv32i/ilp32;@march=rv32i at mabi=ilp32
> rv32im/ilp32;@march=rv32im at mabi=ilp32
> rv32iac/ilp32;@march=rv32iac at mabi=ilp32
> rv32imac/ilp32;@march=rv32imac at mabi=ilp32
> rv32imafc/ilp32f;@march=rv32imafc at mabi=ilp32f
> rv64imac/lp64;@march=rv64imac at mabi=lp64
> rv64imafdc/lp64d;@march=rv64imafdc at mabi=lp64d
>
> riscv64-rtems5-gcc --print-multi-lib
> .;
> rv32i/ilp32;@march=rv32i at mabi=ilp32
> rv32im/ilp32;@march=rv32im at mabi=ilp32
> rv32iac/ilp32;@march=rv32iac at mabi=ilp32
> rv32imac/ilp32;@march=rv32imac at mabi=ilp32
> rv32imafc/ilp32f;@march=rv32imafc at mabi=ilp32f
> rv64imac/lp64;@march=rv64imac at mabi=lp64
> rv64imafdc/lp64d;@march=rv64imafdc at mabi=lp64d
>
> The only difference is the default ISA.
>
> I suggest to merge the two tool chains into one riscv-rtems* variant.
>
> The riscv64_generic BSP uses -mcmodel=medany. Is this ABI compatible to the
> multilibs which use the default (-mcmodel=medlow)?
>
I guess that's one reason for the relocation error I get when I change
RAM to 0x80000000). I'd say no.

> --
> Sebastian Huber, embedded brains GmbH
>
> Address : Dornierstr. 4, D-82178 Puchheim, Germany
> Phone   : +49 89 189 47 41-16
> Fax     : +49 89 189 47 41-09
> E-Mail  : sebastian.huber at embedded-brains.de
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>
> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>



-- 
Hesham