RISC-V BSP memory map

[Sebastian Huber]

On 28/05/18 10:48, Hesham Almatary wrote:
>> The FE310-G000 has the ROM at 0x2000_0000 and RAM (DTIM) at 0x8000_0000.
>>
>> The FU540-C000 (and Qemu "virt") has the ROM at 0x2000_0000 and RAM (DDR) at
>> 0x8000_0000.
>>
>> So, why is the memory at 0x1000_0000 and not 0x8000_0000?
>>
> That's basically a hack. The reason is when I tried to change RAM to
> 0x80000000 (above 2GiB), I get relocations errors even when I pass
> -mcmodel=medany (riscv-pk and seL4 but they don't use stdlib or
> startfiles from gcc). Maybe you can help with that error and suggest a
> solution as I don't know?
> The errors happen during linking stage of libc and crt* stuff. Please
> see error log below:

It looks like there is a blocking issue in the RISC-V tool chain here if 
we want to support 64-bit variants running at 0x80000000:

https://sourceware.org/bugzilla/show_bug.cgi?id=23244

-- 
Sebastian Huber, embedded brains GmbH

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