Synchronization Problem on MPCI/shmdr on 2 Cores

[李MY]

Hi Joel,

I ported RTEMS 4.11 to TI C6678 DSP. To enable multicore communication, I
leveraged shared memory template provided in shmdr directory. When I tested
it on 2 cores, there was a problem I currently cannot solve.

Say, core 0 creates a *GLOBAL* message queue. Core 1 is the sender and core
0 the receiver. Everything goes well: core 0 receives a message instantly
after core 1 sends one. However, when I switch their roles, things are
beyond expectation: core 1 does not receive any until core 0 finishes its
sending. The worst case is that if core 0 keeps on sending messages, core 1
will stay blocked and gets starved, which impacts its real-time
requirements badly.

I think that's because core 0 takes the preemptive opportunities to always
manipulate global objects created on itself. For a stopgap, I had to rely
on manually (hard-coded) explicit delay to meet the anticipation (ABABAB
pattern between two nodes). But that is brittle since the latency of cache
access and shared memory access may vary on different boards.

Was I porting it wrong? Or is there already a solution to this?

Thanks,
Maxul
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