[PATCH v2 0/4] Xilinx Zynq UltraScale+ MPSoC BSP
Sebastian Huber
sebastian.huber at embedded-brains.de
Thu Apr 11 05:30:47 UTC 2019
Hello Jeff,
On 11/04/2019 01:38, Jeff Kubascik wrote:
> From: Jeff Kubascik <jeff.kubascik at dornerworks.com>
>
> This set of patches creates a new BSP layer for the Xilinx Zynq UltraScale+
> MPSoC.
>
> The first two patches move the zynq-uart driver into a common directory, so that
> both the xilinx-zynq and xilinx-zynqmp BSPs can use it.
>
> The third patch copies the xilinx-zynq BSP layer to xilinx-zynqmp, to use as a
> starting point.
>
> The fourth patch modifies the xilinx-zynqmp BSP layer as needed to work for the
> Ultra96 board, which is based on the MPSoC. Only AArch32 mode is currently
> supported.
I checked in a slightly modified patch set. Please update also the
documentation:
https://git.rtems.org/rtems-docs/tree/user/bsps/bsps-arm.rst
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47 41-09
E-Mail : sebastian.huber at embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
More information about the devel
mailing list