GSoC 2019: POSIX Compliance - FENV Environment probably not working properly in RISCV

[Vaibhav Gupta]

On Wed, Aug 14, 2019 at 8:56 PM Hesham Almatary <heshamelmatary at gmail.com>
wrote:

> On Wed, 14 Aug 2019 at 16:18, Vaibhav Gupta <vaibhavgupta40 at gmail.com>
> wrote:
> >
> >
> >
> > On Wed, Aug 14, 2019, 8:09 PM Joel Sherrill <joel at rtems.org> wrote:
> >>
> >> On Wed, Aug 14, 2019 at 9:35 AM Vaibhav Gupta <vaibhavgupta40 at gmail.com>
> wrote:
> >> >
> >> > You are also getting same error :(
> >> > I thought problem is with my system/laptop and was trying to correct
> things.
> >> > Should we take the discussion to newlib?
> >>
> >> I would like Jiri and Hesham to chime in on the next step. I don't
> >> know the RISC-V
> >> well enough to say if this is a bug in risc-v fenv or not.
> >
> > Okay
>
> Can you try to build a BSP with FPU instructions? rv32imafdc? and test
> again? I assume this will eventually do FPU calculations that will
> emit FPU instructions in the case of rv32imafdc or softfloat in the
> case of rv32imac.
>
Hello, I tried with rv32imafdc too, same problem. I have sent a more proper
report on
devel with the patch for code I was working on.
It seems to be riscv specific issue.

-- Vaibhav Gupta

>
>
>
> --
> Hesham
>
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