BSP for Xilinx Zynq UltraScale+ MPSoC platform

[Alan Cudmore]

I would like to see both R5 and A53 support. Having RTEMS on the R5 could
allow it to be used for OpenAMP communication with the A53. Normally the
OpenAMP port for the Xilinx board uses bare metal or FreeRTOS on the R5.

For the A53, is there a reason for choosing Aarch32 vs Aarch64 for the
RTEMS port?

I hope we will see a future Beagle board based on the one of the Ti Sitara
SoCs that has R5 and A53.
http://www.ti.com/processors/sitara-arm/am6x-cortex-a53-r5/overview.html

Alan


On Wed, Jan 23, 2019 at 11:31 AM Joel Sherrill <joel at rtems.org> wrote:

>
>
> On Wed, Jan 23, 2019 at 2:34 AM Sebastian Huber <
> sebastian.huber at embedded-brains.de> wrote:
>
>> Hello,
>>
>> we will very likely soon work a BSP for the Xilinx Zynq UltraScale+
>> MPSoC platform:
>>
>> https://devel.rtems.org/ticket/3682
>>
>> Please let me know, if you are interested in support for the Cortex-R5
>> processors or AArch64 mode.
>>
>
> We are currently working on a BSP for an R52 in a custom SoC. When
> ready, it will be submitted. There will be a public qemu repo with support
> for the SoC. Some of the ARM IP is a bit newer than what has drivers
> in the tree.
>
> --joel
>
>
>>
>> The development platform will be this evaluation kit:
>>
>> https://www.xilinx.com/products/boards-and-kits/zcu104.html
>>
>> --
>> Sebastian Huber, embedded brains GmbH
>>
>> Address : Dornierstr. 4, D-82178 Puchheim, Germany
>> Phone   : +49 89 189 47 41-16
>> Fax     : +49 89 189 47 41-09
>> E-Mail  : sebastian.huber at embedded-brains.de
>> PGP     : Public key available on request.
>>
>> Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>>
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>
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