Status of RISCV port on sis

[Jiri Gaisler]

On 1/11/19 1:45 PM, Sebastian Huber wrote:
> ----- Am 11. Jan 2019 um 13:36 schrieb Jiri Gaisler jiri at gaisler.se:
>
>> On 1/9/19 10:46 AM, Sebastian Huber wrote:
>>> Hello Jiri,
>>>
>>> could you please rebase your work to this RTEMS commit:
>>>
>>> https://git.rtems.org/rtems/commit/?id=b9ffc41c9678fb3c5386c1a6ab394656ec85dbc6
>>>
>> This works fine for me - I can now pass all uni-processor tests. On SMP, I still
>> have a few fails but I think they are related to the simulator and the
>> compressed RISC-V instruction set. I will investigate further ...
> If you use the latest tools, then the OpenMP tests don't link. I have to update the RSB to include this fix:
>
> https://github.com/gcc-mirror/gcc/commit/a415601710979a5e6ca443c7e914b7e334055642

I have not been hit by this (yet), but I will keep it in mind.


>
>> $ rtems-test --rtems-bsp=riscv-sis riscv-rtems5/c/grlib/testsuites
>>
>> Passed:        574
>> Failed:          0
>> User Input:      5
>> Expected Fail:   0
>> Indeterminate:   0
>> Benchmark:       3
>> Timeout:         0
>> Invalid:         0
>> Wrong Version:   0
>> Wrong Build:     0
>> Wrong Tools:     0
>> ------------------
>> Total:         582
>> User Input:
>>  monitor.exe
>>  termios.exe
>>  top.exe
>>  capture.exe
>>  fileio.exe
>> Benchmark:
>>  dhrystone.exe
>>  whetstone.exe
>>  linpack.exe
>> Average test time: 0:00:00.711573
>> Testing time     : 0:06:54.135695
> This is great. You mentioned some spintrcritical* failures in your last report. Was this a simulator issue?

Yes, the sim did not always disable external interrupts after a trap. Obviously not a good idea ... :-)