Strange RTEMS DMA Access on Zynq [Solved]

Chris Johns chrisj at
Sun Jan 13 22:24:08 UTC 2019

On 14/1/19 9:02 am, Misra, Avinash wrote:
> Thank you for your insightful email below, it went a long way towards solving my issue. I wanted to describe what I ran into here in case someone else runs into this in the future.  

Thank you for the follow up and nice work getting it running.

> My issue was comprised of 2 parts:
> 1.) Turns out I had an alignment issue with the DMA to begin with, which is why I kept getting random offsets in where my data would appear and also as to why my data would appear clipped. I'm using the AXI DMA IP and it was configured to be an "auto size" on the READ which ended up doing 64-bit transactions on a 32-bit bus. Sizing this back to 32-bit gave me what I would expect to see on the ILA in the firmware. The next thing I did was ensured my static buffer was aligned on a  32-bit address boundary this was done using the  GCC align attribute to do this. Then, finally, to make sure that I wouldn't run into future alignment issues I enabled the "Allow Unaligned Transactions" option in the AXI DMA IP which, per the Xilinx Documentation, allows for and resolves unaligned address issues.
> 2.) The next thing that I had to do after getting the alignment issues sorted out was to ensure I was invalidating the cache. What I learned was that I had to do a rtems_cache_flush_multiple_data_lines() before starting the DMA and after the DMA had finished.

If you are reading from the memory in to the IP then you would need to flush the
memory otherwise I do not think you need too.

> By taking the steps outlined above I am able to obtain my data from the DMA.

I have not used the AXI DMA IP. I know with the CMDA IP you need to be careful
when handling the done interrupt because the DMA can still be active by the time
the software enters the interrupt. The DMA engine is finished however the data
is still working it's way to the memory.


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