[PATCH] rtems-tools/covoar: -f switch was not used to select coverage format
joel at rtems.org
Thu Jan 24 15:19:53 UTC 2019
On Thu, Jan 24, 2019 at 8:46 AM Jiri Gaisler <jiri at gaisler.se> wrote:
> On 1/24/19 2:19 PM, Joel Sherrill wrote:
> On Thu, Jan 24, 2019, 6:38 AM Jiri Gaisler <jiri at gaisler.se wrote:
>> Small patch to fix covoar to work with TSIM coverage files. It should be
>> noted that covoar erroneously marks some code as uncovered while it is
>> marked as covered in the coverage file. This seems to be due to incorrect
>> parsing of the symbol table in the exec file. I will file a ticket for this
>> on trac ..
> Is this the entry and exit code of a method or something else? The switch
> to dwarf info seems to have caused that and not marking assembly from
> inlined methods.
> I notice two problems: the first instruction in a range is sometimes
> marked as uncovered:
> 4000807c <_Freechain_Get>:
> Freechain_Control *freechain,
> Freechain_Allocator allocator,
> size_t number_nodes_to_extend,
> size_t node_size
> 4000807c: 9d e3 bf a0 save %sp, -96, %sp
> <== NOT EXECUTED
> 40008080: ba 10 00 18 mov %i0, %i5
> return _Chain_Immutable_head( the_chain )->next;
> 40008084: f0 06 00 00 ld [ %i0 ], %i0
> even though it is marked as executed in the coverage file. The second
> problems is that the size of ranges is sometimes off by one byte, e.g. 21
> bytes instead of 20. This can only be seen when debugging covoar in gdb.
I recall that the CoverageReaderTSIM code did an offset of +1 to +4 from
the address. Perhaps it just needs to be 0-3. :)
The off by one on the ranges is something else.
> I will prepare a patch for sis to add the coverage, and then covoar can be
> debugged using our standard tools. Maybe it could be a task for GSoC ...?
> An additional task could also be to add RISC-V support to covoar, which is
> currently missing...
Yes on GSoC. Use the keywords "SoC, testing" and it will show up in the
Clearly one bug isn't a GSoC project but if we file tickets for all the
issues, then that's a GSoC project.
RISC-V support would be awesome! I am thrilled you have added support for
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