RTEMS on embedded CPUs(RISCV)

[Sebastian Huber]

On 05/06/2019 15:09, Hesham Almatary wrote:
> On Wed, 5 Jun 2019 at 07:11, Sebastian Huber
> <sebastian.huber at embedded-brains.de>  wrote:
>> Hello Sachin,
>>
>> On 05/06/2019 06:15,sachin.ghadi at sifive.com  wrote:
>>> Hi RTEMS dev team,
>>>
>>> I don’t know if I should send this query to users list or developer list.
>>>
>>> I am working on the getting RTEMS BSP ported on the one of RISC-V
>>> based SoC.
>>>
>>> Current RTEMS has support only for Spike simulator.
>>>
>> we have also support for Qemu. At least at some point in time it worked
>> with a non-upstream Qemu. I am not sure how far the upstreaming of the
>> Qemu support progressed in the last months.
>>
> Upstream QEMU runs RTEMS fine with -virt board. Also, I tested 32-bit RTEMS
> variants on Zynq-based FPGA with Bluespec cores, UART and DTB [1].
>
> [1]https://github.com/bluespec/Piccolo
>

This reminds me off your patch set you sent a couple of weeks ago. 
Sorry, I forgot it after my holidays. Would you mind sending it again 
rebased to the current master?

-- 
Sebastian Huber, embedded brains GmbH

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