[PATCH] arm: Select the TLB invalidate based on the core's Id variant.

[chrisj at rtems.org]

From: Chris Johns <chrisj at rtems.org>

Closes #3760
---
 bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index c2be0f566e..8e261366ed 100644
--- a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
+++ b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
@@ -42,6 +42,7 @@ static uint32_t set_translation_table_entries(
   uint32_t ctrl;
   uint32_t section_flags_of_first_entry;
   uint32_t i;
+  uint32_t variant = (arm_cp15_get_id_code() >> 20) & 0xf;
   void *first_ttb_addr;
   void *last_ttb_end;
 
@@ -65,12 +66,15 @@ static uint32_t set_translation_table_entries(
 
   for ( i = istart; i != iend; i = (i + 1U) & index_mask ) {
     void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT);
-    #if defined(__ARM_ARCH_7A__)
-    arm_cp15_tlb_invalidate_entry_all_asids(mva);
-    #else
-    arm_cp15_tlb_instruction_invalidate_entry(mva);
-    arm_cp15_tlb_data_invalidate_entry(mva);
-    #endif
+    if (variant <= 3) {
+      /* Cortex-A8 or earlier */
+      arm_cp15_tlb_instruction_invalidate_entry(mva);
+      arm_cp15_tlb_data_invalidate_entry(mva);
+    }
+    else {
+      /* Cortex-A9 or later */
+      arm_cp15_tlb_invalidate_entry_all_asids(mva);
+    }
   }
 
   _ARM_Data_synchronization_barrier();
-- 
2.20.1 (Apple Git-117)