RTEMS on embedded CPUs(RISCV)

[Joel Sherrill]

On Tue, Jun 4, 2019, 11:15 PM <sachin.ghadi at sifive.com> wrote:

> Hi RTEMS dev team,
>
> I don’t know if I should send this query to users list or developer list.
>
> I am working on the getting RTEMS BSP ported on the one of RISC-V based
> SoC.
>
> Current RTEMS has support only for Spike simulator.
>
>
>
> It looks like RTEMS does not fit very well on the systems having less RAM.
>
> We have 64K of RAM on our standard FPGA development kit for our E series
> embedded cores.
>
> All of the RTEMS test does not fit within this given RAM and linker throws
> error.
>

Mark these in a .tcfg in the BSP config directory. As Sebastian notes there
are other BSPs that disable many tests. Individual tests do not fit either
due to test size issues (say 1MB RAM disk or many object instances) or
feature (dynamic loading). It is expected. You should still have enough
tests for confidence.

>
>
> Regarding this I have few questions
>
>    1. Does RTEMS accept support for new core with limited tests passing?
>    Or one need full test suit passing to qualify complete test?
>
> If you mean BSP rather than multilib variant, the answer is usually yes.
If it is passing what will fit.


>    1.
>    2. I saw some thread regarding tinyRTEMS
>
> https://devel.rtems.org/wiki/Projects/TinyRTEMS
>
> Is there any plan for this to support as separate port for embedded cores
> with limited resources?
>

This Wiki page was mine to capture ideas on how to drop size. All of them
and more have been implemented.

The issue is that although you can do some things in low memory
environments, there are limits. Some features are off the table and you
will be limited in the number of instances of objects you can instance.

--joel

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> Thanks and Regards,
>
> /Sachin
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