[PATCH] cpukit/arm: Correct register definition

[Jonathan Brandmeyer]

The register definition for the CP15 PMCR (performance monitor control
register) has the bits for X (export enable) and D (clock divider
enable) backwards.  Correct them according to ARMv7-A/R Architecture
Reference Manual, Rev C, Section B4.1.117.

Consequences: On an implementation that starts off with D set at reset,
the clock divider will not be disabled by using RTEMS' definition of the
D bit.

Tested by using the counter on Xilinx Zynq 7020 to measure some atomic
accesses and cache flushing operations.
---
 cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index a7e7542bcb..b3a61d2fe1 100644
--- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
+++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
@@ -1604,8 +1604,8 @@ arm_cp15_set_performance_monitors_count_enable_set(uint32_t val)
 #define ARM_CP15_PMCR_IDCODE(x) ((x) << 16)
 #define ARM_CP15_PMCR_N(x) ((x) << 11)
 #define ARM_CP15_PMCR_DP (1U << 5)
-#define ARM_CP15_PMCR_X (1U << 3)
-#define ARM_CP15_PMCR_D (1U << 4)
+#define ARM_CP15_PMCR_X (1U << 4)
+#define ARM_CP15_PMCR_D (1U << 3)
 #define ARM_CP15_PMCR_C (1U << 2)
 #define ARM_CP15_PMCR_P (1U << 1)
 #define ARM_CP15_PMCR_E (1U << 0)
-- 
2.11.0