Odd Formatting in CPU Supplement

[Sebastian Huber]

Hello Joel,

it is in line what GCC prints:

riscv-rtems5-gcc -print-multi-lib
.;
rv32i/ilp32;@march=rv32i at mabi=ilp32
rv32im/ilp32;@march=rv32im at mabi=ilp32
rv32imafd/ilp32d;@march=rv32imafd at mabi=ilp32d
rv32iac/ilp32;@march=rv32iac at mabi=ilp32
rv32imac/ilp32;@march=rv32imac at mabi=ilp32
rv32imafc/ilp32f;@march=rv32imafc at mabi=ilp32f
rv64imafd/lp64d;@march=rv64imafd at mabi=lp64d
rv64imafd/lp64d/medany;@march=rv64imafd at mabi=lp64d at mcmodel=medany
rv64imac/lp64;@march=rv64imac at mabi=lp64
rv64imac/lp64/medany;@march=rv64imac at mabi=lp64 at mcmodel=medany
rv64imafdc/lp64d;@march=rv64imafdc at mabi=lp64d
rv64imafdc/lp64d/medany;@march=rv64imafdc at mabi=lp64d at mcmodel=medany

I don't mind to change it, but it should be consistent with ARM.

-- 
Sebastian Huber, embedded brains GmbH

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