Potential SIS or RTEMS/libbsd problem
jiri at gaisler.se
Mon May 27 09:03:58 UTC 2019
On 5/23/19 1:47 PM, Sebastian Huber wrote:
> On 22/05/2019 22:34, Jiri Gaisler wrote:
>> Adding a pseudo-random delay of 0 - 15 clocks to each trap/interrupt causes the test to pass on all cpu configurations with the default time slice (50)..! I am not sure what this means - it could be a hidden race condition, the algorithm might need some jitter to work or it could still be a simulator issue.
> Adding a pseudo-random delay to interrupts is probably not enough. Sometimes the atomic instructions are carried out with interrupts disabled. Would it be possible to add a pseudo-random delay to each of the instruction cycles per core?
I have pushed a patch to my sis repository at rtems.org that adds an emulated L1 cache to SMP configurations and also improves timing for a few instructions. The epoch.exe test now runs on both SPARC and RISC-V for 3 and 4 cpus. To pass on 2 cpus, a smaller time-slice in the simulator is needed, e.g. -d 17. Feel free to test...
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