Support for AXI interconnect targetting the XILINX ZC706

[Chris Johns]

On 6/11/19 10:51 am, Misra, Avinash wrote:
> Tiago, another "gotcha" I want to point out is when launching your target application via Xilinx SDK and using RTEMS with SMP Mode (setting # of processors > 1). When you program and launch your application to CPU0 on the Zynq via Xilinx SDK, Xilinx will place CPU1 in Idle Mode. RTEMS will be stuck in a perpetual wait state waiting for CPU1 to come up before launching. You will need to physical click start on CPU1 in SDK in order for CPU1 to resume execution and allow RTEMS to exit its wait barrier. If you program your image to a SD Card or the onboard flash and use FSBL then you will not need to do this.

Nice and thanks.

> Chris -- Does RTEMS have a wiki where we can maybe compile a list of Gotchas/FAQs/Things to be aware of when programming for the Zynq and other platforms? 

Yes, here ....

https://docs.rtems.org/branches/master/user/bsps/bsps-arm.html#xilinx-zynq

This is where we need to collect the pieces we have. In the wiki there is:

https://devel.rtems.org/wiki/Boards/Zynq%20-%20Zedboard
https://devel.rtems.org/wiki/Debugging/OpenOCD/Xilinx_Zynq

I would welcome patches.

Chris