[RTEMS][PATCH v2 2/2] bsp/riscv: Remove duplicate files
Pragnesh Patel
pragnesh.patel at sifive.com
Tue Sep 10 06:34:20 UTC 2019
Delete clockdrv.c, irq.c and bsp_fatal_halt.c and
Makefile.am now points to bsps/riscv/shared directory
Update #3785.
Signed-off-by: Pragnesh Patel <pragnesh.patel at sifive.com>
---
bsps/riscv/riscv/clock/clockdrv.c | 212 -----------------
bsps/riscv/riscv/irq/irq.c | 379 -------------------------------
bsps/riscv/riscv/start/bsp_fatal_halt.c | 53 -----
c/src/lib/libbsp/riscv/riscv/Makefile.am | 6 +-
4 files changed, 3 insertions(+), 647 deletions(-)
delete mode 100644 bsps/riscv/riscv/clock/clockdrv.c
delete mode 100644 bsps/riscv/riscv/irq/irq.c
delete mode 100644 bsps/riscv/riscv/start/bsp_fatal_halt.c
diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c
deleted file mode 100644
index 7e6034d..0000000
--- a/bsps/riscv/riscv/clock/clockdrv.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/**
- * @file
- *
- * @ingroup bsp_clock
- *
- * @brief riscv clock support.
- */
-
-/*
- * Copyright (c) 2018 embedded brains GmbH
- * COPYRIGHT (c) 2015 Hesham Alatary <hesham at alumni.york.ac.uk>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <bsp/fatal.h>
-#include <bsp/fdt.h>
-#include <bsp/irq.h>
-#include <bsp/riscv.h>
-
-#include <rtems/sysinit.h>
-#include <rtems/timecounter.h>
-#include <rtems/score/cpuimpl.h>
-#include <rtems/score/riscv-utility.h>
-
-#include <libfdt.h>
-
-/* This is defined in dev/clock/clockimpl.h */
-void Clock_isr(void *arg);
-
-typedef struct {
- struct timecounter base;
- volatile RISCV_CLINT_regs *clint;
- uint32_t interval;
-} riscv_timecounter;
-
-static riscv_timecounter riscv_clock_tc;
-
-static void riscv_clock_write_mtimecmp(
- volatile RISCV_CLINT_timer_reg *mtimecmp,
- uint64_t value
-)
-{
-#if __riscv_xlen == 32
- mtimecmp->val_32[0] = 0xffffffff;
- mtimecmp->val_32[1] = (uint32_t) (value >> 32);
- mtimecmp->val_32[0] = (uint32_t) value;
-#elif __riscv_xlen == 64
- mtimecmp->val_64 = value;
-#endif
-}
-
-static uint64_t riscv_clock_read_mtime(volatile RISCV_CLINT_timer_reg *mtime)
-{
-#if __riscv_xlen == 32
- uint32_t low;
- uint32_t high_0;
- uint32_t high_1;
-
- do {
- high_0 = mtime->val_32[1];
- low = mtime->val_32[0];
- high_1 = mtime->val_32[1];
- } while (high_0 != high_1);
-
- return (((uint64_t) high_0) << 32) | low;
-#elif __riscv_xlen == 64
- return mtime->val_64;
-#endif
-}
-
-static void riscv_clock_at_tick(riscv_timecounter *tc)
-{
- volatile RISCV_CLINT_regs *clint;
- uint64_t value;
-
- clint = tc->clint;
-
- value = clint->mtimecmp[0].val_64;
- value += tc->interval;
-
- riscv_clock_write_mtimecmp(&clint->mtimecmp[0], value);
-}
-
-static void riscv_clock_handler_install(void)
-{
- rtems_status_code sc;
-
- sc = rtems_interrupt_handler_install(
- RISCV_INTERRUPT_VECTOR_TIMER,
- "Clock",
- RTEMS_INTERRUPT_UNIQUE,
- (rtems_interrupt_handler) Clock_isr,
- NULL
- );
- if (sc != RTEMS_SUCCESSFUL) {
- bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL);
- }
-}
-
-static uint32_t riscv_clock_get_timecount(struct timecounter *base)
-{
- riscv_timecounter *tc;
- volatile RISCV_CLINT_regs *clint;
-
- tc = (riscv_timecounter *) base;
- clint = tc->clint;
- return clint->mtime.val_32[0];
-}
-
-static uint32_t riscv_clock_get_timebase_frequency(const void *fdt)
-{
- int node;
- const uint32_t *val;
- int len;
-
- node = fdt_path_offset(fdt, "/cpus");
- val = fdt_getprop(fdt, node, "timebase-frequency", &len);
- if (val == NULL || len < 4) {
- bsp_fatal(RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE);
- }
-
- return fdt32_to_cpu(*val);
-}
-
-static void riscv_clock_initialize(void)
-{
- const char *fdt;
- riscv_timecounter *tc;
- volatile RISCV_CLINT_regs *clint;
- uint32_t tb_freq;
- uint64_t us_per_tick;
- uint32_t interval;
-
- fdt = bsp_fdt_get();
- tb_freq = riscv_clock_get_timebase_frequency(fdt);
- us_per_tick = rtems_configuration_get_microseconds_per_tick();
- interval = (uint32_t) ((tb_freq * us_per_tick) / 1000000);
- clint = riscv_clint;
- tc = &riscv_clock_tc;
-
- tc->clint = clint;
- tc->interval = interval;
-
- riscv_clock_write_mtimecmp(
- &clint->mtimecmp[0],
- riscv_clock_read_mtime(&clint->mtime) + interval
- );
-
- /* Enable mtimer interrupts */
- set_csr(mie, MIP_MTIP);
-
- /* Initialize timecounter */
- tc->base.tc_get_timecount = riscv_clock_get_timecount;
- tc->base.tc_counter_mask = 0xffffffff;
- tc->base.tc_frequency = tb_freq;
- tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
- rtems_timecounter_install(&tc->base);
-}
-
-volatile uint32_t _RISCV_Counter_register;
-
-static void riscv_counter_initialize(void)
-{
- _RISCV_Counter_mutable = &riscv_clint->mtime.val_32[0];
-}
-
-uint32_t _CPU_Counter_frequency( void )
-{
- return riscv_clock_get_timebase_frequency(bsp_fdt_get());
-}
-
-CPU_Counter_ticks _CPU_Counter_read( void )
-{
- return *_RISCV_Counter;
-}
-
-RTEMS_SYSINIT_ITEM(
- riscv_counter_initialize,
- RTEMS_SYSINIT_CPU_COUNTER,
- RTEMS_SYSINIT_ORDER_FIRST
-);
-
-#define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc)
-
-#define Clock_driver_support_initialize_hardware() riscv_clock_initialize()
-
-#define Clock_driver_support_install_isr(isr) \
- riscv_clock_handler_install()
-
-#define CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR
-
-#include "../../../shared/dev/clock/clockimpl.h"
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
deleted file mode 100644
index ffd9bbe..0000000
--- a/bsps/riscv/riscv/irq/irq.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
- * @file
- *
- * @ingroup riscv_interrupt
- *
- * @brief Interrupt support.
- */
-
-/*
- * Copyright (c) 2018 embedded brains GmbH
- *
- * Copyright (c) 2015 University of York.
- * Hesham Almatary <hesham at alumni.york.ac.uk>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <bsp/irq.h>
-#include <bsp/fatal.h>
-#include <bsp/fdt.h>
-#include <bsp/irq-generic.h>
-#include <bsp/riscv.h>
-
-#include <rtems/score/percpu.h>
-#include <rtems/score/riscv-utility.h>
-#include <rtems/score/smpimpl.h>
-
-#include <libfdt.h>
-
-volatile RISCV_CLINT_regs *riscv_clint;
-
-/*
- * The lovely PLIC has an interrupt enable bit per hart for each interrupt
- * source. This makes the interrupt enable/disable a bit difficult. We have
- * to store the interrupt distribution in software. To keep it simple, we
- * support only a one-to-one and one-to-all interrupt to processor
- * distribution. For a one-to-one distribution, the array member must point to
- * the enable register block of the corresponding. For a one-to-all
- * distribution, the array member must be NULL. The array index is the
- * external interrupt index minus one (external interrupt index zero is a
- * special value, see PLIC documentation).
- */
-static volatile uint32_t *
-riscv_plic_irq_to_cpu[RISCV_MAXIMUM_EXTERNAL_INTERRUPTS];
-
-RTEMS_INTERRUPT_LOCK_DEFINE(static, riscv_plic_lock, "PLIC")
-
-void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
-{
- /*
- * Get rid of the most significant bit which indicates if the exception was
- * caused by an interrupt or not.
- */
- mcause <<= 1;
-
- if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) {
- bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER);
- } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) {
- volatile RISCV_PLIC_hart_regs *plic_hart_regs;
- uint32_t interrupt_index;
-
- plic_hart_regs = cpu_self->cpu_per_cpu.plic_hart_regs;
-
- while ((interrupt_index = plic_hart_regs->claim_complete) != 0) {
- bsp_interrupt_handler_dispatch(
- RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index)
- );
-
- plic_hart_regs->claim_complete = interrupt_index;
-
- /*
- * FIXME: It is not clear which fence is necessary here or if a fence is
- * necessary at all. The goal is that the complete signal is somehow
- * recognized by the PLIC before the next claim is issued.
- */
- __asm__ volatile ("fence o, i" : : : "memory");
- }
- } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
-#ifdef RTEMS_SMP
- /*
- * Clear the software interrupt on this processor. Synchronization of
- * inter-processor interrupts is done via Per_CPU_Control::message in
- * _SMP_Inter_processor_interrupt_handler().
- */
- *cpu_self->cpu_per_cpu.clint_msip = 0;
-
- _SMP_Inter_processor_interrupt_handler(cpu_self);
-#else
- bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
-#endif
- } else {
- bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
- }
-}
-
-static void riscv_clint_init(const void *fdt)
-{
- volatile RISCV_CLINT_regs *clint;
- int node;
- const uint32_t *val;
- int len;
- int i;
-
- node = fdt_node_offset_by_compatible(fdt, -1, "riscv,clint0");
-
- clint = riscv_fdt_get_address(fdt, node);
- if (clint == NULL) {
- bsp_fatal(RISCV_FATAL_NO_CLINT_REG_IN_DEVICE_TREE);
- }
-
- riscv_clint = clint;
-
- val = fdt_getprop(fdt, node, "interrupts-extended", &len);
-
- for (i = 0; i < len; i += 16) {
- uint32_t hart_index;
- Per_CPU_Control *cpu;
-
- hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
- if (hart_index >= rtems_configuration_get_maximum_processors()) {
- continue;
- }
-
- cpu = _Per_CPU_Get_by_index(hart_index);
- cpu->cpu_per_cpu.clint_msip = &clint->msip[i / 16];
- cpu->cpu_per_cpu.clint_mtimecmp = &clint->mtimecmp[i / 16];
- }
-}
-
-static void riscv_plic_init(const void *fdt)
-{
- volatile RISCV_PLIC_regs *plic;
- int node;
- int i;
- const uint32_t *val;
- int len;
- uint32_t interrupt_index;
- uint32_t ndev;
- Per_CPU_Control *cpu;
-
- node = fdt_node_offset_by_compatible(fdt, -1, "riscv,plic0");
-
- plic = riscv_fdt_get_address(fdt, node);
- if (plic == NULL) {
-#if RISCV_ENABLE_HTIF_SUPPORT != 0
- /* Spike platform has HTIF and does not have a PLIC */
- return;
-#else
- bsp_fatal(RISCV_FATAL_NO_PLIC_REG_IN_DEVICE_TREE);
-#endif
- }
-
- val = fdt_getprop(fdt, node, "riscv,ndev", &len);
- if (val == NULL || len != 4) {
- bsp_fatal(RISCV_FATAL_INVALID_PLIC_NDEV_IN_DEVICE_TREE);
- }
-
- ndev = fdt32_to_cpu(val[0]);
- if (ndev > RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) {
- bsp_fatal(RISCV_FATAL_TOO_LARGE_PLIC_NDEV_IN_DEVICE_TREE);
- }
-
- val = fdt_getprop(fdt, node, "interrupts-extended", &len);
-
- for (i = 0; i < len; i += 8) {
- uint32_t hart_index;
-
- hart_index = riscv_get_hart_index_by_phandle(fdt32_to_cpu(val[i / 4]));
- if (hart_index >= rtems_configuration_get_maximum_processors()) {
- continue;
- }
-
- interrupt_index = fdt32_to_cpu(val[i / 4 + 1]);
- if (interrupt_index != RISCV_INTERRUPT_EXTERNAL_MACHINE) {
- continue;
- }
-
- plic->harts[i / 8].priority_threshold = 0;
-
- cpu = _Per_CPU_Get_by_index(hart_index);
- cpu->cpu_per_cpu.plic_hart_regs = &plic->harts[i / 8];
- cpu->cpu_per_cpu.plic_m_ie = &plic->enable[i / 8][0];
- }
-
- cpu = _Per_CPU_Get_by_index(0);
-
- for (interrupt_index = 1; interrupt_index <= ndev; ++interrupt_index) {
- plic->priority[interrupt_index] = 1;
- riscv_plic_irq_to_cpu[interrupt_index - 1] = cpu->cpu_per_cpu.plic_m_ie;
- }
-
- /*
- * External M-mode interrupts on secondary processors are enabled in
- * bsp_start_on_secondary_processor().
- */
- set_csr(mie, MIP_MEIP);
-}
-
-rtems_status_code bsp_interrupt_facility_initialize(void)
-{
- const void *fdt;
-
- fdt = bsp_fdt_get();
- riscv_clint_init(fdt);
- riscv_plic_init(fdt);
-
- return RTEMS_SUCCESSFUL;
-}
-
-void bsp_interrupt_vector_enable(rtems_vector_number vector)
-{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
-
- if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) {
- uint32_t interrupt_index;
- volatile uint32_t *enable;
- uint32_t group;
- uint32_t bit;
- rtems_interrupt_lock_context lock_context;
-
- interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector);
- enable = riscv_plic_irq_to_cpu[interrupt_index - 1];
- group = interrupt_index / 32;
- bit = UINT32_C(1) << (interrupt_index % 32);
-
- rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context);
-
- if (enable != NULL) {
- enable[group] |= bit;
- } else {
- uint32_t cpu_max;
- uint32_t cpu_index;
-
- cpu_max = _SMP_Get_processor_maximum();
-
- for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) {
- Per_CPU_Control *cpu;
-
- cpu = _Per_CPU_Get_by_index(cpu_index);
- enable = cpu->cpu_per_cpu.plic_m_ie;
-
- if (enable != NULL) {
- enable[group] |= bit;
- }
- }
- }
-
- rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
- }
-}
-
-void bsp_interrupt_vector_disable(rtems_vector_number vector)
-{
- bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
-
- if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) {
- uint32_t interrupt_index;
- volatile uint32_t *enable;
- uint32_t group;
- uint32_t bit;
- rtems_interrupt_lock_context lock_context;
-
- interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector);
- enable = riscv_plic_irq_to_cpu[interrupt_index - 1];
- group = interrupt_index / 32;
- bit = UINT32_C(1) << (interrupt_index % 32);
-
- rtems_interrupt_lock_acquire(&riscv_plic_lock, &lock_context);
-
- if (enable != NULL) {
- enable[group] &= ~bit;
- } else {
- uint32_t cpu_max;
- uint32_t cpu_index;
-
- cpu_max = _SMP_Get_processor_maximum();
-
- for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) {
- Per_CPU_Control *cpu;
-
- cpu = _Per_CPU_Get_by_index(cpu_index);
- enable = cpu->cpu_per_cpu.plic_m_ie;
-
- if (enable != NULL) {
- enable[group] &= ~bit;
- }
- }
- }
-
- rtems_interrupt_lock_release(&riscv_plic_lock, &lock_context);
- }
-}
-
-void bsp_interrupt_set_affinity(
- rtems_vector_number vector,
- const Processor_mask *affinity
-)
-{
- if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) {
- uint32_t interrupt_index;
- Processor_mask mask;
-
- interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector);
-
- _Processor_mask_And(&mask, affinity, _SMP_Get_online_processors());
-
- if (_Processor_mask_Is_equal(&mask, _SMP_Get_online_processors())) {
- riscv_plic_irq_to_cpu[interrupt_index - 1] = NULL;
- return;
- }
-
- if (_Processor_mask_Count(&mask) == 1) {
- uint32_t cpu_index;
- Per_CPU_Control *cpu;
-
- cpu_index = _Processor_mask_Find_last_set(&mask) - 1;
- cpu = _Per_CPU_Get_by_index(cpu_index);
- riscv_plic_irq_to_cpu[interrupt_index - 1] = cpu->cpu_per_cpu.plic_m_ie;
- return;
- }
-
- bsp_fatal(RISCV_FATAL_INVALID_INTERRUPT_AFFINITY);
- }
-}
-
-void bsp_interrupt_get_affinity(
- rtems_vector_number vector,
- Processor_mask *affinity
-)
-{
- _Processor_mask_Zero(affinity);
-
- if (RISCV_INTERRUPT_VECTOR_IS_EXTERNAL(vector)) {
- uint32_t interrupt_index;
- volatile uint32_t *enable;
-
- interrupt_index = RISCV_INTERRUPT_VECTOR_EXTERNAL_TO_INDEX(vector);
- enable = riscv_plic_irq_to_cpu[interrupt_index - 1];
-
- if (enable != NULL) {
- uint32_t cpu_max;
- uint32_t cpu_index;
-
- cpu_max = _SMP_Get_processor_maximum();
-
- for (cpu_index = 0; cpu_index < cpu_max; ++cpu_index) {
- Per_CPU_Control *cpu;
-
- cpu = _Per_CPU_Get_by_index(cpu_index);
-
- if (enable == cpu->cpu_per_cpu.plic_m_ie) {
- _Processor_mask_Set(affinity, cpu_index);
- break;
- }
- }
- } else {
- _Processor_mask_Assign(affinity, _SMP_Get_online_processors());
- }
- }
-}
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c
deleted file mode 100644
index af9e2ac..0000000
--- a/bsps/riscv/riscv/start/bsp_fatal_halt.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2018 embedded brains GmbH
- *
- * Copyright (c) 2015 University of York.
- * Hesham Almatary <hesham at alumni.york.ac.uk>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <bsp/riscv.h>
-#include <bsp/fdt.h>
-
-#include <libfdt.h>
-
-void _CPU_Fatal_halt(uint32_t source, uint32_t error)
-{
- const char *fdt;
- int node;
- volatile uintptr_t *sifive_test;
-
-#if RISCV_ENABLE_HTIF_SUPPORT != 0
- htif_poweroff();
-#endif
-
- fdt = bsp_fdt_get();
- node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0");
- sifive_test = riscv_fdt_get_address(fdt, node);
-
- while (true) {
- if (sifive_test != NULL) {
- *sifive_test = 0x5555;
- }
- }
-}
diff --git a/c/src/lib/libbsp/riscv/riscv/Makefile.am b/c/src/lib/libbsp/riscv/riscv/Makefile.am
index 34bedf8..2f08218 100644
--- a/c/src/lib/libbsp/riscv/riscv/Makefile.am
+++ b/c/src/lib/libbsp/riscv/riscv/Makefile.am
@@ -34,7 +34,7 @@ project_lib_LIBRARIES = librtemsbsp.a
# Startup
librtemsbsp_a_SOURCES = ../../../../../../bsps/shared/start/bspreset-empty.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bspstart.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bsp_fatal_halt.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/shared/start/bsp_fatal_halt.c
# Shared
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspfatal-default.c
@@ -43,14 +43,14 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bsp-fdt.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c
# clock
-librtemsbsp_a_SOURCES +=../../../../../../bsps/riscv/riscv/clock/clockdrv.c
+librtemsbsp_a_SOURCES +=../../../../../../bsps/riscv/shared/clock/clockdrv.c
# Timer
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/btimer/btimer-stub.c
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
-librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/irq/irq.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/shared/irq/irq.c
# Cache
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/cache/nocache.c
--
2.7.4
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