Status of fenv.h header and floating point environment support in newlib

Vaibhav Gupta vaibhav.varodek at gmail.com
Mon Feb 17 16:38:38 UTC 2020


On Mon, 17 Feb 2020 at 21:06, Joel Sherrill <joel at rtems.org> wrote:

> Ayush please add yourself to  https://devel.rtems.org/wiki/GSoC/2020.
>
> Vaibhav.. we haven't asked others to add themselves to the table.
> Please ping anyone we missed.
>
Sure, I will inform them.

>
> On the fenv.h side, there are some basic guidelines on how to provide
> the fenv functionality and subtleties from the POSIX requirements.
>
And Dr Joel have already re-structured fenv implementation of RISCV
last summer. I would recommend everyone to study that structure for
once, those who are planning to work on fenv.
Porting fenv for other architectures under same structure will make
thing simple.
Also, check the weekly updates of
last year https://devel.rtems.org/wiki/GSoC/2019#VaibhavGupta
and go through the discussions done on mailing list. Check archives.
They will be of lot help to get to know the work done till now.

--Vaibhav Gupta

>
> First, the preferred origin of the implementation is another open source
> project with FreeBSD and NetBSD being at the top of the list. For example,
> here is the NetBSD implementation for the m68k:
>
> https://github.com/NetBSD/src/blob/trunk/sys/arch/m68k/include/fenv.h
>
> But there are differences between vanilla m68k and coldfire so that may
> not support all CPU variations. Would have to be determined.
>
> I have not found a SPARC implementation with an appropriate license.
> Jiri may have a better source.
>
> I would put ARM, PowerPC, and MIPS at the top of the desired list that we
> should be able to find BSD implementations for. We don't have an aarch64
> port yet but I wouldn't stop a GSoC student from adding it to newlib. Just
> can't
> be tested with RTEMS yet. Beyond that, architectures like the m68k where it
> is porting, not writing from scratch are priorities. Covering as many
> architectures
> that are popular with RTEMS is the goal. SPARC64 would be down the list
> based on that.
>
> Next POSIX allows an implementation to not support much if it isn't there
> in hardware.
>
>
> https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/fenv.h.html#tag_13_12
>
>
> The fact that an architecture may not support a feature is challenging to
> testing.
>
> --joel
>
> On Mon, Feb 17, 2020 at 5:54 AM Jiri Gaisler <jiri at gaisler.se> wrote:
>
>>
>> On 2/17/20 11:16 AM, Vaibhav Gupta wrote:
>>
>>
>>
>> On Mon, Feb 17, 2020, 3:07 PM Ayush Dwivedi <21cencturyayush at gmail.com>
>> wrote:
>>
>>> Hello Joel,
>>> This is regarding the open project #2966 POSIX-Compliance #2971( Add
>>> fenv.h to newlib). The task is about adding the floating point environment
>>> header to the newlib library but the source code of the library already has
>>> the header with the listed function declarations and data struct as needed.
>>> The implementations for the following architectures are available in the
>>> newlib-cygwin repository:
>>> >RISCV
>>> >i386
>>> >x86_64
>>> As pointed out in the POSIX Compliance project sub-task page the
>>> implementations for following architectures are yet to be added:
>>> >ARM(software float implementation for this exists but no fenv
>>> implementation)
>>> >AArch64(software float implementation for this exists but no fenv
>>> implementation)
>>> >SPARC and SPARC64(directories for these architectures are missing from
>>> libm/machine/ so no implementation of any sort)
>>>
>>> I would like to try and implement the functions declared in the header
>>> using BSD libc of FreeBSD as reference for the ARM and SPARC architectures.
>>>
>>> Following is the output after running test for posix fenv
>>> header(psxfenv01.exe) for SPARC using sparc-rtems5-sis and
>>> sparc-rtems5-gdb.(The Test failed)
>>>
>> Yes because testsuite needs modifications and moreover fenv on SPARC is
>> not yet supported. Since the support for RISCV and x86_64 is present, you
>> can make a testsuite for them. You can use qemu for running riscv files.
>>
>> Note that sis (riscv-rtems5-sis) also supports RISCV32 using the griscv
>> BSP in RTEMS.
>>
>> Jiri.
>>
>> _______________________________________________
>> devel mailing list
>> devel at rtems.org
>> http://lists.rtems.org/mailman/listinfo/devel
>
>
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