[PATCH] Reflect removal of the epiphany target

[Sebastian Huber]

---
 cpu-supplement/epiphany.rst | 89 ++-----------------------------------
 user/bsps/bsps-epiphany.rst | 11 -----
 user/bsps/index.rst         |  1 -
 3 files changed, 4 insertions(+), 97 deletions(-)
 delete mode 100644 user/bsps/bsps-epiphany.rst

diff --git a/cpu-supplement/epiphany.rst b/cpu-supplement/epiphany.rst
index 7d39476..c2b2d86 100644
--- a/cpu-supplement/epiphany.rst
+++ b/cpu-supplement/epiphany.rst
@@ -1,91 +1,10 @@
 .. SPDX-License-Identifier: CC-BY-SA-4.0
 
-.. Copyright (C) 2015 Hesham Almatary
-.. Copyright (C) 1988, 2002 On-Line Applications Research Corporation (OAR)
+.. Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
 
 Epiphany Specific Information
 *****************************
 
-This chapter discusses the`Epiphany Architecture
-http://adapteva.com/docs/epiphany_sdk_ref.pdf dependencies in this port of
-RTEMS. Epiphany is a chip that can come with 16 and 64 cores, each of which can
-run RTEMS separately or they can work together to run a SMP RTEMS application.
-
-**Architecture Documents**
-
-For information on the Epiphany architecture refer to the *Epiphany
-Architecture Reference* http://adapteva.com/docs/epiphany_arch_ref.pdf.
-
-Calling Conventions
-===================
-
-Please refer to the *Epiphany SDK*
-http://adapteva.com/docs/epiphany_sdk_ref.pdf Appendix A: Application Binary
-Interface
-
-Floating Point Unit
--------------------
-
-A floating point unit is currently not supported.
-
-Memory Model
-============
-
-A flat 32-bit memory model is supported, no caches. Each core has its own 32
-KiB strictly ordered local memory along with an access to a shared 32 MiB
-external DRAM.
-
-Interrupt Processing
-====================
-
-Every Epiphany core has 10 exception types:
-
-- Reset
-
-- Software Exception
-
-- Data Page Fault
-
-- Timer 0
-
-- Timer 1
-
-- Message Interrupt
-
-- DMA0 Interrupt
-
-- DMA1 Interrupt
-
-- WANT Interrupt
-
-- User Interrupt
-
-Interrupt Levels
-----------------
-
-There are only two levels: interrupts enabled and interrupts disabled.
-
-Interrupt Stack
----------------
-
-The Epiphany RTEMS port uses a dedicated software interrupt stack.  The stack
-for interrupts is allocated during interrupt driver initialization.  When an
-interrupt is entered, the _ISR_Handler routine is responsible for switching
-from the interrupted task stack to RTEMS software interrupt stack.
-
-Default Fatal Error Processing
-==============================
-
-The default fatal error handler for this architecture performs the following
-actions:
-
-- disables operating system supported interrupts (IRQ),
-
-- places the error code in ``r0``, and
-
-- executes an infinite loop to simulate a halt processor instruction.
-
-Symmetric Multiprocessing
-=========================
-
-SMP is not supported.
+Due to an unmaintained toolchain (internal errors in GCC, no FSF GDB
+integration) the Epiphany architecture was obsoleted in
+RTEMS 5.1 and removed in RTEMS 6.1.
diff --git a/user/bsps/bsps-epiphany.rst b/user/bsps/bsps-epiphany.rst
deleted file mode 100644
index 82b05e6..0000000
--- a/user/bsps/bsps-epiphany.rst
+++ /dev/null
@@ -1,11 +0,0 @@
-.. SPDX-License-Identifier: CC-BY-SA-4.0
-
-.. Copyright (C) 2018 embedded brains GmbH
-
-epiphany (Epiphany)
-*******************
-
-epiphany_sim
-============
-
-TODO.
diff --git a/user/bsps/index.rst b/user/bsps/index.rst
index 0c3b2f6..bf590e0 100644
--- a/user/bsps/index.rst
+++ b/user/bsps/index.rst
@@ -27,7 +27,6 @@ You can see the current BSP list in the RTEMS sources by asking RTEMS with:
     bsps-aarch64
     bsps-arm
     bsps-bfin
-    bsps-epiphany
     bsps-i386
     bsps-lm32
     bsps-m68k
-- 
2.26.2